stats.txt revision 11515:c48c7cc5a522
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.232865 # Number of seconds simulated 4sim_ticks 232864525000 # Number of ticks simulated 5final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 230904 # Simulator instruction rate (inst/s) 8host_op_rate 250150 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 106424359 # Simulator tick rate (ticks/s) 10host_mem_usage 342436 # Number of bytes of host memory used 11host_seconds 2188.08 # Real time elapsed on the host 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 423921 # Number of read requests accepted 44system.physmem.writeReqs 292354 # Number of write requests accepted 45system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 26585 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25966 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25309 # Per bank write bursts 58system.physmem.perBankRdBursts::3 32108 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27451 # Per bank write bursts 60system.physmem.perBankRdBursts::5 28247 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25115 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24228 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25496 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25694 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25307 # Per bank write bursts 66system.physmem.perBankRdBursts::11 26044 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27396 # Per bank write bursts 68system.physmem.perBankRdBursts::13 26024 # Per bank write bursts 69system.physmem.perBankRdBursts::14 24983 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25596 # Per bank write bursts 71system.physmem.perBankWrBursts::0 18605 # Per bank write bursts 72system.physmem.perBankWrBursts::1 18353 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18036 # Per bank write bursts 74system.physmem.perBankWrBursts::3 17927 # Per bank write bursts 75system.physmem.perBankWrBursts::4 18566 # Per bank write bursts 76system.physmem.perBankWrBursts::5 18339 # Per bank write bursts 77system.physmem.perBankWrBursts::6 17904 # Per bank write bursts 78system.physmem.perBankWrBursts::7 17705 # Per bank write bursts 79system.physmem.perBankWrBursts::8 17878 # Per bank write bursts 80system.physmem.perBankWrBursts::9 17947 # Per bank write bursts 81system.physmem.perBankWrBursts::10 18182 # Per bank write bursts 82system.physmem.perBankWrBursts::11 18731 # Per bank write bursts 83system.physmem.perBankWrBursts::12 18803 # Per bank write bursts 84system.physmem.perBankWrBursts::13 18363 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18474 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18505 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 232864472500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 423921 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 292354 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads 246system.physmem.totQLat 8669198966 # Total ticks spent queuing 247system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM 248system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers 249system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst 250system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 251system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst 252system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s 253system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s 254system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s 255system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s 256system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 257system.physmem.busUtil 1.53 # Data bus utilization in percentage 258system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 259system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 260system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing 261system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing 262system.physmem.readRowHits 306141 # Number of row buffer hits during reads 263system.physmem.writeRowHits 85116 # Number of row buffer hits during writes 264system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads 265system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes 266system.physmem.avgGap 325104.84 # Average gap between requests 267system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined 268system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) 269system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) 270system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) 271system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) 272system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) 273system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) 274system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) 275system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) 276system.physmem_0.averagePower 728.002962 # Core power per rank (mW) 277system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states 278system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states 279system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states 281system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 282system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) 283system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) 284system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) 285system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) 286system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) 287system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) 288system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) 289system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) 290system.physmem_1.averagePower 725.972811 # Core power per rank (mW) 291system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states 292system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states 293system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states 295system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.cpu.branchPred.lookups 174583649 # Number of BP lookups 297system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 302system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage 303system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. 305system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. 306system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. 307system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. 308system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. 309system.cpu_clk_domain.clock 500 # Clock period in ticks 310system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 319system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 320system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 321system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 322system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 323system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 339system.cpu.dtb.walker.walks 0 # Table walker walks requested 340system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.inst_hits 0 # ITB inst hits 348system.cpu.dtb.inst_misses 0 # ITB inst misses 349system.cpu.dtb.read_hits 0 # DTB read hits 350system.cpu.dtb.read_misses 0 # DTB read misses 351system.cpu.dtb.write_hits 0 # DTB write hits 352system.cpu.dtb.write_misses 0 # DTB write misses 353system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 354system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 355system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 356system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 357system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 358system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 359system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 360system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dtb.read_accesses 0 # DTB read accesses 363system.cpu.dtb.write_accesses 0 # DTB write accesses 364system.cpu.dtb.inst_accesses 0 # ITB inst accesses 365system.cpu.dtb.hits 0 # DTB hits 366system.cpu.dtb.misses 0 # DTB misses 367system.cpu.dtb.accesses 0 # DTB accesses 368system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 377system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 378system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 379system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 380system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 381system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 382system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 386system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 387system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 388system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 389system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 397system.cpu.itb.walker.walks 0 # Table walker walks requested 398system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.inst_hits 0 # ITB inst hits 406system.cpu.itb.inst_misses 0 # ITB inst misses 407system.cpu.itb.read_hits 0 # DTB read hits 408system.cpu.itb.read_misses 0 # DTB read misses 409system.cpu.itb.write_hits 0 # DTB write hits 410system.cpu.itb.write_misses 0 # DTB write misses 411system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 412system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 413system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 414system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 415system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 416system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 417system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 418system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu.itb.read_accesses 0 # DTB read accesses 421system.cpu.itb.write_accesses 0 # DTB write accesses 422system.cpu.itb.inst_accesses 0 # ITB inst accesses 423system.cpu.itb.hits 0 # DTB hits 424system.cpu.itb.misses 0 # DTB misses 425system.cpu.itb.accesses 0 # DTB accesses 426system.cpu.workload.num_syscalls 548 # Number of system calls 427system.cpu.numCycles 465729051 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing 436system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 437system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps 438system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR 439system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched 440system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed 441system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle 454system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle 455system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle 456system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked 457system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running 458system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking 459system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing 460system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch 461system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction 462system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode 463system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode 464system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing 465system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle 466system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking 467system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst 468system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running 469system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking 470system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename 471system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename 472system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full 473system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full 474system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full 475system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full 476system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed 477system.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made 478system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups 479system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 480system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed 481system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing 482system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed 483system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed 484system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer 485system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. 486system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. 487system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. 488system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. 489system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) 490system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ 491system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued 492system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued 493system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling 494system.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph 495system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed 496system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle 513system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 514system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available 543system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available 545system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 548system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued 549system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued 550system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued 577system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued 578system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued 579system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 580system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued 582system.cpu.iq.rate 1.307470 # Inst issue rate 583system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested 584system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) 585system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads 586system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes 587system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses 588system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads 589system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes 590system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 591system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses 592system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses 593system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores 594system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 595system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed 596system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed 597system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations 598system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed 599system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 600system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 601system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled 602system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked 603system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 604system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing 605system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking 606system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking 607system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ 608system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 609system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions 610system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions 611system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions 612system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall 613system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall 614system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations 615system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly 616system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly 617system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute 618system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions 619system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed 620system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute 621system.cpu.iew.exec_swp 0 # number of swp insts executed 622system.cpu.iew.exec_nop 1492919 # number of nop insts executed 623system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed 624system.cpu.iew.exec_branches 131263664 # Number of branches executed 625system.cpu.iew.exec_stores 60919662 # Number of stores executed 626system.cpu.iew.exec_rate 1.284925 # Inst execution rate 627system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit 628system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back 629system.cpu.iew.wb_producers 349565798 # num instructions producing a value 630system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value 631system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle 632system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back 633system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit 634system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 635system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted 636system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle 653system.cpu.commit.committedInsts 506578818 # Number of instructions committed 654system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed 655system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 656system.cpu.commit.refs 172743503 # Number of memory references committed 657system.cpu.commit.loads 115883283 # Number of loads committed 658system.cpu.commit.membars 1488542 # Number of memory barriers committed 659system.cpu.commit.branches 121552863 # Number of branches committed 660system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 661system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. 662system.cpu.commit.function_calls 9757362 # Number of function calls committed. 663system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 664system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction 665system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 666system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 669system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 693system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 694system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction 695system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 696system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 697system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction 698system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached 699system.cpu.rob.rob_reads 1090292113 # The number of ROB reads 700system.cpu.rob.rob_writes 1328334369 # The number of ROB writes 701system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself 702system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling 703system.cpu.committedInsts 505234934 # Number of Instructions Simulated 704system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated 705system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction 706system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads 707system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle 708system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads 709system.cpu.int_regfile_reads 610135542 # number of integer regfile reads 710system.cpu.int_regfile_writes 327337405 # number of integer regfile writes 711system.cpu.fp_regfile_reads 16 # number of floating regfile reads 712system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads 713system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes 714system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads 715system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 716system.cpu.dcache.tags.replacements 2817145 # number of replacements 717system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use 718system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. 719system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. 720system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. 721system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 722system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor 723system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy 724system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy 725system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 727system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 728system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 729system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 730system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses 731system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses 732system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits 733system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits 734system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits 735system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits 736system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits 737system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits 738system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 739system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits 740system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 741system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 742system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits 743system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits 744system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits 745system.cpu.dcache.overall_hits::total 165893629 # number of overall hits 746system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses 747system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses 748system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses 749system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses 750system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 751system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 752system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 753system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 754system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses 755system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses 756system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses 757system.cpu.dcache.overall_misses::total 7353956 # number of overall misses 758system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles 759system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles 760system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles 761system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles 762system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles 763system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles 764system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles 765system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles 766system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles 767system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles 768system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) 769system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) 770system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 771system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 772system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) 773system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) 774system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) 775system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) 776system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 777system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 778system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses 779system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses 780system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses 781system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses 782system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses 783system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses 784system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses 785system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses 786system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses 787system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses 788system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 789system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 790system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses 791system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses 792system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses 793system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses 794system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency 795system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency 797system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency 798system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency 799system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency 800system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency 801system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency 804system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked 805system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 807system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked 809system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked 810system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks 811system.cpu.dcache.writebacks::total 2817145 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits 819system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits 820system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits 821system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits 822system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses 823system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 827system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 828system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses 829system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses 830system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses 831system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses 832system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses 847system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses 848system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses 849system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses 850system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses 851system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency 862system.cpu.icache.tags.replacements 76528 # number of replacements 863system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 867system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 868system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy 870system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 872system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses 880system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits 885system.cpu.icache.overall_hits::total 235186472 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses 888system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses 889system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses 890system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses 891system.cpu.icache.overall_misses::total 84972 # number of overall misses 892system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles 893system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles 894system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles 895system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles 896system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles 897system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles 898system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses 901system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses 902system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses 903system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses 904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses 905system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses 906system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses 907system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses 908system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses 909system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses 910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency 911system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency 912system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 913system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked 922system.cpu.icache.writebacks::writebacks 76528 # number of writebacks 923system.cpu.icache.writebacks::total 76528 # number of writebacks 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits 930system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses 931system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses 932system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses 933system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses 934system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses 935system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses 936system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles 937system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles 938system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles 942system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses 943system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses 944system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses 945system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 954system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing 960system.cpu.l2cache.tags.replacements 395630 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use 962system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. 963system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. 964system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. 965system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. 966system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor 967system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor 968system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy 970system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 986system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses 987system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses 988system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits 990system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits 991system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits 994system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits 995system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits 996system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits 997system.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits 998system.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits 1001system.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits 1002system.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits 1003system.cpu.l2cache.overall_hits::total 2722440 # number of overall hits 1004system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses 1005system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses 1006system.cpu.l2cache.ReadExReq_misses::cpu.data 5096 # number of ReadExReq misses 1007system.cpu.l2cache.ReadExReq_misses::total 5096 # number of ReadExReq misses 1008system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8194 # number of ReadCleanReq misses 1009system.cpu.l2cache.ReadCleanReq_misses::total 8194 # number of ReadCleanReq misses 1010system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158964 # number of ReadSharedReq misses 1011system.cpu.l2cache.ReadSharedReq_misses::total 158964 # number of ReadSharedReq misses 1012system.cpu.l2cache.demand_misses::cpu.inst 8194 # number of demand (read+write) misses 1013system.cpu.l2cache.demand_misses::cpu.data 164060 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::total 172254 # number of demand (read+write) misses 1015system.cpu.l2cache.overall_misses::cpu.inst 8194 # number of overall misses 1016system.cpu.l2cache.overall_misses::cpu.data 164060 # number of overall misses 1017system.cpu.l2cache.overall_misses::total 172254 # number of overall misses 1018system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40500 # number of UpgradeReq miss cycles 1019system.cpu.l2cache.UpgradeReq_miss_latency::total 40500 # number of UpgradeReq miss cycles 1020system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484398500 # number of ReadExReq miss cycles 1021system.cpu.l2cache.ReadExReq_miss_latency::total 484398500 # number of ReadExReq miss cycles 1022system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 596844000 # number of ReadCleanReq miss cycles 1023system.cpu.l2cache.ReadCleanReq_miss_latency::total 596844000 # number of ReadCleanReq miss cycles 1024system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12095410500 # number of ReadSharedReq miss cycles 1025system.cpu.l2cache.ReadSharedReq_miss_latency::total 12095410500 # number of ReadSharedReq miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.inst 596844000 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::cpu.data 12579809000 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.demand_miss_latency::total 13176653000 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.inst 596844000 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::cpu.data 12579809000 # number of overall miss cycles 1031system.cpu.l2cache.overall_miss_latency::total 13176653000 # number of overall miss cycles 1032system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350571 # number of WritebackDirty accesses(hits+misses) 1033system.cpu.l2cache.WritebackDirty_accesses::total 2350571 # number of WritebackDirty accesses(hits+misses) 1034system.cpu.l2cache.WritebackClean_accesses::writebacks 519224 # number of WritebackClean accesses(hits+misses) 1035system.cpu.l2cache.WritebackClean_accesses::total 519224 # number of WritebackClean accesses(hits+misses) 1036system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::cpu.data 522011 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.ReadExReq_accesses::total 522011 # number of ReadExReq accesses(hits+misses) 1040system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77037 # number of ReadCleanReq accesses(hits+misses) 1041system.cpu.l2cache.ReadCleanReq_accesses::total 77037 # number of ReadCleanReq accesses(hits+misses) 1042system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295646 # number of ReadSharedReq accesses(hits+misses) 1043system.cpu.l2cache.ReadSharedReq_accesses::total 2295646 # number of ReadSharedReq accesses(hits+misses) 1044system.cpu.l2cache.demand_accesses::cpu.inst 77037 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::cpu.data 2817657 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::total 2894694 # number of demand (read+write) accesses 1047system.cpu.l2cache.overall_accesses::cpu.inst 77037 # number of overall (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.data 2817657 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::total 2894694 # number of overall (read+write) accesses 1050system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1051system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1052system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009762 # miss rate for ReadExReq accesses 1053system.cpu.l2cache.ReadExReq_miss_rate::total 0.009762 # miss rate for ReadExReq accesses 1054system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.106364 # miss rate for ReadCleanReq accesses 1055system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.106364 # miss rate for ReadCleanReq accesses 1056system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069246 # miss rate for ReadSharedReq accesses 1057system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069246 # miss rate for ReadSharedReq accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106364 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.data 0.058226 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::total 0.059507 # miss rate for demand accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106364 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.data 0.058226 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::total 0.059507 # miss rate for overall accesses 1064system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1350 # average UpgradeReq miss latency 1065system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1350 # average UpgradeReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706 # average ReadExReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598 # average ReadCleanReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847 # average ReadSharedReq miss latency 1071system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847 # average ReadSharedReq miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::total 76495.483414 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency 1078system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference 1085system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks 1086system.cpu.l2cache.writebacks::total 292354 # number of writebacks 1087system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1091system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits 1092system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4126 # number of ReadSharedReq MSHR hits 1093system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits 1094system.cpu.l2cache.demand_mshr_hits::cpu.data 5522 # number of demand (read+write) MSHR hits 1095system.cpu.l2cache.demand_mshr_hits::total 5531 # number of demand (read+write) MSHR hits 1096system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits 1097system.cpu.l2cache.overall_mshr_hits::cpu.data 5522 # number of overall MSHR hits 1098system.cpu.l2cache.overall_mshr_hits::total 5531 # number of overall MSHR hits 1099system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350840 # number of HardPFReq MSHR misses 1100system.cpu.l2cache.HardPFReq_mshr_misses::total 350840 # number of HardPFReq MSHR misses 1101system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses 1102system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses 1103system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3700 # number of ReadExReq MSHR misses 1104system.cpu.l2cache.ReadExReq_mshr_misses::total 3700 # number of ReadExReq MSHR misses 1105system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8185 # number of ReadCleanReq MSHR misses 1106system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8185 # number of ReadCleanReq MSHR misses 1107system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154838 # number of ReadSharedReq MSHR misses 1108system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154838 # number of ReadSharedReq MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::cpu.data 158538 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.demand_mshr_misses::total 166723 # number of demand (read+write) MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.data 158538 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350840 # number of overall MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::total 517563 # number of overall MSHR misses 1116system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of HardPFReq MSHR miss cycles 1117system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18642506693 # number of HardPFReq MSHR miss cycles 1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 439500 # number of UpgradeReq MSHR miss cycles 1119system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 439500 # number of UpgradeReq MSHR miss cycles 1120system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 332568000 # number of ReadExReq MSHR miss cycles 1121system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 332568000 # number of ReadExReq MSHR miss cycles 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 547176500 # number of ReadCleanReq MSHR miss cycles 1123system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 547176500 # number of ReadCleanReq MSHR miss cycles 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10861820000 # number of ReadSharedReq MSHR miss cycles 1125system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10861820000 # number of ReadSharedReq MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 547176500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11194388000 # number of demand (read+write) MSHR miss cycles 1128system.cpu.l2cache.demand_mshr_miss_latency::total 11741564500 # number of demand (read+write) MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 547176500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11194388000 # number of overall MSHR miss cycles 1131system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of overall MSHR miss cycles 1132system.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles 1133system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1134system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses 1139system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses 1140system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses 1141system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses 1142system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses 1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency 1151system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency 1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency 1153system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency 1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency 1157system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency 1167system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 1171system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1172system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1173system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution 1185system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) 1191system.cpu.toL2Bus.snoops 950855 # Total snoops (count) 1192system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram 1203system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) 1204system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1205system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1206system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1207system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) 1208system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1209system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) 1210system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1211system.membus.trans_dist::ReadResp 420223 # Transaction distribution 1212system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution 1213system.membus.trans_dist::CleanEvict 98859 # Transaction distribution 1214system.membus.trans_dist::UpgradeReq 33 # Transaction distribution 1215system.membus.trans_dist::ReadExReq 3697 # Transaction distribution 1216system.membus.trans_dist::ReadExResp 3697 # Transaction distribution 1217system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution 1218system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) 1219system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) 1220system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) 1221system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) 1222system.membus.snoops 0 # Total snoops (count) 1223system.membus.snoop_fanout::samples 815167 # Request fanout histogram 1224system.membus.snoop_fanout::mean 0 # Request fanout histogram 1225system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1226system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1227system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram 1228system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1229system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1230system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1231system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1232system.membus.snoop_fanout::total 815167 # Request fanout histogram 1233system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) 1234system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1235system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) 1236system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 1237 1238---------- End Simulation Statistics ---------- 1239