stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.231519 # Number of seconds simulated 4sim_ticks 231518815500 # Number of ticks simulated 5final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 126327 # Simulator instruction rate (inst/s) 8host_op_rate 136857 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57887815 # Simulator tick rate (ticks/s) 10host_mem_usage 321348 # Number of bytes of host memory used 11host_seconds 3999.44 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 547350944 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory 23system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 448618 # Number of read requests accepted 44system.physmem.writeReqs 303849 # Number of write requests accepted 45system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue 49system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 28534 # Per bank write bursts 56system.physmem.perBankRdBursts::1 27313 # Per bank write bursts 57system.physmem.perBankRdBursts::2 27956 # Per bank write bursts 58system.physmem.perBankRdBursts::3 26702 # Per bank write bursts 59system.physmem.perBankRdBursts::4 30075 # Per bank write bursts 60system.physmem.perBankRdBursts::5 29207 # Per bank write bursts 61system.physmem.perBankRdBursts::6 27700 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26438 # Per bank write bursts 63system.physmem.perBankRdBursts::8 28442 # Per bank write bursts 64system.physmem.perBankRdBursts::9 26796 # Per bank write bursts 65system.physmem.perBankRdBursts::10 28037 # Per bank write bursts 66system.physmem.perBankRdBursts::11 28667 # Per bank write bursts 67system.physmem.perBankRdBursts::12 28663 # Per bank write bursts 68system.physmem.perBankRdBursts::13 27984 # Per bank write bursts 69system.physmem.perBankRdBursts::14 26659 # Per bank write bursts 70system.physmem.perBankRdBursts::15 27067 # Per bank write bursts 71system.physmem.perBankWrBursts::0 19504 # Per bank write bursts 72system.physmem.perBankWrBursts::1 19011 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18881 # Per bank write bursts 74system.physmem.perBankWrBursts::3 18629 # Per bank write bursts 75system.physmem.perBankWrBursts::4 19556 # Per bank write bursts 76system.physmem.perBankWrBursts::5 19014 # Per bank write bursts 77system.physmem.perBankWrBursts::6 18738 # Per bank write bursts 78system.physmem.perBankWrBursts::7 18227 # Per bank write bursts 79system.physmem.perBankWrBursts::8 18808 # Per bank write bursts 80system.physmem.perBankWrBursts::9 18381 # Per bank write bursts 81system.physmem.perBankWrBursts::10 19036 # Per bank write bursts 82system.physmem.perBankWrBursts::11 19525 # Per bank write bursts 83system.physmem.perBankWrBursts::12 19578 # Per bank write bursts 84system.physmem.perBankWrBursts::13 19080 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18969 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18884 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 231518762500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 448618 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 303849 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads 238system.physmem.totQLat 10651839911 # Total ticks spent queuing 239system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 1.62 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing 254system.physmem.readRowHits 331076 # Number of row buffer hits during reads 255system.physmem.writeRowHits 99609 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes 258system.physmem.avgGap 307679.62 # Average gap between requests 259system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states 261system.physmem.memoryStateTime::REF 7730840000 # Time in different power states 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.membus.trans_dist::ReadReq 445006 # Transaction distribution 266system.membus.trans_dist::ReadResp 445005 # Transaction distribution 267system.membus.trans_dist::Writeback 303849 # Transaction distribution 268system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 269system.membus.trans_dist::UpgradeResp 4 # Transaction distribution 270system.membus.trans_dist::ReadExReq 3612 # Transaction distribution 271system.membus.trans_dist::ReadExResp 3612 # Transaction distribution 272system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) 273system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) 274system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) 275system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) 276system.membus.snoops 0 # Total snoops (count) 277system.membus.snoop_fanout::samples 752471 # Request fanout histogram 278system.membus.snoop_fanout::mean 0 # Request fanout histogram 279system.membus.snoop_fanout::stdev 0 # Request fanout histogram 280system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 281system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram 282system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 283system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 284system.membus.snoop_fanout::min_value 0 # Request fanout histogram 285system.membus.snoop_fanout::max_value 0 # Request fanout histogram 286system.membus.snoop_fanout::total 752471 # Request fanout histogram 287system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) 288system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 289system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) 290system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 291system.cpu_clk_domain.clock 500 # Clock period in ticks 292system.cpu.branchPred.lookups 175071152 # Number of BP lookups 293system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 298system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. 301system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 302system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 303system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 304system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 305system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 306system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 311system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 312system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 313system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 314system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 317system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 318system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 319system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 320system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 321system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 322system.cpu.dtb.inst_hits 0 # ITB inst hits 323system.cpu.dtb.inst_misses 0 # ITB inst misses 324system.cpu.dtb.read_hits 0 # DTB read hits 325system.cpu.dtb.read_misses 0 # DTB read misses 326system.cpu.dtb.write_hits 0 # DTB write hits 327system.cpu.dtb.write_misses 0 # DTB write misses 328system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 330system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 331system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 332system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 333system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 334system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses 343system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 344system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 345system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 346system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 347system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 348system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 349system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 350system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 351system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 352system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 353system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 354system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 355system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 356system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 357system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 364system.cpu.itb.inst_hits 0 # ITB inst hits 365system.cpu.itb.inst_misses 0 # ITB inst misses 366system.cpu.itb.read_hits 0 # DTB read hits 367system.cpu.itb.read_misses 0 # DTB read misses 368system.cpu.itb.write_hits 0 # DTB write hits 369system.cpu.itb.write_misses 0 # DTB write misses 370system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.itb.read_accesses 0 # DTB read accesses 380system.cpu.itb.write_accesses 0 # DTB write accesses 381system.cpu.itb.inst_accesses 0 # ITB inst accesses 382system.cpu.itb.hits 0 # DTB hits 383system.cpu.itb.misses 0 # DTB misses 384system.cpu.itb.accesses 0 # DTB accesses 385system.cpu.workload.num_syscalls 548 # Number of system calls 386system.cpu.numCycles 463037632 # number of cpu cycles simulated 387system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 388system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 389system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss 390system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed 391system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered 392system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken 393system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked 394system.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing 395system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 396system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps 397system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR 398system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched 399system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed 400system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle 413system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle 414system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle 415system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked 416system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running 417system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking 418system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing 419system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch 420system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction 421system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode 422system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode 423system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing 424system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle 425system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking 426system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst 427system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running 428system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking 429system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename 430system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename 431system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full 432system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full 433system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full 434system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full 435system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed 436system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made 437system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups 438system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 439system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 440system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing 441system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed 442system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed 443system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer 444system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. 445system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. 446system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. 447system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. 448system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) 449system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ 450system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued 451system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued 452system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling 453system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph 454system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed 455system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle 472system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available 474system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available 475system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 502system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available 503system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available 504system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 506system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 507system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued 508system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued 509system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 536system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued 537system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 539system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 540system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued 541system.cpu.iq.rate 1.317880 # Inst issue rate 542system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested 543system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) 544system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads 545system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes 546system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses 547system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 548system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 549system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 550system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses 551system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 552system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores 553system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 554system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed 555system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed 556system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations 557system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed 558system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 559system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 560system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled 561system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked 562system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 563system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing 564system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking 565system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking 566system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ 567system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 568system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions 569system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions 570system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions 571system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall 572system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall 573system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations 574system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly 575system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly 576system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute 577system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions 578system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed 579system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute 580system.cpu.iew.exec_swp 0 # number of swp insts executed 581system.cpu.iew.exec_nop 1486621 # number of nop insts executed 582system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed 583system.cpu.iew.exec_branches 131372634 # Number of branches executed 584system.cpu.iew.exec_stores 60949141 # Number of stores executed 585system.cpu.iew.exec_rate 1.294450 # Inst execution rate 586system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit 587system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back 588system.cpu.iew.wb_producers 349881958 # num instructions producing a value 589system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value 590system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 591system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle 592system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back 593system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 594system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit 595system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 596system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted 597system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle 614system.cpu.commit.committedInsts 506581607 # Number of instructions committed 615system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 617system.cpu.commit.refs 172745233 # Number of memory references committed 618system.cpu.commit.loads 115884756 # Number of loads committed 619system.cpu.commit.membars 1488542 # Number of memory barriers committed 620system.cpu.commit.branches 121548301 # Number of branches committed 621system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 622system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 623system.cpu.commit.function_calls 9757362 # Number of function calls committed. 624system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 625system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction 626system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 627system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 654system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 655system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 658system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 659system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached 660system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 661system.cpu.rob.rob_reads 1090469902 # The number of ROB reads 662system.cpu.rob.rob_writes 1334452491 # The number of ROB writes 663system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself 664system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling 665system.cpu.committedInsts 505237723 # Number of Instructions Simulated 666system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 667system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction 668system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads 669system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle 670system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads 671system.cpu.int_regfile_reads 611059108 # number of integer regfile reads 672system.cpu.int_regfile_writes 328109228 # number of integer regfile writes 673system.cpu.fp_regfile_reads 16 # number of floating regfile reads 674system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads 675system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes 676system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads 677system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 678system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution 679system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution 681system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution 682system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 683system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution 684system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution 685system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution 686system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution 687system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) 688system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) 689system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) 690system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) 691system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) 692system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) 693system.cpu.toL2Bus.snoops 453214 # Total snoops (count) 694system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram 695system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram 696system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram 697system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 698system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 699system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 700system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 708system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram 709system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) 710system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 711system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) 712system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 713system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) 714system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 715system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) 716system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 717system.cpu.icache.tags.replacements 73538 # number of replacements 718system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use 719system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. 720system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. 721system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. 722system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. 723system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor 724system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy 726system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 731system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id 732system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 733system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses 734system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses 735system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits 736system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits 737system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits 738system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits 739system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits 740system.cpu.icache.overall_hits::total 236609871 # number of overall hits 741system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses 742system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses 743system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses 744system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses 745system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses 746system.cpu.icache.overall_misses::total 78950 # number of overall misses 747system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles 748system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles 749system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles 750system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles 751system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles 752system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles 753system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) 755system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses 756system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses 757system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses 758system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses 759system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses 761system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses 762system.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses 763system.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses 764system.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency 766system.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency 767system.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 768system.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 770system.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency 771system.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked 772system.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked 773system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked 774system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 775system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked 776system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked 777system.cpu.icache.fast_writes 0 # number of fast writes performed 778system.cpu.icache.cache_copies 0 # number of cache copies performed 779system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits 780system.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits 781system.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits 782system.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits 783system.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits 784system.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits 785system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses 786system.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses 787system.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses 788system.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses 789system.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses 790system.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses 791system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles 796system.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles 797system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 798system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 799system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 800system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 801system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 802system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency 804system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 806system.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 808system.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency 809system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 810system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified 811system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr 812system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache 813system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue 814system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 815system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # number of hwpf removed because MSHR allocated 816system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 365354 # number of hwpf issued 817system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 921882 # number of hwpf spanning a virtual page 818system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 819system.cpu.l2cache.tags.replacements 438181 # number of replacements 820system.cpu.l2cache.tags.tagsinuse 15477.013957 # Cycle average of tags in use 821system.cpu.l2cache.tags.total_refs 4572801 # Total number of references to valid blocks. 822system.cpu.l2cache.tags.sampled_refs 454520 # Sample count of references to valid blocks. 823system.cpu.l2cache.tags.avg_refs 10.060726 # Average number of references to valid blocks. 824system.cpu.l2cache.tags.warmup_cycle 34588215000 # Cycle when the warmup percentage was hit. 825system.cpu.l2cache.tags.occ_blocks::writebacks 8046.531064 # Average occupied blocks per requestor 826system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.372204 # Average occupied blocks per requestor 827system.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor 828system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor 829system.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy 830system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy 831system.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy 832system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy 833system.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy 834system.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id 835system.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id 836system.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id 837system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 838system.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id 839system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id 840system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id 841system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 842system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 843system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id 844system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id 845system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id 846system.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id 847system.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id 848system.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses 849system.cpu.l2cache.tags.data_accesses 84920061 # Number of data accesses 850system.cpu.l2cache.ReadReq_hits::cpu.inst 70946 # number of ReadReq hits 851system.cpu.l2cache.ReadReq_hits::cpu.data 2166314 # number of ReadReq hits 852system.cpu.l2cache.ReadReq_hits::total 2237260 # number of ReadReq hits 853system.cpu.l2cache.Writeback_hits::writebacks 2348838 # number of Writeback hits 854system.cpu.l2cache.Writeback_hits::total 2348838 # number of Writeback hits 855system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 856system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 857system.cpu.l2cache.ReadExReq_hits::cpu.data 516602 # number of ReadExReq hits 858system.cpu.l2cache.ReadExReq_hits::total 516602 # number of ReadExReq hits 859system.cpu.l2cache.demand_hits::cpu.inst 70946 # number of demand (read+write) hits 860system.cpu.l2cache.demand_hits::cpu.data 2682916 # number of demand (read+write) hits 861system.cpu.l2cache.demand_hits::total 2753862 # number of demand (read+write) hits 862system.cpu.l2cache.overall_hits::cpu.inst 70946 # number of overall hits 863system.cpu.l2cache.overall_hits::cpu.data 2682916 # number of overall hits 864system.cpu.l2cache.overall_hits::total 2753862 # number of overall hits 865system.cpu.l2cache.ReadReq_misses::cpu.inst 3100 # number of ReadReq misses 866system.cpu.l2cache.ReadReq_misses::cpu.data 135521 # number of ReadReq misses 867system.cpu.l2cache.ReadReq_misses::total 138621 # number of ReadReq misses 868system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 869system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 870system.cpu.l2cache.ReadExReq_misses::cpu.data 5139 # number of ReadExReq misses 871system.cpu.l2cache.ReadExReq_misses::total 5139 # number of ReadExReq misses 872system.cpu.l2cache.demand_misses::cpu.inst 3100 # number of demand (read+write) misses 873system.cpu.l2cache.demand_misses::cpu.data 140660 # number of demand (read+write) misses 874system.cpu.l2cache.demand_misses::total 143760 # number of demand (read+write) misses 875system.cpu.l2cache.overall_misses::cpu.inst 3100 # number of overall misses 876system.cpu.l2cache.overall_misses::cpu.data 140660 # number of overall misses 877system.cpu.l2cache.overall_misses::total 143760 # number of overall misses 878system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221563221 # number of ReadReq miss cycles 879system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9589796237 # number of ReadReq miss cycles 880system.cpu.l2cache.ReadReq_miss_latency::total 9811359458 # number of ReadReq miss cycles 881system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14999 # number of UpgradeReq miss cycles 882system.cpu.l2cache.UpgradeReq_miss_latency::total 14999 # number of UpgradeReq miss cycles 883system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 412963248 # number of ReadExReq miss cycles 884system.cpu.l2cache.ReadExReq_miss_latency::total 412963248 # number of ReadExReq miss cycles 885system.cpu.l2cache.demand_miss_latency::cpu.inst 221563221 # number of demand (read+write) miss cycles 886system.cpu.l2cache.demand_miss_latency::cpu.data 10002759485 # number of demand (read+write) miss cycles 887system.cpu.l2cache.demand_miss_latency::total 10224322706 # number of demand (read+write) miss cycles 888system.cpu.l2cache.overall_miss_latency::cpu.inst 221563221 # number of overall miss cycles 889system.cpu.l2cache.overall_miss_latency::cpu.data 10002759485 # number of overall miss cycles 890system.cpu.l2cache.overall_miss_latency::total 10224322706 # number of overall miss cycles 891system.cpu.l2cache.ReadReq_accesses::cpu.inst 74046 # number of ReadReq accesses(hits+misses) 892system.cpu.l2cache.ReadReq_accesses::cpu.data 2301835 # number of ReadReq accesses(hits+misses) 893system.cpu.l2cache.ReadReq_accesses::total 2375881 # number of ReadReq accesses(hits+misses) 894system.cpu.l2cache.Writeback_accesses::writebacks 2348838 # number of Writeback accesses(hits+misses) 895system.cpu.l2cache.Writeback_accesses::total 2348838 # number of Writeback accesses(hits+misses) 896system.cpu.l2cache.UpgradeReq_accesses::cpu.data 26 # number of UpgradeReq accesses(hits+misses) 897system.cpu.l2cache.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) 898system.cpu.l2cache.ReadExReq_accesses::cpu.data 521741 # number of ReadExReq accesses(hits+misses) 899system.cpu.l2cache.ReadExReq_accesses::total 521741 # number of ReadExReq accesses(hits+misses) 900system.cpu.l2cache.demand_accesses::cpu.inst 74046 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.data 2823576 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::total 2897622 # number of demand (read+write) accesses 903system.cpu.l2cache.overall_accesses::cpu.inst 74046 # number of overall (read+write) accesses 904system.cpu.l2cache.overall_accesses::cpu.data 2823576 # number of overall (read+write) accesses 905system.cpu.l2cache.overall_accesses::total 2897622 # number of overall (read+write) accesses 906system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.041866 # miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.058875 # miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_miss_rate::total 0.058345 # miss rate for ReadReq accesses 909system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses 910system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses 911system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009850 # miss rate for ReadExReq accesses 912system.cpu.l2cache.ReadExReq_miss_rate::total 0.009850 # miss rate for ReadExReq accesses 913system.cpu.l2cache.demand_miss_rate::cpu.inst 0.041866 # miss rate for demand accesses 914system.cpu.l2cache.demand_miss_rate::cpu.data 0.049816 # miss rate for demand accesses 915system.cpu.l2cache.demand_miss_rate::total 0.049613 # miss rate for demand accesses 916system.cpu.l2cache.overall_miss_rate::cpu.inst 0.041866 # miss rate for overall accesses 917system.cpu.l2cache.overall_miss_rate::cpu.data 0.049816 # miss rate for overall accesses 918system.cpu.l2cache.overall_miss_rate::total 0.049613 # miss rate for overall accesses 919system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71472.006774 # average ReadReq miss latency 920system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70762.437091 # average ReadReq miss latency 921system.cpu.l2cache.ReadReq_avg_miss_latency::total 70778.305293 # average ReadReq miss latency 922system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4999.666667 # average UpgradeReq miss latency 923system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4999.666667 # average UpgradeReq miss latency 924system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80358.678342 # average ReadExReq miss latency 925system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80358.678342 # average ReadExReq miss latency 926system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 927system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 928system.cpu.l2cache.demand_avg_miss_latency::total 71120.775640 # average overall miss latency 929system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 930system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 931system.cpu.l2cache.overall_avg_miss_latency::total 71120.775640 # average overall miss latency 932system.cpu.l2cache.blocked_cycles::no_mshrs 8362 # number of cycles access was blocked 933system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 934system.cpu.l2cache.blocked::no_mshrs 219 # number of cycles access was blocked 935system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 936system.cpu.l2cache.avg_blocked_cycles::no_mshrs 38.182648 # average number of cycles each access was blocked 937system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 938system.cpu.l2cache.fast_writes 0 # number of fast writes performed 939system.cpu.l2cache.cache_copies 0 # number of cache copies performed 940system.cpu.l2cache.writebacks::writebacks 303849 # number of writebacks 941system.cpu.l2cache.writebacks::total 303849 # number of writebacks 942system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 992 # number of ReadReq MSHR hits 943system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5184 # number of ReadReq MSHR hits 944system.cpu.l2cache.ReadReq_mshr_hits::total 6176 # number of ReadReq MSHR hits 945system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1526 # number of ReadExReq MSHR hits 946system.cpu.l2cache.ReadExReq_mshr_hits::total 1526 # number of ReadExReq MSHR hits 947system.cpu.l2cache.demand_mshr_hits::cpu.inst 992 # number of demand (read+write) MSHR hits 948system.cpu.l2cache.demand_mshr_hits::cpu.data 6710 # number of demand (read+write) MSHR hits 949system.cpu.l2cache.demand_mshr_hits::total 7702 # number of demand (read+write) MSHR hits 950system.cpu.l2cache.overall_mshr_hits::cpu.inst 992 # number of overall MSHR hits 951system.cpu.l2cache.overall_mshr_hits::cpu.data 6710 # number of overall MSHR hits 952system.cpu.l2cache.overall_mshr_hits::total 7702 # number of overall MSHR hits 953system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2108 # number of ReadReq MSHR misses 954system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 130337 # number of ReadReq MSHR misses 955system.cpu.l2cache.ReadReq_mshr_misses::total 132445 # number of ReadReq MSHR misses 956system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 365353 # number of HardPFReq MSHR misses 957system.cpu.l2cache.HardPFReq_mshr_misses::total 365353 # number of HardPFReq MSHR misses 958system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 959system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 960system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3613 # number of ReadExReq MSHR misses 961system.cpu.l2cache.ReadExReq_mshr_misses::total 3613 # number of ReadExReq MSHR misses 962system.cpu.l2cache.demand_mshr_misses::cpu.inst 2108 # number of demand (read+write) MSHR misses 963system.cpu.l2cache.demand_mshr_misses::cpu.data 133950 # number of demand (read+write) MSHR misses 964system.cpu.l2cache.demand_mshr_misses::total 136058 # number of demand (read+write) MSHR misses 965system.cpu.l2cache.overall_mshr_misses::cpu.inst 2108 # number of overall MSHR misses 966system.cpu.l2cache.overall_mshr_misses::cpu.data 133950 # number of overall MSHR misses 967system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 365353 # number of overall MSHR misses 968system.cpu.l2cache.overall_mshr_misses::total 501411 # number of overall MSHR misses 969system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154832998 # number of ReadReq MSHR miss cycles 970system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8096605997 # number of ReadReq MSHR miss cycles 971system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8251438995 # number of ReadReq MSHR miss cycles 972system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of HardPFReq MSHR miss cycles 973system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21877894699 # number of HardPFReq MSHR miss cycles 974system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 18003 # number of UpgradeReq MSHR miss cycles 975system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 18003 # number of UpgradeReq MSHR miss cycles 976system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 231375752 # number of ReadExReq MSHR miss cycles 977system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 231375752 # number of ReadExReq MSHR miss cycles 978system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154832998 # number of demand (read+write) MSHR miss cycles 979system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8327981749 # number of demand (read+write) MSHR miss cycles 980system.cpu.l2cache.demand_mshr_miss_latency::total 8482814747 # number of demand (read+write) MSHR miss cycles 981system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154832998 # number of overall MSHR miss cycles 982system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8327981749 # number of overall MSHR miss cycles 983system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of overall MSHR miss cycles 984system.cpu.l2cache.overall_mshr_miss_latency::total 30360709446 # number of overall MSHR miss cycles 985system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for ReadReq accesses 986system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.056623 # mshr miss rate for ReadReq accesses 987system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.055746 # mshr miss rate for ReadReq accesses 988system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 989system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 990system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses 991system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses 992system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses 993system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses 994system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses 995system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses 996system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses 997system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses 998system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses 999system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1000system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency 1003system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency 1004system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency 1005system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency 1006system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1007system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1008system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency 1009system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency 1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency 1017system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1018system.cpu.dcache.tags.replacements 2823064 # number of replacements 1019system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use 1020system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. 1021system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. 1022system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. 1023system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. 1024system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor 1025system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy 1026system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy 1027system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1028system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 1029system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 1030system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 1031system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1032system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses 1033system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses 1034system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits 1035system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits 1036system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits 1037system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits 1038system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits 1039system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits 1040system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits 1041system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits 1042system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 1043system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 1044system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits 1045system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits 1046system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits 1047system.cpu.dcache.overall_hits::total 166678355 # number of overall hits 1048system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses 1049system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses 1050system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses 1051system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses 1052system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses 1053system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses 1054system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 1055system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 1056system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses 1057system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses 1058system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses 1059system.cpu.dcache.overall_misses::total 7049008 # number of overall misses 1060system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles 1061system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles 1062system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles 1063system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles 1064system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles 1065system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles 1066system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles 1067system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles 1068system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles 1069system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles 1070system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) 1071system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) 1072system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 1073system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 1074system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) 1075system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) 1076system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) 1077system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) 1078system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 1079system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 1080system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses 1081system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses 1082system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses 1083system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses 1084system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses 1085system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses 1086system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses 1087system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses 1088system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses 1089system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses 1090system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 1091system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 1092system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses 1093system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses 1094system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses 1095system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses 1096system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency 1097system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency 1098system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency 1099system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency 1100system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency 1101system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency 1102system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency 1103system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency 1104system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency 1105system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency 1106system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked 1107system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked 1108system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 1109system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked 1110system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked 1111system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked 1112system.cpu.dcache.fast_writes 0 # number of fast writes performed 1113system.cpu.dcache.cache_copies 0 # number of cache copies performed 1114system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks 1115system.cpu.dcache.writebacks::total 2348838 # number of writebacks 1116system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits 1117system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits 1118system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits 1119system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits 1120system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 1121system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 1122system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits 1123system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits 1124system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits 1125system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits 1126system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses 1127system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses 1128system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses 1129system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses 1130system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 1131system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 1132system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses 1133system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses 1134system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses 1135system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses 1136system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles 1137system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles 1138system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles 1139system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles 1140system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles 1141system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles 1142system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles 1143system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles 1144system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles 1145system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles 1146system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses 1147system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses 1148system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses 1149system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses 1150system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses 1151system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses 1152system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses 1153system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses 1154system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses 1155system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses 1156system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency 1157system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency 1158system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency 1159system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency 1160system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency 1161system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency 1162system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency 1163system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency 1164system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency 1165system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency 1166system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1167 1168---------- End Simulation Statistics ---------- 1169