stats.txt revision 10230:a2bb75a474fd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202425 # Number of seconds simulated 4sim_ticks 202425052500 # Number of ticks simulated 5final_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 117924 # Simulator instruction rate (inst/s) 8host_op_rate 132952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47246555 # Simulator tick rate (ticks/s) 10host_mem_usage 317744 # Number of bytes of host memory used 11host_seconds 4284.44 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9265920 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9482048 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6248320 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6248320 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 144780 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 148157 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 97630 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 97630 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1067694 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 45774571 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 46842265 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1067694 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1067694 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 30867326 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 30867326 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 30867326 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1067694 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 45774571 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 77709591 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 148159 # Number of read requests accepted 40system.physmem.writeReqs 97630 # Number of write requests accepted 41system.physmem.readBursts 148159 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 97630 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9473600 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6247040 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9482176 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6248320 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 5 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9589 # Per bank write bursts 52system.physmem.perBankRdBursts::1 9250 # Per bank write bursts 53system.physmem.perBankRdBursts::2 9271 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8997 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9766 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9623 # Per bank write bursts 57system.physmem.perBankRdBursts::6 9103 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8296 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8815 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8915 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8926 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9755 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9632 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9741 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8922 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9424 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6257 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6164 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6102 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5898 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6263 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6268 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6040 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5542 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5815 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5905 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5986 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6523 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6368 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6315 # Per bank write bursts 81system.physmem.perBankWrBursts::14 6035 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6129 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 202425037000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 148159 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 97630 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 138435 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 9034 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 2247 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5335 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5818 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5824 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5835 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5828 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5866 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5860 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5849 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5863 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5973 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5919 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5829 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5845 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5807 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5734 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 7 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65421 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 240.288837 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 153.819388 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 255.394880 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 26636 40.71% 40.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 17331 26.49% 67.21% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6016 9.20% 76.40% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 6235 9.53% 85.93% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 3111 4.76% 90.69% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1372 2.10% 92.79% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 907 1.39% 94.17% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 656 1.00% 95.17% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 3157 4.83% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65421 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.864057 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 376.771836 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5718 99.91% 99.91% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.055740 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.965515 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.130372 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 3465 60.55% 60.55% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2071 36.19% 96.73% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 82 1.43% 98.17% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 27 0.47% 98.64% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 23 0.40% 99.04% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 13 0.23% 99.60% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 7 0.12% 99.72% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 3 0.05% 99.77% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 3 0.05% 99.83% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.84% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::42-43 3 0.05% 99.90% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::44-45 1 0.02% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::46-47 2 0.03% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::50-51 1 0.02% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::68-69 1 0.02% 100.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads 239system.physmem.totQLat 1821123750 # Total ticks spent queuing 240system.physmem.totMemAccLat 4596592500 # Total ticks spent from burst creation until serviced by the DRAM 241system.physmem.totBusLat 740125000 # Total ticks spent in databus transfers 242system.physmem.avgQLat 12302.81 # Average queueing delay per DRAM burst 243system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 244system.physmem.avgMemAccLat 31052.81 # Average memory access latency per DRAM burst 245system.physmem.avgRdBW 46.80 # Average DRAM read bandwidth in MiByte/s 246system.physmem.avgWrBW 30.86 # Average achieved write bandwidth in MiByte/s 247system.physmem.avgRdBWSys 46.84 # Average system read bandwidth in MiByte/s 248system.physmem.avgWrBWSys 30.87 # Average system write bandwidth in MiByte/s 249system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 250system.physmem.busUtil 0.61 # Data bus utilization in percentage 251system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 252system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 253system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 254system.physmem.avgWrQLen 19.22 # Average write queue length when enqueuing 255system.physmem.readRowHits 115945 # Number of row buffer hits during reads 256system.physmem.writeRowHits 64262 # Number of row buffer hits during writes 257system.physmem.readRowHitRate 78.33 # Row buffer hit rate for reads 258system.physmem.writeRowHitRate 65.82 # Row buffer hit rate for writes 259system.physmem.avgGap 823572.40 # Average gap between requests 260system.physmem.pageHitRate 73.36 # Row buffer hit rate, read and write combined 261system.physmem.memoryStateTime::IDLE 121085417750 # Time in different power states 262system.physmem.memoryStateTime::REF 6759220000 # Time in different power states 263system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 264system.physmem.memoryStateTime::ACT 74577349250 # Time in different power states 265system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 266system.membus.throughput 77709591 # Throughput (bytes/s) 267system.membus.trans_dist::ReadReq 46864 # Transaction distribution 268system.membus.trans_dist::ReadResp 46862 # Transaction distribution 269system.membus.trans_dist::Writeback 97630 # Transaction distribution 270system.membus.trans_dist::UpgradeReq 5 # Transaction distribution 271system.membus.trans_dist::UpgradeResp 5 # Transaction distribution 272system.membus.trans_dist::ReadExReq 101295 # Transaction distribution 273system.membus.trans_dist::ReadExResp 101295 # Transaction distribution 274system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393956 # Packet count per connected master and slave (bytes) 275system.membus.pkt_count::total 393956 # Packet count per connected master and slave (bytes) 276system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15730368 # Cumulative packet size per connected master and slave (bytes) 277system.membus.tot_pkt_size::total 15730368 # Cumulative packet size per connected master and slave (bytes) 278system.membus.data_through_bus 15730368 # Total data (bytes) 279system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 280system.membus.reqLayer0.occupancy 1082435500 # Layer occupancy (ticks) 281system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 282system.membus.respLayer1.occupancy 1397409745 # Layer occupancy (ticks) 283system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 284system.cpu_clk_domain.clock 500 # Clock period in ticks 285system.cpu.branchPred.lookups 182802818 # Number of BP lookups 286system.cpu.branchPred.condPredicted 143112021 # Number of conditional branches predicted 287system.cpu.branchPred.condIncorrect 7267941 # Number of conditional branches incorrect 288system.cpu.branchPred.BTBLookups 93011295 # Number of BTB lookups 289system.cpu.branchPred.BTBHits 87213055 # Number of BTB hits 290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 291system.cpu.branchPred.BTBHitPct 93.766090 # BTB Hit Percentage 292system.cpu.branchPred.usedRAS 12678218 # Number of times the RAS was used to get a target. 293system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. 294system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 295system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 296system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 297system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 298system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 299system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 301system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 302system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 304system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 305system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 306system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 307system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 308system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 309system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 310system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 311system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 312system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 313system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 314system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 315system.cpu.dtb.inst_hits 0 # ITB inst hits 316system.cpu.dtb.inst_misses 0 # ITB inst misses 317system.cpu.dtb.read_hits 0 # DTB read hits 318system.cpu.dtb.read_misses 0 # DTB read misses 319system.cpu.dtb.write_hits 0 # DTB write hits 320system.cpu.dtb.write_misses 0 # DTB write misses 321system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 322system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 323system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 324system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 325system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 326system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 327system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 328system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 329system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 330system.cpu.dtb.read_accesses 0 # DTB read accesses 331system.cpu.dtb.write_accesses 0 # DTB write accesses 332system.cpu.dtb.inst_accesses 0 # ITB inst accesses 333system.cpu.dtb.hits 0 # DTB hits 334system.cpu.dtb.misses 0 # DTB misses 335system.cpu.dtb.accesses 0 # DTB accesses 336system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 337system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 338system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 339system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 340system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 341system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 343system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 344system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 346system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 347system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 348system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 349system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 350system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 351system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 352system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 353system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 354system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 355system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 356system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 357system.cpu.itb.inst_hits 0 # ITB inst hits 358system.cpu.itb.inst_misses 0 # ITB inst misses 359system.cpu.itb.read_hits 0 # DTB read hits 360system.cpu.itb.read_misses 0 # DTB read misses 361system.cpu.itb.write_hits 0 # DTB write hits 362system.cpu.itb.write_misses 0 # DTB write misses 363system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 364system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 365system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 366system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 367system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 368system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 369system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 370system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 371system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.itb.read_accesses 0 # DTB read accesses 373system.cpu.itb.write_accesses 0 # DTB write accesses 374system.cpu.itb.inst_accesses 0 # ITB inst accesses 375system.cpu.itb.hits 0 # DTB hits 376system.cpu.itb.misses 0 # DTB misses 377system.cpu.itb.accesses 0 # DTB accesses 378system.cpu.workload.num_syscalls 548 # Number of system calls 379system.cpu.numCycles 404850106 # number of cpu cycles simulated 380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 382system.cpu.fetch.icacheStallCycles 119389916 # Number of cycles fetch is stalled on an Icache miss 383system.cpu.fetch.Insts 761628718 # Number of instructions fetch has processed 384system.cpu.fetch.Branches 182802818 # Number of branches that fetch encountered 385system.cpu.fetch.predictedBranches 99891273 # Number of branches that fetch has predicted taken 386system.cpu.fetch.Cycles 170150143 # Number of cycles fetch has run and was not squashing or blocked 387system.cpu.fetch.SquashCycles 35691365 # Number of cycles fetch has spent squashing 388system.cpu.fetch.BlockedCycles 77449263 # Number of cycles fetch has spent blocked 389system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 390system.cpu.fetch.PendingTrapStallCycles 486 # Number of stall cycles due to pending traps 391system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 392system.cpu.fetch.CacheLines 114538694 # Number of cache lines fetched 393system.cpu.fetch.IcacheSquashes 2440341 # Number of outstanding Icache misses that were squashed 394system.cpu.fetch.rateDist::samples 394609388 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::mean 2.164838 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::stdev 2.986971 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::0 224471880 56.88% 56.88% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::1 14182431 3.59% 60.48% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::2 22892997 5.80% 66.28% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::3 22746730 5.76% 72.04% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::4 20891038 5.29% 77.34% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::5 11596009 2.94% 80.28% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::6 13056866 3.31% 83.59% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::7 12000205 3.04% 86.63% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::8 52771232 13.37% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::total 394609388 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.branchRate 0.451532 # Number of branch fetches per cycle 412system.cpu.fetch.rate 1.881261 # Number of inst fetches per cycle 413system.cpu.decode.IdleCycles 129090145 # Number of cycles decode is idle 414system.cpu.decode.BlockedCycles 72932890 # Number of cycles decode is blocked 415system.cpu.decode.RunCycles 158811519 # Number of cycles decode is running 416system.cpu.decode.UnblockCycles 6229483 # Number of cycles decode is unblocking 417system.cpu.decode.SquashCycles 27545351 # Number of cycles decode is squashing 418system.cpu.decode.BranchResolved 26129524 # Number of times decode resolved a branch 419system.cpu.decode.BranchMispred 76858 # Number of times decode detected a branch misprediction 420system.cpu.decode.DecodedInsts 825625828 # Number of instructions handled by decode 421system.cpu.decode.SquashedInsts 295316 # Number of squashed instructions handled by decode 422system.cpu.rename.SquashCycles 27545351 # Number of cycles rename is squashing 423system.cpu.rename.IdleCycles 135687065 # Number of cycles rename is idle 424system.cpu.rename.BlockCycles 10105791 # Number of cycles rename is blocking 425system.cpu.rename.serializeStallCycles 47805401 # count of cycles rename stalled for serializing inst 426system.cpu.rename.RunCycles 158260364 # Number of cycles rename is running 427system.cpu.rename.UnblockCycles 15205416 # Number of cycles rename is unblocking 428system.cpu.rename.RenamedInsts 800656323 # Number of instructions processed by rename 429system.cpu.rename.ROBFullEvents 1334 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 3053839 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LSQFullEvents 8954907 # Number of times rename has blocked due to LSQ full 432system.cpu.rename.FullRegisterEvents 385 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 954272169 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 3518760229 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 3237464445 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed 438system.cpu.rename.UndoneMaps 288019878 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 2292922 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 2292918 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 41836509 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 170268509 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 73501316 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 28634884 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 15888043 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 755077640 # Number of instructions added to the IQ (excludes non-spec) 447system.cpu.iq.iqNonSpecInstsAdded 3775313 # Number of non-speculative instructions added to the IQ 448system.cpu.iq.iqInstsIssued 665327015 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 1386285 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 187386746 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 479953007 # Number of squashed operands that are examined and possibly removed from graph 452system.cpu.iq.iqSquashedNonSpecRemoved 797681 # Number of squashed non-spec instructions that were removed 453system.cpu.iq.issued_per_cycle::samples 394609388 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 1.686039 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.735073 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::0 139096453 35.25% 35.25% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 69938770 17.72% 52.97% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 71532009 18.13% 71.10% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 53395901 13.53% 84.63% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 31139583 7.89% 92.52% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 15999118 4.05% 96.58% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 8786717 2.23% 98.80% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 2904396 0.74% 99.54% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 1816441 0.46% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::total 394609388 # Number of insts issued each cycle 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntAlu 479561 5.00% 5.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 6536466 68.14% 73.13% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 2577260 26.87% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 505system.cpu.iq.FU_type_0::IntAlu 447787138 67.30% 67.30% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 383414 0.06% 67.36% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 153368040 23.05% 90.41% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 63788326 9.59% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::total 665327015 # Type of FU issued 539system.cpu.iq.rate 1.643391 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 9593287 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.014419 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 1736242767 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 947046337 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 646056325 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 674920189 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 8551877 # Number of loads that had data forwarded from stores 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 552system.cpu.iew.lsq.thread0.squashedLoads 44238954 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 41472 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 810610 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 16640839 # Number of stores squashed 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 558system.cpu.iew.lsq.thread0.rescheduledLoads 19493 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 7969 # Number of times an access to memory failed due to the cache being blocked 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 561system.cpu.iew.iewSquashCycles 27545351 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 5256121 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 385567 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 760412013 # Number of instructions dispatched to IQ 565system.cpu.iew.iewDispSquashedInsts 1120947 # Number of squashed instructions skipped by dispatch 566system.cpu.iew.iewDispLoadInsts 170268509 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 73501316 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 2286771 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 219704 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 12090 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 810610 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 4341838 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 4001214 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 8343052 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 655907838 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 150084771 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 9419177 # Number of squashed instructions skipped in execute 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 1559060 # number of nop insts executed 580system.cpu.iew.exec_refs 212583673 # number of memory reference insts executed 581system.cpu.iew.exec_branches 138498504 # Number of branches executed 582system.cpu.iew.exec_stores 62498902 # Number of stores executed 583system.cpu.iew.exec_rate 1.620125 # Inst execution rate 584system.cpu.iew.wb_sent 651026464 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 646056341 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 374698942 # num instructions producing a value 587system.cpu.iew.wb_consumers 646299992 # num instructions consuming a value 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 589system.cpu.iew.wb_rate 1.595791 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 592system.cpu.commit.commitSquashedInsts 189472037 # The number of squashed insts skipped by commit 593system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 7193780 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 367064037 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.555500 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.230573 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::0 159337830 43.41% 43.41% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 98602437 26.86% 70.27% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 33803348 9.21% 79.48% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 18720540 5.10% 84.58% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 16173781 4.41% 88.99% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 7454535 2.03% 91.02% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 6985415 1.90% 92.92% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 3172083 0.86% 93.78% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 22814068 6.22% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::total 367064037 # Number of insts commited each cycle 612system.cpu.commit.committedInsts 506581607 # Number of instructions committed 613system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 182890032 # Number of memory references committed 616system.cpu.commit.loads 126029555 # Number of loads committed 617system.cpu.commit.membars 1488542 # Number of memory barriers committed 618system.cpu.commit.branches 121548301 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 620system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 621system.cpu.commit.function_calls 9757362 # Number of function calls committed. 622system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 623system.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction 624system.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction 625system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction 626system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction 627system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction 657system.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 659system.cpu.rob.rob_reads 1104683035 # The number of ROB reads 660system.cpu.rob.rob_writes 1548546574 # The number of ROB writes 661system.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling 663system.cpu.committedInsts 505237723 # Number of Instructions Simulated 664system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 665system.cpu.cpi 0.801306 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads 667system.cpu.ipc 1.247962 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 3058680468 # number of integer regfile reads 670system.cpu.int_regfile_writes 751974394 # number of integer regfile writes 671system.cpu.fp_regfile_reads 16 # number of floating regfile reads 672system.cpu.misc_regfile_reads 237852228 # number of misc regfile reads 673system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 674system.cpu.toL2Bus.throughput 734945552 # Throughput (bytes/s) 675system.cpu.toL2Bus.trans_dist::ReadReq 864760 # Transaction distribution 676system.cpu.toL2Bus.trans_dist::ReadResp 864758 # Transaction distribution 677system.cpu.toL2Bus.trans_dist::Writeback 1110914 # Transaction distribution 678system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution 679system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::ReadExReq 348881 # Transaction distribution 681system.cpu.toL2Bus.trans_dist::ReadExResp 348881 # Transaction distribution 682system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33826 # Packet count per connected master and slave (bytes) 683system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504415 # Packet count per connected master and slave (bytes) 684system.cpu.toL2Bus.pkt_count::total 3538241 # Packet count per connected master and slave (bytes) 685system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079872 # Cumulative packet size per connected master and slave (bytes) 686system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147686464 # Cumulative packet size per connected master and slave (bytes) 687system.cpu.toL2Bus.tot_pkt_size::total 148766336 # Cumulative packet size per connected master and slave (bytes) 688system.cpu.toL2Bus.data_through_bus 148766336 # Total data (bytes) 689system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) 690system.cpu.toL2Bus.reqLayer0.occupancy 2273224996 # Layer occupancy (ticks) 691system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 692system.cpu.toL2Bus.respLayer0.occupancy 26000486 # Layer occupancy (ticks) 693system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 694system.cpu.toL2Bus.respLayer1.occupancy 1824563475 # Layer occupancy (ticks) 695system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 696system.cpu.icache.tags.replacements 15031 # number of replacements 697system.cpu.icache.tags.tagsinuse 1100.518238 # Cycle average of tags in use 698system.cpu.icache.tags.total_refs 114517542 # Total number of references to valid blocks. 699system.cpu.icache.tags.sampled_refs 16885 # Sample count of references to valid blocks. 700system.cpu.icache.tags.avg_refs 6782.205626 # Average number of references to valid blocks. 701system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 702system.cpu.icache.tags.occ_blocks::cpu.inst 1100.518238 # Average occupied blocks per requestor 703system.cpu.icache.tags.occ_percent::cpu.inst 0.537362 # Average percentage of cache occupancy 704system.cpu.icache.tags.occ_percent::total 0.537362 # Average percentage of cache occupancy 705system.cpu.icache.tags.occ_task_id_blocks::1024 1854 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 707system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 709system.cpu.icache.tags.age_task_id_blocks_1024::3 292 # Occupied blocks per task id 710system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id 711system.cpu.icache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id 712system.cpu.icache.tags.tag_accesses 229094338 # Number of tag accesses 713system.cpu.icache.tags.data_accesses 229094338 # Number of data accesses 714system.cpu.icache.ReadReq_hits::cpu.inst 114517542 # number of ReadReq hits 715system.cpu.icache.ReadReq_hits::total 114517542 # number of ReadReq hits 716system.cpu.icache.demand_hits::cpu.inst 114517542 # number of demand (read+write) hits 717system.cpu.icache.demand_hits::total 114517542 # number of demand (read+write) hits 718system.cpu.icache.overall_hits::cpu.inst 114517542 # number of overall hits 719system.cpu.icache.overall_hits::total 114517542 # number of overall hits 720system.cpu.icache.ReadReq_misses::cpu.inst 21151 # number of ReadReq misses 721system.cpu.icache.ReadReq_misses::total 21151 # number of ReadReq misses 722system.cpu.icache.demand_misses::cpu.inst 21151 # number of demand (read+write) misses 723system.cpu.icache.demand_misses::total 21151 # number of demand (read+write) misses 724system.cpu.icache.overall_misses::cpu.inst 21151 # number of overall misses 725system.cpu.icache.overall_misses::total 21151 # number of overall misses 726system.cpu.icache.ReadReq_miss_latency::cpu.inst 554005735 # number of ReadReq miss cycles 727system.cpu.icache.ReadReq_miss_latency::total 554005735 # number of ReadReq miss cycles 728system.cpu.icache.demand_miss_latency::cpu.inst 554005735 # number of demand (read+write) miss cycles 729system.cpu.icache.demand_miss_latency::total 554005735 # number of demand (read+write) miss cycles 730system.cpu.icache.overall_miss_latency::cpu.inst 554005735 # number of overall miss cycles 731system.cpu.icache.overall_miss_latency::total 554005735 # number of overall miss cycles 732system.cpu.icache.ReadReq_accesses::cpu.inst 114538693 # number of ReadReq accesses(hits+misses) 733system.cpu.icache.ReadReq_accesses::total 114538693 # number of ReadReq accesses(hits+misses) 734system.cpu.icache.demand_accesses::cpu.inst 114538693 # number of demand (read+write) accesses 735system.cpu.icache.demand_accesses::total 114538693 # number of demand (read+write) accesses 736system.cpu.icache.overall_accesses::cpu.inst 114538693 # number of overall (read+write) accesses 737system.cpu.icache.overall_accesses::total 114538693 # number of overall (read+write) accesses 738system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses 739system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses 740system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses 741system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses 742system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses 743system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses 744system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152 # average ReadReq miss latency 745system.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152 # average ReadReq miss latency 746system.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency 747system.cpu.icache.demand_avg_miss_latency::total 26192.886152 # average overall miss latency 748system.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::total 26192.886152 # average overall miss latency 750system.cpu.icache.blocked_cycles::no_mshrs 775 # number of cycles access was blocked 751system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked 753system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.icache.avg_blocked_cycles::no_mshrs 51.666667 # average number of cycles each access was blocked 755system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.icache.fast_writes 0 # number of fast writes performed 757system.cpu.icache.cache_copies 0 # number of cache copies performed 758system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4198 # number of ReadReq MSHR hits 759system.cpu.icache.ReadReq_mshr_hits::total 4198 # number of ReadReq MSHR hits 760system.cpu.icache.demand_mshr_hits::cpu.inst 4198 # number of demand (read+write) MSHR hits 761system.cpu.icache.demand_mshr_hits::total 4198 # number of demand (read+write) MSHR hits 762system.cpu.icache.overall_mshr_hits::cpu.inst 4198 # number of overall MSHR hits 763system.cpu.icache.overall_mshr_hits::total 4198 # number of overall MSHR hits 764system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16953 # number of ReadReq MSHR misses 765system.cpu.icache.ReadReq_mshr_misses::total 16953 # number of ReadReq MSHR misses 766system.cpu.icache.demand_mshr_misses::cpu.inst 16953 # number of demand (read+write) MSHR misses 767system.cpu.icache.demand_mshr_misses::total 16953 # number of demand (read+write) MSHR misses 768system.cpu.icache.overall_mshr_misses::cpu.inst 16953 # number of overall MSHR misses 769system.cpu.icache.overall_mshr_misses::total 16953 # number of overall MSHR misses 770system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401201263 # number of ReadReq MSHR miss cycles 771system.cpu.icache.ReadReq_mshr_miss_latency::total 401201263 # number of ReadReq MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401201263 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::total 401201263 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401201263 # number of overall MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::total 401201263 # number of overall MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 777system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 778system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 779system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 780system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 781system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses 782system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.502448 # average ReadReq mshr miss latency 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.502448 # average ReadReq mshr miss latency 784system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency 786system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency 788system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 789system.cpu.l2cache.tags.replacements 115416 # number of replacements 790system.cpu.l2cache.tags.tagsinuse 27085.834103 # Cycle average of tags in use 791system.cpu.l2cache.tags.total_refs 1781268 # Total number of references to valid blocks. 792system.cpu.l2cache.tags.sampled_refs 146665 # Sample count of references to valid blocks. 793system.cpu.l2cache.tags.avg_refs 12.145147 # Average number of references to valid blocks. 794system.cpu.l2cache.tags.warmup_cycle 89916309500 # Cycle when the warmup percentage was hit. 795system.cpu.l2cache.tags.occ_blocks::writebacks 23017.620858 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 361.438946 # Average occupied blocks per requestor 797system.cpu.l2cache.tags.occ_blocks::cpu.data 3706.774299 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_percent::writebacks 0.702442 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011030 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.113122 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.826594 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 31249 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7681 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21304 # Occupied blocks per task id 807system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id 808system.cpu.l2cache.tags.tag_accesses 19091917 # Number of tag accesses 809system.cpu.l2cache.tags.data_accesses 19091917 # Number of data accesses 810system.cpu.l2cache.ReadReq_hits::cpu.inst 13492 # number of ReadReq hits 811system.cpu.l2cache.ReadReq_hits::cpu.data 804297 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::total 817789 # number of ReadReq hits 813system.cpu.l2cache.Writeback_hits::writebacks 1110914 # number of Writeback hits 814system.cpu.l2cache.Writeback_hits::total 1110914 # number of Writeback hits 815system.cpu.l2cache.UpgradeReq_hits::cpu.data 59 # number of UpgradeReq hits 816system.cpu.l2cache.UpgradeReq_hits::total 59 # number of UpgradeReq hits 817system.cpu.l2cache.ReadExReq_hits::cpu.data 247585 # number of ReadExReq hits 818system.cpu.l2cache.ReadExReq_hits::total 247585 # number of ReadExReq hits 819system.cpu.l2cache.demand_hits::cpu.inst 13492 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.data 1051882 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::total 1065374 # number of demand (read+write) hits 822system.cpu.l2cache.overall_hits::cpu.inst 13492 # number of overall hits 823system.cpu.l2cache.overall_hits::cpu.data 1051882 # number of overall hits 824system.cpu.l2cache.overall_hits::total 1065374 # number of overall hits 825system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses 826system.cpu.l2cache.ReadReq_misses::cpu.data 43510 # number of ReadReq misses 827system.cpu.l2cache.ReadReq_misses::total 46892 # number of ReadReq misses 828system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 829system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 830system.cpu.l2cache.ReadExReq_misses::cpu.data 101296 # number of ReadExReq misses 831system.cpu.l2cache.ReadExReq_misses::total 101296 # number of ReadExReq misses 832system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses 833system.cpu.l2cache.demand_misses::cpu.data 144806 # number of demand (read+write) misses 834system.cpu.l2cache.demand_misses::total 148188 # number of demand (read+write) misses 835system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses 836system.cpu.l2cache.overall_misses::cpu.data 144806 # number of overall misses 837system.cpu.l2cache.overall_misses::total 148188 # number of overall misses 838system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248983750 # number of ReadReq miss cycles 839system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3325064500 # number of ReadReq miss cycles 840system.cpu.l2cache.ReadReq_miss_latency::total 3574048250 # number of ReadReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7369870249 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 7369870249 # number of ReadExReq miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.inst 248983750 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.data 10694934749 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 10943918499 # number of demand (read+write) miss cycles 846system.cpu.l2cache.overall_miss_latency::cpu.inst 248983750 # number of overall miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.data 10694934749 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::total 10943918499 # number of overall miss cycles 849system.cpu.l2cache.ReadReq_accesses::cpu.inst 16874 # number of ReadReq accesses(hits+misses) 850system.cpu.l2cache.ReadReq_accesses::cpu.data 847807 # number of ReadReq accesses(hits+misses) 851system.cpu.l2cache.ReadReq_accesses::total 864681 # number of ReadReq accesses(hits+misses) 852system.cpu.l2cache.Writeback_accesses::writebacks 1110914 # number of Writeback accesses(hits+misses) 853system.cpu.l2cache.Writeback_accesses::total 1110914 # number of Writeback accesses(hits+misses) 854system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) 855system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::cpu.data 348881 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadExReq_accesses::total 348881 # number of ReadExReq accesses(hits+misses) 858system.cpu.l2cache.demand_accesses::cpu.inst 16874 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.data 1196688 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::total 1213562 # number of demand (read+write) accesses 861system.cpu.l2cache.overall_accesses::cpu.inst 16874 # number of overall (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.data 1196688 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::total 1213562 # number of overall (read+write) accesses 864system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200427 # miss rate for ReadReq accesses 865system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051321 # miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_miss_rate::total 0.054230 # miss rate for ReadReq accesses 867system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.063492 # miss rate for UpgradeReq accesses 868system.cpu.l2cache.UpgradeReq_miss_rate::total 0.063492 # miss rate for UpgradeReq accesses 869system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290345 # miss rate for ReadExReq accesses 870system.cpu.l2cache.ReadExReq_miss_rate::total 0.290345 # miss rate for ReadExReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200427 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 0.121006 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.122110 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200427 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 0.121006 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.122110 # miss rate for overall accesses 877system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73620.269072 # average ReadReq miss latency 878system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76420.696392 # average ReadReq miss latency 879system.cpu.l2cache.ReadReq_avg_miss_latency::total 76218.720677 # average ReadReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72755.787484 # average ReadExReq miss latency 881system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72755.787484 # average ReadExReq miss latency 882system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::total 73851.583792 # average overall miss latency 885system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::total 73851.583792 # average overall miss latency 888system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 889system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 892system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 894system.cpu.l2cache.fast_writes 0 # number of fast writes performed 895system.cpu.l2cache.cache_copies 0 # number of cache copies performed 896system.cpu.l2cache.writebacks::writebacks 97630 # number of writebacks 897system.cpu.l2cache.writebacks::total 97630 # number of writebacks 898system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 899system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 900system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 901system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 902system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits 903system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 904system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 905system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits 906system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits 907system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses 908system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43486 # number of ReadReq MSHR misses 909system.cpu.l2cache.ReadReq_mshr_misses::total 46864 # number of ReadReq MSHR misses 910system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses 911system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses 912system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101296 # number of ReadExReq MSHR misses 913system.cpu.l2cache.ReadExReq_mshr_misses::total 101296 # number of ReadExReq MSHR misses 914system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses 915system.cpu.l2cache.demand_mshr_misses::cpu.data 144782 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.demand_mshr_misses::total 148160 # number of demand (read+write) MSHR misses 917system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses 918system.cpu.l2cache.overall_mshr_misses::cpu.data 144782 # number of overall MSHR misses 919system.cpu.l2cache.overall_mshr_misses::total 148160 # number of overall MSHR misses 920system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 206192500 # number of ReadReq MSHR miss cycles 921system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2779400500 # number of ReadReq MSHR miss cycles 922system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2985593000 # number of ReadReq MSHR miss cycles 923system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 40004 # number of UpgradeReq MSHR miss cycles 924system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 40004 # number of UpgradeReq MSHR miss cycles 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6084575751 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6084575751 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206192500 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8863976251 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.demand_mshr_miss_latency::total 9070168751 # number of demand (read+write) MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206192500 # number of overall MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8863976251 # number of overall MSHR miss cycles 932system.cpu.l2cache.overall_mshr_miss_latency::total 9070168751 # number of overall MSHR miss cycles 933system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for ReadReq accesses 934system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051292 # mshr miss rate for ReadReq accesses 935system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054198 # mshr miss rate for ReadReq accesses 936system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for UpgradeReq accesses 937system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.063492 # mshr miss rate for UpgradeReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses 940system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for demand accesses 941system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses 942system.cpu.l2cache.demand_mshr_miss_rate::total 0.122087 # mshr miss rate for demand accesses 943system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for overall accesses 944system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses 945system.cpu.l2cache.overall_mshr_miss_rate::total 0.122087 # mshr miss rate for overall accesses 946system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61039.816459 # average ReadReq mshr miss latency 947system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63914.834659 # average ReadReq mshr miss latency 948system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.600717 # average ReadReq mshr miss latency 949system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 950system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 951system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60067.285490 # average ReadExReq mshr miss latency 952system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60067.285490 # average ReadExReq mshr miss latency 953system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency 954system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency 956system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency 957system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency 959system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 960system.cpu.dcache.tags.replacements 1192591 # number of replacements 961system.cpu.dcache.tags.tagsinuse 4057.481628 # Cycle average of tags in use 962system.cpu.dcache.tags.total_refs 190175522 # Total number of references to valid blocks. 963system.cpu.dcache.tags.sampled_refs 1196687 # Sample count of references to valid blocks. 964system.cpu.dcache.tags.avg_refs 158.918349 # Average number of references to valid blocks. 965system.cpu.dcache.tags.warmup_cycle 4252802250 # Cycle when the warmup percentage was hit. 966system.cpu.dcache.tags.occ_blocks::cpu.data 4057.481628 # Average occupied blocks per requestor 967system.cpu.dcache.tags.occ_percent::cpu.data 0.990596 # Average percentage of cache occupancy 968system.cpu.dcache.tags.occ_percent::total 0.990596 # Average percentage of cache occupancy 969system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 970system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 971system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 972system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id 973system.cpu.dcache.tags.age_task_id_blocks_1024::3 1688 # Occupied blocks per task id 974system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 975system.cpu.dcache.tags.tag_accesses 391451119 # Number of tag accesses 976system.cpu.dcache.tags.data_accesses 391451119 # Number of data accesses 977system.cpu.dcache.ReadReq_hits::cpu.data 136209146 # number of ReadReq hits 978system.cpu.dcache.ReadReq_hits::total 136209146 # number of ReadReq hits 979system.cpu.dcache.WriteReq_hits::cpu.data 50988846 # number of WriteReq hits 980system.cpu.dcache.WriteReq_hits::total 50988846 # number of WriteReq hits 981system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488796 # number of LoadLockedReq hits 982system.cpu.dcache.LoadLockedReq_hits::total 1488796 # number of LoadLockedReq hits 983system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 984system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 985system.cpu.dcache.demand_hits::cpu.data 187197992 # number of demand (read+write) hits 986system.cpu.dcache.demand_hits::total 187197992 # number of demand (read+write) hits 987system.cpu.dcache.overall_hits::cpu.data 187197992 # number of overall hits 988system.cpu.dcache.overall_hits::total 187197992 # number of overall hits 989system.cpu.dcache.ReadReq_misses::cpu.data 1701390 # number of ReadReq misses 990system.cpu.dcache.ReadReq_misses::total 1701390 # number of ReadReq misses 991system.cpu.dcache.WriteReq_misses::cpu.data 3250460 # number of WriteReq misses 992system.cpu.dcache.WriteReq_misses::total 3250460 # number of WriteReq misses 993system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses 994system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses 995system.cpu.dcache.demand_misses::cpu.data 4951850 # number of demand (read+write) misses 996system.cpu.dcache.demand_misses::total 4951850 # number of demand (read+write) misses 997system.cpu.dcache.overall_misses::cpu.data 4951850 # number of overall misses 998system.cpu.dcache.overall_misses::total 4951850 # number of overall misses 999system.cpu.dcache.ReadReq_miss_latency::cpu.data 29115477457 # number of ReadReq miss cycles 1000system.cpu.dcache.ReadReq_miss_latency::total 29115477457 # number of ReadReq miss cycles 1001system.cpu.dcache.WriteReq_miss_latency::cpu.data 71211038449 # number of WriteReq miss cycles 1002system.cpu.dcache.WriteReq_miss_latency::total 71211038449 # number of WriteReq miss cycles 1003system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles 1004system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles 1005system.cpu.dcache.demand_miss_latency::cpu.data 100326515906 # number of demand (read+write) miss cycles 1006system.cpu.dcache.demand_miss_latency::total 100326515906 # number of demand (read+write) miss cycles 1007system.cpu.dcache.overall_miss_latency::cpu.data 100326515906 # number of overall miss cycles 1008system.cpu.dcache.overall_miss_latency::total 100326515906 # number of overall miss cycles 1009system.cpu.dcache.ReadReq_accesses::cpu.data 137910536 # number of ReadReq accesses(hits+misses) 1010system.cpu.dcache.ReadReq_accesses::total 137910536 # number of ReadReq accesses(hits+misses) 1011system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 1012system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 1013system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488833 # number of LoadLockedReq accesses(hits+misses) 1014system.cpu.dcache.LoadLockedReq_accesses::total 1488833 # number of LoadLockedReq accesses(hits+misses) 1015system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 1016system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 1017system.cpu.dcache.demand_accesses::cpu.data 192149842 # number of demand (read+write) accesses 1018system.cpu.dcache.demand_accesses::total 192149842 # number of demand (read+write) accesses 1019system.cpu.dcache.overall_accesses::cpu.data 192149842 # number of overall (read+write) accesses 1020system.cpu.dcache.overall_accesses::total 192149842 # number of overall (read+write) accesses 1021system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012337 # miss rate for ReadReq accesses 1022system.cpu.dcache.ReadReq_miss_rate::total 0.012337 # miss rate for ReadReq accesses 1023system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059928 # miss rate for WriteReq accesses 1024system.cpu.dcache.WriteReq_miss_rate::total 0.059928 # miss rate for WriteReq accesses 1025system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses 1026system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses 1027system.cpu.dcache.demand_miss_rate::cpu.data 0.025771 # miss rate for demand accesses 1028system.cpu.dcache.demand_miss_rate::total 0.025771 # miss rate for demand accesses 1029system.cpu.dcache.overall_miss_rate::cpu.data 0.025771 # miss rate for overall accesses 1030system.cpu.dcache.overall_miss_rate::total 0.025771 # miss rate for overall accesses 1031system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248 # average ReadReq miss latency 1032system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248 # average ReadReq miss latency 1033system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931 # average WriteReq miss latency 1034system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931 # average WriteReq miss latency 1035system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency 1036system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency 1037system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency 1038system.cpu.dcache.demand_avg_miss_latency::total 20260.410939 # average overall miss latency 1039system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency 1040system.cpu.dcache.overall_avg_miss_latency::total 20260.410939 # average overall miss latency 1041system.cpu.dcache.blocked_cycles::no_mshrs 17276 # number of cycles access was blocked 1042system.cpu.dcache.blocked_cycles::no_targets 49920 # number of cycles access was blocked 1043system.cpu.dcache.blocked::no_mshrs 1691 # number of cycles access was blocked 1044system.cpu.dcache.blocked::no_targets 664 # number of cycles access was blocked 1045system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.216440 # average number of cycles each access was blocked 1046system.cpu.dcache.avg_blocked_cycles::no_targets 75.180723 # average number of cycles each access was blocked 1047system.cpu.dcache.fast_writes 0 # number of fast writes performed 1048system.cpu.dcache.cache_copies 0 # number of cache copies performed 1049system.cpu.dcache.writebacks::writebacks 1110914 # number of writebacks 1050system.cpu.dcache.writebacks::total 1110914 # number of writebacks 1051system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853047 # number of ReadReq MSHR hits 1052system.cpu.dcache.ReadReq_mshr_hits::total 853047 # number of ReadReq MSHR hits 1053system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902052 # number of WriteReq MSHR hits 1054system.cpu.dcache.WriteReq_mshr_hits::total 2902052 # number of WriteReq MSHR hits 1055system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits 1056system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits 1057system.cpu.dcache.demand_mshr_hits::cpu.data 3755099 # number of demand (read+write) MSHR hits 1058system.cpu.dcache.demand_mshr_hits::total 3755099 # number of demand (read+write) MSHR hits 1059system.cpu.dcache.overall_mshr_hits::cpu.data 3755099 # number of overall MSHR hits 1060system.cpu.dcache.overall_mshr_hits::total 3755099 # number of overall MSHR hits 1061system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848343 # number of ReadReq MSHR misses 1062system.cpu.dcache.ReadReq_mshr_misses::total 848343 # number of ReadReq MSHR misses 1063system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348408 # number of WriteReq MSHR misses 1064system.cpu.dcache.WriteReq_mshr_misses::total 348408 # number of WriteReq MSHR misses 1065system.cpu.dcache.demand_mshr_misses::cpu.data 1196751 # number of demand (read+write) MSHR misses 1066system.cpu.dcache.demand_mshr_misses::total 1196751 # number of demand (read+write) MSHR misses 1067system.cpu.dcache.overall_mshr_misses::cpu.data 1196751 # number of overall MSHR misses 1068system.cpu.dcache.overall_mshr_misses::total 1196751 # number of overall MSHR misses 1069system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12254549779 # number of ReadReq MSHR miss cycles 1070system.cpu.dcache.ReadReq_mshr_miss_latency::total 12254549779 # number of ReadReq MSHR miss cycles 1071system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10243730741 # number of WriteReq MSHR miss cycles 1072system.cpu.dcache.WriteReq_mshr_miss_latency::total 10243730741 # number of WriteReq MSHR miss cycles 1073system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22498280520 # number of demand (read+write) MSHR miss cycles 1074system.cpu.dcache.demand_mshr_miss_latency::total 22498280520 # number of demand (read+write) MSHR miss cycles 1075system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22498280520 # number of overall MSHR miss cycles 1076system.cpu.dcache.overall_mshr_miss_latency::total 22498280520 # number of overall MSHR miss cycles 1077system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses 1078system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses 1079system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses 1080system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 1081system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses 1082system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses 1083system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses 1084system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses 1085system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180 # average ReadReq mshr miss latency 1086system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180 # average ReadReq mshr miss latency 1087system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109 # average WriteReq mshr miss latency 1088system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109 # average WriteReq mshr miss latency 1089system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency 1090system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency 1091system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency 1092system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency 1093system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1094 1095---------- End Simulation Statistics ---------- 1096