stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202742 # Number of seconds simulated 4sim_ticks 202741893000 # Number of ticks simulated 5final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 148118 # Simulator instruction rate (inst/s) 8host_op_rate 166994 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59436990 # Simulator tick rate (ticks/s) 10host_mem_usage 253144 # Number of bytes of host memory used 11host_seconds 3411.04 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 148209 # Number of read requests accepted 40system.physmem.writeReqs 97655 # Number of write requests accepted 41system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9585 # Per bank write bursts 52system.physmem.perBankRdBursts::1 9243 # Per bank write bursts 53system.physmem.perBankRdBursts::2 9257 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8972 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9761 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9639 # Per bank write bursts 57system.physmem.perBankRdBursts::6 9125 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8321 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8799 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8911 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8951 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9736 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9644 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9766 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8945 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9461 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6262 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6160 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6087 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5881 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6253 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6276 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6048 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5555 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5811 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5907 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5994 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6518 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6370 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6328 # Per bank write bursts 81system.physmem.perBankWrBursts::14 6055 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6145 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 202741873000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 148209 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 97655 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see 164system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation 249system.physmem.totQLat 1735354000 # Total ticks spent queuing 250system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM 251system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers 252system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks 253system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst 254system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 256system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 0.61 # Data bus utilization in percentage 263system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing 266system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing 267system.physmem.readRowHits 118629 # Number of row buffer hits during reads 268system.physmem.writeRowHits 57942 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes 271system.physmem.avgGap 824609.84 # Average gap between requests 272system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined 273system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state 274system.membus.throughput 77612139 # Throughput (bytes/s) 275system.membus.trans_dist::ReadReq 46927 # Transaction distribution 276system.membus.trans_dist::ReadResp 46926 # Transaction distribution 277system.membus.trans_dist::Writeback 97655 # Transaction distribution 278system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 279system.membus.trans_dist::UpgradeResp 9 # Transaction distribution 280system.membus.trans_dist::ReadExReq 101282 # Transaction distribution 281system.membus.trans_dist::ReadExResp 101282 # Transaction distribution 282system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) 283system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) 284system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) 285system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) 286system.membus.data_through_bus 15735232 # Total data (bytes) 287system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 288system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) 289system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 290system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) 291system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 292system.cpu_clk_domain.clock 500 # Clock period in ticks 293system.cpu.branchPred.lookups 182821881 # Number of BP lookups 294system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 299system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. 302system.cpu.dtb.inst_hits 0 # ITB inst hits 303system.cpu.dtb.inst_misses 0 # ITB inst misses 304system.cpu.dtb.read_hits 0 # DTB read hits 305system.cpu.dtb.read_misses 0 # DTB read misses 306system.cpu.dtb.write_hits 0 # DTB write hits 307system.cpu.dtb.write_misses 0 # DTB write misses 308system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 309system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 310system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 311system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 312system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 313system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 314system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 315system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 316system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 317system.cpu.dtb.read_accesses 0 # DTB read accesses 318system.cpu.dtb.write_accesses 0 # DTB write accesses 319system.cpu.dtb.inst_accesses 0 # ITB inst accesses 320system.cpu.dtb.hits 0 # DTB hits 321system.cpu.dtb.misses 0 # DTB misses 322system.cpu.dtb.accesses 0 # DTB accesses 323system.cpu.itb.inst_hits 0 # ITB inst hits 324system.cpu.itb.inst_misses 0 # ITB inst misses 325system.cpu.itb.read_hits 0 # DTB read hits 326system.cpu.itb.read_misses 0 # DTB read misses 327system.cpu.itb.write_hits 0 # DTB write hits 328system.cpu.itb.write_misses 0 # DTB write misses 329system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 330system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 331system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 332system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 333system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 334system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 335system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 336system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_accesses 0 # DTB write accesses 340system.cpu.itb.inst_accesses 0 # ITB inst accesses 341system.cpu.itb.hits 0 # DTB hits 342system.cpu.itb.misses 0 # DTB misses 343system.cpu.itb.accesses 0 # DTB accesses 344system.cpu.workload.num_syscalls 548 # Number of system calls 345system.cpu.numCycles 405483787 # number of cpu cycles simulated 346system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 347system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 348system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss 349system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed 350system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered 351system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken 352system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked 353system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing 354system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked 355system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 356system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps 357system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR 358system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched 359system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed 360system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle 378system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle 379system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle 380system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked 381system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running 382system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking 383system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing 384system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch 385system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction 386system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode 387system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode 388system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing 389system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle 390system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking 391system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst 392system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running 393system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking 394system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename 395system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full 396system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full 397system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full 398system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers 399system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed 400system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made 401system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups 402system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups 403system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed 404system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing 405system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed 406system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed 407system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer 408system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. 409system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. 410system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. 411system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. 412system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) 413system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ 414system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued 415system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued 416system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling 417system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph 418system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed 419system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle 436system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available 438system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available 439system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available 466system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available 467system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 469system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 470system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 471system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued 472system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued 473system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued 500system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued 501system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 503system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 504system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued 505system.cpu.iq.rate 1.640858 # Inst issue rate 506system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested 507system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) 508system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads 509system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes 510system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses 511system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads 512system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 513system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 514system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses 515system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses 516system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores 517system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 518system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed 519system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed 520system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations 521system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed 522system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 523system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 524system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled 525system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked 526system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 527system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing 528system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking 529system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking 530system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ 531system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch 532system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions 533system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions 534system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions 535system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall 536system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall 537system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations 538system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly 539system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly 540system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute 541system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions 542system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed 543system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute 544system.cpu.iew.exec_swp 0 # number of swp insts executed 545system.cpu.iew.exec_nop 1558919 # number of nop insts executed 546system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed 547system.cpu.iew.exec_branches 138505177 # Number of branches executed 548system.cpu.iew.exec_stores 62475461 # Number of stores executed 549system.cpu.iew.exec_rate 1.617619 # Inst execution rate 550system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit 551system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back 552system.cpu.iew.wb_producers 374710129 # num instructions producing a value 553system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value 554system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 555system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle 556system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back 557system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 558system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit 559system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 560system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted 561system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle 578system.cpu.commit.committedInsts 506581607 # Number of instructions committed 579system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 580system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 581system.cpu.commit.refs 182890032 # Number of memory references committed 582system.cpu.commit.loads 126029555 # Number of loads committed 583system.cpu.commit.membars 1488542 # Number of memory barriers committed 584system.cpu.commit.branches 121548301 # Number of branches committed 585system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 586system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 587system.cpu.commit.function_calls 9757362 # Number of function calls committed. 588system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached 589system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 590system.cpu.rob.rob_reads 1104828701 # The number of ROB reads 591system.cpu.rob.rob_writes 1548619548 # The number of ROB writes 592system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself 593system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling 594system.cpu.committedInsts 505237723 # Number of Instructions Simulated 595system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 596system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated 597system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction 598system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads 599system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle 600system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads 601system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads 602system.cpu.int_regfile_writes 752019512 # number of integer regfile writes 603system.cpu.fp_regfile_reads 16 # number of floating regfile reads 604system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads 605system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 606system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) 607system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution 614system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) 619system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) 620system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) 621system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) 622system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) 623system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 624system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) 625system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 626system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) 627system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 628system.cpu.icache.tags.replacements 15017 # number of replacements 629system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use 630system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. 631system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. 632system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. 633system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 634system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor 635system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy 636system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy 637system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id 638system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 639system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 640system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 641system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id 642system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id 643system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id 644system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses 645system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses 646system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits 647system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits 648system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits 649system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits 650system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits 651system.cpu.icache.overall_hits::total 114523215 # number of overall hits 652system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses 653system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses 654system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses 655system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses 656system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses 657system.cpu.icache.overall_misses::total 21116 # number of overall misses 658system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles 659system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles 660system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles 661system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles 662system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles 663system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles 664system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) 665system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) 666system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses 667system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses 668system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses 669system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses 670system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses 671system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses 672system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses 673system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses 674system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses 675system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses 676system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency 677system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency 678system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency 679system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency 680system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency 681system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency 682system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked 683system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 685system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked 687system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.icache.fast_writes 0 # number of fast writes performed 689system.cpu.icache.cache_copies 0 # number of cache copies performed 690system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits 691system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits 692system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits 693system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits 694system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits 695system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits 696system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses 697system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses 698system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses 699system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses 700system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses 701system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses 702system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles 703system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles 704system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles 705system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles 706system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles 707system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 709system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 710system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 711system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 712system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 713system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses 714system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency 715system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency 716system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency 717system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency 718system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency 719system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency 720system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 721system.cpu.l2cache.tags.replacements 115463 # number of replacements 722system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use 723system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks. 724system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks. 725system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks. 726system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. 727system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor 728system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor 729system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor 730system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy 731system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy 732system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy 733system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy 734system.cpu.l2cache.tags.occ_task_id_blocks::1024 31255 # Occupied blocks per task id 735system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 736system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 737system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id 738system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21321 # Occupied blocks per task id 740system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953827 # Percentage of cache occupancy per task id 741system.cpu.l2cache.tags.tag_accesses 19093617 # Number of tag accesses 742system.cpu.l2cache.tags.data_accesses 19093617 # Number of data accesses 743system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits 744system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits 745system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits 746system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits 747system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits 748system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits 749system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits 750system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits 751system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits 752system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits 753system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits 754system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits 755system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits 756system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits 757system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits 758system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses 759system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses 760system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses 761system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses 762system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses 763system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses 764system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses 765system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses 766system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses 767system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses 768system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses 769system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses 770system.cpu.l2cache.overall_misses::total 148236 # number of overall misses 771system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles 772system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles 773system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles 774system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles 775system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles 776system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles 777system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles 778system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles 779system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles 780system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles 781system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles 782system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses) 783system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses) 785system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses) 786system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses) 787system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses) 788system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses) 789system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses 792system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses 794system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses 797system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses 800system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses 804system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses 805system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses 807system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses 808system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses 810system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency 813system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency 814system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency 815system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency 816system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency 817system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency 818system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency 819system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency 820system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency 821system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 822system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 823system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 824system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 825system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 826system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 827system.cpu.l2cache.fast_writes 0 # number of fast writes performed 828system.cpu.l2cache.cache_copies 0 # number of cache copies performed 829system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks 830system.cpu.l2cache.writebacks::total 97655 # number of writebacks 831system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 832system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 833system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits 834system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 835system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 836system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits 837system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 838system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 839system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 840system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses 842system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses 843system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses 844system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses 853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles 857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles 865system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles 866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses 869system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses 870system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses 871system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses 872system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses 873system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses 874system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses 875system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses 876system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses 877system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses 878system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses 879system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency 880system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency 881system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency 882system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 883system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 884system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency 885system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893system.cpu.dcache.tags.replacements 1192730 # number of replacements 894system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use 895system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. 896system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. 897system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. 898system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. 899system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor 900system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy 901system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy 902system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 903system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 904system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 905system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id 906system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id 907system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 908system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses 909system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses 910system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits 911system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits 912system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits 913system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits 914system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits 915system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits 916system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 917system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 918system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits 919system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits 920system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits 921system.cpu.dcache.overall_hits::total 187223724 # number of overall hits 922system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses 923system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses 924system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses 925system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses 926system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses 927system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses 928system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses 929system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses 930system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses 931system.cpu.dcache.overall_misses::total 4951929 # number of overall misses 932system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles 933system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles 934system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles 935system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles 936system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles 937system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles 938system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles 939system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles 940system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles 941system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles 942system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 946system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) 947system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) 948system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 949system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 950system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses 951system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses 952system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses 953system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses 954system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses 955system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses 956system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses 957system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses 958system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses 959system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses 960system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses 961system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses 962system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses 963system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses 964system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency 965system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency 966system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency 967system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency 969system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency 970system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency 971system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency 973system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency 974system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked 975system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked 976system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked 977system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked 978system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked 979system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked 980system.cpu.dcache.fast_writes 0 # number of fast writes performed 981system.cpu.dcache.cache_copies 0 # number of cache copies performed 982system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks 983system.cpu.dcache.writebacks::total 1110997 # number of writebacks 984system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits 985system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits 987system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits 988system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits 989system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits 990system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits 991system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits 992system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits 993system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits 994system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses 995system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses 996system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses 997system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses 998system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses 999system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses 1001system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses 1002system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles 1003system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles 1004system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles 1005system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles 1006system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles 1007system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles 1008system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles 1009system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles 1010system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses 1011system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses 1012system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses 1013system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses 1014system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses 1015system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses 1016system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses 1017system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses 1018system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency 1019system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency 1020system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency 1021system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency 1022system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency 1023system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency 1024system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency 1025system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency 1026system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1027 1028---------- End Simulation Statistics ---------- 1029