stats.txt revision 9978
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39978Sandreas.hansson@arm.comsim_seconds 0.202724 # Number of seconds simulated 49978Sandreas.hansson@arm.comsim_ticks 202723760000 # Number of ticks simulated 59978Sandreas.hansson@arm.comfinal_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79978Sandreas.hansson@arm.comhost_inst_rate 119496 # Simulator instruction rate (inst/s) 89978Sandreas.hansson@arm.comhost_op_rate 134724 # Simulator op (including micro ops) rate (op/s) 99978Sandreas.hansson@arm.comhost_tick_rate 47946894 # Simulator tick rate (ticks/s) 109978Sandreas.hansson@arm.comhost_mem_usage 278932 # Number of bytes of host memory used 119978Sandreas.hansson@arm.comhost_seconds 4228.09 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 505237723 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 569624283 # Number of ops (including micro ops) simulated 149978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory 159978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory 169978Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 9484928 # Number of bytes read from this memory 179978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory 189978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory 199978Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory 209978Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 6251136 # Number of bytes written to this memory 219978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory 229978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory 239978Sandreas.hansson@arm.comsystem.physmem.num_reads::total 148202 # Number of read requests responded to by this memory 249978Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory 259978Sandreas.hansson@arm.comsystem.physmem.num_writes::total 97674 # Number of write requests responded to by this memory 269978Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) 279978Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) 289978Sandreas.hansson@arm.comsystem.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) 299978Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) 309978Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) 319978Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) 339978Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) 349978Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) 359978Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) 369978Sandreas.hansson@arm.comsystem.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) 379978Sandreas.hansson@arm.comsystem.physmem.readReqs 148203 # Number of read requests accepted 389978Sandreas.hansson@arm.comsystem.physmem.writeReqs 97674 # Number of write requests accepted 399978Sandreas.hansson@arm.comsystem.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue 409978Sandreas.hansson@arm.comsystem.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue 419978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM 429978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue 439978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM 449978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side 459978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side 469978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue 479978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 489978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 9589 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 9263 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 9230 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 8983 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 9781 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 9608 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 9123 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 8333 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 8801 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 8921 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 8939 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 9732 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9670 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 9771 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 8945 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 9431 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 6268 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 6168 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 6085 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 5885 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 6259 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6263 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6041 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 5560 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 5811 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 5905 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 5991 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6522 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 6386 # Per bank write bursts 789978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 6332 # Per bank write bursts 799978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 6056 # Per bank write bursts 809978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 6134 # Per bank write bursts 819978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 829978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 839978Sandreas.hansson@arm.comsystem.physmem.totGap 202723740000 # Total gap between requests 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 148203 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 97674 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see 999978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see 1009978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see 1019978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see 1029978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 1039978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1049322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1309978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see 1319978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see 1329978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see 1339978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see 1349978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see 1359978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see 1369978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see 1379978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see 1389978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see 1399978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see 1409978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see 1419978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see 1429978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see 1439978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see 1449978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see 1459978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see 1469978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see 1479978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see 1489978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see 1499978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see 1509978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see 1519978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see 1529978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 1539978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see 1549978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 1559978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see 1569978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1579978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1589978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1599978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1609978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1619978Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1629978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation 1639978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation 1649978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation 1659978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation 1669978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation 1679978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation 1689978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation 1699978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation 1709978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation 1719978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation 1729978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation 1739978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation 1749978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation 1759978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation 1769978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation 1779978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation 1789978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation 1799978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation 1809978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation 1819978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation 1829978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation 1839978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation 1849978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation 1859978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation 1869978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation 1879978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation 1889978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation 1899978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation 1909978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation 1919978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation 1929978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation 1939978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation 1949978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation 1959978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation 1969978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation 1979978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation 1989978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation 1999978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation 2009978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation 2019978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation 2029978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation 2039978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation 2049978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation 2059978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation 2069978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation 2079978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation 2089978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation 2099978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation 2109978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation 2119978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation 2129978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation 2139978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation 2149978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation 2159978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation 2169978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation 2179978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation 2189978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation 2199978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation 2209978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation 2219978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation 2229978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation 2239978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation 2249978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation 2259978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation 2269978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation 2279978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation 2289978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation 2299978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation 2309978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation 2319978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation 2329978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation 2339978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation 2349978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation 2359978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation 2369978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation 2379978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation 2389978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation 2399978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation 2409978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation 2419978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation 2429978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation 2439978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation 2449978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation 2459978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation 2469978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation 2479978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation 2489978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation 2499978Sandreas.hansson@arm.comsystem.physmem.totQLat 1733533250 # Total ticks spent queuing 2509978Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM 2519978Sandreas.hansson@arm.comsystem.physmem.totBusLat 740600000 # Total ticks spent in databus transfers 2529978Sandreas.hansson@arm.comsystem.physmem.totBankLat 2464357500 # Total ticks spent accessing banks 2539978Sandreas.hansson@arm.comsystem.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst 2549978Sandreas.hansson@arm.comsystem.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst 2559978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 2569978Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst 2579978Sandreas.hansson@arm.comsystem.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s 2589978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s 2599978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s 2609978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s 2619978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2629490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.61 # Data bus utilization in percentage 2639978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 2649978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 2659978Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing 2669978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing 2679978Sandreas.hansson@arm.comsystem.physmem.readRowHits 118615 # Number of row buffer hits during reads 2689978Sandreas.hansson@arm.comsystem.physmem.writeRowHits 57916 # Number of row buffer hits during writes 2699978Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 2709978Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes 2719978Sandreas.hansson@arm.comsystem.physmem.avgGap 824492.49 # Average gap between requests 2729978Sandreas.hansson@arm.comsystem.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined 2739978Sandreas.hansson@arm.comsystem.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state 2749978Sandreas.hansson@arm.comsystem.membus.throughput 77623185 # Throughput (bytes/s) 2759978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 46911 # Transaction distribution 2769978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 46910 # Transaction distribution 2779978Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 97674 # Transaction distribution 2789978Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 11 # Transaction distribution 2799978Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 11 # Transaction distribution 2809978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 101292 # Transaction distribution 2819978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 101292 # Transaction distribution 2829978Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) 2839978Sandreas.hansson@arm.comsystem.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) 2849978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) 2859978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) 2869978Sandreas.hansson@arm.comsystem.membus.data_through_bus 15736064 # Total data (bytes) 2879729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2889978Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) 2899729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 2909978Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) 2919729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.7 # Layer utilization (%) 2929978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 182800422 # Number of BP lookups 2939978Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted 2949978Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect 2959978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups 2969978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 87212337 # Number of BTB hits 2979482Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2989978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage 2999978Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. 3009978Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. 3018317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3028317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3038317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3048317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3058317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3068317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3078317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3088317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3098317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3108317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3118317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3128317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3138317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3148317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3158317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3168317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3178317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3188317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3198317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3208317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3218317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 3228317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3238317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3248317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3258317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3268317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3278317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3288317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3298317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3308317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3318317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3328317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3338317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3348317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3358317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3368317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3378317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3388317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3398317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3408317SN/Asystem.cpu.itb.hits 0 # DTB hits 3418317SN/Asystem.cpu.itb.misses 0 # DTB misses 3428317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3438317SN/Asystem.cpu.workload.num_syscalls 548 # Number of system calls 3449978Sandreas.hansson@arm.comsystem.cpu.numCycles 405447521 # number of cpu cycles simulated 3458317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3468317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3479978Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss 3489978Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed 3499978Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered 3509978Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken 3519978Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked 3529978Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing 3539978Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked 3549978Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 3559978Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps 3569978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR 3579978Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched 3589978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed 3599978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) 3609978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) 3619978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) 3628317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3639978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) 3649978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) 3659978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) 3669978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) 3679978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) 3689978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) 3699978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) 3709978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) 3719978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) 3728317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3738317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3748317SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3759978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) 3769978Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle 3779978Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle 3789978Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle 3799978Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked 3809978Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 158814938 # Number of cycles decode is running 3819978Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking 3829978Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing 3839978Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch 3849978Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction 3859978Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode 3869978Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode 3879978Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing 3889978Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle 3899978Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking 3909978Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst 3919978Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 158263751 # Number of cycles rename is running 3929978Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking 3939978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename 3949978Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full 3959978Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full 3969978Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full 3979978Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers 3989978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed 3999978Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made 4009978Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups 4019978Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups 4029459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed 4039978Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing 4049978Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed 4059978Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed 4069978Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer 4079978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. 4089978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. 4099978Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. 4109978Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. 4119978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) 4129978Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ 4139978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued 4149978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued 4159978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling 4169978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph 4179978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed 4189978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle 4199978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle 4209978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle 4218317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 4229978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle 4239978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle 4249978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle 4259978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle 4269978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle 4279978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle 4289978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle 4299978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle 4309978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle 4318317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4328317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4338317SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 4349978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle 4358317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 4369978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available 4379797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available 4389797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available 4399797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available 4409797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available 4419797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available 4429797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available 4439797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available 4449797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available 4459797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available 4469797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available 4479797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available 4489797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available 4499797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available 4509797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available 4519797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available 4529797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available 4539797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available 4549797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available 4559797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available 4569797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available 4579797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available 4589797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available 4599797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available 4609797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available 4619797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available 4629797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available 4639797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available 4649797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available 4659978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available 4669978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available 4678317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4688317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4698317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 4709978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued 4719978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued 4729459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued 4739978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued 4749459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 4759459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 4769459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 4779459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 4789459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 4799459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 4809459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 4819459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued 4829459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued 4839459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued 4849459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued 4859459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued 4869459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued 4879459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued 4889459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued 4899459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued 4909459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued 4919459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 4929459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 4939459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 4949459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 4959459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 4969459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 4979459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 4989459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued 4999978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued 5009978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued 5018317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5028317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 5039978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 665355613 # Type of FU issued 5049978Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.641040 # Inst issue rate 5059978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested 5069978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) 5079978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads 5089978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes 5099978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses 5109978Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads 5119978Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 5128317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 5139978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses 5149978Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses 5159978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores 5168317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5179978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed 5189978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed 5199978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations 5209978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed 5218317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5228317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5239978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled 5249978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked 5258317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 5269978Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing 5279978Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking 5289978Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking 5299978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ 5309978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch 5319978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions 5329978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions 5339978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions 5349978Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall 5359978Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall 5369978Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations 5379978Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly 5389978Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly 5399978Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute 5409978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions 5419978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed 5429978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute 5438317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5449978Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1559155 # number of nop insts executed 5459978Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 212603914 # number of memory reference insts executed 5469978Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 138495848 # Number of branches executed 5479978Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 62487508 # Number of stores executed 5489978Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.617786 # Inst execution rate 5499978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit 5509978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 646070390 # cumulative count of insts written-back 5519978Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 374730881 # num instructions producing a value 5529978Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 646348309 # num instructions consuming a value 5538317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 5549978Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.593475 # insts written-back per cycle 5559978Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back 5568317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5579978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit 5589459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 5599978Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted 5609978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle 5619978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle 5629978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle 5638241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5649978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle 5659978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle 5669978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle 5679978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle 5689978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle 5699978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle 5709978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle 5719978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle 5729978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle 5738241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5748241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5758241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5769978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle 5779459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 506581607 # Number of instructions committed 5789459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 5798317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5809459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 182890032 # Number of memory references committed 5819459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 126029555 # Number of loads committed 5828317SN/Asystem.cpu.commit.membars 1488542 # Number of memory barriers committed 5839459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 121548301 # Number of branches committed 5848241SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 5859459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 5868241SN/Asystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 5879978Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached 5888317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5899978Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1104768676 # The number of ROB reads 5909978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1548495185 # The number of ROB writes 5919978Sandreas.hansson@arm.comsystem.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself 5929978Sandreas.hansson@arm.comsystem.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling 5939459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 505237723 # Number of Instructions Simulated 5949459Ssaidi@eecs.umich.edusystem.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 5959459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 505237723 # Number of Instructions Simulated 5969978Sandreas.hansson@arm.comsystem.cpu.cpi 0.802489 # CPI: Cycles Per Instruction 5979978Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads 5989978Sandreas.hansson@arm.comsystem.cpu.ipc 1.246124 # IPC: Instructions Per Cycle 5999978Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads 6009978Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 3058844384 # number of integer regfile reads 6019978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 752016829 # number of integer regfile writes 6028317SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 6039978Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 210849022 # number of misc regfile reads 6049459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 6059978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) 6069978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution 6079978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution 6089978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution 6099978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution 6109978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution 6119978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution 6129978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution 6139978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) 6149978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) 6159978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) 6169978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) 6179978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) 6189978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) 6199978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) 6209978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) 6219978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) 6229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 6239978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) 6249729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 6259978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) 6269729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 6279978Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15073 # number of replacements 6289978Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use 6299978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. 6309978Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. 6319978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. 6329838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6339978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor 6349978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy 6359978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy 6369978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits 6379978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits 6389978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits 6399978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits 6409978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits 6419978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 114510320 # number of overall hits 6429978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses 6439978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses 6449978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses 6459978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses 6469978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses 6479978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 21232 # number of overall misses 6489978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles 6499978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles 6509978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles 6519978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles 6529978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles 6539978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles 6549978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) 6559978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) 6569978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses 6579978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses 6589978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses 6599978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses 6609978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses 6619978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses 6629978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses 6639978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses 6649978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses 6659978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses 6669978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency 6679978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency 6689978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency 6699978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency 6709978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency 6719978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency 6729978Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked 6738317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6749978Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked 6758317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6769978Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked 6778983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6788317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6798317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6809978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits 6819978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits 6829978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits 6839978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits 6849978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits 6859978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits 6869978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses 6879978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses 6889978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses 6899978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses 6909978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses 6919978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses 6929978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles 6939978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles 6949978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles 6959978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles 6969978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles 6979978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles 6989978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses 6999978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses 7009978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses 7019978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses 7029978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses 7039978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses 7049978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency 7059978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency 7069978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency 7079978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency 7089978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency 7099978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency 7108317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7119978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 115458 # number of replacements 7129978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use 7139978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. 7149978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. 7159978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. 7169978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. 7179978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor 7189978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor 7199978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor 7209978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy 7219978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy 7229978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy 7239978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy 7249978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits 7259978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits 7269978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits 7279978Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits 7289978Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits 7299978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits 7309978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits 7319978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits 7329978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits 7339978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits 7349978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits 7359978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits 7369978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits 7379978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits 7389978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1065591 # number of overall hits 7399978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses 7409978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses 7419978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses 7429978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 7439978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses 7449978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses 7459978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses 7469978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses 7479978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses 7489978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses 7499978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses 7509978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses 7519978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 148228 # number of overall misses 7529978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles 7539978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles 7549978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles 7559978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles 7569978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles 7579978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles 7589978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles 7599978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles 7609978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles 7619978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles 7629978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles 7639978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles 7649978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles 7659978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) 7669978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) 7679978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) 7689978Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) 7699978Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) 7709978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) 7719978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) 7729978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) 7739978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) 7749978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses 7759978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses 7769978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses 7779978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses 7789978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses 7799978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses 7809978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses 7819978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses 7829797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses 7839978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses 7849978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses 7859978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses 7869978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses 7879978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses 7889978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses 7899978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses 7909978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses 7919978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses 7929978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses 7939978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency 7949978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency 7959978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency 7969978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency 7979978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency 7989978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency 7999978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency 8009978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency 8019978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency 8029978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency 8039978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency 8049978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency 8059978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency 8068317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8078317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8088317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8098317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8108983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8118983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8128317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8137860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8149978Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks 8159978Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 97674 # number of writebacks 8169797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 8179978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits 8189978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits 8199797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 8209978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits 8219978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 8229797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 8239978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits 8249978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 8259978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses 8269978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses 8279978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses 8289978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 8299978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses 8309978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses 8319978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses 8329978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses 8339978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses 8349978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses 8359978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses 8369978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses 8379978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses 8389978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles 8399978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles 8409978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles 8419978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles 8429978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles 8439978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles 8449978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles 8459978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles 8469978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles 8479978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles 8489978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles 8499978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles 8509978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles 8519978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses 8529978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses 8539978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses 8549978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses 8559978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses 8569978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses 8579978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses 8589978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses 8599978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses 8609978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses 8619978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses 8629978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses 8639978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses 8649978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency 8659978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency 8669978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency 8679978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 8689978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 8699978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency 8709978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency 8719978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency 8729978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency 8739978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency 8749978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency 8759978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency 8769978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency 8777860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8789978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1192807 # number of replacements 8799978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use 8809978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. 8819978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. 8829978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. 8839978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. 8849978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor 8859978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy 8869978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy 8879978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits 8889978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits 8899978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits 8909978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits 8919978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits 8929978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits 8939459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 8949459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 8959978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits 8969978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits 8979978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits 8989978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 187221113 # number of overall hits 8999978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses 9009978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses 9019978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses 9029978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses 9039978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses 9049978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses 9059978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses 9069978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses 9079978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses 9089978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 4954972 # number of overall misses 9099978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles 9109978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles 9119978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles 9129978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles 9139978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles 9149978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles 9159978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles 9169978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles 9179978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles 9189978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles 9199978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) 9209978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) 9219449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 9229449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 9239978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) 9249978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) 9259459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 9269459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 9279978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses 9289978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses 9299978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses 9309978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses 9319978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses 9329978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses 9339978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses 9349978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses 9359978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses 9369978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses 9379978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses 9389978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses 9399978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses 9409978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses 9419978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency 9429978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency 9439978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency 9449978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency 9459978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency 9469978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency 9479978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency 9489978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency 9499978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency 9509978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency 9519978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked 9529978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked 9539978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked 9549978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked 9559978Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked 9569978Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked 9579449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9589449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 9599978Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks 9609978Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1111085 # number of writebacks 9619978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits 9629978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits 9639978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits 9649978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits 9659978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits 9669978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits 9679978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits 9689978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits 9699978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits 9709978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits 9719978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses 9729978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses 9739978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses 9749978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses 9759978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses 9769978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses 9779978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses 9789978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses 9799978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles 9809978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles 9819978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles 9829978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles 9839978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles 9849978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles 9859978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles 9869978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles 9879797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses 9889797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses 9899978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses 9909978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 9919797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses 9929797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses 9939797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses 9949797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses 9959978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency 9969978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency 9979978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency 9989978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency 9999978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency 10009978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency 10019978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency 10029978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency 10039449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10047860SN/A 10057860SN/A---------- End Simulation Statistics ---------- 1006