stats.txt revision 8317
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.320953 # Number of seconds simulated 4sim_ticks 320953109000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 40042 # Simulator instruction rate (inst/s) 7host_tick_rate 22415184 # Simulator tick rate (ticks/s) 8host_mem_usage 260460 # Number of bytes of host memory used 9host_seconds 14318.56 # Real time elapsed on the host 10sim_insts 573342262 # Number of instructions simulated 11system.cpu.dtb.inst_hits 0 # ITB inst hits 12system.cpu.dtb.inst_misses 0 # ITB inst misses 13system.cpu.dtb.read_hits 0 # DTB read hits 14system.cpu.dtb.read_misses 0 # DTB read misses 15system.cpu.dtb.write_hits 0 # DTB write hits 16system.cpu.dtb.write_misses 0 # DTB write misses 17system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 18system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 22system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 23system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 24system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 25system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 26system.cpu.dtb.read_accesses 0 # DTB read accesses 27system.cpu.dtb.write_accesses 0 # DTB write accesses 28system.cpu.dtb.inst_accesses 0 # ITB inst accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses 31system.cpu.dtb.accesses 0 # DTB accesses 32system.cpu.itb.inst_hits 0 # ITB inst hits 33system.cpu.itb.inst_misses 0 # ITB inst misses 34system.cpu.itb.read_hits 0 # DTB read hits 35system.cpu.itb.read_misses 0 # DTB read misses 36system.cpu.itb.write_hits 0 # DTB write hits 37system.cpu.itb.write_misses 0 # DTB write misses 38system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 39system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 43system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 44system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 45system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 46system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 47system.cpu.itb.read_accesses 0 # DTB read accesses 48system.cpu.itb.write_accesses 0 # DTB write accesses 49system.cpu.itb.inst_accesses 0 # ITB inst accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 548 # Number of system calls 54system.cpu.numCycles 641906219 # number of cpu cycles simulated 55system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57system.cpu.BPredUnit.lookups 223949599 # Number of BP lookups 58system.cpu.BPredUnit.condPredicted 179054613 # Number of conditional branches predicted 59system.cpu.BPredUnit.condIncorrect 19156129 # Number of conditional branches incorrect 60system.cpu.BPredUnit.BTBLookups 184229626 # Number of BTB lookups 61system.cpu.BPredUnit.BTBHits 147971030 # Number of BTB hits 62system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 63system.cpu.BPredUnit.usedRAS 11972868 # Number of times the RAS was used to get a target. 64system.cpu.BPredUnit.RASInCorrect 2532941 # Number of incorrect RAS predictions. 65system.cpu.fetch.icacheStallCycles 130565917 # Number of cycles fetch is stalled on an Icache miss 66system.cpu.fetch.Insts 973113322 # Number of instructions fetch has processed 67system.cpu.fetch.Branches 223949599 # Number of branches that fetch encountered 68system.cpu.fetch.predictedBranches 159943898 # Number of branches that fetch has predicted taken 69system.cpu.fetch.Cycles 241546376 # Number of cycles fetch has run and was not squashing or blocked 70system.cpu.fetch.SquashCycles 21862580 # Number of cycles fetch has spent squashing 71system.cpu.fetch.MiscStallCycles 2406 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 72system.cpu.fetch.CacheLines 130565917 # Number of cache lines fetched 73system.cpu.fetch.IcacheSquashes 3998860 # Number of outstanding Icache misses that were squashed 74system.cpu.fetch.rateDist::samples 637850640 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::mean 1.791502 # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::stdev 2.743865 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::0 396316059 62.13% 62.13% # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::1 20357816 3.19% 65.32% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::2 35705192 5.60% 70.92% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::3 35959525 5.64% 76.56% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::4 37219035 5.84% 82.40% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::5 17602838 2.76% 85.15% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::6 18536216 2.91% 88.06% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::7 14275483 2.24% 90.30% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::8 61878476 9.70% 100.00% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::total 637850640 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.branchRate 0.348882 # Number of branch fetches per cycle 92system.cpu.fetch.rate 1.515974 # Number of inst fetches per cycle 93system.cpu.decode.IdleCycles 274650627 # Number of cycles decode is idle 94system.cpu.decode.BlockedCycles 79437827 # Number of cycles decode is blocked 95system.cpu.decode.RunCycles 227463937 # Number of cycles decode is running 96system.cpu.decode.UnblockCycles 2944119 # Number of cycles decode is unblocking 97system.cpu.decode.SquashCycles 53354130 # Number of cycles decode is squashing 98system.cpu.decode.BranchResolved 31952595 # Number of times decode resolved a branch 99system.cpu.decode.BranchMispred 76091 # Number of times decode detected a branch misprediction 100system.cpu.decode.DecodedInsts 1091620209 # Number of instructions handled by decode 101system.cpu.decode.SquashedInsts 217331 # Number of squashed instructions handled by decode 102system.cpu.rename.SquashCycles 53354130 # Number of cycles rename is squashing 103system.cpu.rename.IdleCycles 289506174 # Number of cycles rename is idle 104system.cpu.rename.BlockCycles 9893108 # Number of cycles rename is blocking 105system.cpu.rename.serializeStallCycles 49317817 # count of cycles rename stalled for serializing inst 106system.cpu.rename.RunCycles 215240896 # Number of cycles rename is running 107system.cpu.rename.UnblockCycles 20538515 # Number of cycles rename is unblocking 108system.cpu.rename.RenamedInsts 1036732054 # Number of instructions processed by rename 109system.cpu.rename.ROBFullEvents 236 # Number of times rename has blocked due to ROB full 110system.cpu.rename.IQFullEvents 6072390 # Number of times rename has blocked due to IQ full 111system.cpu.rename.LSQFullEvents 9974912 # Number of times rename has blocked due to LSQ full 112system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers 113system.cpu.rename.RenamedOperands 1156982067 # Number of destination operands rename has renamed 114system.cpu.rename.RenameLookups 4582431546 # Number of register rename lookups that rename has made 115system.cpu.rename.int_rename_lookups 4582430193 # Number of integer rename lookups 116system.cpu.rename.fp_rename_lookups 1353 # Number of floating rename lookups 117system.cpu.rename.CommittedMaps 672201056 # Number of HB maps that are committed 118system.cpu.rename.UndoneMaps 484781006 # Number of HB maps that are undone due to squashing 119system.cpu.rename.serializingInsts 2811540 # count of serializing insts renamed 120system.cpu.rename.tempSerializingInsts 2811485 # count of temporary serializing insts renamed 121system.cpu.rename.skidInsts 54423240 # count of insts added to the skid buffer 122system.cpu.memDep0.insertedLoads 192516932 # Number of loads inserted to the mem dependence unit. 123system.cpu.memDep0.insertedStores 113728531 # Number of stores inserted to the mem dependence unit. 124system.cpu.memDep0.conflictingLoads 52019514 # Number of conflicting loads. 125system.cpu.memDep0.conflictingStores 56045106 # Number of conflicting stores. 126system.cpu.iq.iqInstsAdded 898220409 # Number of instructions added to the IQ (excludes non-spec) 127system.cpu.iq.iqNonSpecInstsAdded 4649392 # Number of non-speculative instructions added to the IQ 128system.cpu.iq.iqInstsIssued 742085900 # Number of instructions issued 129system.cpu.iq.iqSquashedInstsIssued 4028217 # Number of squashed instructions issued 130system.cpu.iq.iqSquashedInstsExamined 325034737 # Number of squashed instructions iterated over during squash; mainly for profiling 131system.cpu.iq.iqSquashedOperandsExamined 902951971 # Number of squashed operands that are examined and possibly removed from graph 132system.cpu.iq.iqSquashedNonSpecRemoved 771526 # Number of squashed non-spec instructions that were removed 133system.cpu.iq.issued_per_cycle::samples 637850640 # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::mean 1.163416 # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::stdev 1.451606 # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::0 296239264 46.44% 46.44% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::1 133409185 20.92% 67.36% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::2 102098632 16.01% 83.37% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::3 53722534 8.42% 91.79% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::4 32322089 5.07% 96.86% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::5 11168911 1.75% 98.61% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::6 5441714 0.85% 99.46% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::7 2057834 0.32% 99.78% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::8 1390477 0.22% 100.00% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::total 637850640 # Number of insts issued each cycle 150system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 151system.cpu.iq.fu_full::IntAlu 95830 1.04% 1.04% # attempts to use FU when none available 152system.cpu.iq.fu_full::IntMult 0 0.00% 1.04% # attempts to use FU when none available 153system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available 154system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available 155system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available 156system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available 157system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available 158system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available 159system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available 180system.cpu.iq.fu_full::MemRead 5443662 59.10% 60.15% # attempts to use FU when none available 181system.cpu.iq.fu_full::MemWrite 3670689 39.85% 100.00% # attempts to use FU when none available 182system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 183system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 184system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 185system.cpu.iq.FU_type_0::IntAlu 503818075 67.89% 67.89% # Type of FU issued 186system.cpu.iq.FU_type_0::IntMult 366199 0.05% 67.94% # Type of FU issued 187system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.94% # Type of FU issued 188system.cpu.iq.FU_type_0::FloatAdd 82 0.00% 67.94% # Type of FU issued 189system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued 190system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued 191system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued 192system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued 193system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.94% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued 214system.cpu.iq.FU_type_0::MemRead 163695097 22.06% 90.00% # Type of FU issued 215system.cpu.iq.FU_type_0::MemWrite 74206444 10.00% 100.00% # Type of FU issued 216system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 217system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 218system.cpu.iq.FU_type_0::total 742085900 # Type of FU issued 219system.cpu.iq.rate 1.156066 # Inst issue rate 220system.cpu.iq.fu_busy_cnt 9210181 # FU busy when requested 221system.cpu.iq.fu_busy_rate 0.012411 # FU busy rate (busy events/executed inst) 222system.cpu.iq.int_inst_queue_reads 2135260638 # Number of integer instruction queue reads 223system.cpu.iq.int_inst_queue_writes 1228450518 # Number of integer instruction queue writes 224system.cpu.iq.int_inst_queue_wakeup_accesses 694522935 # Number of integer instruction queue wakeup accesses 225system.cpu.iq.fp_inst_queue_reads 200 # Number of floating instruction queue reads 226system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes 227system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 228system.cpu.iq.int_alu_accesses 751295979 # Number of integer alu accesses 229system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses 230system.cpu.iew.lsq.thread0.forwLoads 5771553 # Number of loads that had data forwarded from stores 231system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 232system.cpu.iew.lsq.thread0.squashedLoads 65743781 # Number of loads squashed 233system.cpu.iew.lsq.thread0.ignoredResponses 15629 # Number of memory responses ignored because the instruction is squashed 234system.cpu.iew.lsq.thread0.memOrderViolation 596063 # Number of memory ordering violations 235system.cpu.iew.lsq.thread0.squashedStores 56124460 # Number of stores squashed 236system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 237system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 238system.cpu.iew.lsq.thread0.rescheduledLoads 24980 # Number of loads that were rescheduled 239system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked 240system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 241system.cpu.iew.iewSquashCycles 53354130 # Number of cycles IEW is squashing 242system.cpu.iew.iewBlockCycles 2618576 # Number of cycles IEW is blocking 243system.cpu.iew.iewUnblockCycles 142825 # Number of cycles IEW is unblocking 244system.cpu.iew.iewDispatchedInsts 912051296 # Number of instructions dispatched to IQ 245system.cpu.iew.iewDispSquashedInsts 21556193 # Number of squashed instructions skipped by dispatch 246system.cpu.iew.iewDispLoadInsts 192516932 # Number of dispatched load instructions 247system.cpu.iew.iewDispStoreInsts 113728531 # Number of dispatched store instructions 248system.cpu.iew.iewDispNonSpecInsts 2788498 # Number of dispatched non-speculative instructions 249system.cpu.iew.iewIQFullEvents 84227 # Number of times the IQ has become full, causing a stall 250system.cpu.iew.iewLSQFullEvents 8711 # Number of times the LSQ has become full, causing a stall 251system.cpu.iew.memOrderViolationEvents 596063 # Number of memory order violations 252system.cpu.iew.predictedTakenIncorrect 17931306 # Number of branches that were predicted taken incorrectly 253system.cpu.iew.predictedNotTakenIncorrect 6522754 # Number of branches that were predicted not taken incorrectly 254system.cpu.iew.branchMispredicts 24454060 # Number of branch mispredicts detected at execute 255system.cpu.iew.iewExecutedInsts 711877956 # Number of executed instructions 256system.cpu.iew.iewExecLoadInsts 154430876 # Number of load instructions executed 257system.cpu.iew.iewExecSquashedInsts 30207944 # Number of squashed instructions skipped in execute 258system.cpu.iew.exec_swp 0 # number of swp insts executed 259system.cpu.iew.exec_nop 9181495 # number of nop insts executed 260system.cpu.iew.exec_refs 222561224 # number of memory reference insts executed 261system.cpu.iew.exec_branches 143781551 # Number of branches executed 262system.cpu.iew.exec_stores 68130348 # Number of stores executed 263system.cpu.iew.exec_rate 1.109006 # Inst execution rate 264system.cpu.iew.wb_sent 704134955 # cumulative count of insts sent to commit 265system.cpu.iew.wb_count 694522951 # cumulative count of insts written-back 266system.cpu.iew.wb_producers 388125156 # num instructions producing a value 267system.cpu.iew.wb_consumers 688020690 # num instructions consuming a value 268system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 269system.cpu.iew.wb_rate 1.081970 # insts written-back per cycle 270system.cpu.iew.wb_fanout 0.564118 # average fanout of values written-back 271system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 272system.cpu.commit.commitCommittedInsts 574686146 # The number of committed instructions 273system.cpu.commit.commitSquashedInsts 337368429 # The number of squashed insts skipped by commit 274system.cpu.commit.commitNonSpecStalls 3877866 # The number of times commit has been forced to stall to communicate backwards 275system.cpu.commit.branchMispredicts 21251956 # The number of times a branch was mispredicted 276system.cpu.commit.committed_per_cycle::samples 584496511 # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::mean 0.983216 # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::stdev 1.594536 # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::0 311654164 53.32% 53.32% # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::1 150316632 25.72% 79.04% # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::2 55227209 9.45% 88.49% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::3 24753339 4.23% 92.72% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::4 15848741 2.71% 95.43% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::5 6546524 1.12% 96.55% # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::6 7691194 1.32% 97.87% # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::7 2289333 0.39% 98.26% # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::8 10169375 1.74% 100.00% # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::total 584496511 # Number of insts commited each cycle 293system.cpu.commit.count 574686146 # Number of instructions committed 294system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 295system.cpu.commit.refs 184377221 # Number of memory references committed 296system.cpu.commit.loads 126773150 # Number of loads committed 297system.cpu.commit.membars 1488542 # Number of memory barriers committed 298system.cpu.commit.branches 120192335 # Number of branches committed 299system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 300system.cpu.commit.int_insts 473702077 # Number of committed integer instructions. 301system.cpu.commit.function_calls 9757362 # Number of function calls committed. 302system.cpu.commit.bw_lim_events 10169375 # number cycles where commit BW limit reached 303system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 304system.cpu.rob.rob_reads 1486374573 # The number of ROB reads 305system.cpu.rob.rob_writes 1877592139 # The number of ROB writes 306system.cpu.timesIdled 93100 # Number of times that the entire CPU went into an idle state and unscheduled itself 307system.cpu.idleCycles 4055579 # Total number of cycles that the CPU has spent unscheduled due to idling 308system.cpu.committedInsts 573342262 # Number of Instructions Simulated 309system.cpu.committedInsts_total 573342262 # Number of Instructions Simulated 310system.cpu.cpi 1.119586 # CPI: Cycles Per Instruction 311system.cpu.cpi_total 1.119586 # CPI: Total CPI of All Threads 312system.cpu.ipc 0.893187 # IPC: Instructions Per Cycle 313system.cpu.ipc_total 0.893187 # IPC: Total IPC of All Threads 314system.cpu.int_regfile_reads 3288876394 # number of integer regfile reads 315system.cpu.int_regfile_writes 807633235 # number of integer regfile writes 316system.cpu.fp_regfile_reads 16 # number of floating regfile reads 317system.cpu.misc_regfile_reads 1209708694 # number of misc regfile reads 318system.cpu.misc_regfile_writes 4464272 # number of misc regfile writes 319system.cpu.icache.replacements 11767 # number of replacements 320system.cpu.icache.tagsinuse 1053.166926 # Cycle average of tags in use 321system.cpu.icache.total_refs 130550979 # Total number of references to valid blocks. 322system.cpu.icache.sampled_refs 13545 # Sample count of references to valid blocks. 323system.cpu.icache.avg_refs 9638.315172 # Average number of references to valid blocks. 324system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 325system.cpu.icache.occ_blocks::0 1053.166926 # Average occupied blocks per context 326system.cpu.icache.occ_percent::0 0.514242 # Average percentage of cache occupancy 327system.cpu.icache.ReadReq_hits 130550990 # number of ReadReq hits 328system.cpu.icache.demand_hits 130550990 # number of demand (read+write) hits 329system.cpu.icache.overall_hits 130550990 # number of overall hits 330system.cpu.icache.ReadReq_misses 14927 # number of ReadReq misses 331system.cpu.icache.demand_misses 14927 # number of demand (read+write) misses 332system.cpu.icache.overall_misses 14927 # number of overall misses 333system.cpu.icache.ReadReq_miss_latency 215353500 # number of ReadReq miss cycles 334system.cpu.icache.demand_miss_latency 215353500 # number of demand (read+write) miss cycles 335system.cpu.icache.overall_miss_latency 215353500 # number of overall miss cycles 336system.cpu.icache.ReadReq_accesses 130565917 # number of ReadReq accesses(hits+misses) 337system.cpu.icache.demand_accesses 130565917 # number of demand (read+write) accesses 338system.cpu.icache.overall_accesses 130565917 # number of overall (read+write) accesses 339system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses 340system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses 341system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses 342system.cpu.icache.ReadReq_avg_miss_latency 14427.111945 # average ReadReq miss latency 343system.cpu.icache.demand_avg_miss_latency 14427.111945 # average overall miss latency 344system.cpu.icache.overall_avg_miss_latency 14427.111945 # average overall miss latency 345system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 346system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 348system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 349system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 350system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 351system.cpu.icache.fast_writes 0 # number of fast writes performed 352system.cpu.icache.cache_copies 0 # number of cache copies performed 353system.cpu.icache.writebacks 2 # number of writebacks 354system.cpu.icache.ReadReq_mshr_hits 1072 # number of ReadReq MSHR hits 355system.cpu.icache.demand_mshr_hits 1072 # number of demand (read+write) MSHR hits 356system.cpu.icache.overall_mshr_hits 1072 # number of overall MSHR hits 357system.cpu.icache.ReadReq_mshr_misses 13855 # number of ReadReq MSHR misses 358system.cpu.icache.demand_mshr_misses 13855 # number of demand (read+write) MSHR misses 359system.cpu.icache.overall_mshr_misses 13855 # number of overall MSHR misses 360system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 361system.cpu.icache.ReadReq_mshr_miss_latency 147833000 # number of ReadReq MSHR miss cycles 362system.cpu.icache.demand_mshr_miss_latency 147833000 # number of demand (read+write) MSHR miss cycles 363system.cpu.icache.overall_mshr_miss_latency 147833000 # number of overall MSHR miss cycles 364system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 365system.cpu.icache.ReadReq_mshr_miss_rate 0.000106 # mshr miss rate for ReadReq accesses 366system.cpu.icache.demand_mshr_miss_rate 0.000106 # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate 0.000106 # mshr miss rate for overall accesses 368system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826 # average ReadReq mshr miss latency 369system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency 370system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency 371system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 372system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 373system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 374system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 375system.cpu.dcache.replacements 1189612 # number of replacements 376system.cpu.dcache.tagsinuse 4060.806862 # Cycle average of tags in use 377system.cpu.dcache.total_refs 200134121 # Total number of references to valid blocks. 378system.cpu.dcache.sampled_refs 1193708 # Sample count of references to valid blocks. 379system.cpu.dcache.avg_refs 167.657518 # Average number of references to valid blocks. 380system.cpu.dcache.warmup_cycle 6159317000 # Cycle when the warmup percentage was hit. 381system.cpu.dcache.occ_blocks::0 4060.806862 # Average occupied blocks per context 382system.cpu.dcache.occ_percent::0 0.991408 # Average percentage of cache occupancy 383system.cpu.dcache.ReadReq_hits 142442366 # number of ReadReq hits 384system.cpu.dcache.WriteReq_hits 52854608 # number of WriteReq hits 385system.cpu.dcache.LoadLockedReq_hits 2604415 # number of LoadLockedReq hits 386system.cpu.dcache.StoreCondReq_hits 2232135 # number of StoreCondReq hits 387system.cpu.dcache.demand_hits 195296974 # number of demand (read+write) hits 388system.cpu.dcache.overall_hits 195296974 # number of overall hits 389system.cpu.dcache.ReadReq_misses 1102250 # number of ReadReq misses 390system.cpu.dcache.WriteReq_misses 1384698 # number of WriteReq misses 391system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses 392system.cpu.dcache.demand_misses 2486948 # number of demand (read+write) misses 393system.cpu.dcache.overall_misses 2486948 # number of overall misses 394system.cpu.dcache.ReadReq_miss_latency 11846428500 # number of ReadReq miss cycles 395system.cpu.dcache.WriteReq_miss_latency 20406027500 # number of WriteReq miss cycles 396system.cpu.dcache.LoadLockedReq_miss_latency 313000 # number of LoadLockedReq miss cycles 397system.cpu.dcache.demand_miss_latency 32252456000 # number of demand (read+write) miss cycles 398system.cpu.dcache.overall_miss_latency 32252456000 # number of overall miss cycles 399system.cpu.dcache.ReadReq_accesses 143544616 # number of ReadReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.LoadLockedReq_accesses 2604451 # number of LoadLockedReq accesses(hits+misses) 402system.cpu.dcache.StoreCondReq_accesses 2232135 # number of StoreCondReq accesses(hits+misses) 403system.cpu.dcache.demand_accesses 197783922 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses 197783922 # number of overall (read+write) accesses 405system.cpu.dcache.ReadReq_miss_rate 0.007679 # miss rate for ReadReq accesses 406system.cpu.dcache.WriteReq_miss_rate 0.025529 # miss rate for WriteReq accesses 407system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses 408system.cpu.dcache.demand_miss_rate 0.012574 # miss rate for demand accesses 409system.cpu.dcache.overall_miss_rate 0.012574 # miss rate for overall accesses 410system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938 # average ReadReq miss latency 411system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232 # average WriteReq miss latency 412system.cpu.dcache.LoadLockedReq_avg_miss_latency 8694.444444 # average LoadLockedReq miss latency 413system.cpu.dcache.demand_avg_miss_latency 12968.689333 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency 12968.689333 # average overall miss latency 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked 421system.cpu.dcache.fast_writes 0 # number of fast writes performed 422system.cpu.dcache.cache_copies 0 # number of cache copies performed 423system.cpu.dcache.writebacks 1065401 # number of writebacks 424system.cpu.dcache.ReadReq_mshr_hits 244002 # number of ReadReq MSHR hits 425system.cpu.dcache.WriteReq_mshr_hits 1048961 # number of WriteReq MSHR hits 426system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits 427system.cpu.dcache.demand_mshr_hits 1292963 # number of demand (read+write) MSHR hits 428system.cpu.dcache.overall_mshr_hits 1292963 # number of overall MSHR hits 429system.cpu.dcache.ReadReq_mshr_misses 858248 # number of ReadReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses 335737 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses 1193985 # number of demand (read+write) MSHR misses 432system.cpu.dcache.overall_mshr_misses 1193985 # number of overall MSHR misses 433system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 434system.cpu.dcache.ReadReq_mshr_miss_latency 6157877500 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency 4228090500 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.demand_mshr_miss_latency 10385968000 # number of demand (read+write) MSHR miss cycles 437system.cpu.dcache.overall_mshr_miss_latency 10385968000 # number of overall MSHR miss cycles 438system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 439system.cpu.dcache.ReadReq_mshr_miss_rate 0.005979 # mshr miss rate for ReadReq accesses 440system.cpu.dcache.WriteReq_mshr_miss_rate 0.006190 # mshr miss rate for WriteReq accesses 441system.cpu.dcache.demand_mshr_miss_rate 0.006037 # mshr miss rate for demand accesses 442system.cpu.dcache.overall_mshr_miss_rate 0.006037 # mshr miss rate for overall accesses 443system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7174.939528 # average ReadReq mshr miss latency 444system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060 # average WriteReq mshr miss latency 445system.cpu.dcache.demand_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency 446system.cpu.dcache.overall_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency 447system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 448system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 449system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 450system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 451system.cpu.l2cache.replacements 214616 # number of replacements 452system.cpu.l2cache.tagsinuse 21258.843371 # Cycle average of tags in use 453system.cpu.l2cache.total_refs 1538764 # Total number of references to valid blocks. 454system.cpu.l2cache.sampled_refs 234845 # Sample count of references to valid blocks. 455system.cpu.l2cache.avg_refs 6.552254 # Average number of references to valid blocks. 456system.cpu.l2cache.warmup_cycle 231195370000 # Cycle when the warmup percentage was hit. 457system.cpu.l2cache.occ_blocks::0 7817.837138 # Average occupied blocks per context 458system.cpu.l2cache.occ_blocks::1 13441.006233 # Average occupied blocks per context 459system.cpu.l2cache.occ_percent::0 0.238581 # Average percentage of cache occupancy 460system.cpu.l2cache.occ_percent::1 0.410187 # Average percentage of cache occupancy 461system.cpu.l2cache.ReadReq_hits 742273 # number of ReadReq hits 462system.cpu.l2cache.Writeback_hits 1065403 # number of Writeback hits 463system.cpu.l2cache.UpgradeReq_hits 160 # number of UpgradeReq hits 464system.cpu.l2cache.ReadExReq_hits 231247 # number of ReadExReq hits 465system.cpu.l2cache.demand_hits 973520 # number of demand (read+write) hits 466system.cpu.l2cache.overall_hits 973520 # number of overall hits 467system.cpu.l2cache.ReadReq_misses 129152 # number of ReadReq misses 468system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses 469system.cpu.l2cache.ReadExReq_misses 104568 # number of ReadExReq misses 470system.cpu.l2cache.demand_misses 233720 # number of demand (read+write) misses 471system.cpu.l2cache.overall_misses 233720 # number of overall misses 472system.cpu.l2cache.ReadReq_miss_latency 4416243000 # number of ReadReq miss cycles 473system.cpu.l2cache.UpgradeReq_miss_latency 547000 # number of UpgradeReq miss cycles 474system.cpu.l2cache.ReadExReq_miss_latency 3581590000 # number of ReadExReq miss cycles 475system.cpu.l2cache.demand_miss_latency 7997833000 # number of demand (read+write) miss cycles 476system.cpu.l2cache.overall_miss_latency 7997833000 # number of overall miss cycles 477system.cpu.l2cache.ReadReq_accesses 871425 # number of ReadReq accesses(hits+misses) 478system.cpu.l2cache.Writeback_accesses 1065403 # number of Writeback accesses(hits+misses) 479system.cpu.l2cache.UpgradeReq_accesses 272 # number of UpgradeReq accesses(hits+misses) 480system.cpu.l2cache.ReadExReq_accesses 335815 # number of ReadExReq accesses(hits+misses) 481system.cpu.l2cache.demand_accesses 1207240 # number of demand (read+write) accesses 482system.cpu.l2cache.overall_accesses 1207240 # number of overall (read+write) accesses 483system.cpu.l2cache.ReadReq_miss_rate 0.148208 # miss rate for ReadReq accesses 484system.cpu.l2cache.UpgradeReq_miss_rate 0.411765 # miss rate for UpgradeReq accesses 485system.cpu.l2cache.ReadExReq_miss_rate 0.311386 # miss rate for ReadExReq accesses 486system.cpu.l2cache.demand_miss_rate 0.193599 # miss rate for demand accesses 487system.cpu.l2cache.overall_miss_rate 0.193599 # miss rate for overall accesses 488system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078 # average ReadReq miss latency 489system.cpu.l2cache.UpgradeReq_avg_miss_latency 4883.928571 # average UpgradeReq miss latency 490system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589 # average ReadExReq miss latency 491system.cpu.l2cache.demand_avg_miss_latency 34219.720178 # average overall miss latency 492system.cpu.l2cache.overall_avg_miss_latency 34219.720178 # average overall miss latency 493system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 498system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 499system.cpu.l2cache.fast_writes 0 # number of fast writes performed 500system.cpu.l2cache.cache_copies 0 # number of cache copies performed 501system.cpu.l2cache.writebacks 169760 # number of writebacks 502system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits 503system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits 504system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits 505system.cpu.l2cache.ReadReq_mshr_misses 129137 # number of ReadReq MSHR misses 506system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses 507system.cpu.l2cache.ReadExReq_mshr_misses 104568 # number of ReadExReq MSHR misses 508system.cpu.l2cache.demand_mshr_misses 233705 # number of demand (read+write) MSHR misses 509system.cpu.l2cache.overall_mshr_misses 233705 # number of overall MSHR misses 510system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 511system.cpu.l2cache.ReadReq_mshr_miss_latency 4006675000 # number of ReadReq MSHR miss cycles 512system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3473000 # number of UpgradeReq MSHR miss cycles 513system.cpu.l2cache.ReadExReq_mshr_miss_latency 3242222500 # number of ReadExReq MSHR miss cycles 514system.cpu.l2cache.demand_mshr_miss_latency 7248897500 # number of demand (read+write) MSHR miss cycles 515system.cpu.l2cache.overall_mshr_miss_latency 7248897500 # number of overall MSHR miss cycles 516system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 517system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148191 # mshr miss rate for ReadReq accesses 518system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.411765 # mshr miss rate for UpgradeReq accesses 519system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311386 # mshr miss rate for ReadExReq accesses 520system.cpu.l2cache.demand_mshr_miss_rate 0.193586 # mshr miss rate for demand accesses 521system.cpu.l2cache.overall_mshr_miss_rate 0.193586 # mshr miss rate for overall accesses 522system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452 # average ReadReq mshr miss latency 523system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571 # average UpgradeReq mshr miss latency 524system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559 # average ReadExReq mshr miss latency 525system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency 526system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency 527system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 528system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 529system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 530system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 531 532---------- End Simulation Statistics ---------- 533