stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 191028 # Simulator instruction rate (inst/s) 4host_mem_usage 221120 # Number of bytes of host memory used 5host_seconds 3001.36 # Real time elapsed on the host 6host_tick_rate 110860138 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 573342397 # Number of instructions simulated 9sim_seconds 0.332731 # Number of seconds simulated 10sim_ticks 332731219000 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 157170154 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 189971474 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 2546633 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 18809964 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 186338321 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 233659814 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 11860569 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 20926821 # The number of times a branch was mispredicted 20system.cpu.commit.branches 120192362 # Number of branches committed 21system.cpu.commit.bw_lim_events 6858146 # number cycles where commit BW limit reached 22system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 23system.cpu.commit.commitCommittedInsts 574686281 # The number of committed instructions 24system.cpu.commit.commitNonSpecStalls 3877893 # The number of times commit has been forced to stall to communicate backwards 25system.cpu.commit.commitSquashedInsts 381923221 # The number of squashed insts skipped by commit 26system.cpu.commit.committed_per_cycle::samples 603587786 # Number of insts commited each cycle 27system.cpu.commit.committed_per_cycle::mean 0.952117 # Number of insts commited each cycle 28system.cpu.commit.committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle 29system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 30system.cpu.commit.committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::total 603587786 # Number of insts commited each cycle 43system.cpu.commit.count 574686281 # Number of instructions committed 44system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 45system.cpu.commit.function_calls 9757362 # Number of function calls committed. 46system.cpu.commit.int_insts 473702185 # Number of committed integer instructions. 47system.cpu.commit.loads 126773177 # Number of loads committed 48system.cpu.commit.membars 1488542 # Number of memory barriers committed 49system.cpu.commit.refs 184377275 # Number of memory references committed 50system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51system.cpu.committedInsts 573342397 # Number of Instructions Simulated 52system.cpu.committedInsts_total 573342397 # Number of Instructions Simulated 53system.cpu.cpi 1.160672 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 1.160672 # CPI: Total CPI of All Threads 55system.cpu.dcache.LoadLockedReq_accesses 2604457 # number of LoadLockedReq accesses(hits+misses) 56system.cpu.dcache.LoadLockedReq_avg_miss_latency 7857.142857 # average LoadLockedReq miss latency 57system.cpu.dcache.LoadLockedReq_hits 2604422 # number of LoadLockedReq hits 58system.cpu.dcache.LoadLockedReq_miss_latency 275000 # number of LoadLockedReq miss cycles 59system.cpu.dcache.LoadLockedReq_miss_rate 0.000013 # miss rate for LoadLockedReq accesses 60system.cpu.dcache.LoadLockedReq_misses 35 # number of LoadLockedReq misses 61system.cpu.dcache.LoadLockedReq_mshr_hits 35 # number of LoadLockedReq MSHR hits 62system.cpu.dcache.ReadReq_accesses 143454074 # number of ReadReq accesses(hits+misses) 63system.cpu.dcache.ReadReq_avg_miss_latency 10689.937494 # average ReadReq miss latency 64system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7026.878867 # average ReadReq mshr miss latency 65system.cpu.dcache.ReadReq_hits 142382969 # number of ReadReq hits 66system.cpu.dcache.ReadReq_miss_latency 11450045500 # number of ReadReq miss cycles 67system.cpu.dcache.ReadReq_miss_rate 0.007467 # miss rate for ReadReq accesses 68system.cpu.dcache.ReadReq_misses 1071105 # number of ReadReq misses 69system.cpu.dcache.ReadReq_mshr_hits 217572 # number of ReadReq MSHR hits 70system.cpu.dcache.ReadReq_mshr_miss_latency 5997673000 # number of ReadReq MSHR miss cycles 71system.cpu.dcache.ReadReq_mshr_miss_rate 0.005950 # mshr miss rate for ReadReq accesses 72system.cpu.dcache.ReadReq_mshr_misses 853533 # number of ReadReq MSHR misses 73system.cpu.dcache.StoreCondReq_accesses 2232162 # number of StoreCondReq accesses(hits+misses) 74system.cpu.dcache.StoreCondReq_hits 2232162 # number of StoreCondReq hits 75system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) 76system.cpu.dcache.WriteReq_avg_miss_latency 15503.883790 # average WriteReq miss latency 77system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12993.978894 # average WriteReq mshr miss latency 78system.cpu.dcache.WriteReq_hits 52863588 # number of WriteReq hits 79system.cpu.dcache.WriteReq_miss_latency 21328972000 # number of WriteReq miss cycles 80system.cpu.dcache.WriteReq_miss_rate 0.025364 # miss rate for WriteReq accesses 81system.cpu.dcache.WriteReq_misses 1375718 # number of WriteReq misses 82system.cpu.dcache.WriteReq_mshr_hits 1033256 # number of WriteReq MSHR hits 83system.cpu.dcache.WriteReq_mshr_miss_latency 4449944000 # number of WriteReq MSHR miss cycles 84system.cpu.dcache.WriteReq_mshr_miss_rate 0.006314 # mshr miss rate for WriteReq accesses 85system.cpu.dcache.WriteReq_mshr_misses 342462 # number of WriteReq MSHR misses 86system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 87system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 88system.cpu.dcache.avg_refs 167.338700 # Average number of references to valid blocks. 89system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 90system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 91system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93system.cpu.dcache.cache_copies 0 # number of cache copies performed 94system.cpu.dcache.demand_accesses 197693380 # number of demand (read+write) accesses 95system.cpu.dcache.demand_avg_miss_latency 13396.562604 # average overall miss latency 96system.cpu.dcache.demand_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency 97system.cpu.dcache.demand_hits 195246557 # number of demand (read+write) hits 98system.cpu.dcache.demand_miss_latency 32779017500 # number of demand (read+write) miss cycles 99system.cpu.dcache.demand_miss_rate 0.012377 # miss rate for demand accesses 100system.cpu.dcache.demand_misses 2446823 # number of demand (read+write) misses 101system.cpu.dcache.demand_mshr_hits 1250828 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency 10447617000 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_rate 0.006050 # mshr miss rate for demand accesses 104system.cpu.dcache.demand_mshr_misses 1195995 # number of demand (read+write) MSHR misses 105system.cpu.dcache.fast_writes 0 # number of fast writes performed 106system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 107system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 108system.cpu.dcache.occ_blocks::0 4061.060335 # Average occupied blocks per context 109system.cpu.dcache.occ_percent::0 0.991470 # Average percentage of cache occupancy 110system.cpu.dcache.overall_accesses 197693380 # number of overall (read+write) accesses 111system.cpu.dcache.overall_avg_miss_latency 13396.562604 # average overall miss latency 112system.cpu.dcache.overall_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency 113system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 114system.cpu.dcache.overall_hits 195246557 # number of overall hits 115system.cpu.dcache.overall_miss_latency 32779017500 # number of overall miss cycles 116system.cpu.dcache.overall_miss_rate 0.012377 # miss rate for overall accesses 117system.cpu.dcache.overall_misses 2446823 # number of overall misses 118system.cpu.dcache.overall_mshr_hits 1250828 # number of overall MSHR hits 119system.cpu.dcache.overall_mshr_miss_latency 10447617000 # number of overall MSHR miss cycles 120system.cpu.dcache.overall_mshr_miss_rate 0.006050 # mshr miss rate for overall accesses 121system.cpu.dcache.overall_mshr_misses 1195995 # number of overall MSHR misses 122system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 123system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 124system.cpu.dcache.replacements 1191585 # number of replacements 125system.cpu.dcache.sampled_refs 1195681 # Sample count of references to valid blocks. 126system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 127system.cpu.dcache.tagsinuse 4061.060335 # Cycle average of tags in use 128system.cpu.dcache.total_refs 200083704 # Total number of references to valid blocks. 129system.cpu.dcache.warmup_cycle 6358781000 # Cycle when the warmup percentage was hit. 130system.cpu.dcache.writebacks 1064793 # number of writebacks 131system.cpu.decode.BlockedCycles 85842380 # Number of cycles decode is blocked 132system.cpu.decode.BranchMispred 76871 # Number of times decode detected a branch misprediction 133system.cpu.decode.BranchResolved 34367828 # Number of times decode resolved a branch 134system.cpu.decode.DecodedInsts 1126968144 # Number of instructions handled by decode 135system.cpu.decode.IdleCycles 277630014 # Number of cycles decode is idle 136system.cpu.decode.RunCycles 236143765 # Number of cycles decode is running 137system.cpu.decode.SquashCycles 57332647 # Number of cycles decode is squashing 138system.cpu.decode.SquashedInsts 218235 # Number of squashed instructions handled by decode 139system.cpu.decode.UnblockCycles 3971626 # Number of cycles decode is unblocking 140system.cpu.dtb.accesses 0 # DTB accesses 141system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 142system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 144system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 145system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu.dtb.hits 0 # DTB hits 149system.cpu.dtb.inst_accesses 0 # ITB inst accesses 150system.cpu.dtb.inst_hits 0 # ITB inst hits 151system.cpu.dtb.inst_misses 0 # ITB inst misses 152system.cpu.dtb.misses 0 # DTB misses 153system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 155system.cpu.dtb.read_accesses 0 # DTB read accesses 156system.cpu.dtb.read_hits 0 # DTB read hits 157system.cpu.dtb.read_misses 0 # DTB read misses 158system.cpu.dtb.write_accesses 0 # DTB write accesses 159system.cpu.dtb.write_hits 0 # DTB write hits 160system.cpu.dtb.write_misses 0 # DTB write misses 161system.cpu.fetch.Branches 233659814 # Number of branches that fetch encountered 162system.cpu.fetch.CacheLines 132169265 # Number of cache lines fetched 163system.cpu.fetch.Cycles 250543993 # Number of cycles fetch has run and was not squashing or blocked 164system.cpu.fetch.IcacheSquashes 4563312 # Number of outstanding Icache misses that were squashed 165system.cpu.fetch.Insts 1003583241 # Number of instructions fetch has processed 166system.cpu.fetch.MiscStallCycles 3753 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 167system.cpu.fetch.SquashCycles 21196803 # Number of cycles fetch has spent squashing 168system.cpu.fetch.branchRate 0.351124 # Number of branch fetches per cycle 169system.cpu.fetch.icacheStallCycles 132169265 # Number of cycles fetch is stalled on an Icache miss 170system.cpu.fetch.predictedBranches 169030723 # Number of branches that fetch has predicted taken 171system.cpu.fetch.rate 1.508099 # Number of inst fetches per cycle 172system.cpu.fetch.rateDist::samples 660920432 # Number of instructions fetched each cycle (Total) 173system.cpu.fetch.rateDist::mean 1.774764 # Number of instructions fetched each cycle (Total) 174system.cpu.fetch.rateDist::stdev 2.719580 # Number of instructions fetched each cycle (Total) 175system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 176system.cpu.fetch.rateDist::0 410388026 62.09% 62.09% # Number of instructions fetched each cycle (Total) 177system.cpu.fetch.rateDist::1 20297992 3.07% 65.16% # Number of instructions fetched each cycle (Total) 178system.cpu.fetch.rateDist::2 37708836 5.71% 70.87% # Number of instructions fetched each cycle (Total) 179system.cpu.fetch.rateDist::3 39874346 6.03% 76.90% # Number of instructions fetched each cycle (Total) 180system.cpu.fetch.rateDist::4 40511205 6.13% 83.03% # Number of instructions fetched each cycle (Total) 181system.cpu.fetch.rateDist::5 16776062 2.54% 85.57% # Number of instructions fetched each cycle (Total) 182system.cpu.fetch.rateDist::6 18545890 2.81% 88.38% # Number of instructions fetched each cycle (Total) 183system.cpu.fetch.rateDist::7 14106044 2.13% 90.51% # Number of instructions fetched each cycle (Total) 184system.cpu.fetch.rateDist::8 62712031 9.49% 100.00% # Number of instructions fetched each cycle (Total) 185system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 186system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 187system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 188system.cpu.fetch.rateDist::total 660920432 # Number of instructions fetched each cycle (Total) 189system.cpu.fp_regfile_reads 16 # number of floating regfile reads 190system.cpu.icache.ReadReq_accesses 132169265 # number of ReadReq accesses(hits+misses) 191system.cpu.icache.ReadReq_avg_miss_latency 14331.781024 # average ReadReq miss latency 192system.cpu.icache.ReadReq_avg_mshr_miss_latency 10612.450522 # average ReadReq mshr miss latency 193system.cpu.icache.ReadReq_hits 132154341 # number of ReadReq hits 194system.cpu.icache.ReadReq_miss_latency 213887500 # number of ReadReq miss cycles 195system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses 196system.cpu.icache.ReadReq_misses 14924 # number of ReadReq misses 197system.cpu.icache.ReadReq_mshr_hits 1029 # number of ReadReq MSHR hits 198system.cpu.icache.ReadReq_mshr_miss_latency 147460000 # number of ReadReq MSHR miss cycles 199system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses 200system.cpu.icache.ReadReq_mshr_misses 13895 # number of ReadReq MSHR misses 201system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 202system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 203system.cpu.icache.avg_refs 9748.051560 # Average number of references to valid blocks. 204system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 205system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 206system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu.icache.cache_copies 0 # number of cache copies performed 209system.cpu.icache.demand_accesses 132169265 # number of demand (read+write) accesses 210system.cpu.icache.demand_avg_miss_latency 14331.781024 # average overall miss latency 211system.cpu.icache.demand_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency 212system.cpu.icache.demand_hits 132154341 # number of demand (read+write) hits 213system.cpu.icache.demand_miss_latency 213887500 # number of demand (read+write) miss cycles 214system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses 215system.cpu.icache.demand_misses 14924 # number of demand (read+write) misses 216system.cpu.icache.demand_mshr_hits 1029 # number of demand (read+write) MSHR hits 217system.cpu.icache.demand_mshr_miss_latency 147460000 # number of demand (read+write) MSHR miss cycles 218system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses 219system.cpu.icache.demand_mshr_misses 13895 # number of demand (read+write) MSHR misses 220system.cpu.icache.fast_writes 0 # number of fast writes performed 221system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 222system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 223system.cpu.icache.occ_blocks::0 1053.520934 # Average occupied blocks per context 224system.cpu.icache.occ_percent::0 0.514415 # Average percentage of cache occupancy 225system.cpu.icache.overall_accesses 132169265 # number of overall (read+write) accesses 226system.cpu.icache.overall_avg_miss_latency 14331.781024 # average overall miss latency 227system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency 228system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 229system.cpu.icache.overall_hits 132154341 # number of overall hits 230system.cpu.icache.overall_miss_latency 213887500 # number of overall miss cycles 231system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses 232system.cpu.icache.overall_misses 14924 # number of overall misses 233system.cpu.icache.overall_mshr_hits 1029 # number of overall MSHR hits 234system.cpu.icache.overall_mshr_miss_latency 147460000 # number of overall MSHR miss cycles 235system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses 236system.cpu.icache.overall_mshr_misses 13895 # number of overall MSHR misses 237system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 238system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 239system.cpu.icache.replacements 11791 # number of replacements 240system.cpu.icache.sampled_refs 13557 # Sample count of references to valid blocks. 241system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 242system.cpu.icache.tagsinuse 1053.520934 # Cycle average of tags in use 243system.cpu.icache.total_refs 132154335 # Total number of references to valid blocks. 244system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 245system.cpu.icache.writebacks 4 # number of writebacks 246system.cpu.idleCycles 4542007 # Total number of cycles that the CPU has spent unscheduled due to idling 247system.cpu.iew.branchMispredicts 25100140 # Number of branch mispredicts detected at execute 248system.cpu.iew.exec_branches 142399885 # Number of branches executed 249system.cpu.iew.exec_nop 9420990 # number of nop insts executed 250system.cpu.iew.exec_rate 1.051214 # Inst execution rate 251system.cpu.iew.exec_refs 220838036 # number of memory reference insts executed 252system.cpu.iew.exec_stores 66554903 # Number of stores executed 253system.cpu.iew.exec_swp 0 # number of swp insts executed 254system.cpu.iew.iewBlockCycles 2947924 # Number of cycles IEW is blocking 255system.cpu.iew.iewDispLoadInsts 196892006 # Number of dispatched load instructions 256system.cpu.iew.iewDispNonSpecInsts 2816035 # Number of dispatched non-speculative instructions 257system.cpu.iew.iewDispSquashedInsts 18822753 # Number of squashed instructions skipped by dispatch 258system.cpu.iew.iewDispStoreInsts 114373867 # Number of dispatched store instructions 259system.cpu.iew.iewDispatchedInsts 956606524 # Number of instructions dispatched to IQ 260system.cpu.iew.iewExecLoadInsts 154283133 # Number of load instructions executed 261system.cpu.iew.iewExecSquashedInsts 25300490 # Number of squashed instructions skipped in execute 262system.cpu.iew.iewExecutedInsts 699543688 # Number of executed instructions 263system.cpu.iew.iewIQFullEvents 130928 # Number of times the IQ has become full, causing a stall 264system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 265system.cpu.iew.iewLSQFullEvents 7156 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.iewSquashCycles 57332647 # Number of cycles IEW is squashing 267system.cpu.iew.iewUnblockCycles 209223 # Number of cycles IEW is unblocking 268system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 269system.cpu.iew.lsq.thread.0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked 270system.cpu.iew.lsq.thread.0.forwLoads 5626597 # Number of loads that had data forwarded from stores 271system.cpu.iew.lsq.thread.0.ignoredResponses 13730 # Number of memory responses ignored because the instruction is squashed 272system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 273system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 274system.cpu.iew.lsq.thread.0.memOrderViolation 241250 # Number of memory ordering violations 275system.cpu.iew.lsq.thread.0.rescheduledLoads 24511 # Number of loads that were rescheduled 276system.cpu.iew.lsq.thread.0.squashedLoads 70118828 # Number of loads squashed 277system.cpu.iew.lsq.thread.0.squashedStores 56769769 # Number of stores squashed 278system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations 279system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly 280system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.wb_consumers 782273717 # num instructions consuming a value 282system.cpu.iew.wb_count 680637923 # cumulative count of insts written-back 283system.cpu.iew.wb_fanout 0.486169 # average fanout of values written-back 284system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 285system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 286system.cpu.iew.wb_producers 380317186 # num instructions producing a value 287system.cpu.iew.wb_rate 1.022804 # insts written-back per cycle 288system.cpu.iew.wb_sent 691183006 # cumulative count of insts sent to commit 289system.cpu.int_regfile_reads 1609052037 # number of integer regfile reads 290system.cpu.int_regfile_writes 524399004 # number of integer regfile writes 291system.cpu.ipc 0.861570 # IPC: Instructions Per Cycle 292system.cpu.ipc_total 0.861570 # IPC: Total IPC of All Threads 293system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 294system.cpu.iq.FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued 295system.cpu.iq.FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued 296system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued 297system.cpu.iq.FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued 298system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued 299system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued 300system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued 301system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued 302system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued 303system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued 304system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued 305system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued 306system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued 307system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued 308system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued 309system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued 310system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued 311system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued 312system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued 313system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued 314system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued 316system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued 317system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued 318system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued 319system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued 323system.cpu.iq.FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued 324system.cpu.iq.FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued 325system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 326system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 327system.cpu.iq.FU_type_0::total 724844178 # Type of FU issued 328system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses 329system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads 330system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 331system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes 332system.cpu.iq.fu_busy_cnt 8619148 # FU busy when requested 333system.cpu.iq.fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst) 334system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 335system.cpu.iq.fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available 336system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available 364system.cpu.iq.fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available 365system.cpu.iq.fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available 366system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 367system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 368system.cpu.iq.int_alu_accesses 733463200 # Number of integer alu accesses 369system.cpu.iq.int_inst_queue_reads 2121563604 # Number of integer instruction queue reads 370system.cpu.iq.int_inst_queue_wakeup_accesses 680637907 # Number of integer instruction queue wakeup accesses 371system.cpu.iq.int_inst_queue_writes 1319150008 # Number of integer instruction queue writes 372system.cpu.iq.iqInstsAdded 942508573 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqInstsIssued 724844178 # Number of instructions issued 374system.cpu.iq.iqNonSpecInstsAdded 4676961 # Number of non-speculative instructions added to the IQ 375system.cpu.iq.iqSquashedInstsExamined 371760121 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedInstsIssued 2335916 # Number of squashed instructions issued 377system.cpu.iq.iqSquashedNonSpecRemoved 799068 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.iqSquashedOperandsExamined 680735331 # Number of squashed operands that are examined and possibly removed from graph 379system.cpu.iq.issued_per_cycle::samples 660920432 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 1.096719 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::total 660920432 # Number of insts issued each cycle 396system.cpu.iq.rate 1.089234 # Inst issue rate 397system.cpu.itb.accesses 0 # DTB accesses 398system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 399system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 401system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu.itb.hits 0 # DTB hits 406system.cpu.itb.inst_accesses 0 # ITB inst accesses 407system.cpu.itb.inst_hits 0 # ITB inst hits 408system.cpu.itb.inst_misses 0 # ITB inst misses 409system.cpu.itb.misses 0 # DTB misses 410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.read_accesses 0 # DTB read accesses 413system.cpu.itb.read_hits 0 # DTB read hits 414system.cpu.itb.read_misses 0 # DTB read misses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.write_hits 0 # DTB write hits 417system.cpu.itb.write_misses 0 # DTB write misses 418system.cpu.l2cache.ReadExReq_accesses 342473 # number of ReadExReq accesses(hits+misses) 419system.cpu.l2cache.ReadExReq_avg_miss_latency 34244.416047 # average ReadExReq miss latency 420system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.822429 # average ReadExReq mshr miss latency 421system.cpu.l2cache.ReadExReq_hits 231351 # number of ReadExReq hits 422system.cpu.l2cache.ReadExReq_miss_latency 3805308000 # number of ReadExReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_rate 0.324469 # miss rate for ReadExReq accesses 424system.cpu.l2cache.ReadExReq_misses 111122 # number of ReadExReq misses 425system.cpu.l2cache.ReadExReq_mshr_miss_latency 3445429000 # number of ReadExReq MSHR miss cycles 426system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.324469 # mshr miss rate for ReadExReq accesses 427system.cpu.l2cache.ReadExReq_mshr_misses 111122 # number of ReadExReq MSHR misses 428system.cpu.l2cache.ReadReq_accesses 866749 # number of ReadReq accesses(hits+misses) 429system.cpu.l2cache.ReadReq_avg_miss_latency 34192.097787 # average ReadReq miss latency 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.522397 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_hits 741784 # number of ReadReq hits 432system.cpu.l2cache.ReadReq_miss_latency 4272815500 # number of ReadReq miss cycles 433system.cpu.l2cache.ReadReq_miss_rate 0.144177 # miss rate for ReadReq accesses 434system.cpu.l2cache.ReadReq_misses 124965 # number of ReadReq misses 435system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits 436system.cpu.l2cache.ReadReq_mshr_miss_latency 3876795000 # number of ReadReq MSHR miss cycles 437system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144161 # mshr miss rate for ReadReq accesses 438system.cpu.l2cache.ReadReq_mshr_misses 124951 # number of ReadReq MSHR misses 439system.cpu.l2cache.UpgradeReq_accesses 298 # number of UpgradeReq accesses(hits+misses) 440system.cpu.l2cache.UpgradeReq_avg_miss_latency 4635.416667 # average UpgradeReq miss latency 441system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31057.291667 # average UpgradeReq mshr miss latency 442system.cpu.l2cache.UpgradeReq_hits 202 # number of UpgradeReq hits 443system.cpu.l2cache.UpgradeReq_miss_latency 445000 # number of UpgradeReq miss cycles 444system.cpu.l2cache.UpgradeReq_miss_rate 0.322148 # miss rate for UpgradeReq accesses 445system.cpu.l2cache.UpgradeReq_misses 96 # number of UpgradeReq misses 446system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2981500 # number of UpgradeReq MSHR miss cycles 447system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.322148 # mshr miss rate for UpgradeReq accesses 448system.cpu.l2cache.UpgradeReq_mshr_misses 96 # number of UpgradeReq MSHR misses 449system.cpu.l2cache.Writeback_accesses 1064797 # number of Writeback accesses(hits+misses) 450system.cpu.l2cache.Writeback_hits 1064797 # number of Writeback hits 451system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 452system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 453system.cpu.l2cache.avg_refs 6.452091 # Average number of references to valid blocks. 454system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 455system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 456system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 457system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 458system.cpu.l2cache.cache_copies 0 # number of cache copies performed 459system.cpu.l2cache.demand_accesses 1209222 # number of demand (read+write) accesses 460system.cpu.l2cache.demand_avg_miss_latency 34216.723072 # average overall miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency 462system.cpu.l2cache.demand_hits 973135 # number of demand (read+write) hits 463system.cpu.l2cache.demand_miss_latency 8078123500 # number of demand (read+write) miss cycles 464system.cpu.l2cache.demand_miss_rate 0.195239 # miss rate for demand accesses 465system.cpu.l2cache.demand_misses 236087 # number of demand (read+write) misses 466system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits 467system.cpu.l2cache.demand_mshr_miss_latency 7322224000 # number of demand (read+write) MSHR miss cycles 468system.cpu.l2cache.demand_mshr_miss_rate 0.195227 # mshr miss rate for demand accesses 469system.cpu.l2cache.demand_mshr_misses 236073 # number of demand (read+write) MSHR misses 470system.cpu.l2cache.fast_writes 0 # number of fast writes performed 471system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 472system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 473system.cpu.l2cache.occ_blocks::0 7099.133966 # Average occupied blocks per context 474system.cpu.l2cache.occ_blocks::1 13800.334539 # Average occupied blocks per context 475system.cpu.l2cache.occ_percent::0 0.216648 # Average percentage of cache occupancy 476system.cpu.l2cache.occ_percent::1 0.421153 # Average percentage of cache occupancy 477system.cpu.l2cache.overall_accesses 1209222 # number of overall (read+write) accesses 478system.cpu.l2cache.overall_avg_miss_latency 34216.723072 # average overall miss latency 479system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency 480system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 481system.cpu.l2cache.overall_hits 973135 # number of overall hits 482system.cpu.l2cache.overall_miss_latency 8078123500 # number of overall miss cycles 483system.cpu.l2cache.overall_miss_rate 0.195239 # miss rate for overall accesses 484system.cpu.l2cache.overall_misses 236087 # number of overall misses 485system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits 486system.cpu.l2cache.overall_mshr_miss_latency 7322224000 # number of overall MSHR miss cycles 487system.cpu.l2cache.overall_mshr_miss_rate 0.195227 # mshr miss rate for overall accesses 488system.cpu.l2cache.overall_mshr_misses 236073 # number of overall MSHR misses 489system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 490system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 491system.cpu.l2cache.replacements 217008 # number of replacements 492system.cpu.l2cache.sampled_refs 237229 # Sample count of references to valid blocks. 493system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 494system.cpu.l2cache.tagsinuse 20899.468505 # Cycle average of tags in use 495system.cpu.l2cache.total_refs 1530623 # Total number of references to valid blocks. 496system.cpu.l2cache.warmup_cycle 239794586000 # Cycle when the warmup percentage was hit. 497system.cpu.l2cache.writebacks 171527 # number of writebacks 498system.cpu.memDep0.conflictingLoads 54793834 # Number of conflicting loads. 499system.cpu.memDep0.conflictingStores 61680450 # Number of conflicting stores. 500system.cpu.memDep0.insertedLoads 196892006 # Number of loads inserted to the mem dependence unit. 501system.cpu.memDep0.insertedStores 114373867 # Number of stores inserted to the mem dependence unit. 502system.cpu.misc_regfile_reads 1238278234 # number of misc regfile reads 503system.cpu.misc_regfile_writes 4464326 # number of misc regfile writes 504system.cpu.numCycles 665462439 # number of cpu cycles simulated 505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 506system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 507system.cpu.rename.BlockCycles 11783884 # Number of cycles rename is blocking 508system.cpu.rename.CommittedMaps 448493735 # Number of HB maps that are committed 509system.cpu.rename.IQFullEvents 9081964 # Number of times rename has blocked due to IQ full 510system.cpu.rename.IdleCycles 293899856 # Number of cycles rename is idle 511system.cpu.rename.LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full 512system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full 513system.cpu.rename.RenameLookups 2673538298 # Number of register rename lookups that rename has made 514system.cpu.rename.RenamedInsts 1068521543 # Number of instructions processed by rename 515system.cpu.rename.RenamedOperands 798521782 # Number of destination operands rename has renamed 516system.cpu.rename.RunCycles 223635059 # Number of cycles rename is running 517system.cpu.rename.SquashCycles 57332647 # Number of cycles rename is squashing 518system.cpu.rename.UnblockCycles 24492193 # Number of cycles rename is unblocking 519system.cpu.rename.UndoneMaps 350028044 # Number of HB maps that are undone due to squashing 520system.cpu.rename.fp_rename_lookups 1141 # Number of floating rename lookups 521system.cpu.rename.int_rename_lookups 2673537157 # Number of integer rename lookups 522system.cpu.rename.serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst 523system.cpu.rename.serializingInsts 2837350 # count of serializing insts renamed 524system.cpu.rename.skidInsts 62579735 # count of insts added to the skid buffer 525system.cpu.rename.tempSerializingInsts 2837280 # count of temporary serializing insts renamed 526system.cpu.rob.rob_reads 1553332004 # The number of ROB reads 527system.cpu.rob.rob_writes 1970603439 # The number of ROB writes 528system.cpu.timesIdled 108463 # Number of times that the entire CPU went into an idle state and unscheduled itself 529system.cpu.workload.num_syscalls 548 # Number of system calls 530 531---------- End Simulation Statistics ---------- 532