stats.txt revision 7860
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 95936 # Simulator instruction rate (inst/s) 4host_mem_usage 255716 # Number of bytes of host memory used 5host_seconds 5851.87 # Real time elapsed on the host 6host_tick_rate 62464794 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 561403855 # Number of instructions simulated 9sim_seconds 0.365536 # Number of seconds simulated 10sim_ticks 365535797000 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 140412857 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 174405829 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 15516134 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 191856696 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 191856696 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 110089780 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 3543910 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 660408748 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.850085 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.259950 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0 341979114 51.78% 51.78% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1 195474584 29.60% 81.38% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2 65236254 9.88% 91.26% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3 25100650 3.80% 95.06% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4 18282819 2.77% 97.83% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5 7231568 1.10% 98.92% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6 2404526 0.36% 99.29% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7 1155323 0.17% 99.46% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 3543910 0.54% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle 39system.cpu.commit.COM:count 561403855 # Number of instructions committed 40system.cpu.commit.COM:loads 128127024 # Number of loads committed 41system.cpu.commit.COM:membars 0 # Number of memory barriers committed 42system.cpu.commit.COM:refs 184987501 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 27361456 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 561403855 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 157189 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 399600068 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 561403855 # Number of Instructions Simulated 49system.cpu.committedInsts_total 561403855 # Number of Instructions Simulated 50system.cpu.cpi 1.302220 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 1.302220 # CPI: Total CPI of All Threads 52system.cpu.dcache.ReadReq_accesses 149781892 # number of ReadReq accesses(hits+misses) 53system.cpu.dcache.ReadReq_avg_miss_latency 10115.689557 # average ReadReq miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6757.918127 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_hits 148783591 # number of ReadReq hits 56system.cpu.dcache.ReadReq_miss_latency 10098503000 # number of ReadReq miss cycles 57system.cpu.dcache.ReadReq_miss_rate 0.006665 # miss rate for ReadReq accesses 58system.cpu.dcache.ReadReq_misses 998301 # number of ReadReq misses 59system.cpu.dcache.ReadReq_mshr_hits 174053 # number of ReadReq MSHR hits 60system.cpu.dcache.ReadReq_mshr_miss_latency 5570200500 # number of ReadReq MSHR miss cycles 61system.cpu.dcache.ReadReq_mshr_miss_rate 0.005503 # mshr miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_mshr_misses 824248 # number of ReadReq MSHR misses 63system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) 64system.cpu.dcache.WriteReq_avg_miss_latency 14769.740800 # average WriteReq miss latency 65system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13602.051977 # average WriteReq mshr miss latency 66system.cpu.dcache.WriteReq_hits 54444667 # number of WriteReq hits 67system.cpu.dcache.WriteReq_miss_latency 18952236000 # number of WriteReq miss cycles 68system.cpu.dcache.WriteReq_miss_rate 0.023026 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses 1283180 # number of WriteReq misses 70system.cpu.dcache.WriteReq_mshr_hits 935759 # number of WriteReq MSHR hits 71system.cpu.dcache.WriteReq_mshr_miss_latency 4725638500 # number of WriteReq MSHR miss cycles 72system.cpu.dcache.WriteReq_mshr_miss_rate 0.006234 # mshr miss rate for WriteReq accesses 73system.cpu.dcache.WriteReq_mshr_misses 347421 # number of WriteReq MSHR misses 74system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.dcache.avg_refs 173.452238 # Average number of references to valid blocks. 77system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 79system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81system.cpu.dcache.cache_copies 0 # number of cache copies performed 82system.cpu.dcache.demand_accesses 205509739 # number of demand (read+write) accesses 83system.cpu.dcache.demand_avg_miss_latency 12733.281145 # average overall miss latency 84system.cpu.dcache.demand_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency 85system.cpu.dcache.demand_hits 203228258 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency 29050739000 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_rate 0.011102 # miss rate for demand accesses 88system.cpu.dcache.demand_misses 2281481 # number of demand (read+write) misses 89system.cpu.dcache.demand_mshr_hits 1109812 # number of demand (read+write) MSHR hits 90system.cpu.dcache.demand_mshr_miss_latency 10295839000 # number of demand (read+write) MSHR miss cycles 91system.cpu.dcache.demand_mshr_miss_rate 0.005701 # mshr miss rate for demand accesses 92system.cpu.dcache.demand_mshr_misses 1171669 # number of demand (read+write) MSHR misses 93system.cpu.dcache.fast_writes 0 # number of fast writes performed 94system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 95system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.cpu.dcache.occ_%::0 0.992538 # Average percentage of cache occupancy 97system.cpu.dcache.occ_blocks::0 4065.435193 # Average occupied blocks per context 98system.cpu.dcache.overall_accesses 205509739 # number of overall (read+write) accesses 99system.cpu.dcache.overall_avg_miss_latency 12733.281145 # average overall miss latency 100system.cpu.dcache.overall_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency 101system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 102system.cpu.dcache.overall_hits 203228258 # number of overall hits 103system.cpu.dcache.overall_miss_latency 29050739000 # number of overall miss cycles 104system.cpu.dcache.overall_miss_rate 0.011102 # miss rate for overall accesses 105system.cpu.dcache.overall_misses 2281481 # number of overall misses 106system.cpu.dcache.overall_mshr_hits 1109812 # number of overall MSHR hits 107system.cpu.dcache.overall_mshr_miss_latency 10295839000 # number of overall MSHR miss cycles 108system.cpu.dcache.overall_mshr_miss_rate 0.005701 # mshr miss rate for overall accesses 109system.cpu.dcache.overall_mshr_misses 1171669 # number of overall MSHR misses 110system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 111system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 112system.cpu.dcache.replacements 1167571 # number of replacements 113system.cpu.dcache.sampled_refs 1171667 # Sample count of references to valid blocks. 114system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 115system.cpu.dcache.tagsinuse 4065.435193 # Cycle average of tags in use 116system.cpu.dcache.total_refs 203228263 # Total number of references to valid blocks. 117system.cpu.dcache.warmup_cycle 6053773000 # Cycle when the warmup percentage was hit. 118system.cpu.dcache.writebacks 1048319 # number of writebacks 119system.cpu.decode.DECODE:BlockedCycles 23914899 # Number of cycles decode is blocked 120system.cpu.decode.DECODE:DecodedInsts 1082691365 # Number of instructions handled by decode 121system.cpu.decode.DECODE:IdleCycles 293791436 # Number of cycles decode is idle 122system.cpu.decode.DECODE:RunCycles 339619753 # Number of cycles decode is running 123system.cpu.decode.DECODE:SquashCycles 66259738 # Number of cycles decode is squashing 124system.cpu.decode.DECODE:UnblockCycles 3082660 # Number of cycles decode is unblocking 125system.cpu.dtb.accesses 0 # DTB accesses 126system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 127system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 128system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 129system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 130system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 133system.cpu.dtb.hits 0 # DTB hits 134system.cpu.dtb.inst_accesses 0 # ITB inst accesses 135system.cpu.dtb.inst_hits 0 # ITB inst hits 136system.cpu.dtb.inst_misses 0 # ITB inst misses 137system.cpu.dtb.misses 0 # DTB misses 138system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 140system.cpu.dtb.read_accesses 0 # DTB read accesses 141system.cpu.dtb.read_hits 0 # DTB read hits 142system.cpu.dtb.read_misses 0 # DTB read misses 143system.cpu.dtb.write_accesses 0 # DTB write accesses 144system.cpu.dtb.write_hits 0 # DTB write hits 145system.cpu.dtb.write_misses 0 # DTB write misses 146system.cpu.fetch.Branches 191856696 # Number of branches that fetch encountered 147system.cpu.fetch.CacheLines 122785155 # Number of cache lines fetched 148system.cpu.fetch.Cycles 351913139 # Number of cycles fetch has run and was not squashing or blocked 149system.cpu.fetch.IcacheSquashes 3732953 # Number of outstanding Icache misses that were squashed 150system.cpu.fetch.Insts 938955668 # Number of instructions fetch has processed 151system.cpu.fetch.MiscStallCycles 5443516 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 152system.cpu.fetch.SquashCycles 27647770 # Number of cycles fetch has spent squashing 153system.cpu.fetch.branchRate 0.262432 # Number of branch fetches per cycle 154system.cpu.fetch.icacheStallCycles 122785155 # Number of cycles fetch is stalled on an Icache miss 155system.cpu.fetch.predictedBranches 140412857 # Number of branches that fetch has predicted taken 156system.cpu.fetch.rate 1.284355 # Number of inst fetches per cycle 157system.cpu.fetch.rateDist::samples 726668486 # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::mean 1.538402 # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::stdev 2.455586 # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::0 375480392 51.67% 51.67% # Number of instructions fetched each cycle (Total) 162system.cpu.fetch.rateDist::1 167711007 23.08% 74.75% # Number of instructions fetched each cycle (Total) 163system.cpu.fetch.rateDist::2 28511073 3.92% 78.67% # Number of instructions fetched each cycle (Total) 164system.cpu.fetch.rateDist::3 34539499 4.75% 83.43% # Number of instructions fetched each cycle (Total) 165system.cpu.fetch.rateDist::4 26732700 3.68% 87.11% # Number of instructions fetched each cycle (Total) 166system.cpu.fetch.rateDist::5 10963415 1.51% 88.62% # Number of instructions fetched each cycle (Total) 167system.cpu.fetch.rateDist::6 11441350 1.57% 90.19% # Number of instructions fetched each cycle (Total) 168system.cpu.fetch.rateDist::7 11151746 1.53% 91.72% # Number of instructions fetched each cycle (Total) 169system.cpu.fetch.rateDist::8 60137304 8.28% 100.00% # Number of instructions fetched each cycle (Total) 170system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 171system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 172system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 173system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total) 174system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses) 175system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency 177system.cpu.icache.ReadReq_hits 122768369 # number of ReadReq hits 178system.cpu.icache.ReadReq_miss_latency 223842500 # number of ReadReq miss cycles 179system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_misses 16786 # number of ReadReq misses 181system.cpu.icache.ReadReq_mshr_hits 916 # number of ReadReq MSHR hits 182system.cpu.icache.ReadReq_mshr_miss_latency 153275000 # number of ReadReq MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses 184system.cpu.icache.ReadReq_mshr_misses 15870 # number of ReadReq MSHR misses 185system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 187system.cpu.icache.avg_refs 7736.852092 # Average number of references to valid blocks. 188system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 189system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 190system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 191system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 192system.cpu.icache.cache_copies 0 # number of cache copies performed 193system.cpu.icache.demand_accesses 122785155 # number of demand (read+write) accesses 194system.cpu.icache.demand_avg_miss_latency 13335.070892 # average overall miss latency 195system.cpu.icache.demand_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency 196system.cpu.icache.demand_hits 122768369 # number of demand (read+write) hits 197system.cpu.icache.demand_miss_latency 223842500 # number of demand (read+write) miss cycles 198system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses 199system.cpu.icache.demand_misses 16786 # number of demand (read+write) misses 200system.cpu.icache.demand_mshr_hits 916 # number of demand (read+write) MSHR hits 201system.cpu.icache.demand_mshr_miss_latency 153275000 # number of demand (read+write) MSHR miss cycles 202system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses 203system.cpu.icache.demand_mshr_misses 15870 # number of demand (read+write) MSHR misses 204system.cpu.icache.fast_writes 0 # number of fast writes performed 205system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 206system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 207system.cpu.icache.occ_%::0 0.542928 # Average percentage of cache occupancy 208system.cpu.icache.occ_blocks::0 1111.916228 # Average occupied blocks per context 209system.cpu.icache.overall_accesses 122785155 # number of overall (read+write) accesses 210system.cpu.icache.overall_avg_miss_latency 13335.070892 # average overall miss latency 211system.cpu.icache.overall_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency 212system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 213system.cpu.icache.overall_hits 122768369 # number of overall hits 214system.cpu.icache.overall_miss_latency 223842500 # number of overall miss cycles 215system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses 216system.cpu.icache.overall_misses 16786 # number of overall misses 217system.cpu.icache.overall_mshr_hits 916 # number of overall MSHR hits 218system.cpu.icache.overall_mshr_miss_latency 153275000 # number of overall MSHR miss cycles 219system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses 220system.cpu.icache.overall_mshr_misses 15870 # number of overall MSHR misses 221system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 222system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 223system.cpu.icache.replacements 14020 # number of replacements 224system.cpu.icache.sampled_refs 15868 # Sample count of references to valid blocks. 225system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 226system.cpu.icache.tagsinuse 1111.916228 # Cycle average of tags in use 227system.cpu.icache.total_refs 122768369 # Total number of references to valid blocks. 228system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 229system.cpu.icache.writebacks 0 # number of writebacks 230system.cpu.idleCycles 4403109 # Total number of cycles that the CPU has spent unscheduled due to idling 231system.cpu.iew.EXEC:branches 125406817 # Number of branches executed 232system.cpu.iew.EXEC:nop 0 # number of nop insts executed 233system.cpu.iew.EXEC:rate 0.996154 # Inst execution rate 234system.cpu.iew.EXEC:refs 229537979 # number of memory reference insts executed 235system.cpu.iew.EXEC:stores 71989836 # Number of stores executed 236system.cpu.iew.EXEC:swp 0 # number of swp insts executed 237system.cpu.iew.WB:consumers 715317405 # num instructions consuming a value 238system.cpu.iew.WB:count 674936623 # cumulative count of insts written-back 239system.cpu.iew.WB:fanout 0.509545 # average fanout of values written-back 240system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 241system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 242system.cpu.iew.WB:producers 364486134 # num instructions producing a value 243system.cpu.iew.WB:rate 0.923215 # insts written-back per cycle 244system.cpu.iew.WB:sent 715720315 # cumulative count of insts sent to commit 245system.cpu.iew.branchMispredicts 30103584 # Number of branch mispredicts detected at execute 246system.cpu.iew.iewBlockCycles 2644883 # Number of cycles IEW is blocking 247system.cpu.iew.iewDispLoadInsts 200154824 # Number of dispatched load instructions 248system.cpu.iew.iewDispNonSpecInsts 162257 # Number of dispatched non-speculative instructions 249system.cpu.iew.iewDispSquashedInsts 12097440 # Number of squashed instructions skipped by dispatch 250system.cpu.iew.iewDispStoreInsts 140083731 # Number of dispatched store instructions 251system.cpu.iew.iewDispatchedInsts 960991852 # Number of instructions dispatched to IQ 252system.cpu.iew.iewExecLoadInsts 157548143 # Number of load instructions executed 253system.cpu.iew.iewExecSquashedInsts 31983856 # Number of squashed instructions skipped in execute 254system.cpu.iew.iewExecutedInsts 728259959 # Number of executed instructions 255system.cpu.iew.iewIQFullEvents 123835 # Number of times the IQ has become full, causing a stall 256system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 257system.cpu.iew.iewLSQFullEvents 3633 # Number of times the LSQ has become full, causing a stall 258system.cpu.iew.iewSquashCycles 66259738 # Number of cycles IEW is squashing 259system.cpu.iew.iewUnblockCycles 187555 # Number of cycles IEW is unblocking 260system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 261system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 262system.cpu.iew.lsq.thread.0.forwLoads 4454393 # Number of loads that had data forwarded from stores 263system.cpu.iew.lsq.thread.0.ignoredResponses 9891 # Number of memory responses ignored because the instruction is squashed 264system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 265system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 266system.cpu.iew.lsq.thread.0.memOrderViolation 352056 # Number of memory ordering violations 267system.cpu.iew.lsq.thread.0.rescheduledLoads 12768 # Number of loads that were rescheduled 268system.cpu.iew.lsq.thread.0.squashedLoads 72027799 # Number of loads squashed 269system.cpu.iew.lsq.thread.0.squashedStores 83223254 # Number of stores squashed 270system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations 271system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly 272system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly 273system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle 274system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads 275system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 276system.cpu.iq.ISSUE:FU_type_0::IntAlu 514982916 67.74% 67.74% # Type of FU issued 277system.cpu.iq.ISSUE:FU_type_0::IntMult 348808 0.05% 67.79% # Type of FU issued 278system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.79% # Type of FU issued 279system.cpu.iq.ISSUE:FU_type_0::FloatAdd 120 0.00% 67.79% # Type of FU issued 280system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued 281system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued 282system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued 283system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued 284system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued 285system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued 286system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued 287system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued 288system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued 289system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued 290system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued 291system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued 292system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued 293system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued 294system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued 295system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued 296system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued 297system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued 298system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued 299system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued 300system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued 301system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.79% # Type of FU issued 302system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued 303system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued 304system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued 305system.cpu.iq.ISSUE:FU_type_0::MemRead 162349838 21.35% 89.14% # Type of FU issued 306system.cpu.iq.ISSUE:FU_type_0::MemWrite 82562130 10.86% 100.00% # Type of FU issued 307system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 308system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 309system.cpu.iq.ISSUE:FU_type_0::total 760243815 # Type of FU issued 310system.cpu.iq.ISSUE:fu_busy_cnt 11461228 # FU busy when requested 311system.cpu.iq.ISSUE:fu_busy_rate 0.015076 # FU busy rate (busy events/executed inst) 312system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 313system.cpu.iq.ISSUE:fu_full::IntAlu 133776 1.17% 1.17% # attempts to use FU when none available 314system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available 315system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available 316system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available 317system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available 318system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available 319system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available 320system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available 321system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available 322system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available 323system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available 324system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available 325system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available 326system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available 327system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available 328system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available 329system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available 330system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available 331system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available 332system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available 333system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available 334system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available 335system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available 336system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available 337system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available 338system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available 339system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available 340system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available 341system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available 342system.cpu.iq.ISSUE:fu_full::MemRead 5928179 51.72% 52.89% # attempts to use FU when none available 343system.cpu.iq.ISSUE:fu_full::MemWrite 5399273 47.11% 100.00% # attempts to use FU when none available 344system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 346system.cpu.iq.ISSUE:issued_per_cycle::samples 726668486 # Number of insts issued each cycle 347system.cpu.iq.ISSUE:issued_per_cycle::mean 1.046204 # Number of insts issued each cycle 348system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384447 # Number of insts issued each cycle 349system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 350system.cpu.iq.ISSUE:issued_per_cycle::0 339626130 46.74% 46.74% # Number of insts issued each cycle 351system.cpu.iq.ISSUE:issued_per_cycle::1 195069580 26.84% 73.58% # Number of insts issued each cycle 352system.cpu.iq.ISSUE:issued_per_cycle::2 101922937 14.03% 87.61% # Number of insts issued each cycle 353system.cpu.iq.ISSUE:issued_per_cycle::3 40650184 5.59% 93.20% # Number of insts issued each cycle 354system.cpu.iq.ISSUE:issued_per_cycle::4 24674774 3.40% 96.60% # Number of insts issued each cycle 355system.cpu.iq.ISSUE:issued_per_cycle::5 15399691 2.12% 98.72% # Number of insts issued each cycle 356system.cpu.iq.ISSUE:issued_per_cycle::6 3388059 0.47% 99.18% # Number of insts issued each cycle 357system.cpu.iq.ISSUE:issued_per_cycle::7 4145144 0.57% 99.75% # Number of insts issued each cycle 358system.cpu.iq.ISSUE:issued_per_cycle::8 1791987 0.25% 100.00% # Number of insts issued each cycle 359system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 360system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 361system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 362system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle 363system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate 364system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued 366system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ 367system.cpu.iq.iqSquashedInstsExamined 389023744 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedInstsIssued 7997557 # Number of squashed instructions issued 369system.cpu.iq.iqSquashedNonSpecRemoved 5068 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.iqSquashedOperandsExamined 710003502 # Number of squashed operands that are examined and possibly removed from graph 371system.cpu.itb.accesses 0 # DTB accesses 372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 376system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 377system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.itb.hits 0 # DTB hits 380system.cpu.itb.inst_accesses 0 # ITB inst accesses 381system.cpu.itb.inst_hits 0 # ITB inst hits 382system.cpu.itb.inst_misses 0 # ITB inst misses 383system.cpu.itb.misses 0 # DTB misses 384system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 386system.cpu.itb.read_accesses 0 # DTB read accesses 387system.cpu.itb.read_hits 0 # DTB read hits 388system.cpu.itb.read_misses 0 # DTB read misses 389system.cpu.itb.write_accesses 0 # DTB write accesses 390system.cpu.itb.write_hits 0 # DTB write hits 391system.cpu.itb.write_misses 0 # DTB write misses 392system.cpu.l2cache.ReadExReq_accesses 347847 # number of ReadExReq accesses(hits+misses) 393system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.310886 # average ReadExReq miss latency 394system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.170745 # average ReadExReq mshr miss latency 395system.cpu.l2cache.ReadExReq_hits 228324 # number of ReadExReq hits 396system.cpu.l2cache.ReadExReq_miss_latency 4094178000 # number of ReadExReq miss cycles 397system.cpu.l2cache.ReadExReq_miss_rate 0.343608 # miss rate for ReadExReq accesses 398system.cpu.l2cache.ReadExReq_misses 119523 # number of ReadExReq misses 399system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705711500 # number of ReadExReq MSHR miss cycles 400system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343608 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_mshr_misses 119523 # number of ReadExReq MSHR misses 402system.cpu.l2cache.ReadReq_accesses 839688 # number of ReadReq accesses(hits+misses) 403system.cpu.l2cache.ReadReq_avg_miss_latency 34183.859863 # average ReadReq miss latency 404system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.526653 # average ReadReq mshr miss latency 405system.cpu.l2cache.ReadReq_hits 724943 # number of ReadReq hits 406system.cpu.l2cache.ReadReq_miss_latency 3922427000 # number of ReadReq miss cycles 407system.cpu.l2cache.ReadReq_miss_rate 0.136652 # miss rate for ReadReq accesses 408system.cpu.l2cache.ReadReq_misses 114745 # number of ReadReq misses 409system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits 410system.cpu.l2cache.ReadReq_mshr_miss_latency 3558405000 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadReq_mshr_miss_rate 0.136616 # mshr miss rate for ReadReq accesses 412system.cpu.l2cache.ReadReq_mshr_misses 114715 # number of ReadReq MSHR misses 413system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) 414system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits 415system.cpu.l2cache.Writeback_accesses 1048319 # number of Writeback accesses(hits+misses) 416system.cpu.l2cache.Writeback_hits 1048319 # number of Writeback hits 417system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 418system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 419system.cpu.l2cache.avg_refs 6.336020 # Average number of references to valid blocks. 420system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 421system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 422system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.cache_copies 0 # number of cache copies performed 425system.cpu.l2cache.demand_accesses 1187535 # number of demand (read+write) accesses 426system.cpu.l2cache.demand_avg_miss_latency 34219.803814 # average overall miss latency 427system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency 428system.cpu.l2cache.demand_hits 953267 # number of demand (read+write) hits 429system.cpu.l2cache.demand_miss_latency 8016605000 # number of demand (read+write) miss cycles 430system.cpu.l2cache.demand_miss_rate 0.197273 # miss rate for demand accesses 431system.cpu.l2cache.demand_misses 234268 # number of demand (read+write) misses 432system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits 433system.cpu.l2cache.demand_mshr_miss_latency 7264116500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.demand_mshr_miss_rate 0.197247 # mshr miss rate for demand accesses 435system.cpu.l2cache.demand_mshr_misses 234238 # number of demand (read+write) MSHR misses 436system.cpu.l2cache.fast_writes 0 # number of fast writes performed 437system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 438system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.cpu.l2cache.occ_%::0 0.185686 # Average percentage of cache occupancy 440system.cpu.l2cache.occ_%::1 0.450094 # Average percentage of cache occupancy 441system.cpu.l2cache.occ_blocks::0 6084.559967 # Average occupied blocks per context 442system.cpu.l2cache.occ_blocks::1 14748.682079 # Average occupied blocks per context 443system.cpu.l2cache.overall_accesses 1187535 # number of overall (read+write) accesses 444system.cpu.l2cache.overall_avg_miss_latency 34219.803814 # average overall miss latency 445system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency 446system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 447system.cpu.l2cache.overall_hits 953267 # number of overall hits 448system.cpu.l2cache.overall_miss_latency 8016605000 # number of overall miss cycles 449system.cpu.l2cache.overall_miss_rate 0.197273 # miss rate for overall accesses 450system.cpu.l2cache.overall_misses 234268 # number of overall misses 451system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits 452system.cpu.l2cache.overall_mshr_miss_latency 7264116500 # number of overall MSHR miss cycles 453system.cpu.l2cache.overall_mshr_miss_rate 0.197247 # mshr miss rate for overall accesses 454system.cpu.l2cache.overall_mshr_misses 234238 # number of overall MSHR misses 455system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 456system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 457system.cpu.l2cache.replacements 215168 # number of replacements 458system.cpu.l2cache.sampled_refs 235364 # Sample count of references to valid blocks. 459system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 460system.cpu.l2cache.tagsinuse 20833.242046 # Cycle average of tags in use 461system.cpu.l2cache.total_refs 1491271 # Total number of references to valid blocks. 462system.cpu.l2cache.warmup_cycle 262458362000 # Cycle when the warmup percentage was hit. 463system.cpu.l2cache.writebacks 171581 # number of writebacks 464system.cpu.memDep0.conflictingLoads 60170710 # Number of conflicting loads. 465system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores. 466system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit. 467system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit. 468system.cpu.numCycles 731071595 # number of cpu cycles simulated 469system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking 470system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed 471system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full 472system.cpu.rename.RENAME:IdleCycles 309286671 # Number of cycles rename is idle 473system.cpu.rename.RENAME:LSQFullEvents 9288405 # Number of times rename has blocked due to LSQ full 474system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full 475system.cpu.rename.RENAME:RenameLookups 2644676144 # Number of register rename lookups that rename has made 476system.cpu.rename.RENAME:RenamedInsts 1043986494 # Number of instructions processed by rename 477system.cpu.rename.RENAME:RenamedOperands 713690265 # Number of destination operands rename has renamed 478system.cpu.rename.RENAME:RunCycles 326862324 # Number of cycles rename is running 479system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing 480system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking 481system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing 482system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst 483system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed 484system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer 485system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed 486system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself 487system.cpu.workload.PROG:num_syscalls 548 # Number of system calls 488 489---------- End Simulation Statistics ---------- 490