xref: /gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.233363                       # Number of seconds simulated
sim_ticks                                233363457000                       # Number of ticks simulated
final_tick                               233363457000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 153279                       # Simulator instruction rate (inst/s)
host_op_rate                                   166055                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               70798116                       # Simulator tick rate (ticks/s)
host_mem_usage                                 302508                       # Number of bytes of host memory used
host_seconds                                  3296.18                       # Real time elapsed on the host
sim_insts                                   505234934                       # Number of instructions simulated
sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            641792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10513600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     16409344                       # Number of bytes read from this memory
system.physmem.bytes_read::total             27564736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       641792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          641792                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18651328                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18651328                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              10028                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             164275                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       256396                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                430699                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          291427                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               291427                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2750182                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             45052469                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     70316682                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               118119333                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2750182                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2750182                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          79923945                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               79923945                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          79923945                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2750182                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            45052469                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     70316682                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              198043278                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        430699                       # Number of read requests accepted
system.physmem.writeReqs                       291427                       # Number of write requests accepted
system.physmem.readBursts                      430699                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     291427                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 27407296                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    157440                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18649728                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  27564736                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18651328                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     2460                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               27205                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26463                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25602                       # Per bank write bursts
system.physmem.perBankRdBursts::3               32969                       # Per bank write bursts
system.physmem.perBankRdBursts::4               28037                       # Per bank write bursts
system.physmem.perBankRdBursts::5               29890                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25340                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24398                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25649                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25581                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25884                       # Per bank write bursts
system.physmem.perBankRdBursts::11              26303                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27555                       # Per bank write bursts
system.physmem.perBankRdBursts::13              26148                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24908                       # Per bank write bursts
system.physmem.perBankRdBursts::15              26307                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18644                       # Per bank write bursts
system.physmem.perBankWrBursts::1               18139                       # Per bank write bursts
system.physmem.perBankWrBursts::2               17950                       # Per bank write bursts
system.physmem.perBankWrBursts::3               17944                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18581                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18235                       # Per bank write bursts
system.physmem.perBankWrBursts::6               17841                       # Per bank write bursts
system.physmem.perBankWrBursts::7               17708                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18005                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17734                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18244                       # Per bank write bursts
system.physmem.perBankWrBursts::11              18783                       # Per bank write bursts
system.physmem.perBankWrBursts::12              18680                       # Per bank write bursts
system.physmem.perBankWrBursts::13              18156                       # Per bank write bursts
system.physmem.perBankWrBursts::14              18369                       # Per bank write bursts
system.physmem.perBankWrBursts::15              18389                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    233363404500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  430699                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 291427                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    330391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     50226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8880                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6027                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4235                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3274                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     7756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    12492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    15016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    16255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    16901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    18074                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    18193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    18541                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    18646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    18700                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    18837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       328347                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      140.266048                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      98.833830                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     178.808988                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         208753     63.58%     63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        80037     24.38%     87.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        14980      4.56%     92.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7256      2.21%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4857      1.48%     96.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2521      0.77%     96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1858      0.57%     97.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1524      0.46%     98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6561      2.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         328347                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         16970                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.230642                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      145.328941                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          16968     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           16970                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         16970                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.171597                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.099419                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.840930                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            9436     55.60%     55.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            6694     39.45%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21             588      3.46%     98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23             150      0.88%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              55      0.32%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              20      0.12%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               4      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               8      0.05%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               2      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               4      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-77               1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::94-95               1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           16970                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8687632010                       # Total ticks spent queuing
system.physmem.totMemAccLat               16717113260                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2141195000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20286.88                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39036.88                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         117.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          79.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      118.12                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       79.92                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.54                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.62                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.52                       # Average write queue length when enqueuing
system.physmem.readRowHits                     308039                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     83248                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   71.93                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  28.57                       # Row buffer hit rate for writes
system.physmem.avgGap                       323161.62                       # Average gap between requests
system.physmem.pageHitRate                      54.37                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1261242360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  688177875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1715142000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                939872160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            15242051760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86511761685                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            64129665000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             170487912840                       # Total energy per rank (pJ)
system.physmem_0.averagePower              730.572857                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   106127593352                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7792460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    119441919148                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1221045840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  666245250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1624857000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                948412800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            15242051760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            81485025165                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            68539083000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             169726720815                       # Total energy per rank (pJ)
system.physmem_1.averagePower              727.311005                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   113492657633                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7792460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    112077139867                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               174594135                       # Number of BP lookups
system.cpu.branchPred.condPredicted         131061438                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7233022                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             90315091                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                79002409                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             87.474206                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12105110                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             104499                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         4687937                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            4674274                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            13663                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        53871                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        466726915                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            7649319                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      727510991                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   174594135                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           95781793                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     451018276                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                14520177                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 5415                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           146                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13360                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 235275678                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 36827                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          465946604                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.690437                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.183518                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 96241342     20.66%     20.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                132050994     28.34%     49.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 57360477     12.31%     61.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                180293791     38.69%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            465946604                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.374082                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.558751                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32536552                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             120918293                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 282902203                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              22817634                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6771922                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             23855471                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                495849                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              710960604                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              29091371                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6771922                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 63349282                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                56784032                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       40401553                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 273510163                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              25129652                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              682692967                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              12844145                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               9945202                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2511648                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1805093                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1905777                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           827472920                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3000392013                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        718609980                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                96                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                173377246                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1545812                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1536134                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43839802                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            142358029                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            67522859                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          12902461                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11335768                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  664750936                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2979334                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 608926553                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5748894                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       120382115                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    306467952                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1702                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     465946604                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.306859                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.102130                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           149520607     32.09%     32.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           100880237     21.65%     53.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           145552540     31.24%     84.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            63032249     13.53%     98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6960366      1.49%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 605      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       465946604                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                71896734     53.12%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     30      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44291867     32.73%     85.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              19147796     14.15%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             412590919     67.76%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               352109      0.06%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            133574983     21.94%     89.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            62408539     10.25%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              608926553                       # Type of FU issued
system.cpu.iq.rate                           1.304674                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   135336427                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.222254                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1824884935                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         788141663                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    594200588                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  96                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 76                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              744262920                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      60                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          7284479                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     26474746                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        24624                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29798                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     10662639                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       225013                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         22508                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6771922                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                22843049                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                918168                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           669223084                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             142358029                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             67522859                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1490792                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 256633                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                523882                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29798                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3590923                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3742651                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7333574                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             598420503                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             129081054                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10506050                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1492814                       # number of nop insts executed
system.cpu.iew.exec_refs                    190002009                       # number of memory reference insts executed
system.cpu.iew.exec_branches                131263961                       # Number of branches executed
system.cpu.iew.exec_stores                   60920955                       # Number of stores executed
system.cpu.iew.exec_rate                     1.282164                       # Inst execution rate
system.cpu.iew.wb_sent                      595445456                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     594200604                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 349565575                       # num instructions producing a value
system.cpu.iew.wb_consumers                 571385188                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.273123                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611786                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       107116116                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6744856                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    449285999                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.221253                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.890713                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    220514428     49.08%     49.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    116376748     25.90%     74.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     43480691      9.68%     84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     23177999      5.16%     89.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     11514242      2.56%     92.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7755129      1.73%     94.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8259802      1.84%     95.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4227193      0.94%     96.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     13979767      3.11%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    449285999                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506578818                       # Number of instructions committed
system.cpu.commit.committedOps              548692039                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      172743503                       # Number of memory references committed
system.cpu.commit.loads                     115883283                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121552863                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 448447003                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        375609314     68.46%     68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       115883283     21.12%     89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       56860220     10.36%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         548692039                       # Class of committed instruction
system.cpu.commit.bw_lim_events              13979767                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1091107249                       # The number of ROB reads
system.cpu.rob.rob_writes                  1328306301                       # The number of ROB writes
system.cpu.timesIdled                           14326                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          780311                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505234934                       # Number of Instructions Simulated
system.cpu.committedOps                     547348155                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.923782                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.923782                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.082507                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.082507                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                610129735                       # number of integer regfile reads
system.cpu.int_regfile_writes               327331512                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                2166233884                       # number of cc regfile reads
system.cpu.cc_regfile_writes                376536291                       # number of cc regfile writes
system.cpu.misc_regfile_reads               217601523                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2817306                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.628303                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           168866082                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2817818                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             59.927959                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         501259000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.628303                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999274                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999274                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          280                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         355259202                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        355259202                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    114162091                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114162091                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     51724043                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       51724043                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2789                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2789                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     165886134                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        165886134                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    165888923                       # number of overall hits
system.cpu.dcache.overall_hits::total       165888923                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      4839586                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       4839586                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2515006                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2515006                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           10                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           10                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      7354592                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7354592                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      7354602                       # number of overall misses
system.cpu.dcache.overall_misses::total       7354602                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  58596122500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  58596122500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18922626430                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18922626430                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1155000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      1155000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  77518748930                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  77518748930                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  77518748930                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  77518748930                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    119001677                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    119001677                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2799                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2799                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    173240726                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    173240726                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    173243525                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    173243525                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040668                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040668                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046369                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.046369                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.003573                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.003573                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.042453                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.042453                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.042452                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.042452                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7523.889180                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  7523.889180                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        17500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        17500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10540.183457                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10540.169125                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           21                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       907373                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          221320                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.500000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     4.099824                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      2817306                       # number of writebacks
system.cpu.dcache.writebacks::total           2817306                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2541564                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      2541564                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995189                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1995189                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4536753                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4536753                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4536753                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4536753                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2298022                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2298022                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519817                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       519817                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            9                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            9                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2817839                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2817839                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2817848                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2817848                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30115234500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  30115234500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603448995                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603448995                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       602500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       602500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34718683495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  34718683495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34719285995                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  34719285995                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019311                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019311                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009584                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009584                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003215                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003215                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016265                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016265                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016265                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.016265                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.903126                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.903126                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             76636                       # number of replacements
system.cpu.icache.tags.tagsinuse           466.486924                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           235189788                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             77148                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           3048.553274                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      115712400500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   466.486924                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.911107                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.911107                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         470628332                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        470628332                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    235189788                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       235189788                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     235189788                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        235189788                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    235189788                       # number of overall hits
system.cpu.icache.overall_hits::total       235189788                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        85789                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         85789                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        85789                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          85789                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        85789                       # number of overall misses
system.cpu.icache.overall_misses::total         85789                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1556704687                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1556704687                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1556704687                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1556704687                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1556704687                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1556704687                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    235275577                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    235275577                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    235275577                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    235275577                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    235275577                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    235275577                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000365                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000365                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000365                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000365                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000365                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000365                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18145.737647                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18145.737647                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       171831                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          200                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              6857                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    25.059210                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           50                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        76636                       # number of writebacks
system.cpu.icache.writebacks::total             76636                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8610                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         8610                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         8610                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         8610                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         8610                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         8610                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        77179                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        77179                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        77179                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        77179                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        77179                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        77179                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1268632793                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1268632793                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1268632793                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1268632793                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1268632793                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1268632793                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000328                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000328                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000328                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued      8513734                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      8515093                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit          374                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage       743899                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           390403                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15000.108571                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2699085                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           406018                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.647698                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    74.046079                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.911015                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004519                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.915534                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          114                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15501                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           17                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           46                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           49                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          655                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5426                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6626                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2533                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.006958                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.946106                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         95370697                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        95370697                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      2353941                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2353941                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       516320                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       516320                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       516934                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       516934                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        67108                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        67108                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2130993                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      2130993                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        67108                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2647927                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2715035                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        67108                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2647927                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2715035                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           30                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         5078                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         5078                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10036                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        10036                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       164813                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       164813                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10036                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169891                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        179927                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10036                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169891                       # number of overall misses
system.cpu.l2cache.overall_misses::total       179927                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        21000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        21000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    484083500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    484083500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    750585000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    750585000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12710440000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  12710440000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    750585000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13194523500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13945108500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    750585000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13194523500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13945108500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2353941                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2353941                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       516320                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       516320                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           30                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           30                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       522012                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       522012                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        77144                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        77144                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295806                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      2295806                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        77144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2817818                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2894962                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        77144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2817818                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2894962                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009728                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.009728                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.130094                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.130094                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.071789                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.071789                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.130094                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.060292                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.062152                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.130094                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.060292                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.062152                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data          700                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total          700                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95329.558881                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95329.558881                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74789.258669                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74789.258669                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77120.372786                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77120.372786                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74789.258669                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77664.640858                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77504.257282                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74789.258669                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77664.640858                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77504.257282                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches             2029                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks       291427                       # number of writebacks
system.cpu.l2cache.writebacks::total           291427                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1416                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1416                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            8                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4197                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4197                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         5613                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         5621                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         5613                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         5621                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       356222                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       356222                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3662                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3662                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10028                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10028                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       160616                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       160616                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10028                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       164278                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       174306                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10028                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       164278                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       356222                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       530528                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18747915458                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18747915458                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       462000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       462000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    336888000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    336888000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    689794500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    689794500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  11439165000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  11439165000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    689794500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11776053000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12465847500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    689794500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11776053000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18747915458                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  31213762958                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007015                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007015                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.129991                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.069961                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.069961                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058300                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060210                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058300                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.183259                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15400                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15400                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      5788969                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893984                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23717                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        99826                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        99825                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       2372984                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2645368                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       540001                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        98976                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       397627                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           30                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           30                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       522012                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       522012                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        77179                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295806                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8453003                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8683961                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9841856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360648000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          370489856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      788066                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              18653632                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      3683057                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.033555                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.180083                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3559472     96.64%     96.64% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             123584      3.36%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3683057                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5788426505                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     115796940                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4226763956                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        821136                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       414105                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             427040                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       291427                       # Transaction distribution
system.membus.trans_dist::CleanEvict            98976                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               34                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3658                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3658                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        427041                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1251834                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1251834                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     46216000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                46216000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            430733                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  430733    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              430733                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2217216132                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2280002282                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------