stats.txt revision 11570
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.232865 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 232864525000 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 156445 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 169485 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 72105974 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 295816 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 3229.48 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 505234934 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 547348155 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611530Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 27130944 # Number of bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 18710656 # Number of bytes written to this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 423921 # Number of read requests responded to by this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 292354 # Number of write requests responded to by this memory 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) 4411507SCurtis.Dunham@arm.comsystem.physmem.readReqs 423921 # Number of read requests accepted 4511507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 292354 # Number of write requests accepted 4611507SCurtis.Dunham@arm.comsystem.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue 4711507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM 4911507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM 5111507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side 5211507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side 5311507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue 5411507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one 5511507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 26585 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 25966 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 25309 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 32108 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 27451 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 28247 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 25115 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 24228 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 25496 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 25694 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 25307 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 26044 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 27396 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 26024 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 24983 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 25596 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 18605 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 18353 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 18036 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 17927 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 18566 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 18339 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 17904 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 17705 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 17878 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 17947 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 18182 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 18731 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 18803 # Per bank write bursts 8511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 18363 # Per bank write bursts 8611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 18474 # Per bank write bursts 8711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 18505 # Per bank write bursts 8811507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8911507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 9011507SCurtis.Dunham@arm.comsystem.physmem.totGap 232864472500 # Total gap between requests 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 423921 # Read request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 10111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 10211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 10311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 292354 # Write request sizes (log2) 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 20011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation 21111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation 21211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation 21311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation 21411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes 21911507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 22011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes 22111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes 22211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads 22411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads 22511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads 22611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads 22711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads 22811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads 22911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads 23011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads 23111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads 23211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads 23311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads 23411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads 23511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads 23611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads 23711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads 23811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads 23911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads 24011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads 24111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads 24211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads 24311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads 24511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads 24611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads 24711507SCurtis.Dunham@arm.comsystem.physmem.totQLat 8669198966 # Total ticks spent queuing 24811507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM 24911507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers 25011507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst 25111507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 25211507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst 25311507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s 25411507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s 25511507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s 25611507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s 25711507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 25811507SCurtis.Dunham@arm.comsystem.physmem.busUtil 1.53 # Data bus utilization in percentage 25911507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 26011507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 26111507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing 26211507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing 26311507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 306141 # Number of row buffer hits during reads 26411507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 85116 # Number of row buffer hits during writes 26511507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads 26611507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes 26711507SCurtis.Dunham@arm.comsystem.physmem.avgGap 325104.84 # Average gap between requests 26811507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined 26911507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) 27011507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) 27111507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) 27211507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) 27311507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) 27411507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) 27511507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) 27611507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) 27711507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 728.002962 # Core power per rank (mW) 27811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states 27911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states 28011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states 28211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 28311507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) 28411507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) 28511507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) 28611507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) 28711507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) 28811507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) 28911507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) 29011507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) 29111507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 725.972811 # Core power per rank (mW) 29211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states 29311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states 29411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states 29611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 29711530Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 29811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 174583649 # Number of BP lookups 29911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted 30011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect 30111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups 30211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 79003628 # Number of BTB hits 30311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage 30511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. 30611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. 30711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. 30811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. 30911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. 31011507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. 31111507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 31211530Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 34011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 34111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34211530Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36611507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36711507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 36911507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 37011507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 37111507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 37211530Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 40211530Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42611507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42711507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42911507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 43011507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 43111507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 43211507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 43311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states 43411507SCurtis.Dunham@arm.comsystem.cpu.numCycles 465729051 # number of cpu cycles simulated 43511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43611507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43711507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss 43811507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed 43911507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered 44011507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken 44111507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked 44211507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing 44311507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 44411507SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps 44511507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR 44611507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched 44711507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed 44811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) 44911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) 45011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) 45111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 45211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) 45311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) 45411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) 45511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) 45611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 45711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 45811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 45911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) 46011507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle 46111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle 46211507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle 46311507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked 46411507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 282921194 # Number of cycles decode is running 46511507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking 46611507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing 46711507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch 46811507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction 46911507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode 47011507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode 47111507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing 47211507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle 47311507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking 47411507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst 47511507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 273519607 # Number of cycles rename is running 47611507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking 47711507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename 47811507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename 47911507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full 48011507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full 48111507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full 48211507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full 48311507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed 48411515Sandreas.sandberg@arm.comsystem.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made 48511507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups 48611507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 48711507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed 48811507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing 48911507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed 49011507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed 49111507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer 49211507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. 49311507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. 49411507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. 49511507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. 49611507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) 49711507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ 49811507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued 49911507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued 50011507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling 50111515Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph 50211507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed 50311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle 50411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle 50511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle 50611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 50711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle 50811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle 50911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle 51011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle 51111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle 51211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle 51311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 51411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 51511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 51611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 51711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 51811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 51911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle 52011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 52111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available 52211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available 52311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available 52411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available 52511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available 52611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available 52711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available 52811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available 52911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available 53011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available 53111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available 53211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available 53311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available 53411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available 53511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available 53611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available 53711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available 53811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available 53911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available 54011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available 54111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available 54211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available 54311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available 54411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available 54511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available 54611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available 54711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available 54811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available 54911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available 55011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available 55111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available 55211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 55311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 55411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 55511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued 55611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued 55711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued 55811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued 55911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued 56011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued 56111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued 56211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued 56311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued 56411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued 56511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued 56611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued 56711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued 56811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued 56911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued 57011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued 57111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued 57211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued 57311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued 57411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued 57511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued 57611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued 57711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued 57811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued 57911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued 58011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued 58111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued 58211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued 58311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued 58411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued 58511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued 58611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 58711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 58811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 608926727 # Type of FU issued 58911507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 1.307470 # Inst issue rate 59011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested 59111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) 59211507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads 59311507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes 59411507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses 59511507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads 59611507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes 59711507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 59811507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses 59911507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses 60011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores 60111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 60211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed 60311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed 60411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations 60511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed 60611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 60711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 60811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled 60911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked 61011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 61111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing 61211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking 61311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking 61411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ 61511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 61611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions 61711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions 61811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions 61911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall 62011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall 62111507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations 62211507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly 62311507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly 62411507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute 62511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions 62611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed 62711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute 62811507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 62911507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 1492919 # number of nop insts executed 63011507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 190006687 # number of memory reference insts executed 63111507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 131263664 # Number of branches executed 63211507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 60919662 # Number of stores executed 63311507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 1.284925 # Inst execution rate 63411507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit 63511507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 594203292 # cumulative count of insts written-back 63611507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 349565798 # num instructions producing a value 63711507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 571378084 # num instructions consuming a value 63811507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 1.275856 # insts written-back per cycle 63911507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back 64011507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit 64111507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 64211507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted 64311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle 64411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle 64511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle 64611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 64711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle 64811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle 64911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle 65011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle 65111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle 65211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle 65311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle 65411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle 65511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle 65611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 65711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 65811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle 66011507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 506578818 # Number of instructions committed 66111507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed 66211507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 66311507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 172743503 # Number of memory references committed 66411507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 115883283 # Number of loads committed 66511507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 1488542 # Number of memory barriers committed 66611507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 121552863 # Number of branches committed 66711507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 66811507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 448447003 # Number of committed integer instructions. 66911507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 67011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 67111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction 67211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 67311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 67411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 67511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 67611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 67711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 67811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 67911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 68011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 68111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 68211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 68311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 68411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 68511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 68611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 68711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 68811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 68911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 69011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 69111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 69211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 69311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 69411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 69511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 69611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 69711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 69811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 69911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 70011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 70111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction 70211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 70311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 70411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 548692039 # Class of committed instruction 70511507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached 70611507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 1090292113 # The number of ROB reads 70711507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 1328334369 # The number of ROB writes 70811507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself 70911507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling 71011507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 505234934 # Number of Instructions Simulated 71111507SCurtis.Dunham@arm.comsystem.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated 71211507SCurtis.Dunham@arm.comsystem.cpu.cpi 0.921807 # CPI: Cycles Per Instruction 71311507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads 71411507SCurtis.Dunham@arm.comsystem.cpu.ipc 1.084826 # IPC: Instructions Per Cycle 71511507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads 71611507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 610135542 # number of integer regfile reads 71711507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 327337405 # number of integer regfile writes 71811507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 71911507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads 72011507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 376539611 # number of cc regfile writes 72111515Sandreas.sandberg@arm.comsystem.cpu.misc_regfile_reads 217603177 # number of misc regfile reads 72211507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 72311530Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 72411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2817145 # number of replacements 72511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use 72611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. 72711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. 72811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. 72911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 73011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor 73111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy 73211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy 73311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 73411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 73511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 73611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 73711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses 73911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses 74011530Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 74111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits 74211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits 74311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits 74411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits 74511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits 74611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits 74711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 74811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits 74911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 75011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 75111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits 75211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits 75311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits 75411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 165893629 # number of overall hits 75511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses 75611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses 75711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses 75811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses 75911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 76011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 76111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 76211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 76311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses 76411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses 76511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses 76611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 7353956 # number of overall misses 76711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles 76811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles 76911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles 77011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles 77111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles 77211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles 77311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles 77411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles 77511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles 77611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles 77711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) 77811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) 77911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 78011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 78111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) 78211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) 78311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) 78411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) 78511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 78611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 78711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses 78811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses 78911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses 79011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses 79111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses 79211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses 79311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses 79411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses 79511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses 79611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses 79711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 79811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 79911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses 80011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses 80111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses 80211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses 80311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency 80411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency 80511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency 80611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency 80711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency 80811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency 80911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency 81011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency 81111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency 81211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency 81311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked 81411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked 81511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 81611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked 81711507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked 81811507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked 81911507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks 82011507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2817145 # number of writebacks 82111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits 82211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits 82311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits 82411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits 82511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 82611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 82711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits 82811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits 82911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits 83011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits 83111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses 83211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses 83311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses 83411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses 83511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 83611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 83711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses 83811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses 83911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses 84011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses 84111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles 84211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles 84311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles 84411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles 84511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles 84611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles 84711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles 84811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles 84911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles 85011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles 85111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses 85211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses 85311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses 85411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses 85511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses 85611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses 85711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses 85811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses 85911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses 86011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses 86111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency 86211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency 86311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency 86411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency 86511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency 86611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency 86711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency 86811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency 86911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency 87011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency 87111530Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 87211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 76528 # number of replacements 87311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use 87411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. 87511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. 87611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. 87711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. 87811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor 87911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy 88011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy 88111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 88311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 88411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 88511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 88611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 88711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses 88911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 470619957 # Number of data accesses 89011530Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 89111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits 89211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits 89311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits 89411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits 89511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits 89611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 235186472 # number of overall hits 89711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses 89811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses 89911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses 90011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses 90111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses 90211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 84972 # number of overall misses 90311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles 90411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles 90511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles 90611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles 90711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles 90811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles 90911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) 91011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) 91111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses 91211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses 91311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses 91411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses 91511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses 91611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses 91711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses 91811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses 91911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses 92011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses 92111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency 92211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency 92311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 92411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency 92511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency 92611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency 92711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked 92811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked 92911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked 93011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 93111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked 93211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked 93311507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 76528 # number of writebacks 93411507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 76528 # number of writebacks 93511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits 93611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits 93711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits 93811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits 93911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits 94011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits 94111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses 94211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses 94311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses 94411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses 94511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses 94611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses 94711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles 94811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles 94911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles 95011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles 95111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles 95211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles 95311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses 95411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses 95511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses 95611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses 95711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 95811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 95911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency 96011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency 96111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 96211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 96311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency 96411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency 96511530Sandreas.sandberg@arm.comsystem.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 96611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued 96711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified 96811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue 96911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing 97211530Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 97311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 395630 # number of replacements 97411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use 97511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. 97611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. 97711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. 97811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. 97911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor 98011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor 98111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor 98211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy 98311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy 98411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy 98511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy 98611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id 98711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id 98811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 98911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id 99011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id 99111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id 99211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 99311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 99411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id 99511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id 99611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id 99711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id 99811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 99911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses 100011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses 100111530Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 100211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits 100311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits 100411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits 100511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits 100611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits 100711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits 100811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits 100911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits 101011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits 101111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits 101211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits 101311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits 101411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits 101511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits 101611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits 101711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 2722440 # number of overall hits 101811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses 101911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses 102011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 5096 # number of ReadExReq misses 102111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 5096 # number of ReadExReq misses 102211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8194 # number of ReadCleanReq misses 102311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 8194 # number of ReadCleanReq misses 102411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 158964 # number of ReadSharedReq misses 102511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 158964 # number of ReadSharedReq misses 102611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 8194 # number of demand (read+write) misses 102711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 164060 # number of demand (read+write) misses 102811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 172254 # number of demand (read+write) misses 102911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 8194 # number of overall misses 103011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 164060 # number of overall misses 103111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 172254 # number of overall misses 103211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40500 # number of UpgradeReq miss cycles 103311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 40500 # number of UpgradeReq miss cycles 103411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484398500 # number of ReadExReq miss cycles 103511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 484398500 # number of ReadExReq miss cycles 103611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 596844000 # number of ReadCleanReq miss cycles 103711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 596844000 # number of ReadCleanReq miss cycles 103811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12095410500 # number of ReadSharedReq miss cycles 103911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 12095410500 # number of ReadSharedReq miss cycles 104011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 596844000 # number of demand (read+write) miss cycles 104111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 12579809000 # number of demand (read+write) miss cycles 104211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 13176653000 # number of demand (read+write) miss cycles 104311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 596844000 # number of overall miss cycles 104411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 12579809000 # number of overall miss cycles 104511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 13176653000 # number of overall miss cycles 104611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2350571 # number of WritebackDirty accesses(hits+misses) 104711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2350571 # number of WritebackDirty accesses(hits+misses) 104811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 519224 # number of WritebackClean accesses(hits+misses) 104911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 519224 # number of WritebackClean accesses(hits+misses) 105011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses) 105111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses) 105211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 522011 # number of ReadExReq accesses(hits+misses) 105311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 522011 # number of ReadExReq accesses(hits+misses) 105411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77037 # number of ReadCleanReq accesses(hits+misses) 105511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 77037 # number of ReadCleanReq accesses(hits+misses) 105611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295646 # number of ReadSharedReq accesses(hits+misses) 105711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 2295646 # number of ReadSharedReq accesses(hits+misses) 105811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 77037 # number of demand (read+write) accesses 105911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2817657 # number of demand (read+write) accesses 106011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 2894694 # number of demand (read+write) accesses 106111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 77037 # number of overall (read+write) accesses 106211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2817657 # number of overall (read+write) accesses 106311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 2894694 # number of overall (read+write) accesses 106411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 106511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 106611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009762 # miss rate for ReadExReq accesses 106711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.009762 # miss rate for ReadExReq accesses 106811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.106364 # miss rate for ReadCleanReq accesses 106911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.106364 # miss rate for ReadCleanReq accesses 107011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069246 # miss rate for ReadSharedReq accesses 107111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069246 # miss rate for ReadSharedReq accesses 107211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.106364 # miss rate for demand accesses 107311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.058226 # miss rate for demand accesses 107411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.059507 # miss rate for demand accesses 107511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.106364 # miss rate for overall accesses 107611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.058226 # miss rate for overall accesses 107711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.059507 # miss rate for overall accesses 107811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1350 # average UpgradeReq miss latency 107911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1350 # average UpgradeReq miss latency 108011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706 # average ReadExReq miss latency 108111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706 # average ReadExReq miss latency 108211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598 # average ReadCleanReq miss latency 108311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598 # average ReadCleanReq miss latency 108411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847 # average ReadSharedReq miss latency 108511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847 # average ReadSharedReq miss latency 108611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency 108711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 108811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 76495.483414 # average overall miss latency 108911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency 109011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency 109111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency 109211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 109311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 109411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 109511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 109611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 109711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 109811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference 109911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks 110011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 292354 # number of writebacks 110111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits 110211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits 110311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits 110411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 110511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits 110611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 4126 # number of ReadSharedReq MSHR hits 110711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits 110811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5522 # number of demand (read+write) MSHR hits 110911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 5531 # number of demand (read+write) MSHR hits 111011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits 111111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5522 # number of overall MSHR hits 111211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 5531 # number of overall MSHR hits 111311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350840 # number of HardPFReq MSHR misses 111411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 350840 # number of HardPFReq MSHR misses 111511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses 111611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses 111711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3700 # number of ReadExReq MSHR misses 111811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 3700 # number of ReadExReq MSHR misses 111911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8185 # number of ReadCleanReq MSHR misses 112011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 8185 # number of ReadCleanReq MSHR misses 112111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154838 # number of ReadSharedReq MSHR misses 112211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 154838 # number of ReadSharedReq MSHR misses 112311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses 112411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 158538 # number of demand (read+write) MSHR misses 112511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 166723 # number of demand (read+write) MSHR misses 112611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses 112711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 158538 # number of overall MSHR misses 112811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350840 # number of overall MSHR misses 112911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 517563 # number of overall MSHR misses 113011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of HardPFReq MSHR miss cycles 113111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18642506693 # number of HardPFReq MSHR miss cycles 113211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 439500 # number of UpgradeReq MSHR miss cycles 113311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 439500 # number of UpgradeReq MSHR miss cycles 113411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 332568000 # number of ReadExReq MSHR miss cycles 113511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 332568000 # number of ReadExReq MSHR miss cycles 113611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 547176500 # number of ReadCleanReq MSHR miss cycles 113711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 547176500 # number of ReadCleanReq MSHR miss cycles 113811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10861820000 # number of ReadSharedReq MSHR miss cycles 113911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10861820000 # number of ReadSharedReq MSHR miss cycles 114011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 547176500 # number of demand (read+write) MSHR miss cycles 114111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11194388000 # number of demand (read+write) MSHR miss cycles 114211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 11741564500 # number of demand (read+write) MSHR miss cycles 114311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 547176500 # number of overall MSHR miss cycles 114411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11194388000 # number of overall MSHR miss cycles 114511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of overall MSHR miss cycles 114611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles 114711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 114811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 114911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 115011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 115111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses 115211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses 115311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses 115411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses 115511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses 115611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses 115711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses 115811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses 115911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses 116011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses 116111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses 116211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 116311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses 116411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency 116511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency 116611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency 116711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency 116811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency 116911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency 117011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency 117111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency 117211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency 117311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency 117411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 117511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 117611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency 117711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency 117811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency 117911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency 118011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency 118111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. 118211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. 118311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 118411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. 118511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 118611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 118711530Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 118811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution 118911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution 119011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution 119111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution 119211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution 119311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 119411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution 119511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution 119611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution 119711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution 119811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution 119911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution 120011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) 120111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) 120211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) 120311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) 120411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) 120511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) 120611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 950855 # Total snoops (count) 120711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 18712896 # Total snoop traffic (bytes) 120811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram 120911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram 121011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram 121111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 121211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram 121311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram 121411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram 121511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 121611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 121711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 121811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram 121911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) 122011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 122111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 122211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 122311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) 122411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 122511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) 122611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 122711530Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states 122811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 420223 # Transaction distribution 122911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 292354 # Transaction distribution 123011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 98859 # Transaction distribution 123111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 33 # Transaction distribution 123211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 3697 # Transaction distribution 123311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 3697 # Transaction distribution 123411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution 123511507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) 123611507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) 123711507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) 123811507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) 123911507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 124011570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 124111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 815167 # Request fanout histogram 124211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 124311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 124411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 124511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram 124611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 124711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 124811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 124911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 125011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 815167 # Request fanout histogram 125111507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) 125211507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 125311507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) 125411507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.0 # Layer utilization (%) 125511507SCurtis.Dunham@arm.com 125611507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1257