stats.txt revision 11138
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 311138Sandreas.hansson@arm.comsim_seconds 0.233306 # Number of seconds simulated 411138Sandreas.hansson@arm.comsim_ticks 233306027000 # Number of ticks simulated 511138Sandreas.hansson@arm.comfinal_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711138Sandreas.hansson@arm.comhost_inst_rate 128535 # Simulator instruction rate (inst/s) 811138Sandreas.hansson@arm.comhost_op_rate 139249 # Simulator op (including micro ops) rate (op/s) 911138Sandreas.hansson@arm.comhost_tick_rate 59354207 # Simulator tick rate (ticks/s) 1011138Sandreas.hansson@arm.comhost_mem_usage 322028 # Number of bytes of host memory used 1111138Sandreas.hansson@arm.comhost_seconds 3930.74 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 505237724 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 547350945 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory 1711138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory 1811138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory 1911138Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26349056 # Number of bytes read from this memory 2011138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory 2111138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory 2211138Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory 2311138Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 18702784 # Number of bytes written to this memory 2411138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory 2511138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory 2611138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory 2711138Sandreas.hansson@arm.comsystem.physmem.num_reads::total 411704 # Number of read requests responded to by this memory 2811138Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory 2911138Sandreas.hansson@arm.comsystem.physmem.num_writes::total 292231 # Number of write requests responded to by this memory 3011138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s) 3111138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s) 3211138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s) 3311138Sandreas.hansson@arm.comsystem.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s) 3411138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s) 3511138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s) 3611138Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s) 3711138Sandreas.hansson@arm.comsystem.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s) 3811138Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s) 3911138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s) 4011138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s) 4111138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s) 4211138Sandreas.hansson@arm.comsystem.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s) 4311138Sandreas.hansson@arm.comsystem.physmem.readReqs 411704 # Number of read requests accepted 4411138Sandreas.hansson@arm.comsystem.physmem.writeReqs 292231 # Number of write requests accepted 4511138Sandreas.hansson@arm.comsystem.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue 4611138Sandreas.hansson@arm.comsystem.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue 4711138Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM 4811138Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue 4911138Sandreas.hansson@arm.comsystem.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM 5011138Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side 5111138Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side 5211138Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue 5311138Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 5411138Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 5511138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 26604 # Per bank write bursts 5611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25479 # Per bank write bursts 5711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25122 # Per bank write bursts 5811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 24753 # Per bank write bursts 5911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 27168 # Per bank write bursts 6011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 26312 # Per bank write bursts 6111138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 25243 # Per bank write bursts 6211138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 24096 # Per bank write bursts 6311138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 25848 # Per bank write bursts 6411138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 24676 # Per bank write bursts 6511138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25150 # Per bank write bursts 6611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 26103 # Per bank write bursts 6711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 26513 # Per bank write bursts 6811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25940 # Per bank write bursts 6911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25062 # Per bank write bursts 7011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25488 # Per bank write bursts 7111138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 18828 # Per bank write bursts 7211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 18294 # Per bank write bursts 7311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 17806 # Per bank write bursts 7411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 17978 # Per bank write bursts 7511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 18719 # Per bank write bursts 7611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 18281 # Per bank write bursts 7711138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 17995 # Per bank write bursts 7811138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 17635 # Per bank write bursts 7911138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 18144 # Per bank write bursts 8010944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 17824 # Per bank write bursts 8111138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 18107 # Per bank write bursts 8211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 18749 # Per bank write bursts 8311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 18847 # Per bank write bursts 8411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 18260 # Per bank write bursts 8511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 18418 # Per bank write bursts 8611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 18313 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 889978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8911138Sandreas.hansson@arm.comsystem.physmem.totGap 233306009000 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611138Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 411704 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311138Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 292231 # Write request sizes (log2) 10411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see 10511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see 10611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see 10711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see 10811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see 10911138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see 11011138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see 11111138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see 11211138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see 11311138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see 11411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see 11511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see 11611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see 11711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see 11810726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see 15211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see 15311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see 15411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see 15511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see 15611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see 15711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see 15811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see 15911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see 16011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see 16111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see 16211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see 16311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see 16411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see 16511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see 16611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see 16711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see 16811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see 16911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see 17011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see 17111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see 17211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see 17311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 17411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see 17510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 17610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20011138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation 20111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation 20211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation 20311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation 20411138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation 20511138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation 20611138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation 20711138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation 20811138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation 20911138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation 21011138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation 21111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation 21211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation 21311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation 21411138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes 21511138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes 21611138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes 21711138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes 21810628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes 21911138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes 22011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads 22111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads 22211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads 22311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads 22411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads 22511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads 22611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads 22711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads 22811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads 22911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads 23011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads 23111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads 23211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads 23311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads 23411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads 23511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads 23611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads 23711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads 23811138Sandreas.hansson@arm.comsystem.physmem.totQLat 9105020732 # Total ticks spent queuing 23911138Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM 24011138Sandreas.hansson@arm.comsystem.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers 24111138Sandreas.hansson@arm.comsystem.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst 2429978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24311138Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst 24411138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s 24511138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s 24611138Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s 24711138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s 2489978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24911138Sandreas.hansson@arm.comsystem.physmem.busUtil 1.50 # Data bus utilization in percentage 25010628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads 25110628Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 25211138Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 25311138Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing 25411138Sandreas.hansson@arm.comsystem.physmem.readRowHits 299267 # Number of row buffer hits during reads 25511138Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95628 # Number of row buffer hits during writes 25611138Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads 25711138Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes 25811138Sandreas.hansson@arm.comsystem.physmem.avgGap 331431.18 # Average gap between requests 25911138Sandreas.hansson@arm.comsystem.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined 26011138Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ) 26111138Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ) 26211138Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ) 26311138Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ) 26411138Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) 26511138Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ) 26611138Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ) 26711138Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ) 26811138Sandreas.hansson@arm.comsystem.physmem_0.averagePower 723.246471 # Core power per rank (mW) 26911138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states 27011138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states 27110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 27211138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states 27310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 27411138Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ) 27511138Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ) 27611138Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ) 27711138Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ) 27811138Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) 27911138Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ) 28011138Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ) 28111138Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ) 28211138Sandreas.hansson@arm.comsystem.physmem_1.averagePower 722.989890 # Core power per rank (mW) 28311138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states 28411138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states 28510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 28611138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states 28710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28811138Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 175092094 # Number of BP lookups 28911138Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted 29011138Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect 29111138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups 29211138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 83876326 # Number of BTB hits 29310628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29411138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage 29511138Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target. 29611138Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions. 29710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 29910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 32710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 32810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3358317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3368317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3378317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3388317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3398317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3408317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3418317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3428317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3438317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3448317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3458317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3468317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3478317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3488317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3498317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3508317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3518317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3528317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3538317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3548317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3558317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 35610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 38410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 38610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3938317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3948317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3958317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3968317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3978317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3988317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3998317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4008317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4018317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4028317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4038317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4048317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4058317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4068317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4078317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4088317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4098317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4108317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4118317SN/Asystem.cpu.itb.hits 0 # DTB hits 4128317SN/Asystem.cpu.itb.misses 0 # DTB misses 4138317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 4148317SN/Asystem.cpu.workload.num_syscalls 548 # Number of system calls 41511138Sandreas.hansson@arm.comsystem.cpu.numCycles 466612055 # number of cpu cycles simulated 4168317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4178317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41811138Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss 41911138Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed 42011138Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered 42111138Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken 42211138Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked 42311138Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing 42411138Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 42511138Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps 42611138Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR 42711138Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched 42811138Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed 42911138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total) 43011138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total) 43111138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total) 4328317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 43311138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total) 43411138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total) 43511138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total) 43611138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total) 4378317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4388317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 43910409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 44011138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total) 44111138Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle 44211138Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle 44311138Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle 44411138Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked 44511138Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 287098365 # Number of cycles decode is running 44611138Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking 44711138Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing 44811138Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch 44911138Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction 45011138Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode 45111138Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode 45211138Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing 45311138Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle 45411138Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking 45511138Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst 45611138Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 276695654 # Number of cycles rename is running 45711138Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking 45811138Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename 45911138Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename 46011138Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full 46111138Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full 46211138Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full 46311138Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full 46411138Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed 46511138Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made 46611138Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups 46710409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 46810352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 46911138Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing 47011138Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed 47111138Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed 47211138Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer 47311138Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit. 47411138Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit. 47511138Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads. 47611138Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores. 47711138Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec) 47811138Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ 47911138Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued 48011138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued 48111138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling 48211138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph 48311138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed 48411138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle 48511138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle 48611138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle 4878317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 48811138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle 48911138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle 49011138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle 49111138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle 49211138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle 49311138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle 49410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 49510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 49610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4978317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4988317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 49910409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 50011138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle 5018317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 50211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available 50311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available 50411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available 50511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available 50611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available 50711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available 50811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available 50911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available 51011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available 51111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available 51211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available 51311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available 51411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available 51511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available 51611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available 51711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available 51811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available 51911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available 52011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available 52111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available 52211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available 52311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available 52411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available 52511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available 52611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available 52711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available 52811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available 52911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available 53011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available 53111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available 53211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available 5338317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5348317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5358317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 53611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued 53711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued 53810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 53910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 54010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 54110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 54210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 54310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 54410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 54510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 54610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 54710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 54810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 54910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 55010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 55110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 55210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 55310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 55410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 55510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 55610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 55710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 55810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 55910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 56010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 56110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 56210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 56310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 56410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 56511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued 56611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued 5678317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5688317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 56911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 610256171 # Type of FU issued 57011138Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.307845 # Inst issue rate 57111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested 57211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst) 57311138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads 57411138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes 57511138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses 57610409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 57710409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 5788317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 57911138Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses 58010409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 58111138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores 5828317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 58311138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed 58411138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed 58511138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations 58611138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed 5878317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5888317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 58911138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled 59011138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked 5918317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 59211138Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing 59311138Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking 59411138Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking 59511138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ 59610409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 59711138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions 59811138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions 59911138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions 60011138Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall 60111138Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall 60211138Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations 60311138Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly 60411138Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly 60511138Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute 60611138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions 60711138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed 60811138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute 6098317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 61011138Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1487415 # number of nop insts executed 61111138Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 190539133 # number of memory reference insts executed 61211138Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 131373270 # Number of branches executed 61311138Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 60964533 # Number of stores executed 61411138Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.284586 # Inst execution rate 61511138Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit 61611138Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 594986597 # cumulative count of insts written-back 61711138Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 349903865 # num instructions producing a value 61811138Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 570650112 # num instructions consuming a value 6198317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 62011138Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.275121 # insts written-back per cycle 62111138Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back 6228317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 62311138Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit 6249459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 62511138Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted 62611138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle 62711138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle 62811138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle 6298241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 63011138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle 63111138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle 63211138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle 63311138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle 63411138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle 63511138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle 63611138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle 63711138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle 63811138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle 6398241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6408241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6418241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 64211138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle 64310812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 506581608 # Number of instructions committed 64410812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed 6458317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 64610352Sandreas.hansson@arm.comsystem.cpu.commit.refs 172745233 # Number of memory references committed 64710352Sandreas.hansson@arm.comsystem.cpu.commit.loads 115884756 # Number of loads committed 6488317SN/Asystem.cpu.commit.membars 1488542 # Number of memory barriers committed 64910812Snilay@cs.wisc.edusystem.cpu.commit.branches 121548302 # Number of branches committed 6508241SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 65110352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 6528241SN/Asystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 65310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 65410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction 65510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 65610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 65710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 65810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 65910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 66010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 66110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 66210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 66310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 66410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 66510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 66610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 66710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 66810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 66910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 67010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 67110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 67210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 67310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 67410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 67510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 67610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 67710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 67810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 67910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 68010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 68110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 68210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 68310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 68410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 68510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 68610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 68710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 548694829 # Class of committed instruction 68811138Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached 68911138Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1093559316 # The number of ROB reads 69011138Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1334598854 # The number of ROB writes 69111138Sandreas.hansson@arm.comsystem.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself 69211138Sandreas.hansson@arm.comsystem.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling 69310812Snilay@cs.wisc.edusystem.cpu.committedInsts 505237724 # Number of Instructions Simulated 69410812Snilay@cs.wisc.edusystem.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated 69511138Sandreas.hansson@arm.comsystem.cpu.cpi 0.923550 # CPI: Cycles Per Instruction 69611138Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads 69711138Sandreas.hansson@arm.comsystem.cpu.ipc 1.082779 # IPC: Instructions Per Cycle 69811138Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads 69911138Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 611100755 # number of integer regfile reads 70011138Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 328116502 # number of integer regfile writes 7018317SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 70211138Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads 70311138Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 376538117 # number of cc regfile writes 70411138Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 217976814 # number of misc regfile reads 7059459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 70611138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2820876 # number of replacements 70711138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use 70811138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks. 70911138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks. 71011138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks. 71111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit. 71211138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor 71311138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy 71411138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy 71510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 71611138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 71711138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 71810726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 71910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72011138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses 72111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses 72211138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits 72311138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits 72411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits 72511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits 72611138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits 72711138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits 72810892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits 72910892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits 73010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 73110628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 73211138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits 73311138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits 73411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits 73511138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 166378633 # number of overall hits 73611138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses 73711138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses 73811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses 73911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses 74011138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 74111138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 74210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 74310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 74411138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses 74511138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses 74611138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses 74711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 7357619 # number of overall misses 74811138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles 74911138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles 75011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles 75111138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles 75211138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles 75311138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles 75411138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles 75511138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles 75611138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles 75711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles 75811138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses) 75911138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses) 76010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 76110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 76211138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) 76311138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) 76410892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) 76510892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) 76610628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 76710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 76811138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses 76911138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses 77011138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses 77111138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses 77211138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses 77311138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses 77411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses 77511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses 77611138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses 77711138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses 77810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 77910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 78011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses 78111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses 78211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses 78311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses 78411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency 78511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency 78611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency 78711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency 78811138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency 78911138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency 79011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency 79111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency 79211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency 79311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency 79411138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked 79511138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked 79611138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked 79711138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked 79811138Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked 79911138Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked 80010628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 80110628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 80211138Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks 80311138Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 2352880 # number of writebacks 80411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits 80511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits 80611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits 80711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits 80810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 80910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 81011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits 81111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits 81211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits 81311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits 81411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses 81511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses 81611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses 81711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses 81810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 81910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 82011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses 82111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses 82211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses 82311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses 82411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles 82511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles 82611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles 82711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles 82811138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles 82911138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles 83011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles 83111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles 83211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles 83311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles 83411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses 83511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses 83610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses 83710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses 83811138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003573 # mshr miss rate for SoftPFReq accesses 83911138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003573 # mshr miss rate for SoftPFReq accesses 84011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses 84111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses 84210892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses 84310892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses 84411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency 84511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency 84611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency 84711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency 84811138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency 84911138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency 85011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency 85111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency 85211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency 85311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # average overall mshr miss latency 85410628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 85511138Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 73459 # number of replacements 85611138Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 466.213956 # Cycle average of tags in use 85711138Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks. 85811138Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks. 85911138Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks. 86011138Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit. 86111138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor 86211138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy 86311138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy 86410628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 86510812Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 86610812Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 86710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 86810892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 86910892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 87010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 87111138Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses 87211138Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 473512362 # Number of data accesses 87311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits 87411138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits 87511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits 87611138Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits 87711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits 87811138Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 236636536 # number of overall hits 87911138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses 88011138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses 88111138Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses 88211138Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses 88311138Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses 88411138Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 82647 # number of overall misses 88511138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles 88611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles 88711138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles 88811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles 88911138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles 89011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles 89111138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses) 89211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses) 89311138Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses 89411138Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses 89511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses 89611138Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses 89710892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses 89810892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses 89910892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses 90010892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses 90110892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses 90210892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses 90311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18934.319128 # average ReadReq miss latency 90411138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 18934.319128 # average ReadReq miss latency 90511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency 90611138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 18934.319128 # average overall miss latency 90711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency 90811138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 18934.319128 # average overall miss latency 90911138Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 190768 # number of cycles access was blocked 91011138Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked 91111138Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 6939 # number of cycles access was blocked 91211138Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 91311138Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 27.492146 # average number of cycles each access was blocked 91411138Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked 91510628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 91610628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 91711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 8650 # number of ReadReq MSHR hits 91811138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 8650 # number of ReadReq MSHR hits 91911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 8650 # number of demand (read+write) MSHR hits 92011138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 8650 # number of demand (read+write) MSHR hits 92111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 8650 # number of overall MSHR hits 92211138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 8650 # number of overall MSHR hits 92311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 73997 # number of ReadReq MSHR misses 92411138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 73997 # number of ReadReq MSHR misses 92511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 73997 # number of demand (read+write) MSHR misses 92611138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 73997 # number of demand (read+write) MSHR misses 92711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 73997 # number of overall MSHR misses 92811138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 73997 # number of overall MSHR misses 92911138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1275745779 # number of ReadReq MSHR miss cycles 93011138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 1275745779 # number of ReadReq MSHR miss cycles 93111138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 1275745779 # number of demand (read+write) MSHR miss cycles 93211138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 1275745779 # number of demand (read+write) MSHR miss cycles 93311138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 1275745779 # number of overall MSHR miss cycles 93411138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 1275745779 # number of overall MSHR miss cycles 93510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 93610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 93710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 93810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 93910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 94010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 94111138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17240.506764 # average ReadReq mshr miss latency 94211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17240.506764 # average ReadReq mshr miss latency 94311138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency 94411138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency 94511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency 94611138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency 94710628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94811138Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 8512194 # number of hwpf issued 94911138Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 8513359 # number of prefetch candidates identified 95011138Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 195 # number of redundant prefetches already in prefetch queue 95110628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 95210628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 95311138Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 743225 # number of prefetches not generated due to page crossing 95411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 400641 # number of replacements 95511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 15417.686844 # Cycle average of tags in use 95611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 5068283 # Total number of references to valid blocks. 95711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 416978 # Sample count of references to valid blocks. 95811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 12.154797 # Average number of references to valid blocks. 95911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 34590463000 # Cycle when the warmup percentage was hit. 96011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 8465.103002 # Average occupied blocks per requestor 96111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 476.521367 # Average occupied blocks per requestor 96211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4913.026142 # Average occupied blocks per requestor 96311138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1563.036333 # Average occupied blocks per requestor 96411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.516669 # Average percentage of cache occupancy 96511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.029085 # Average percentage of cache occupancy 96611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.299867 # Average percentage of cache occupancy 96711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095400 # Average percentage of cache occupancy 96811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.941021 # Average percentage of cache occupancy 96911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 1142 # Occupied blocks per task id 97011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id 97111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 26 # Occupied blocks per task id 97211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 276 # Occupied blocks per task id 97311138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 840 # Occupied blocks per task id 97411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 97511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 97611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 1545 # Occupied blocks per task id 97711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 9909 # Occupied blocks per task id 97811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 3390 # Occupied blocks per task id 97911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.069702 # Percentage of cache occupancy per task id 98011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id 98111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 93194547 # Number of tag accesses 98211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 93194547 # Number of data accesses 98311138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 2352880 # number of Writeback hits 98411138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 2352880 # number of Writeback hits 98511138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 98611138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 98711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 516809 # number of ReadExReq hits 98811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 516809 # number of ReadExReq hits 98911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63278 # number of ReadCleanReq hits 99011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 63278 # number of ReadCleanReq hits 99111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 2155693 # number of ReadSharedReq hits 99211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 2155693 # number of ReadSharedReq hits 99311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 63278 # number of demand (read+write) hits 99411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2672502 # number of demand (read+write) hits 99511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2735780 # number of demand (read+write) hits 99611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 63278 # number of overall hits 99711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2672502 # number of overall hits 99811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2735780 # number of overall hits 99911138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 100011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 100111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 5137 # number of ReadExReq misses 100211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 5137 # number of ReadExReq misses 100311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10691 # number of ReadCleanReq misses 100411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 10691 # number of ReadCleanReq misses 100511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 143749 # number of ReadSharedReq misses 100611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 143749 # number of ReadSharedReq misses 100711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 10691 # number of demand (read+write) misses 100811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 148886 # number of demand (read+write) misses 100911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 159577 # number of demand (read+write) misses 101011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 10691 # number of overall misses 101111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 148886 # number of overall misses 101211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 159577 # number of overall misses 101311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 502200000 # number of ReadExReq miss cycles 101411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 502200000 # number of ReadExReq miss cycles 101511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 787136500 # number of ReadCleanReq miss cycles 101611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 787136500 # number of ReadCleanReq miss cycles 101711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11114003000 # number of ReadSharedReq miss cycles 101811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 11114003000 # number of ReadSharedReq miss cycles 101911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 787136500 # number of demand (read+write) miss cycles 102011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11616203000 # number of demand (read+write) miss cycles 102111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 12403339500 # number of demand (read+write) miss cycles 102211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 787136500 # number of overall miss cycles 102311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11616203000 # number of overall miss cycles 102411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 12403339500 # number of overall miss cycles 102511138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 2352880 # number of Writeback accesses(hits+misses) 102611138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 2352880 # number of Writeback accesses(hits+misses) 102711138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) 102811138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) 102911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 521946 # number of ReadExReq accesses(hits+misses) 103011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 521946 # number of ReadExReq accesses(hits+misses) 103111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73969 # number of ReadCleanReq accesses(hits+misses) 103211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 73969 # number of ReadCleanReq accesses(hits+misses) 103311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299442 # number of ReadSharedReq accesses(hits+misses) 103411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 2299442 # number of ReadSharedReq accesses(hits+misses) 103511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 73969 # number of demand (read+write) accesses 103611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2821388 # number of demand (read+write) accesses 103711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2895357 # number of demand (read+write) accesses 103811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 73969 # number of overall (read+write) accesses 103911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2821388 # number of overall (read+write) accesses 104011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2895357 # number of overall (read+write) accesses 104111138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.041667 # miss rate for UpgradeReq accesses 104211138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.041667 # miss rate for UpgradeReq accesses 104311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009842 # miss rate for ReadExReq accesses 104411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.009842 # miss rate for ReadExReq accesses 104511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.144534 # miss rate for ReadCleanReq accesses 104611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.144534 # miss rate for ReadCleanReq accesses 104711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062515 # miss rate for ReadSharedReq accesses 104811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062515 # miss rate for ReadSharedReq accesses 104911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.144534 # miss rate for demand accesses 105011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.052770 # miss rate for demand accesses 105111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.055115 # miss rate for demand accesses 105211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.144534 # miss rate for overall accesses 105311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.052770 # miss rate for overall accesses 105411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.055115 # miss rate for overall accesses 105511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97761.339303 # average ReadExReq miss latency 105611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 97761.339303 # average ReadExReq miss latency 105711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73626.087363 # average ReadCleanReq miss latency 105811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73626.087363 # average ReadCleanReq miss latency 105911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77315.341324 # average ReadSharedReq miss latency 106011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77315.341324 # average ReadSharedReq miss latency 106111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73626.087363 # average overall miss latency 106211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78020.787717 # average overall miss latency 106311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 77726.360942 # average overall miss latency 106411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73626.087363 # average overall miss latency 106511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78020.787717 # average overall miss latency 106611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 77726.360942 # average overall miss latency 106710628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106810628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 106910628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 107010628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 107110628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 107210628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 107310628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 107410628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 107511138Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 292231 # number of writebacks 107611138Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 292231 # number of writebacks 107711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1476 # number of ReadExReq MSHR hits 107811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 1476 # number of ReadExReq MSHR hits 107911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits 108011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits 108111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4058 # number of ReadSharedReq MSHR hits 108211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 4058 # number of ReadSharedReq MSHR hits 108311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 108411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5534 # number of demand (read+write) MSHR hits 108511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 5542 # number of demand (read+write) MSHR hits 108611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 108711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5534 # number of overall MSHR hits 108811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 5542 # number of overall MSHR hits 108911138Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6918 # number of CleanEvict MSHR misses 109011138Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 6918 # number of CleanEvict MSHR misses 109111138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275358 # number of HardPFReq MSHR misses 109211138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 275358 # number of HardPFReq MSHR misses 109311138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 109411138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 109511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3661 # number of ReadExReq MSHR misses 109611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 3661 # number of ReadExReq MSHR misses 109711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10683 # number of ReadCleanReq MSHR misses 109811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 10683 # number of ReadCleanReq MSHR misses 109911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 139691 # number of ReadSharedReq MSHR misses 110011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 139691 # number of ReadSharedReq MSHR misses 110111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 10683 # number of demand (read+write) MSHR misses 110211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 143352 # number of demand (read+write) MSHR misses 110311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 154035 # number of demand (read+write) MSHR misses 110411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 10683 # number of overall MSHR misses 110511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 143352 # number of overall MSHR misses 110611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275358 # number of overall MSHR misses 110711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 429393 # number of overall MSHR misses 110811138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19097746561 # number of HardPFReq MSHR miss cycles 110911138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19097746561 # number of HardPFReq MSHR miss cycles 111011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17500 # number of UpgradeReq MSHR miss cycles 111111138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17500 # number of UpgradeReq MSHR miss cycles 111211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 337925500 # number of ReadExReq MSHR miss cycles 111311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 337925500 # number of ReadExReq MSHR miss cycles 111411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 722686500 # number of ReadCleanReq MSHR miss cycles 111511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 722686500 # number of ReadCleanReq MSHR miss cycles 111611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9966004000 # number of ReadSharedReq MSHR miss cycles 111711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9966004000 # number of ReadSharedReq MSHR miss cycles 111811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 722686500 # number of demand (read+write) MSHR miss cycles 111911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10303929500 # number of demand (read+write) MSHR miss cycles 112011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 11026616000 # number of demand (read+write) MSHR miss cycles 112111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 722686500 # number of overall MSHR miss cycles 112211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10303929500 # number of overall MSHR miss cycles 112311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19097746561 # number of overall MSHR miss cycles 112411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 30124362561 # number of overall MSHR miss cycles 112510892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 112610892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 112710628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 112810628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 112911138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses 113011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses 113111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses 113211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses 113311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses 113411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses 113511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses 113611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses 113711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses 113811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses 113911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses 114011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses 114111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses 114210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 114311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses 114411138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency 114511138Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency 114611138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency 114711138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency 114811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency 114911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency 115011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency 115111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency 115211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency 115311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency 115411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency 115511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency 115611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency 115711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency 115811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency 115911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency 116011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency 116110628Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 116211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter. 116311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data. 116411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 116511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter. 116611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 116711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 116811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution 116911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution 117011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution 117111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution 117211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution 117311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution 117411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution 117511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution 117611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution 117711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution 117811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes) 117911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes) 118011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes) 118111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes) 118211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes) 118311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes) 118411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 717772 # Total snoops (count) 118511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram 118611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram 118711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram 118810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 118911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram 119011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram 119111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram 119210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 119311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 119410827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 119511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram 119611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks) 119711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%) 119811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks) 11999729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 120011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks) 120110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 120211138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 408044 # Transaction distribution 120311138Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 292231 # Transaction distribution 120411138Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 102781 # Transaction distribution 120511138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 2 # Transaction distribution 120611138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 2 # Transaction distribution 120711138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 3660 # Transaction distribution 120811138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 3660 # Transaction distribution 120911138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution 121011138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes) 121111138Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes) 121211138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes) 121311138Sandreas.hansson@arm.comsystem.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes) 121410628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 121511138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 806718 # Request fanout histogram 121610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 121710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 121810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 121911138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram 122010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 122110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 122210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 122310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 122411138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 806718 # Request fanout histogram 122511138Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks) 122610726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 122711138Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks) 122810726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.9 # Layer utilization (%) 12297860SN/A 12307860SN/A---------- End Simulation Statistics ---------- 1231