stats.txt revision 10409
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 0.231519 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 231518815500 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 126327 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 136857 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 57887815 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 321348 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 3999.44 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 505237723 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 547350944 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28711552 # Number of bytes read from this memory 2010409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory 2110409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory 2310409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 19446336 # Number of bytes written to this memory 2410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory 2510409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory 2610409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory 2710409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 448618 # Number of read requests responded to by this memory 2810409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory 2910409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 303849 # Number of write requests responded to by this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) 3110409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) 3210409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) 3310409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) 3410409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) 3510409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) 3610409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) 3710409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) 3810409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) 4110409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) 4210409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) 4310409Sandreas.hansson@arm.comsystem.physmem.readReqs 448618 # Number of read requests accepted 4410409Sandreas.hansson@arm.comsystem.physmem.writeReqs 303849 # Number of write requests accepted 4510409Sandreas.hansson@arm.comsystem.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue 4610409Sandreas.hansson@arm.comsystem.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue 4710409Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM 4810409Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue 4910409Sandreas.hansson@arm.comsystem.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM 5010409Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side 5110409Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side 5210409Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue 5310409Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 5410409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write 5510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 28534 # Per bank write bursts 5610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 27313 # Per bank write bursts 5710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 27956 # Per bank write bursts 5810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 26702 # Per bank write bursts 5910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 30075 # Per bank write bursts 6010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 29207 # Per bank write bursts 6110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 27700 # Per bank write bursts 6210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 26438 # Per bank write bursts 6310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 28442 # Per bank write bursts 6410409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 26796 # Per bank write bursts 6510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28037 # Per bank write bursts 6610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 28667 # Per bank write bursts 6710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 28663 # Per bank write bursts 6810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 27984 # Per bank write bursts 6910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 26659 # Per bank write bursts 7010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 27067 # Per bank write bursts 7110409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 19504 # Per bank write bursts 7210409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 19011 # Per bank write bursts 7310409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 18881 # Per bank write bursts 7410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 18629 # Per bank write bursts 7510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 19556 # Per bank write bursts 7610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 19014 # Per bank write bursts 7710409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 18738 # Per bank write bursts 7810409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 18227 # Per bank write bursts 7910409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 18808 # Per bank write bursts 8010409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 18381 # Per bank write bursts 8110409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 19036 # Per bank write bursts 8210409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 19525 # Per bank write bursts 8310409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 19578 # Per bank write bursts 8410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 19080 # Per bank write bursts 8510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 18969 # Per bank write bursts 8610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 18884 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 889978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8910409Sandreas.hansson@arm.comsystem.physmem.totGap 231518762500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9610409Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 448618 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10310409Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 303849 # Write request sizes (log2) 10410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see 10510409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see 10610409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see 10710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see 10810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see 10910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see 11010409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see 11110409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see 11210409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see 11310409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see 11410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see 11510409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see 11610409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see 11710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see 11810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see 11910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see 15210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see 15310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see 15410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see 15510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see 15610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see 15710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see 15810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see 15910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see 16010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see 16110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see 16210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see 16310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see 16410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see 16510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see 16610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see 16710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see 16810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see 16910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see 17010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see 17110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see 17210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 17310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see 17410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 17510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 17610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see 17710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 17810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation 20110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation 20210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation 20310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation 20410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation 20510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation 20610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation 20710409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation 20810409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation 20910409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation 21010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation 21110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation 21210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation 21310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation 21410409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes 21510409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes 21610409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes 21710409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes 21810409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes 21910409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes 22010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads 22110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads 22210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads 22310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads 22410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads 22510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads 22610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads 22710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads 22810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads 22910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads 23010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads 23110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads 23210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads 23310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads 23410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads 23510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads 23610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads 23710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads 23810409Sandreas.hansson@arm.comsystem.physmem.totQLat 10651839911 # Total ticks spent queuing 23910409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM 24010409Sandreas.hansson@arm.comsystem.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers 24110409Sandreas.hansson@arm.comsystem.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst 2429978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24310409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst 24410409Sandreas.hansson@arm.comsystem.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s 24510409Sandreas.hansson@arm.comsystem.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s 24610409Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s 24710409Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s 2489978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24910409Sandreas.hansson@arm.comsystem.physmem.busUtil 1.62 # Data bus utilization in percentage 25010409Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads 25110409Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes 25210409Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing 25310409Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing 25410409Sandreas.hansson@arm.comsystem.physmem.readRowHits 331076 # Number of row buffer hits during reads 25510409Sandreas.hansson@arm.comsystem.physmem.writeRowHits 99609 # Number of row buffer hits during writes 25610409Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads 25710409Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes 25810409Sandreas.hansson@arm.comsystem.physmem.avgGap 307679.62 # Average gap between requests 25910409Sandreas.hansson@arm.comsystem.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined 26010409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states 26110409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 7730840000 # Time in different power states 26210220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 26310409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 141344957185 # Time in different power states 26410220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 26510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 445006 # Transaction distribution 26610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 445005 # Transaction distribution 26710409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 303849 # Transaction distribution 26810409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 4 # Transaction distribution 26910409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 4 # Transaction distribution 27010409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 3612 # Transaction distribution 27110409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 3612 # Transaction distribution 27210409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) 27310409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) 27410409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) 27510409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) 27610409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 27710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 752471 # Request fanout histogram 27810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 27910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 28010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 28110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram 28210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 28310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 28410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 28510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 28610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 752471 # Request fanout histogram 28710409Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) 28810409Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 28910409Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) 29010409Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 1.8 # Layer utilization (%) 29110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29210409Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 175071152 # Number of BP lookups 29310409Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted 29410409Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect 29510409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups 29610409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 83861329 # Number of BTB hits 2979482Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29810409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage 29910409Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. 30010409Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. 30110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3228317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3238317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3248317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3258317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3268317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3278317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3288317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3298317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3308317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3318317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3328317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3338317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3348317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3358317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3368317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3378317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3388317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3398317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3408317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3418317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3428317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 36210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 36310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3648317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3658317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3668317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3678317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3688317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3698317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3708317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3718317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3728317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3738317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3748317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3758317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3768317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3778317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3788317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3798317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3808317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3818317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3828317SN/Asystem.cpu.itb.hits 0 # DTB hits 3838317SN/Asystem.cpu.itb.misses 0 # DTB misses 3848317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3858317SN/Asystem.cpu.workload.num_syscalls 548 # Number of system calls 38610409Sandreas.hansson@arm.comsystem.cpu.numCycles 463037632 # number of cpu cycles simulated 3878317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3888317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38910409Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss 39010409Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed 39110409Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered 39210409Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken 39310409Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked 39410409Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing 39510409Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39610409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps 39710409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR 39810409Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched 39910409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed 40010409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) 40110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) 40210409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) 4038317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40410409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) 40510409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) 40610409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) 40710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) 4088317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4098317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 41010409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 41110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) 41210409Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle 41310409Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle 41410409Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle 41510409Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked 41610409Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 287068107 # Number of cycles decode is running 41710409Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking 41810409Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing 41910409Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch 42010409Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction 42110409Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode 42210409Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode 42310409Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing 42410409Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle 42510409Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking 42610409Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst 42710409Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 276671864 # Number of cycles rename is running 42810409Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking 42910409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename 43010409Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename 43110409Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full 43210409Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full 43310409Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full 43410409Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full 43510409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed 43610409Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made 43710409Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups 43810409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 43910352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 44010409Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing 44110409Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed 44210409Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed 44310409Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer 44410409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. 44510409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. 44610409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. 44710409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. 44810409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) 44910409Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ 45010409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued 45110409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued 45210409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling 45310409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph 45410409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed 45510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle 45610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle 45710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle 4588317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45910409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle 46010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle 46110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle 46210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle 46310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle 46410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle 46510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 46610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 46710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4688317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4698317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 47010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 47110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle 4728317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available 47410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available 47510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available 47610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available 47710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available 47810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available 47910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available 48010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available 48110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 48210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available 48310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available 48410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available 48510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available 48610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available 48710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available 48810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available 48910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available 49010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available 49110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available 49210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available 49310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available 49410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available 49510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available 49610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available 49710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available 49810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available 49910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available 50010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available 50110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available 50210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available 50310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available 5048317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5058317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5068317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 50710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued 50810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued 50910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 51010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 51110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 51210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 51310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 51410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 51510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 51610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 51710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 51810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 51910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 52010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 52110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 52210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 52310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 52410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 52510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 52610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 52710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 52810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 52910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 53010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 53110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 53210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 53310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 53410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 53510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 53610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued 53710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued 5388317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5398317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 54010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 610228240 # Type of FU issued 54110409Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.317880 # Inst issue rate 54210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested 54310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) 54410409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads 54510409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes 54610409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses 54710409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 54810409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 5498317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 55010409Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses 55110409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 55210409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores 5538317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55410409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed 55510409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed 55610409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations 55710409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed 5588317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5598317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 56010409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled 56110409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked 5628317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56310409Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing 56410409Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking 56510409Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking 56610409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ 56710409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 56810409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions 56910409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions 57010409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions 57110409Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall 57210409Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall 57310409Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations 57410409Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly 57510409Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly 57610409Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute 57710409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions 57810409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed 57910409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute 5808317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 58110409Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1486621 # number of nop insts executed 58210409Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 190517594 # number of memory reference insts executed 58310409Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 131372634 # Number of branches executed 58410409Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 60949141 # Number of stores executed 58510409Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.294450 # Inst execution rate 58610409Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit 58710409Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 594959773 # cumulative count of insts written-back 58810409Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 349881958 # num instructions producing a value 58910409Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 570306345 # num instructions consuming a value 5908317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 59110409Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.284906 # insts written-back per cycle 59210409Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back 5938317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 59410409Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit 5959459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 59610409Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted 59710409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle 59810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle 59910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle 6008241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 60110409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle 60210409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle 60310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle 60410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle 60510409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle 60610409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle 60710409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle 60810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle 60910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle 6108241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6118241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6128241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle 6149459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 506581607 # Number of instructions committed 61510352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 6168317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61710352Sandreas.hansson@arm.comsystem.cpu.commit.refs 172745233 # Number of memory references committed 61810352Sandreas.hansson@arm.comsystem.cpu.commit.loads 115884756 # Number of loads committed 6198317SN/Asystem.cpu.commit.membars 1488542 # Number of memory barriers committed 6209459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 121548301 # Number of branches committed 6218241SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 62210352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 6238241SN/Asystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 62410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction 62610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 62710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 62810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 62910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 63010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 63110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 63210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 63310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 63410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 63510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 63610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 63710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 63810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 63910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 64010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 64110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 64210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 64310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 64410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 64510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 64610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 64710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 64810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 64910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 65010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 65110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 65210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 65310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 65410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 65510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 65610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 65910409Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached 6608317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 66110409Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1090469902 # The number of ROB reads 66210409Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1334452491 # The number of ROB writes 66310409Sandreas.hansson@arm.comsystem.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself 66410409Sandreas.hansson@arm.comsystem.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling 6659459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 505237723 # Number of Instructions Simulated 66610352Sandreas.hansson@arm.comsystem.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 66710409Sandreas.hansson@arm.comsystem.cpu.cpi 0.916475 # CPI: Cycles Per Instruction 66810409Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads 66910409Sandreas.hansson@arm.comsystem.cpu.ipc 1.091137 # IPC: Instructions Per Cycle 67010409Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads 67110409Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 611059108 # number of integer regfile reads 67210409Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 328109228 # number of integer regfile writes 6738317SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 67410409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads 67510409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 376537944 # number of cc regfile writes 67610409Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 217957701 # number of misc regfile reads 6779459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 67810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution 67910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution 68010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution 68110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution 68210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 68310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution 68410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution 68510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution 68610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution 68710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) 68810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) 68910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) 69010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) 69110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) 69210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) 69310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 453214 # Total snoops (count) 69410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram 69510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram 69610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram 69710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 69810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 69910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 70010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 70110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 70210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 70310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram 70410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram 70510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 70610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 70710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 70810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram 70910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) 71010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 71110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) 71210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 71310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) 7149729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 71510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) 71610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 71710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 73538 # number of replacements 71810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use 71910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. 72010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. 72110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. 72210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. 72310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor 72410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy 72510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy 72610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 72710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 72810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 72910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id 73010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 73110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id 73210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses 73410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 473451718 # Number of data accesses 73510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits 73610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits 73710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits 73810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits 73910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits 74010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 236609871 # number of overall hits 74110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses 74210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses 74310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses 74410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses 74510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses 74610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 78950 # number of overall misses 74710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles 74810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles 74910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles 75010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles 75110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles 75210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles 75310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) 75410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) 75510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses 75610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses 75710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses 75810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses 75910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses 76010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses 76110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses 76210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses 76310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses 76410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses 76510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency 76610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency 76710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 76810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency 76910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency 77010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency 77110409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked 77210409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked 77310409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked 77410409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 77510409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked 77610409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked 7778317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7788317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 77910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits 78010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits 78110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits 78210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits 78310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits 78410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits 78510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses 78610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses 78710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses 78810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses 78910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses 79010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses 79110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles 79210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles 79310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles 79410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles 79510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles 79610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles 79710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 79810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 79910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 80010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 80110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 80210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 80310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency 80410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency 80510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 80610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency 80710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency 80810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency 8098317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 81010409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified 81110409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr 81210409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache 81310409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue 81410409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 81510409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # number of hwpf removed because MSHR allocated 81610409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 365354 # number of hwpf issued 81710409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 921882 # number of hwpf spanning a virtual page 81810409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 81910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 438181 # number of replacements 82010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 15477.013957 # Cycle average of tags in use 82110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4572801 # Total number of references to valid blocks. 82210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 454520 # Sample count of references to valid blocks. 82310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 10.060726 # Average number of references to valid blocks. 82410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 34588215000 # Cycle when the warmup percentage was hit. 82510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 8046.531064 # Average occupied blocks per requestor 82610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 84.372204 # Average occupied blocks per requestor 82710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor 82810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor 82910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy 83010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy 83110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy 83210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy 83310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy 83410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id 83510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id 83610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id 83710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 83810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id 83910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id 84010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id 84110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 84210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 84310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id 84410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id 84510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id 84610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id 84710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id 84810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses 84910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 84920061 # Number of data accesses 85010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 70946 # number of ReadReq hits 85110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 2166314 # number of ReadReq hits 85210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2237260 # number of ReadReq hits 85310409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 2348838 # number of Writeback hits 85410409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 2348838 # number of Writeback hits 85510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 85610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 85710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 516602 # number of ReadExReq hits 85810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 516602 # number of ReadExReq hits 85910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 70946 # number of demand (read+write) hits 86010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2682916 # number of demand (read+write) hits 86110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2753862 # number of demand (read+write) hits 86210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 70946 # number of overall hits 86310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2682916 # number of overall hits 86410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2753862 # number of overall hits 86510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 3100 # number of ReadReq misses 86610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 135521 # number of ReadReq misses 86710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 138621 # number of ReadReq misses 86810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 86910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 87010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 5139 # number of ReadExReq misses 87110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 5139 # number of ReadExReq misses 87210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3100 # number of demand (read+write) misses 87310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 140660 # number of demand (read+write) misses 87410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 143760 # number of demand (read+write) misses 87510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3100 # number of overall misses 87610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 140660 # number of overall misses 87710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 143760 # number of overall misses 87810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221563221 # number of ReadReq miss cycles 87910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 9589796237 # number of ReadReq miss cycles 88010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 9811359458 # number of ReadReq miss cycles 88110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14999 # number of UpgradeReq miss cycles 88210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 14999 # number of UpgradeReq miss cycles 88310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 412963248 # number of ReadExReq miss cycles 88410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 412963248 # number of ReadExReq miss cycles 88510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 221563221 # number of demand (read+write) miss cycles 88610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10002759485 # number of demand (read+write) miss cycles 88710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 10224322706 # number of demand (read+write) miss cycles 88810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 221563221 # number of overall miss cycles 88910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10002759485 # number of overall miss cycles 89010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 10224322706 # number of overall miss cycles 89110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 74046 # number of ReadReq accesses(hits+misses) 89210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 2301835 # number of ReadReq accesses(hits+misses) 89310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2375881 # number of ReadReq accesses(hits+misses) 89410409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 2348838 # number of Writeback accesses(hits+misses) 89510409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 2348838 # number of Writeback accesses(hits+misses) 89610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 26 # number of UpgradeReq accesses(hits+misses) 89710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) 89810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 521741 # number of ReadExReq accesses(hits+misses) 89910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 521741 # number of ReadExReq accesses(hits+misses) 90010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 74046 # number of demand (read+write) accesses 90110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2823576 # number of demand (read+write) accesses 90210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2897622 # number of demand (read+write) accesses 90310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 74046 # number of overall (read+write) accesses 90410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2823576 # number of overall (read+write) accesses 90510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2897622 # number of overall (read+write) accesses 90610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.041866 # miss rate for ReadReq accesses 90710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.058875 # miss rate for ReadReq accesses 90810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.058345 # miss rate for ReadReq accesses 90910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses 91010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses 91110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009850 # miss rate for ReadExReq accesses 91210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.009850 # miss rate for ReadExReq accesses 91310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.041866 # miss rate for demand accesses 91410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.049816 # miss rate for demand accesses 91510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.049613 # miss rate for demand accesses 91610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.041866 # miss rate for overall accesses 91710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.049816 # miss rate for overall accesses 91810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.049613 # miss rate for overall accesses 91910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71472.006774 # average ReadReq miss latency 92010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70762.437091 # average ReadReq miss latency 92110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 70778.305293 # average ReadReq miss latency 92210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4999.666667 # average UpgradeReq miss latency 92310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4999.666667 # average UpgradeReq miss latency 92410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80358.678342 # average ReadExReq miss latency 92510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80358.678342 # average ReadExReq miss latency 92610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 92710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 92810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71120.775640 # average overall miss latency 92910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency 93010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency 93110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71120.775640 # average overall miss latency 93210409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 8362 # number of cycles access was blocked 9338317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93410409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 219 # number of cycles access was blocked 9358317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 93610409Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs 38.182648 # average number of cycles each access was blocked 9378983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9388317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 9397860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 94010409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 303849 # number of writebacks 94110409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 303849 # number of writebacks 94210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 992 # number of ReadReq MSHR hits 94310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5184 # number of ReadReq MSHR hits 94410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 6176 # number of ReadReq MSHR hits 94510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1526 # number of ReadExReq MSHR hits 94610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 1526 # number of ReadExReq MSHR hits 94710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 992 # number of demand (read+write) MSHR hits 94810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6710 # number of demand (read+write) MSHR hits 94910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 7702 # number of demand (read+write) MSHR hits 95010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 992 # number of overall MSHR hits 95110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6710 # number of overall MSHR hits 95210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 7702 # number of overall MSHR hits 95310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2108 # number of ReadReq MSHR misses 95410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 130337 # number of ReadReq MSHR misses 95510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 132445 # number of ReadReq MSHR misses 95610409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 365353 # number of HardPFReq MSHR misses 95710409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 365353 # number of HardPFReq MSHR misses 95810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 95910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 96010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3613 # number of ReadExReq MSHR misses 96110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 3613 # number of ReadExReq MSHR misses 96210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2108 # number of demand (read+write) MSHR misses 96310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 133950 # number of demand (read+write) MSHR misses 96410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 136058 # number of demand (read+write) MSHR misses 96510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2108 # number of overall MSHR misses 96610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 133950 # number of overall MSHR misses 96710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 365353 # number of overall MSHR misses 96810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 501411 # number of overall MSHR misses 96910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154832998 # number of ReadReq MSHR miss cycles 97010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8096605997 # number of ReadReq MSHR miss cycles 97110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 8251438995 # number of ReadReq MSHR miss cycles 97210409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of HardPFReq MSHR miss cycles 97310409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21877894699 # number of HardPFReq MSHR miss cycles 97410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 18003 # number of UpgradeReq MSHR miss cycles 97510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 18003 # number of UpgradeReq MSHR miss cycles 97610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 231375752 # number of ReadExReq MSHR miss cycles 97710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 231375752 # number of ReadExReq MSHR miss cycles 97810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154832998 # number of demand (read+write) MSHR miss cycles 97910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8327981749 # number of demand (read+write) MSHR miss cycles 98010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 8482814747 # number of demand (read+write) MSHR miss cycles 98110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154832998 # number of overall MSHR miss cycles 98210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8327981749 # number of overall MSHR miss cycles 98310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of overall MSHR miss cycles 98410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 30360709446 # number of overall MSHR miss cycles 98510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for ReadReq accesses 98610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.056623 # mshr miss rate for ReadReq accesses 98710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.055746 # mshr miss rate for ReadReq accesses 98810409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 98910409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 99010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses 99110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses 99210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses 99310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses 99410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses 99510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses 99610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses 99710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses 99810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses 99910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 100010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses 100110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency 100210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency 100310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency 100410409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency 100510409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency 100610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 100710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 100810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency 100910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency 101010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 101110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 101210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency 101310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency 101410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency 101510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency 101610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency 10177860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 101810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2823064 # number of replacements 101910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use 102010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. 102110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. 102210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. 102310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. 102410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor 102510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy 102610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy 102710409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 102810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 102910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 103010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id 103110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 103210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses 103310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses 103410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits 103510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits 103610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits 103710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits 103810409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits 103910409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits 104010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits 104110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits 10429459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 10439459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 104410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits 104510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits 104610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits 104710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 166678355 # number of overall hits 104810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses 104910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses 105010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses 105110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses 105210409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses 105310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses 105410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 105510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 105610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses 105710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses 105810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses 105910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 7049008 # number of overall misses 106010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles 106110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles 106210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles 106310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles 106410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles 106510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles 106610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles 106710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles 106810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles 106910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles 107010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) 107110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) 10729449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 10739449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 107410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) 107510409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) 107610409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) 107710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) 10789459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 10799459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 108010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses 108110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses 108210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses 108310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses 108410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses 108510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses 108610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses 108710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses 108810409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses 108910409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses 109010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 109110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 109210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses 109310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses 109410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses 109510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses 109610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency 109710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency 109810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency 109910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency 110010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency 110110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency 110210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency 110310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency 110410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency 110510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency 110610409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked 110710409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked 110810409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 110910409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked 111010409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked 111110409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked 11129449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 11139449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 111410409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks 111510409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 2348838 # number of writebacks 111610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits 111710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits 111810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits 111910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits 112010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 112110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 112210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits 112310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits 112410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits 112510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits 112610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses 112710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses 112810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses 112910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses 113010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 113110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 113210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses 113310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses 113410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses 113510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses 113610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles 113710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles 113810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles 113910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles 114010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles 114110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles 114210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles 114310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles 114410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles 114510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles 114610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses 114710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses 114810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses 114910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses 115010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses 115110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses 115210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses 115310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses 115410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses 115510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses 115610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency 115710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency 115810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency 115910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency 116010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency 116110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency 116210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency 116310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency 116410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency 116510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency 11669449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 11677860SN/A 11687860SN/A---------- End Simulation Statistics ---------- 1169