stats.txt revision 10220
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310220Sandreas.hansson@arm.comsim_seconds 0.202425 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 202425052500 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 117924 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 132952 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 47246555 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 317744 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 4284.44 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 505237723 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 569624283 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory 1710220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9265920 # Number of bytes read from this memory 1810220Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 9482048 # Number of bytes read from this memory 1910220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory 2010220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory 2110220Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 6248320 # Number of bytes written to this memory 2210220Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 6248320 # Number of bytes written to this memory 2310220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 144780 # Number of read requests responded to by this memory 2510220Sandreas.hansson@arm.comsystem.physmem.num_reads::total 148157 # Number of read requests responded to by this memory 2610220Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 97630 # Number of write requests responded to by this memory 2710220Sandreas.hansson@arm.comsystem.physmem.num_writes::total 97630 # Number of write requests responded to by this memory 2810220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1067694 # Total read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 45774571 # Total read bandwidth from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 46842265 # Total read bandwidth from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1067694 # Instruction read bandwidth from this memory (bytes/s) 3210220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1067694 # Instruction read bandwidth from this memory (bytes/s) 3310220Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 30867326 # Write bandwidth from this memory (bytes/s) 3410220Sandreas.hansson@arm.comsystem.physmem.bw_write::total 30867326 # Write bandwidth from this memory (bytes/s) 3510220Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 30867326 # Total bandwidth to/from this memory (bytes/s) 3610220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1067694 # Total bandwidth to/from this memory (bytes/s) 3710220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 45774571 # Total bandwidth to/from this memory (bytes/s) 3810220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 77709591 # Total bandwidth to/from this memory (bytes/s) 3910220Sandreas.hansson@arm.comsystem.physmem.readReqs 148159 # Number of read requests accepted 4010220Sandreas.hansson@arm.comsystem.physmem.writeReqs 97630 # Number of write requests accepted 4110220Sandreas.hansson@arm.comsystem.physmem.readBursts 148159 # Number of DRAM read bursts, including those serviced by the write queue 4210220Sandreas.hansson@arm.comsystem.physmem.writeBursts 97630 # Number of DRAM write bursts, including those merged in the write queue 4310220Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 9473600 # Total number of bytes read from DRAM 4410220Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue 4510220Sandreas.hansson@arm.comsystem.physmem.bytesWritten 6247040 # Total number of bytes written to DRAM 4610220Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 9482176 # Total read bytes from the system interface side 4710220Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 6248320 # Total written bytes from the system interface side 4810220Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue 499978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5010220Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 5 # Number of requests that are neither read nor write 5110220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 9589 # Per bank write bursts 5210220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 9250 # Per bank write bursts 5310220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 9271 # Per bank write bursts 5410220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 8997 # Per bank write bursts 5510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 9766 # Per bank write bursts 5610220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 9623 # Per bank write bursts 5710220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 9103 # Per bank write bursts 5810220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 8296 # Per bank write bursts 5910220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 8815 # Per bank write bursts 6010220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 8915 # Per bank write bursts 6110220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 8926 # Per bank write bursts 6210220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 9755 # Per bank write bursts 6310220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9632 # Per bank write bursts 6410220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 9741 # Per bank write bursts 6510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 8922 # Per bank write bursts 6610220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 9424 # Per bank write bursts 6710220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 6257 # Per bank write bursts 6810220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 6164 # Per bank write bursts 6910220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 6102 # Per bank write bursts 7010220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 5898 # Per bank write bursts 7110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 6263 # Per bank write bursts 7210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6268 # Per bank write bursts 7310220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6040 # Per bank write bursts 7410220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 5542 # Per bank write bursts 7510220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 5815 # Per bank write bursts 7610220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 5905 # Per bank write bursts 7710220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 5986 # Per bank write bursts 7810220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6523 # Per bank write bursts 7910220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 6368 # Per bank write bursts 8010220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 6315 # Per bank write bursts 8110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 6035 # Per bank write bursts 8210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 6129 # Per bank write bursts 839978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 849978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8510220Sandreas.hansson@arm.comsystem.physmem.totGap 202425037000 # Total gap between requests 869978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9210220Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 148159 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9910220Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 97630 # Write request sizes (log2) 10010220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 138435 # What read queue length does an incoming req see 10110220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 9034 # What read queue length does an incoming req see 10210220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see 10310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see 10410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 10510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 10610148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 2247 # What write queue length does an incoming req see 14810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see 14910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 5335 # What write queue length does an incoming req see 15010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see 15110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5818 # What write queue length does an incoming req see 15210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 5824 # What write queue length does an incoming req see 15310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5835 # What write queue length does an incoming req see 15410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5828 # What write queue length does an incoming req see 15510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5866 # What write queue length does an incoming req see 15610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 5860 # What write queue length does an incoming req see 15710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 5849 # What write queue length does an incoming req see 15810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 5863 # What write queue length does an incoming req see 15910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 5973 # What write queue length does an incoming req see 16010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 5919 # What write queue length does an incoming req see 16110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 5829 # What write queue length does an incoming req see 16210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 5845 # What write queue length does an incoming req see 16310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 5807 # What write queue length does an incoming req see 16410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5734 # What write queue length does an incoming req see 16510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see 16610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 7 # What write queue length does an incoming req see 16710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see 16810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 16910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 17010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 17110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 17210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 65421 # Bytes accessed per row activation 19710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 240.288837 # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 153.819388 # Bytes accessed per row activation 19910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 255.394880 # Bytes accessed per row activation 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 26636 40.71% 40.71% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 17331 26.49% 67.21% # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 6016 9.20% 76.40% # Bytes accessed per row activation 20310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 6235 9.53% 85.93% # Bytes accessed per row activation 20410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3111 4.76% 90.69% # Bytes accessed per row activation 20510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1372 2.10% 92.79% # Bytes accessed per row activation 20610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 907 1.39% 94.17% # Bytes accessed per row activation 20710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 656 1.00% 95.17% # Bytes accessed per row activation 20810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 3157 4.83% 100.00% # Bytes accessed per row activation 20910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 65421 # Bytes accessed per row activation 21010220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes 21110220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 25.864057 # Reads before turning the bus around for writes 21210220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 376.771836 # Reads before turning the bus around for writes 21310220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 5718 99.91% 99.91% # Reads before turning the bus around for writes 21410220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes 21510148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 21610220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes 21710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads 21810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.055740 # Writes before turning the bus around for reads 21910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.965515 # Writes before turning the bus around for reads 22010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 2.130372 # Writes before turning the bus around for reads 22110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-17 3465 60.55% 60.55% # Writes before turning the bus around for reads 22210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18-19 2071 36.19% 96.73% # Writes before turning the bus around for reads 22310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-21 82 1.43% 98.17% # Writes before turning the bus around for reads 22410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22-23 27 0.47% 98.64% # Writes before turning the bus around for reads 22510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-25 23 0.40% 99.04% # Writes before turning the bus around for reads 22610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads 22710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-29 13 0.23% 99.60% # Writes before turning the bus around for reads 22810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::30-31 7 0.12% 99.72% # Writes before turning the bus around for reads 22910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-33 3 0.05% 99.77% # Writes before turning the bus around for reads 23010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::34-35 3 0.05% 99.83% # Writes before turning the bus around for reads 23110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-37 1 0.02% 99.84% # Writes before turning the bus around for reads 23210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::42-43 3 0.05% 99.90% # Writes before turning the bus around for reads 23310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-45 1 0.02% 99.91% # Writes before turning the bus around for reads 23410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::46-47 2 0.03% 99.95% # Writes before turning the bus around for reads 23510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::50-51 1 0.02% 99.97% # Writes before turning the bus around for reads 23610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads 23710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-69 1 0.02% 100.00% # Writes before turning the bus around for reads 23810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads 23910220Sandreas.hansson@arm.comsystem.physmem.totQLat 1821123750 # Total ticks spent queuing 24010220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 4596592500 # Total ticks spent from burst creation until serviced by the DRAM 24110220Sandreas.hansson@arm.comsystem.physmem.totBusLat 740125000 # Total ticks spent in databus transfers 24210220Sandreas.hansson@arm.comsystem.physmem.avgQLat 12302.81 # Average queueing delay per DRAM burst 2439978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24410220Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 31052.81 # Average memory access latency per DRAM burst 24510220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 46.80 # Average DRAM read bandwidth in MiByte/s 24610220Sandreas.hansson@arm.comsystem.physmem.avgWrBW 30.86 # Average achieved write bandwidth in MiByte/s 24710220Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 46.84 # Average system read bandwidth in MiByte/s 24810220Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 30.87 # Average system write bandwidth in MiByte/s 2499978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2509490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.61 # Data bus utilization in percentage 2519978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads 2529978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes 25310220Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 25410220Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 19.22 # Average write queue length when enqueuing 25510220Sandreas.hansson@arm.comsystem.physmem.readRowHits 115945 # Number of row buffer hits during reads 25610220Sandreas.hansson@arm.comsystem.physmem.writeRowHits 64262 # Number of row buffer hits during writes 25710220Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 78.33 # Row buffer hit rate for reads 25810220Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 65.82 # Row buffer hit rate for writes 25910220Sandreas.hansson@arm.comsystem.physmem.avgGap 823572.40 # Average gap between requests 26010220Sandreas.hansson@arm.comsystem.physmem.pageHitRate 73.36 # Row buffer hit rate, read and write combined 26110220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 121085417750 # Time in different power states 26210220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 6759220000 # Time in different power states 26310220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 26410220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 74577349250 # Time in different power states 26510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 26610220Sandreas.hansson@arm.comsystem.membus.throughput 77709591 # Throughput (bytes/s) 26710220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 46864 # Transaction distribution 26810220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 46862 # Transaction distribution 26910220Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 97630 # Transaction distribution 27010220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 5 # Transaction distribution 27110220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 5 # Transaction distribution 27210220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 101295 # Transaction distribution 27310220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 101295 # Transaction distribution 27410220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393956 # Packet count per connected master and slave (bytes) 27510220Sandreas.hansson@arm.comsystem.membus.pkt_count::total 393956 # Packet count per connected master and slave (bytes) 27610220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15730368 # Cumulative packet size per connected master and slave (bytes) 27710220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 15730368 # Cumulative packet size per connected master and slave (bytes) 27810220Sandreas.hansson@arm.comsystem.membus.data_through_bus 15730368 # Total data (bytes) 2799729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 28010220Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 1082435500 # Layer occupancy (ticks) 2819729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 28210220Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 1397409745 # Layer occupancy (ticks) 2839729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.7 # Layer utilization (%) 28410036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 28510220Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 182802818 # Number of BP lookups 28610220Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 143112021 # Number of conditional branches predicted 28710220Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 7267941 # Number of conditional branches incorrect 28810220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 93011295 # Number of BTB lookups 28910220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 87213055 # Number of BTB hits 2909482Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29110220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 93.766090 # BTB Hit Percentage 29210220Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 12678218 # Number of times the RAS was used to get a target. 29310148Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. 29410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 31310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 31410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3158317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3168317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3178317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3188317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3198317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3208317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3218317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3228317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3238317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3248317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3258317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3268317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3278317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3288317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3298317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3308317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3318317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3328317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3338317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3348317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3358317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 33610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3578317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3588317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3598317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3608317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3618317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3628317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3638317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3648317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3658317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3668317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3678317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3688317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3698317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3708317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3718317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3728317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3738317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3748317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3758317SN/Asystem.cpu.itb.hits 0 # DTB hits 3768317SN/Asystem.cpu.itb.misses 0 # DTB misses 3778317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3788317SN/Asystem.cpu.workload.num_syscalls 548 # Number of system calls 37910220Sandreas.hansson@arm.comsystem.cpu.numCycles 404850106 # number of cpu cycles simulated 3808317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3818317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38210220Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 119389916 # Number of cycles fetch is stalled on an Icache miss 38310220Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 761628718 # Number of instructions fetch has processed 38410220Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 182802818 # Number of branches that fetch encountered 38510220Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 99891273 # Number of branches that fetch has predicted taken 38610220Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 170150143 # Number of cycles fetch has run and was not squashing or blocked 38710220Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 35691365 # Number of cycles fetch has spent squashing 38810220Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 77449263 # Number of cycles fetch has spent blocked 38910220Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39010220Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 486 # Number of stall cycles due to pending traps 39110220Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 39210220Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 114538694 # Number of cache lines fetched 39310220Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 2440341 # Number of outstanding Icache misses that were squashed 39410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 394609388 # Number of instructions fetched each cycle (Total) 39510220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 2.164838 # Number of instructions fetched each cycle (Total) 39610220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.986971 # Number of instructions fetched each cycle (Total) 3978317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 39810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 224471880 56.88% 56.88% # Number of instructions fetched each cycle (Total) 39910220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 14182431 3.59% 60.48% # Number of instructions fetched each cycle (Total) 40010220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 22892997 5.80% 66.28% # Number of instructions fetched each cycle (Total) 40110220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 22746730 5.76% 72.04% # Number of instructions fetched each cycle (Total) 40210220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 20891038 5.29% 77.34% # Number of instructions fetched each cycle (Total) 40310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 11596009 2.94% 80.28% # Number of instructions fetched each cycle (Total) 40410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 13056866 3.31% 83.59% # Number of instructions fetched each cycle (Total) 40510220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 12000205 3.04% 86.63% # Number of instructions fetched each cycle (Total) 40610220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 52771232 13.37% 100.00% # Number of instructions fetched each cycle (Total) 4078317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4088317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4098317SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 41010220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 394609388 # Number of instructions fetched each cycle (Total) 41110220Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.451532 # Number of branch fetches per cycle 41210220Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.881261 # Number of inst fetches per cycle 41310220Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 129090145 # Number of cycles decode is idle 41410220Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 72932890 # Number of cycles decode is blocked 41510220Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 158811519 # Number of cycles decode is running 41610220Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 6229483 # Number of cycles decode is unblocking 41710220Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 27545351 # Number of cycles decode is squashing 41810220Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 26129524 # Number of times decode resolved a branch 41910220Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 76858 # Number of times decode detected a branch misprediction 42010220Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 825625828 # Number of instructions handled by decode 42110220Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 295316 # Number of squashed instructions handled by decode 42210220Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 27545351 # Number of cycles rename is squashing 42310220Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 135687065 # Number of cycles rename is idle 42410220Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 10105791 # Number of cycles rename is blocking 42510220Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 47805401 # count of cycles rename stalled for serializing inst 42610220Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 158260364 # Number of cycles rename is running 42710220Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 15205416 # Number of cycles rename is unblocking 42810220Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 800656323 # Number of instructions processed by rename 42910220Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 1334 # Number of times rename has blocked due to ROB full 43010220Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 3053839 # Number of times rename has blocked due to IQ full 43110220Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 8954907 # Number of times rename has blocked due to LSQ full 43210220Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 385 # Number of times there has been no free registers 43310220Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 954272169 # Number of destination operands rename has renamed 43410220Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 3518760229 # Number of register rename lookups that rename has made 43510220Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 3237464445 # Number of integer rename lookups 43610220Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 4379459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed 43810220Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 288019878 # Number of HB maps that are undone due to squashing 43910220Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 2292922 # count of serializing insts renamed 44010220Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 2292918 # count of temporary serializing insts renamed 44110220Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 41836509 # count of insts added to the skid buffer 44210220Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 170268509 # Number of loads inserted to the mem dependence unit. 44310220Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 73501316 # Number of stores inserted to the mem dependence unit. 44410220Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 28634884 # Number of conflicting loads. 44510220Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 15888043 # Number of conflicting stores. 44610220Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 755077640 # Number of instructions added to the IQ (excludes non-spec) 44710220Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 3775313 # Number of non-speculative instructions added to the IQ 44810220Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 665327015 # Number of instructions issued 44910220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 1386285 # Number of squashed instructions issued 45010220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 187386746 # Number of squashed instructions iterated over during squash; mainly for profiling 45110220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 479953007 # Number of squashed operands that are examined and possibly removed from graph 45210220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 797681 # Number of squashed non-spec instructions that were removed 45310220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 394609388 # Number of insts issued each cycle 45410220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.686039 # Number of insts issued each cycle 45510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.735073 # Number of insts issued each cycle 4568317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45710220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 139096453 35.25% 35.25% # Number of insts issued each cycle 45810220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 69938770 17.72% 52.97% # Number of insts issued each cycle 45910220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 71532009 18.13% 71.10% # Number of insts issued each cycle 46010220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 53395901 13.53% 84.63% # Number of insts issued each cycle 46110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 31139583 7.89% 92.52% # Number of insts issued each cycle 46210220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 15999118 4.05% 96.58% # Number of insts issued each cycle 46310220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 8786717 2.23% 98.80% # Number of insts issued each cycle 46410220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 2904396 0.74% 99.54% # Number of insts issued each cycle 46510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 1816441 0.46% 100.00% # Number of insts issued each cycle 4668317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4678317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4688317SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 46910220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 394609388 # Number of insts issued each cycle 4708317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 479561 5.00% 5.00% # attempts to use FU when none available 47210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available 47310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available 47410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available 47510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available 47610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available 47710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available 47810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available 47910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available 48010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available 48110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available 48210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available 48310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available 48410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available 48510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available 48610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available 48710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available 48810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available 48910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available 49010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available 49110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available 49210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available 49310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available 49410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available 49510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available 49610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available 49710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available 49810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available 49910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available 50010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 6536466 68.14% 73.13% # attempts to use FU when none available 50110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 2577260 26.87% 100.00% # attempts to use FU when none available 5028317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5038317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5048317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 50510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 447787138 67.30% 67.30% # Type of FU issued 50610220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 383414 0.06% 67.36% # Type of FU issued 5079459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued 50810038SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued 5099459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 5109459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 5119459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 5129459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 5139459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 5149459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 5159459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 5169459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued 5179459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued 5189459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued 5199459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued 5209459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued 5219459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued 5229459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued 5239459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued 5249459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued 5259459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued 5269459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 5279459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 5289459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 5299459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 5309459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 5319459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 5329459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 5339459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued 53410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 153368040 23.05% 90.41% # Type of FU issued 53510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 63788326 9.59% 100.00% # Type of FU issued 5368317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5378317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 53810220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 665327015 # Type of FU issued 53910220Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.643391 # Inst issue rate 54010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 9593287 # FU busy when requested 54110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.014419 # FU busy rate (busy events/executed inst) 54210220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 1736242767 # Number of integer instruction queue reads 54310220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 947046337 # Number of integer instruction queue writes 54410220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 646056325 # Number of integer instruction queue wakeup accesses 54510148Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads 54610148Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes 5478317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 54810220Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 674920189 # Number of integer alu accesses 54910038SAli.Saidi@ARM.comsystem.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses 55010220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 8551877 # Number of loads that had data forwarded from stores 5518317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55210220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 44238954 # Number of loads squashed 55310220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 41472 # Number of memory responses ignored because the instruction is squashed 55410220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 810610 # Number of memory ordering violations 55510220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 16640839 # Number of stores squashed 5568317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5578317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 55810220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 19493 # Number of loads that were rescheduled 55910220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 7969 # Number of times an access to memory failed due to the cache being blocked 5608317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56110220Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 27545351 # Number of cycles IEW is squashing 56210220Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 5256121 # Number of cycles IEW is blocking 56310220Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 385567 # Number of cycles IEW is unblocking 56410220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 760412013 # Number of instructions dispatched to IQ 56510220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 1120947 # Number of squashed instructions skipped by dispatch 56610220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 170268509 # Number of dispatched load instructions 56710220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 73501316 # Number of dispatched store instructions 56810220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 2286771 # Number of dispatched non-speculative instructions 56910220Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 219704 # Number of times the IQ has become full, causing a stall 57010220Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 12090 # Number of times the LSQ has become full, causing a stall 57110220Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 810610 # Number of memory order violations 57210220Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 4341838 # Number of branches that were predicted taken incorrectly 57310220Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 4001214 # Number of branches that were predicted not taken incorrectly 57410220Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 8343052 # Number of branch mispredicts detected at execute 57510220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 655907838 # Number of executed instructions 57610220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 150084771 # Number of load instructions executed 57710220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 9419177 # Number of squashed instructions skipped in execute 5788317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 57910220Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1559060 # number of nop insts executed 58010220Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 212583673 # number of memory reference insts executed 58110220Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 138498504 # Number of branches executed 58210220Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 62498902 # Number of stores executed 58310220Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.620125 # Inst execution rate 58410220Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 651026464 # cumulative count of insts sent to commit 58510220Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 646056341 # cumulative count of insts written-back 58610220Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 374698942 # num instructions producing a value 58710220Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 646299992 # num instructions consuming a value 5888317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 58910220Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.595791 # insts written-back per cycle 59010220Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back 5918317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 59210220Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 189472037 # The number of squashed insts skipped by commit 5939459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 59410220Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 7193780 # The number of times a branch was mispredicted 59510220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 367064037 # Number of insts commited each cycle 59610220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.555500 # Number of insts commited each cycle 59710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.230573 # Number of insts commited each cycle 5988241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 59910220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 159337830 43.41% 43.41% # Number of insts commited each cycle 60010220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 98602437 26.86% 70.27% # Number of insts commited each cycle 60110220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 33803348 9.21% 79.48% # Number of insts commited each cycle 60210220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 18720540 5.10% 84.58% # Number of insts commited each cycle 60310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 16173781 4.41% 88.99% # Number of insts commited each cycle 60410220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 7454535 2.03% 91.02% # Number of insts commited each cycle 60510220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 6985415 1.90% 92.92% # Number of insts commited each cycle 60610220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 3172083 0.86% 93.78% # Number of insts commited each cycle 60710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 22814068 6.22% 100.00% # Number of insts commited each cycle 6088241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6098241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6108241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61110220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 367064037 # Number of insts commited each cycle 6129459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 506581607 # Number of instructions committed 6139459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 6148317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 6159459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 182890032 # Number of memory references committed 6169459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 126029555 # Number of loads committed 6178317SN/Asystem.cpu.commit.membars 1488542 # Number of memory barriers committed 6189459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 121548301 # Number of branches committed 6198241SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 6209459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 6218241SN/Asystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 62210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction 62410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction 62510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction 62610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction 62710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction 62810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction 62910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction 63010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction 63110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction 63210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction 63310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction 63410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction 63510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction 63610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction 63710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction 63810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction 63910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction 64010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction 64110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction 64210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction 64310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction 64410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction 64510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction 64610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction 64710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction 64810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction 64910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction 65010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction 65110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction 65210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction 65310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction 65410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 570968167 # Class of committed instruction 65710220Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached 6588317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 65910220Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1104683035 # The number of ROB reads 66010220Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1548546574 # The number of ROB writes 66110220Sandreas.hansson@arm.comsystem.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself 66210220Sandreas.hansson@arm.comsystem.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling 6639459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 505237723 # Number of Instructions Simulated 6649459Ssaidi@eecs.umich.edusystem.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 6659459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 505237723 # Number of Instructions Simulated 66610220Sandreas.hansson@arm.comsystem.cpu.cpi 0.801306 # CPI: Cycles Per Instruction 66710220Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads 66810220Sandreas.hansson@arm.comsystem.cpu.ipc 1.247962 # IPC: Instructions Per Cycle 66910220Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads 67010220Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 3058680468 # number of integer regfile reads 67110220Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 751974394 # number of integer regfile writes 6728317SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 67310220Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 237852228 # number of misc regfile reads 6749459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 67510220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 734945552 # Throughput (bytes/s) 67610220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 864760 # Transaction distribution 67710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 864758 # Transaction distribution 67810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 1110914 # Transaction distribution 67910220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution 68010220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution 68110220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 348881 # Transaction distribution 68210220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 348881 # Transaction distribution 68310220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33826 # Packet count per connected master and slave (bytes) 68410220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504415 # Packet count per connected master and slave (bytes) 68510220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 3538241 # Packet count per connected master and slave (bytes) 68610220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079872 # Cumulative packet size per connected master and slave (bytes) 68710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147686464 # Cumulative packet size per connected master and slave (bytes) 68810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 148766336 # Cumulative packet size per connected master and slave (bytes) 68910220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 148766336 # Total data (bytes) 69010220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) 69110220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2273224996 # Layer occupancy (ticks) 6929729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 69310220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 26000486 # Layer occupancy (ticks) 6949729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 69510220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1824563475 # Layer occupancy (ticks) 6969729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 69710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15031 # number of replacements 69810220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1100.518238 # Cycle average of tags in use 69910220Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 114517542 # Total number of references to valid blocks. 70010220Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 16885 # Sample count of references to valid blocks. 70110220Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 6782.205626 # Average number of references to valid blocks. 7029838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70310220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1100.518238 # Average occupied blocks per requestor 70410220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.537362 # Average percentage of cache occupancy 70510220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.537362 # Average percentage of cache occupancy 70610220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1854 # Occupied blocks per task id 70710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 70810220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 70910220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 71010220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 292 # Occupied blocks per task id 71110220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id 71210220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id 71310220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 229094338 # Number of tag accesses 71410220Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 229094338 # Number of data accesses 71510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 114517542 # number of ReadReq hits 71610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 114517542 # number of ReadReq hits 71710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 114517542 # number of demand (read+write) hits 71810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 114517542 # number of demand (read+write) hits 71910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 114517542 # number of overall hits 72010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 114517542 # number of overall hits 72110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 21151 # number of ReadReq misses 72210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 21151 # number of ReadReq misses 72310220Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 21151 # number of demand (read+write) misses 72410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 21151 # number of demand (read+write) misses 72510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 21151 # number of overall misses 72610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 21151 # number of overall misses 72710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 554005735 # number of ReadReq miss cycles 72810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 554005735 # number of ReadReq miss cycles 72910220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 554005735 # number of demand (read+write) miss cycles 73010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 554005735 # number of demand (read+write) miss cycles 73110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 554005735 # number of overall miss cycles 73210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 554005735 # number of overall miss cycles 73310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 114538693 # number of ReadReq accesses(hits+misses) 73410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 114538693 # number of ReadReq accesses(hits+misses) 73510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 114538693 # number of demand (read+write) accesses 73610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 114538693 # number of demand (read+write) accesses 73710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 114538693 # number of overall (read+write) accesses 73810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 114538693 # number of overall (read+write) accesses 73910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses 74010220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses 74110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses 74210220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses 74310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses 74410220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses 74510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152 # average ReadReq miss latency 74610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152 # average ReadReq miss latency 74710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency 74810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 26192.886152 # average overall miss latency 74910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency 75010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 26192.886152 # average overall miss latency 75110220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 775 # number of cycles access was blocked 7528317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75310220Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked 7548317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 75510220Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 51.666667 # average number of cycles each access was blocked 7568983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7578317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7588317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 75910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 4198 # number of ReadReq MSHR hits 76010220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 4198 # number of ReadReq MSHR hits 76110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 4198 # number of demand (read+write) MSHR hits 76210220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 4198 # number of demand (read+write) MSHR hits 76310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 4198 # number of overall MSHR hits 76410220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 4198 # number of overall MSHR hits 76510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 16953 # number of ReadReq MSHR misses 76610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 16953 # number of ReadReq MSHR misses 76710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 16953 # number of demand (read+write) MSHR misses 76810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 16953 # number of demand (read+write) MSHR misses 76910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 16953 # number of overall MSHR misses 77010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 16953 # number of overall MSHR misses 77110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401201263 # number of ReadReq MSHR miss cycles 77210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 401201263 # number of ReadReq MSHR miss cycles 77310220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 401201263 # number of demand (read+write) MSHR miss cycles 77410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 401201263 # number of demand (read+write) MSHR miss cycles 77510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 401201263 # number of overall MSHR miss cycles 77610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 401201263 # number of overall MSHR miss cycles 77710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 77810148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 77910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 78010148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 78110148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 78210148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses 78310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.502448 # average ReadReq mshr miss latency 78410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.502448 # average ReadReq mshr miss latency 78510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency 78610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency 78710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency 78810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency 7898317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 79010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 115416 # number of replacements 79110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 27085.834103 # Cycle average of tags in use 79210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1781268 # Total number of references to valid blocks. 79310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 146665 # Sample count of references to valid blocks. 79410220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 12.145147 # Average number of references to valid blocks. 79510220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 89916309500 # Cycle when the warmup percentage was hit. 79610220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 23017.620858 # Average occupied blocks per requestor 79710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 361.438946 # Average occupied blocks per requestor 79810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 3706.774299 # Average occupied blocks per requestor 79910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.702442 # Average percentage of cache occupancy 80010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.011030 # Average percentage of cache occupancy 80110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.113122 # Average percentage of cache occupancy 80210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.826594 # Average percentage of cache occupancy 80310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 31249 # Occupied blocks per task id 80410220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 80510220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id 80610220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 7681 # Occupied blocks per task id 80710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 21304 # Occupied blocks per task id 80810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id 80910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 19091917 # Number of tag accesses 81010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 19091917 # Number of data accesses 81110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 13492 # number of ReadReq hits 81210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 804297 # number of ReadReq hits 81310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 817789 # number of ReadReq hits 81410220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1110914 # number of Writeback hits 81510220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1110914 # number of Writeback hits 81610220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 59 # number of UpgradeReq hits 81710220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 59 # number of UpgradeReq hits 81810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 247585 # number of ReadExReq hits 81910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 247585 # number of ReadExReq hits 82010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 13492 # number of demand (read+write) hits 82110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1051882 # number of demand (read+write) hits 82210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1065374 # number of demand (read+write) hits 82310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 13492 # number of overall hits 82410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1051882 # number of overall hits 82510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1065374 # number of overall hits 82610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses 82710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 43510 # number of ReadReq misses 82810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 46892 # number of ReadReq misses 82910220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 83010220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 83110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 101296 # number of ReadExReq misses 83210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 101296 # number of ReadExReq misses 83310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses 83410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 144806 # number of demand (read+write) misses 83510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 148188 # number of demand (read+write) misses 83610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses 83710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 144806 # number of overall misses 83810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 148188 # number of overall misses 83910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248983750 # number of ReadReq miss cycles 84010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3325064500 # number of ReadReq miss cycles 84110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 3574048250 # number of ReadReq miss cycles 84210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7369870249 # number of ReadExReq miss cycles 84310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7369870249 # number of ReadExReq miss cycles 84410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 248983750 # number of demand (read+write) miss cycles 84510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10694934749 # number of demand (read+write) miss cycles 84610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 10943918499 # number of demand (read+write) miss cycles 84710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 248983750 # number of overall miss cycles 84810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10694934749 # number of overall miss cycles 84910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 10943918499 # number of overall miss cycles 85010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 16874 # number of ReadReq accesses(hits+misses) 85110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 847807 # number of ReadReq accesses(hits+misses) 85210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 864681 # number of ReadReq accesses(hits+misses) 85310220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1110914 # number of Writeback accesses(hits+misses) 85410220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1110914 # number of Writeback accesses(hits+misses) 85510220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) 85610220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) 85710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 348881 # number of ReadExReq accesses(hits+misses) 85810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 348881 # number of ReadExReq accesses(hits+misses) 85910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 16874 # number of demand (read+write) accesses 86010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1196688 # number of demand (read+write) accesses 86110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 1213562 # number of demand (read+write) accesses 86210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 16874 # number of overall (read+write) accesses 86310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1196688 # number of overall (read+write) accesses 86410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 1213562 # number of overall (read+write) accesses 86510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200427 # miss rate for ReadReq accesses 86610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051321 # miss rate for ReadReq accesses 86710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.054230 # miss rate for ReadReq accesses 86810220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.063492 # miss rate for UpgradeReq accesses 86910220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.063492 # miss rate for UpgradeReq accesses 87010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290345 # miss rate for ReadExReq accesses 87110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.290345 # miss rate for ReadExReq accesses 87210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.200427 # miss rate for demand accesses 87310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.121006 # miss rate for demand accesses 87410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.122110 # miss rate for demand accesses 87510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.200427 # miss rate for overall accesses 87610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.121006 # miss rate for overall accesses 87710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.122110 # miss rate for overall accesses 87810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73620.269072 # average ReadReq miss latency 87910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76420.696392 # average ReadReq miss latency 88010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 76218.720677 # average ReadReq miss latency 88110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72755.787484 # average ReadExReq miss latency 88210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 72755.787484 # average ReadExReq miss latency 88310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency 88410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency 88510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 73851.583792 # average overall miss latency 88610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency 88710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency 88810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 73851.583792 # average overall miss latency 8898317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8908317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8918317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8928317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8938983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8948983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8958317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8967860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 89710220Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 97630 # number of writebacks 89810220Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 97630 # number of writebacks 89910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 90010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 90110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 90210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 90310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits 90410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 90510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 90610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits 90710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits 90810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses 90910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43486 # number of ReadReq MSHR misses 91010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 46864 # number of ReadReq MSHR misses 91110220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses 91210220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses 91310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101296 # number of ReadExReq MSHR misses 91410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 101296 # number of ReadExReq MSHR misses 91510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses 91610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 144782 # number of demand (read+write) MSHR misses 91710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 148160 # number of demand (read+write) MSHR misses 91810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses 91910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 144782 # number of overall MSHR misses 92010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 148160 # number of overall MSHR misses 92110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 206192500 # number of ReadReq MSHR miss cycles 92210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2779400500 # number of ReadReq MSHR miss cycles 92310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 2985593000 # number of ReadReq MSHR miss cycles 92410220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 40004 # number of UpgradeReq MSHR miss cycles 92510220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 40004 # number of UpgradeReq MSHR miss cycles 92610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6084575751 # number of ReadExReq MSHR miss cycles 92710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6084575751 # number of ReadExReq MSHR miss cycles 92810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206192500 # number of demand (read+write) MSHR miss cycles 92910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8863976251 # number of demand (read+write) MSHR miss cycles 93010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 9070168751 # number of demand (read+write) MSHR miss cycles 93110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206192500 # number of overall MSHR miss cycles 93210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8863976251 # number of overall MSHR miss cycles 93310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 9070168751 # number of overall MSHR miss cycles 93410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for ReadReq accesses 93510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051292 # mshr miss rate for ReadReq accesses 93610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054198 # mshr miss rate for ReadReq accesses 93710220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for UpgradeReq accesses 93810220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.063492 # mshr miss rate for UpgradeReq accesses 93910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses 94010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses 94110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for demand accesses 94210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses 94310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.122087 # mshr miss rate for demand accesses 94410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for overall accesses 94510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses 94610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.122087 # mshr miss rate for overall accesses 94710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61039.816459 # average ReadReq mshr miss latency 94810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63914.834659 # average ReadReq mshr miss latency 94910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.600717 # average ReadReq mshr miss latency 9509978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 9519978Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 95210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60067.285490 # average ReadExReq mshr miss latency 95310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60067.285490 # average ReadExReq mshr miss latency 95410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency 95510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency 95610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency 95710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency 95810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency 95910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency 9607860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 96110220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1192591 # number of replacements 96210220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 4057.481628 # Cycle average of tags in use 96310220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 190175522 # Total number of references to valid blocks. 96410220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1196687 # Sample count of references to valid blocks. 96510220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 158.918349 # Average number of references to valid blocks. 96610220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 4252802250 # Cycle when the warmup percentage was hit. 96710220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4057.481628 # Average occupied blocks per requestor 96810220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.990596 # Average percentage of cache occupancy 96910220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.990596 # Average percentage of cache occupancy 97010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 97110220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 97210220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 97310220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id 97410220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1688 # Occupied blocks per task id 97510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 97610220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 391451119 # Number of tag accesses 97710220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 391451119 # Number of data accesses 97810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 136209146 # number of ReadReq hits 97910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 136209146 # number of ReadReq hits 98010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 50988846 # number of WriteReq hits 98110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 50988846 # number of WriteReq hits 98210220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488796 # number of LoadLockedReq hits 98310220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488796 # number of LoadLockedReq hits 9849459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 9859459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 98610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 187197992 # number of demand (read+write) hits 98710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 187197992 # number of demand (read+write) hits 98810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 187197992 # number of overall hits 98910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 187197992 # number of overall hits 99010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1701390 # number of ReadReq misses 99110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1701390 # number of ReadReq misses 99210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 3250460 # number of WriteReq misses 99310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 3250460 # number of WriteReq misses 99410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses 99510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses 99610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 4951850 # number of demand (read+write) misses 99710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 4951850 # number of demand (read+write) misses 99810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 4951850 # number of overall misses 99910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 4951850 # number of overall misses 100010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 29115477457 # number of ReadReq miss cycles 100110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 29115477457 # number of ReadReq miss cycles 100210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 71211038449 # number of WriteReq miss cycles 100310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 71211038449 # number of WriteReq miss cycles 100410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles 100510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles 100610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 100326515906 # number of demand (read+write) miss cycles 100710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 100326515906 # number of demand (read+write) miss cycles 100810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 100326515906 # number of overall miss cycles 100910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 100326515906 # number of overall miss cycles 101010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 137910536 # number of ReadReq accesses(hits+misses) 101110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 137910536 # number of ReadReq accesses(hits+misses) 10129449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 10139449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 101410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488833 # number of LoadLockedReq accesses(hits+misses) 101510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488833 # number of LoadLockedReq accesses(hits+misses) 10169459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 10179459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 101810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 192149842 # number of demand (read+write) accesses 101910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 192149842 # number of demand (read+write) accesses 102010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 192149842 # number of overall (read+write) accesses 102110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 192149842 # number of overall (read+write) accesses 102210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012337 # miss rate for ReadReq accesses 102310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012337 # miss rate for ReadReq accesses 102410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059928 # miss rate for WriteReq accesses 102510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.059928 # miss rate for WriteReq accesses 102610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses 102710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses 102810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.025771 # miss rate for demand accesses 102910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.025771 # miss rate for demand accesses 103010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.025771 # miss rate for overall accesses 103110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.025771 # miss rate for overall accesses 103210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248 # average ReadReq miss latency 103310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248 # average ReadReq miss latency 103410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931 # average WriteReq miss latency 103510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931 # average WriteReq miss latency 103610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency 103710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency 103810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency 103910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 20260.410939 # average overall miss latency 104010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency 104110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 20260.410939 # average overall miss latency 104210220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 17276 # number of cycles access was blocked 104310220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 49920 # number of cycles access was blocked 104410220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1691 # number of cycles access was blocked 104510220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 664 # number of cycles access was blocked 104610220Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 10.216440 # average number of cycles each access was blocked 104710220Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 75.180723 # average number of cycles each access was blocked 10489449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 10499449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 105010220Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1110914 # number of writebacks 105110220Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1110914 # number of writebacks 105210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 853047 # number of ReadReq MSHR hits 105310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 853047 # number of ReadReq MSHR hits 105410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902052 # number of WriteReq MSHR hits 105510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 2902052 # number of WriteReq MSHR hits 105610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits 105710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits 105810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 3755099 # number of demand (read+write) MSHR hits 105910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 3755099 # number of demand (read+write) MSHR hits 106010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 3755099 # number of overall MSHR hits 106110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 3755099 # number of overall MSHR hits 106210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 848343 # number of ReadReq MSHR misses 106310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 848343 # number of ReadReq MSHR misses 106410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 348408 # number of WriteReq MSHR misses 106510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 348408 # number of WriteReq MSHR misses 106610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1196751 # number of demand (read+write) MSHR misses 106710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1196751 # number of demand (read+write) MSHR misses 106810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1196751 # number of overall MSHR misses 106910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1196751 # number of overall MSHR misses 107010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12254549779 # number of ReadReq MSHR miss cycles 107110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12254549779 # number of ReadReq MSHR miss cycles 107210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10243730741 # number of WriteReq MSHR miss cycles 107310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 10243730741 # number of WriteReq MSHR miss cycles 107410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 22498280520 # number of demand (read+write) MSHR miss cycles 107510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 22498280520 # number of demand (read+write) MSHR miss cycles 107610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 22498280520 # number of overall MSHR miss cycles 107710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 22498280520 # number of overall MSHR miss cycles 107810038SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses 107910038SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses 108010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses 108110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 10829988Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses 10839988Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses 10849988Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses 10859988Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses 108610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180 # average ReadReq mshr miss latency 108710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180 # average ReadReq mshr miss latency 108810220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109 # average WriteReq mshr miss latency 108910220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109 # average WriteReq mshr miss latency 109010220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency 109110220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency 109210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency 109310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency 10949449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10957860SN/A 10967860SN/A---------- End Simulation Statistics ---------- 1097