config.ini revision 9449:56610ab73040
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81isa=system.cpu.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119switched_out=false 120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 134clock=500 135forward_snoops=true 136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null 142response_latency=2 143size=262144 144system=system 145tgts_per_mshr=20 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.dcache_port 149mem_side=system.cpu.toL2Bus.slave[1] 150 151[system.cpu.dtb] 152type=ArmTLB 153children=walker 154size=64 155walker=system.cpu.dtb.walker 156 157[system.cpu.dtb.walker] 158type=ArmTableWalker 159clock=500 160num_squash_per_cycle=2 161sys=system 162port=system.cpu.toL2Bus.slave[3] 163 164[system.cpu.fuPool] 165type=FUPool 166children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 167FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 168 169[system.cpu.fuPool.FUList0] 170type=FUDesc 171children=opList 172count=6 173opList=system.cpu.fuPool.FUList0.opList 174 175[system.cpu.fuPool.FUList0.opList] 176type=OpDesc 177issueLat=1 178opClass=IntAlu 179opLat=1 180 181[system.cpu.fuPool.FUList1] 182type=FUDesc 183children=opList0 opList1 184count=2 185opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 186 187[system.cpu.fuPool.FUList1.opList0] 188type=OpDesc 189issueLat=1 190opClass=IntMult 191opLat=3 192 193[system.cpu.fuPool.FUList1.opList1] 194type=OpDesc 195issueLat=19 196opClass=IntDiv 197opLat=20 198 199[system.cpu.fuPool.FUList2] 200type=FUDesc 201children=opList0 opList1 opList2 202count=4 203opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 204 205[system.cpu.fuPool.FUList2.opList0] 206type=OpDesc 207issueLat=1 208opClass=FloatAdd 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList1] 212type=OpDesc 213issueLat=1 214opClass=FloatCmp 215opLat=2 216 217[system.cpu.fuPool.FUList2.opList2] 218type=OpDesc 219issueLat=1 220opClass=FloatCvt 221opLat=2 222 223[system.cpu.fuPool.FUList3] 224type=FUDesc 225children=opList0 opList1 opList2 226count=2 227opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 228 229[system.cpu.fuPool.FUList3.opList0] 230type=OpDesc 231issueLat=1 232opClass=FloatMult 233opLat=4 234 235[system.cpu.fuPool.FUList3.opList1] 236type=OpDesc 237issueLat=12 238opClass=FloatDiv 239opLat=12 240 241[system.cpu.fuPool.FUList3.opList2] 242type=OpDesc 243issueLat=24 244opClass=FloatSqrt 245opLat=24 246 247[system.cpu.fuPool.FUList4] 248type=FUDesc 249children=opList 250count=0 251opList=system.cpu.fuPool.FUList4.opList 252 253[system.cpu.fuPool.FUList4.opList] 254type=OpDesc 255issueLat=1 256opClass=MemRead 257opLat=1 258 259[system.cpu.fuPool.FUList5] 260type=FUDesc 261children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 262count=4 263opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 264 265[system.cpu.fuPool.FUList5.opList00] 266type=OpDesc 267issueLat=1 268opClass=SimdAdd 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList01] 272type=OpDesc 273issueLat=1 274opClass=SimdAddAcc 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList02] 278type=OpDesc 279issueLat=1 280opClass=SimdAlu 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList03] 284type=OpDesc 285issueLat=1 286opClass=SimdCmp 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList04] 290type=OpDesc 291issueLat=1 292opClass=SimdCvt 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList05] 296type=OpDesc 297issueLat=1 298opClass=SimdMisc 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList06] 302type=OpDesc 303issueLat=1 304opClass=SimdMult 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList07] 308type=OpDesc 309issueLat=1 310opClass=SimdMultAcc 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList08] 314type=OpDesc 315issueLat=1 316opClass=SimdShift 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList09] 320type=OpDesc 321issueLat=1 322opClass=SimdShiftAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList10] 326type=OpDesc 327issueLat=1 328opClass=SimdSqrt 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList11] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAdd 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList12] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatAlu 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList13] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList14] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatCvt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList15] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatDiv 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList16] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMisc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList17] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMult 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList18] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMultAcc 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList19] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatSqrt 383opLat=1 384 385[system.cpu.fuPool.FUList6] 386type=FUDesc 387children=opList 388count=0 389opList=system.cpu.fuPool.FUList6.opList 390 391[system.cpu.fuPool.FUList6.opList] 392type=OpDesc 393issueLat=1 394opClass=MemWrite 395opLat=1 396 397[system.cpu.fuPool.FUList7] 398type=FUDesc 399children=opList0 opList1 400count=4 401opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 402 403[system.cpu.fuPool.FUList7.opList0] 404type=OpDesc 405issueLat=1 406opClass=MemRead 407opLat=1 408 409[system.cpu.fuPool.FUList7.opList1] 410type=OpDesc 411issueLat=1 412opClass=MemWrite 413opLat=1 414 415[system.cpu.fuPool.FUList8] 416type=FUDesc 417children=opList 418count=1 419opList=system.cpu.fuPool.FUList8.opList 420 421[system.cpu.fuPool.FUList8.opList] 422type=OpDesc 423issueLat=3 424opClass=IprAccess 425opLat=3 426 427[system.cpu.icache] 428type=BaseCache 429addr_ranges=0:18446744073709551615 430assoc=2 431block_size=64 432clock=500 433forward_snoops=true 434hit_latency=2 435is_top_level=true 436max_miss_count=0 437mshrs=4 438prefetch_on_access=false 439prefetcher=Null 440response_latency=2 441size=131072 442system=system 443tgts_per_mshr=20 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.slave[0] 448 449[system.cpu.interrupts] 450type=ArmInterrupts 451 452[system.cpu.isa] 453type=ArmISA 454fpsid=1090793632 455id_isar0=34607377 456id_isar1=34677009 457id_isar2=555950401 458id_isar3=17899825 459id_isar4=268501314 460id_isar5=0 461id_mmfr0=3 462id_mmfr1=0 463id_mmfr2=19070976 464id_mmfr3=4027589137 465id_pfr0=49 466id_pfr1=1 467midr=890224640 468 469[system.cpu.itb] 470type=ArmTLB 471children=walker 472size=64 473walker=system.cpu.itb.walker 474 475[system.cpu.itb.walker] 476type=ArmTableWalker 477clock=500 478num_squash_per_cycle=2 479sys=system 480port=system.cpu.toL2Bus.slave[2] 481 482[system.cpu.l2cache] 483type=BaseCache 484addr_ranges=0:18446744073709551615 485assoc=8 486block_size=64 487clock=500 488forward_snoops=true 489hit_latency=20 490is_top_level=false 491max_miss_count=0 492mshrs=20 493prefetch_on_access=false 494prefetcher=Null 495response_latency=20 496size=2097152 497system=system 498tgts_per_mshr=12 499two_queue=false 500write_buffers=8 501cpu_side=system.cpu.toL2Bus.master[0] 502mem_side=system.membus.slave[1] 503 504[system.cpu.toL2Bus] 505type=CoherentBus 506block_size=64 507clock=500 508header_cycles=1 509use_default_range=false 510width=32 511master=system.cpu.l2cache.cpu_side 512slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 513 514[system.cpu.tracer] 515type=ExeTracer 516 517[system.cpu.workload] 518type=LiveProcess 519cmd=parser 2.1.dict -batch 520cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 521egid=100 522env= 523errout=cerr 524euid=100 525executable=/gem5/dist/cpu2000/binaries/arm/linux/parser 526gid=100 527input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in 528max_stack_size=67108864 529output=cout 530pid=100 531ppid=99 532simpoint=114600000000 533system=system 534uid=100 535 536[system.membus] 537type=CoherentBus 538block_size=64 539clock=1000 540header_cycles=1 541use_default_range=false 542width=8 543master=system.physmem.port 544slave=system.system_port system.cpu.l2cache.mem_side 545 546[system.physmem] 547type=SimpleDRAM 548addr_mapping=openmap 549banks_per_rank=8 550clock=1000 551conf_table_reported=false 552in_addr_map=true 553lines_per_rowbuffer=64 554mem_sched_policy=fcfs 555null=false 556page_policy=open 557range=0:134217727 558ranks_per_channel=2 559read_buffer_size=32 560tBURST=4000 561tCL=14000 562tRCD=14000 563tREFI=7800000 564tRFC=300000 565tRP=14000 566tWTR=1000 567write_buffer_size=32 568write_thresh_perc=70 569zero=false 570port=system.membus.master[0] 571 572