config.ini revision 10451
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=16 51LSQCheckLoads=true 52LSQDepCheckShift=0 53SQEntries=16 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=2 69decodeWidth=3 70dispatchWidth=6 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=16 78fetchQueueSize=32 79fetchToDecodeDelay=3 80fetchTrapLatency=1 81fetchWidth=3 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94istage2_mmu=system.cpu.istage2_mmu 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=32 102numPhysCCRegs=640 103numPhysFloatRegs=192 104numPhysIntRegs=128 105numROBEntries=40 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=1 113renameToROBDelay=1 114renameWidth=3 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=2048 140BTBTagSize=18 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=bi-mode 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=6 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=32768 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=8 174two_queue=false 175write_buffers=16 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=32768 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 194tlb=system.cpu.dtb 195 196[system.cpu.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system 211port=system.cpu.toL2Bus.slave[5] 212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker 220 221[system.cpu.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[3] 229 230[system.cpu.fuPool] 231type=FUPool 232children=FUList0 FUList1 FUList2 FUList3 FUList4 233FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 234eventq_index=0 235 236[system.cpu.fuPool.FUList0] 237type=FUDesc 238children=opList 239count=2 240eventq_index=0 241opList=system.cpu.fuPool.FUList0.opList 242 243[system.cpu.fuPool.FUList0.opList] 244type=OpDesc 245eventq_index=0 246issueLat=1 247opClass=IntAlu 248opLat=1 249 250[system.cpu.fuPool.FUList1] 251type=FUDesc 252children=opList0 opList1 opList2 253count=1 254eventq_index=0 255opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 256 257[system.cpu.fuPool.FUList1.opList0] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=IntMult 262opLat=3 263 264[system.cpu.fuPool.FUList1.opList1] 265type=OpDesc 266eventq_index=0 267issueLat=12 268opClass=IntDiv 269opLat=12 270 271[system.cpu.fuPool.FUList1.opList2] 272type=OpDesc 273eventq_index=0 274issueLat=1 275opClass=IprAccess 276opLat=3 277 278[system.cpu.fuPool.FUList2] 279type=FUDesc 280children=opList 281count=1 282eventq_index=0 283opList=system.cpu.fuPool.FUList2.opList 284 285[system.cpu.fuPool.FUList2.opList] 286type=OpDesc 287eventq_index=0 288issueLat=1 289opClass=MemRead 290opLat=2 291 292[system.cpu.fuPool.FUList3] 293type=FUDesc 294children=opList 295count=1 296eventq_index=0 297opList=system.cpu.fuPool.FUList3.opList 298 299[system.cpu.fuPool.FUList3.opList] 300type=OpDesc 301eventq_index=0 302issueLat=1 303opClass=MemWrite 304opLat=2 305 306[system.cpu.fuPool.FUList4] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 309count=2 310eventq_index=0 311opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 312 313[system.cpu.fuPool.FUList4.opList00] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=SimdAdd 318opLat=4 319 320[system.cpu.fuPool.FUList4.opList01] 321type=OpDesc 322eventq_index=0 323issueLat=1 324opClass=SimdAddAcc 325opLat=4 326 327[system.cpu.fuPool.FUList4.opList02] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdAlu 332opLat=4 333 334[system.cpu.fuPool.FUList4.opList03] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdCmp 339opLat=4 340 341[system.cpu.fuPool.FUList4.opList04] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdCvt 346opLat=3 347 348[system.cpu.fuPool.FUList4.opList05] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdMisc 353opLat=3 354 355[system.cpu.fuPool.FUList4.opList06] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdMult 360opLat=5 361 362[system.cpu.fuPool.FUList4.opList07] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdMultAcc 367opLat=5 368 369[system.cpu.fuPool.FUList4.opList08] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdShift 374opLat=3 375 376[system.cpu.fuPool.FUList4.opList09] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdShiftAcc 381opLat=3 382 383[system.cpu.fuPool.FUList4.opList10] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdSqrt 388opLat=9 389 390[system.cpu.fuPool.FUList4.opList11] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdFloatAdd 395opLat=5 396 397[system.cpu.fuPool.FUList4.opList12] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdFloatAlu 402opLat=5 403 404[system.cpu.fuPool.FUList4.opList13] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatCmp 409opLat=3 410 411[system.cpu.fuPool.FUList4.opList14] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatCvt 416opLat=3 417 418[system.cpu.fuPool.FUList4.opList15] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatDiv 423opLat=3 424 425[system.cpu.fuPool.FUList4.opList16] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatMisc 430opLat=3 431 432[system.cpu.fuPool.FUList4.opList17] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatMult 437opLat=3 438 439[system.cpu.fuPool.FUList4.opList18] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatMultAcc 444opLat=1 445 446[system.cpu.fuPool.FUList4.opList19] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatSqrt 451opLat=9 452 453[system.cpu.fuPool.FUList4.opList20] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=FloatAdd 458opLat=5 459 460[system.cpu.fuPool.FUList4.opList21] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=FloatCmp 465opLat=5 466 467[system.cpu.fuPool.FUList4.opList22] 468type=OpDesc 469eventq_index=0 470issueLat=1 471opClass=FloatCvt 472opLat=5 473 474[system.cpu.fuPool.FUList4.opList23] 475type=OpDesc 476eventq_index=0 477issueLat=9 478opClass=FloatDiv 479opLat=9 480 481[system.cpu.fuPool.FUList4.opList24] 482type=OpDesc 483eventq_index=0 484issueLat=33 485opClass=FloatSqrt 486opLat=33 487 488[system.cpu.fuPool.FUList4.opList25] 489type=OpDesc 490eventq_index=0 491issueLat=1 492opClass=FloatMult 493opLat=4 494 495[system.cpu.icache] 496type=BaseCache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain 501eventq_index=0 502forward_snoops=true 503hit_latency=1 504is_top_level=true 505max_miss_count=0 506mshrs=2 507prefetch_on_access=false 508prefetcher=Null 509response_latency=1 510sequential_access=false 511size=32768 512system=system 513tags=system.cpu.icache.tags 514tgts_per_mshr=8 515two_queue=false 516write_buffers=8 517cpu_side=system.cpu.icache_port 518mem_side=system.cpu.toL2Bus.slave[0] 519 520[system.cpu.icache.tags] 521type=LRU 522assoc=2 523block_size=64 524clk_domain=system.cpu_clk_domain 525eventq_index=0 526hit_latency=1 527sequential_access=false 528size=32768 529 530[system.cpu.interrupts] 531type=ArmInterrupts 532eventq_index=0 533 534[system.cpu.isa] 535type=ArmISA 536eventq_index=0 537fpsid=1090793632 538id_aa64afr0_el1=0 539id_aa64afr1_el1=0 540id_aa64dfr0_el1=1052678 541id_aa64dfr1_el1=0 542id_aa64isar0_el1=0 543id_aa64isar1_el1=0 544id_aa64mmfr0_el1=15728642 545id_aa64mmfr1_el1=0 546id_aa64pfr0_el1=17 547id_aa64pfr1_el1=0 548id_isar0=34607377 549id_isar1=34677009 550id_isar2=555950401 551id_isar3=17899825 552id_isar4=268501314 553id_isar5=0 554id_mmfr0=270536963 555id_mmfr1=0 556id_mmfr2=19070976 557id_mmfr3=34611729 558id_pfr0=49 559id_pfr1=4113 560midr=1091551472 561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 568tlb=system.cpu.itb 569 570[system.cpu.istage2_mmu.stage2_tlb] 571type=ArmTLB 572children=walker 573eventq_index=0 574is_stage2=true 575size=32 576walker=system.cpu.istage2_mmu.stage2_tlb.walker 577 578[system.cpu.istage2_mmu.stage2_tlb.walker] 579type=ArmTableWalker 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582is_stage2=true 583num_squash_per_cycle=2 584sys=system 585port=system.cpu.toL2Bus.slave[4] 586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker 594 595[system.cpu.itb.walker] 596type=ArmTableWalker 597clk_domain=system.cpu_clk_domain 598eventq_index=0 599is_stage2=false 600num_squash_per_cycle=2 601sys=system 602port=system.cpu.toL2Bus.slave[2] 603 604[system.cpu.l2cache] 605type=BaseCache 606children=prefetcher tags 607addr_ranges=0:18446744073709551615 608assoc=16 609clk_domain=system.cpu_clk_domain 610eventq_index=0 611forward_snoops=true 612hit_latency=12 613is_top_level=false 614max_miss_count=0 615mshrs=16 616prefetch_on_access=true 617prefetcher=system.cpu.l2cache.prefetcher 618response_latency=12 619sequential_access=false 620size=1048576 621system=system 622tags=system.cpu.l2cache.tags 623tgts_per_mshr=8 624two_queue=false 625write_buffers=8 626cpu_side=system.cpu.toL2Bus.master[0] 627mem_side=system.membus.slave[1] 628 629[system.cpu.l2cache.prefetcher] 630type=StridePrefetcher 631clk_domain=system.cpu_clk_domain 632cross_pages=false 633data_accesses_only=false 634degree=8 635eventq_index=0 636inst_tagged=true 637latency=1 638on_miss_only=false 639on_prefetch=true 640on_read_only=false 641serial_squash=false 642size=100 643sys=system 644use_master_id=true 645 646[system.cpu.l2cache.tags] 647type=RandomRepl 648assoc=16 649block_size=64 650clk_domain=system.cpu_clk_domain 651eventq_index=0 652hit_latency=12 653sequential_access=false 654size=1048576 655 656[system.cpu.toL2Bus] 657type=CoherentXBar 658clk_domain=system.cpu_clk_domain 659eventq_index=0 660header_cycles=1 661snoop_filter=Null 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 667 668[system.cpu.tracer] 669type=ExeTracer 670eventq_index=0 671 672[system.cpu.workload] 673type=LiveProcess 674cmd=parser 2.1.dict -batch 675cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 676egid=100 677env= 678errout=cerr 679euid=100 680eventq_index=0 681executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser 682gid=100 683input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=114600000000 689system=system 690uid=100 691useArchPT=false 692 693[system.cpu_clk_domain] 694type=SrcClockDomain 695clock=500 696domain_id=-1 697eventq_index=0 698init_perf_level=0 699voltage_domain=system.voltage_domain 700 701[system.dvfs_handler] 702type=DVFSHandler 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar 711clk_domain=system.clk_domain 712eventq_index=0 713header_cycles=1 714snoop_filter=Null 715system=system 716use_default_range=false 717width=8 718master=system.physmem.port 719slave=system.system_port system.cpu.l2cache.mem_side 720 721[system.physmem] 722type=DRAMCtrl 723IDD0=0.075000 724IDD02=0.000000 725IDD2N=0.050000 726IDD2N2=0.000000 727IDD2P0=0.000000 728IDD2P02=0.000000 729IDD2P1=0.000000 730IDD2P12=0.000000 731IDD3N=0.057000 732IDD3N2=0.000000 733IDD3P0=0.000000 734IDD3P02=0.000000 735IDD3P1=0.000000 736IDD3P12=0.000000 737IDD4R=0.187000 738IDD4R2=0.000000 739IDD4W=0.165000 740IDD4W2=0.000000 741IDD5=0.220000 742IDD52=0.000000 743IDD6=0.000000 744IDD62=0.000000 745VDD=1.500000 746VDD2=0.000000 747activation_limit=4 748addr_mapping=RoRaBaChCo 749bank_groups_per_rank=0 750banks_per_rank=8 751burst_length=8 752channels=1 753clk_domain=system.clk_domain 754conf_table_reported=true 755device_bus_width=8 756device_rowbuffer_size=1024 757devices_per_rank=8 758dll=true 759eventq_index=0 760in_addr_map=true 761max_accesses_per_row=16 762mem_sched_policy=frfcfs 763min_writes_per_switch=16 764null=false 765page_policy=open_adaptive 766range=0:134217727 767ranks_per_channel=2 768read_buffer_size=32 769static_backend_latency=10000 770static_frontend_latency=10000 771tBURST=5000 772tCCD_L=0 773tCK=1250 774tCL=13750 775tCS=2500 776tRAS=35000 777tRCD=13750 778tREFI=7800000 779tRFC=260000 780tRP=13750 781tRRD=6000 782tRRD_L=0 783tRTP=7500 784tRTW=2500 785tWR=15000 786tWTR=7500 787tXAW=30000 788tXP=0 789tXPDLL=0 790tXS=0 791tXSDLL=0 792write_buffer_size=64 793write_high_thresh_perc=85 794write_low_thresh_perc=50 795port=system.membus.master[0] 796 797[system.voltage_domain] 798type=VoltageDomain 799eventq_index=0 800voltage=1.000000 801 802