config.ini revision 10315
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91issueToExecuteDelay=1 92issueWidth=8 93istage2_mmu=system.cpu.istage2_mmu 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbDepth=1 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=tournament 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=262144 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=20 174two_queue=false 175write_buffers=8 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=262144 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 194tlb=system.cpu.dtb 195 196[system.cpu.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system 211port=system.cpu.toL2Bus.slave[5] 212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker 220 221[system.cpu.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[3] 229 230[system.cpu.fuPool] 231type=FUPool 232children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 233FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 234eventq_index=0 235 236[system.cpu.fuPool.FUList0] 237type=FUDesc 238children=opList 239count=6 240eventq_index=0 241opList=system.cpu.fuPool.FUList0.opList 242 243[system.cpu.fuPool.FUList0.opList] 244type=OpDesc 245eventq_index=0 246issueLat=1 247opClass=IntAlu 248opLat=1 249 250[system.cpu.fuPool.FUList1] 251type=FUDesc 252children=opList0 opList1 253count=2 254eventq_index=0 255opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 256 257[system.cpu.fuPool.FUList1.opList0] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=IntMult 262opLat=3 263 264[system.cpu.fuPool.FUList1.opList1] 265type=OpDesc 266eventq_index=0 267issueLat=19 268opClass=IntDiv 269opLat=20 270 271[system.cpu.fuPool.FUList2] 272type=FUDesc 273children=opList0 opList1 opList2 274count=4 275eventq_index=0 276opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 277 278[system.cpu.fuPool.FUList2.opList0] 279type=OpDesc 280eventq_index=0 281issueLat=1 282opClass=FloatAdd 283opLat=2 284 285[system.cpu.fuPool.FUList2.opList1] 286type=OpDesc 287eventq_index=0 288issueLat=1 289opClass=FloatCmp 290opLat=2 291 292[system.cpu.fuPool.FUList2.opList2] 293type=OpDesc 294eventq_index=0 295issueLat=1 296opClass=FloatCvt 297opLat=2 298 299[system.cpu.fuPool.FUList3] 300type=FUDesc 301children=opList0 opList1 opList2 302count=2 303eventq_index=0 304opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 305 306[system.cpu.fuPool.FUList3.opList0] 307type=OpDesc 308eventq_index=0 309issueLat=1 310opClass=FloatMult 311opLat=4 312 313[system.cpu.fuPool.FUList3.opList1] 314type=OpDesc 315eventq_index=0 316issueLat=12 317opClass=FloatDiv 318opLat=12 319 320[system.cpu.fuPool.FUList3.opList2] 321type=OpDesc 322eventq_index=0 323issueLat=24 324opClass=FloatSqrt 325opLat=24 326 327[system.cpu.fuPool.FUList4] 328type=FUDesc 329children=opList 330count=0 331eventq_index=0 332opList=system.cpu.fuPool.FUList4.opList 333 334[system.cpu.fuPool.FUList4.opList] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=MemRead 339opLat=1 340 341[system.cpu.fuPool.FUList5] 342type=FUDesc 343children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 344count=4 345eventq_index=0 346opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 347 348[system.cpu.fuPool.FUList5.opList00] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdAdd 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList01] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdAddAcc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList02] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdAlu 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList03] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdCmp 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList04] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdCvt 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList05] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdMisc 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList06] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdMult 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList07] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdMultAcc 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList08] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdShift 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList09] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdShiftAcc 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList10] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdSqrt 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList11] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatAdd 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList12] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatAlu 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList13] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatCmp 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList14] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatCvt 451opLat=1 452 453[system.cpu.fuPool.FUList5.opList15] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=SimdFloatDiv 458opLat=1 459 460[system.cpu.fuPool.FUList5.opList16] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=SimdFloatMisc 465opLat=1 466 467[system.cpu.fuPool.FUList5.opList17] 468type=OpDesc 469eventq_index=0 470issueLat=1 471opClass=SimdFloatMult 472opLat=1 473 474[system.cpu.fuPool.FUList5.opList18] 475type=OpDesc 476eventq_index=0 477issueLat=1 478opClass=SimdFloatMultAcc 479opLat=1 480 481[system.cpu.fuPool.FUList5.opList19] 482type=OpDesc 483eventq_index=0 484issueLat=1 485opClass=SimdFloatSqrt 486opLat=1 487 488[system.cpu.fuPool.FUList6] 489type=FUDesc 490children=opList 491count=0 492eventq_index=0 493opList=system.cpu.fuPool.FUList6.opList 494 495[system.cpu.fuPool.FUList6.opList] 496type=OpDesc 497eventq_index=0 498issueLat=1 499opClass=MemWrite 500opLat=1 501 502[system.cpu.fuPool.FUList7] 503type=FUDesc 504children=opList0 opList1 505count=4 506eventq_index=0 507opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 508 509[system.cpu.fuPool.FUList7.opList0] 510type=OpDesc 511eventq_index=0 512issueLat=1 513opClass=MemRead 514opLat=1 515 516[system.cpu.fuPool.FUList7.opList1] 517type=OpDesc 518eventq_index=0 519issueLat=1 520opClass=MemWrite 521opLat=1 522 523[system.cpu.fuPool.FUList8] 524type=FUDesc 525children=opList 526count=1 527eventq_index=0 528opList=system.cpu.fuPool.FUList8.opList 529 530[system.cpu.fuPool.FUList8.opList] 531type=OpDesc 532eventq_index=0 533issueLat=3 534opClass=IprAccess 535opLat=3 536 537[system.cpu.icache] 538type=BaseCache 539children=tags 540addr_ranges=0:18446744073709551615 541assoc=2 542clk_domain=system.cpu_clk_domain 543eventq_index=0 544forward_snoops=true 545hit_latency=2 546is_top_level=true 547max_miss_count=0 548mshrs=4 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557two_queue=false 558write_buffers=8 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain 567eventq_index=0 568hit_latency=2 569sequential_access=false 570size=131072 571 572[system.cpu.interrupts] 573type=ArmInterrupts 574eventq_index=0 575 576[system.cpu.isa] 577type=ArmISA 578eventq_index=0 579fpsid=1090793632 580id_aa64afr0_el1=0 581id_aa64afr1_el1=0 582id_aa64dfr0_el1=1052678 583id_aa64dfr1_el1=0 584id_aa64isar0_el1=0 585id_aa64isar1_el1=0 586id_aa64mmfr0_el1=15728642 587id_aa64mmfr1_el1=0 588id_aa64pfr0_el1=17 589id_aa64pfr1_el1=0 590id_isar0=34607377 591id_isar1=34677009 592id_isar2=555950401 593id_isar3=17899825 594id_isar4=268501314 595id_isar5=0 596id_mmfr0=270536963 597id_mmfr1=0 598id_mmfr2=19070976 599id_mmfr3=34611729 600id_pfr0=49 601id_pfr1=4113 602midr=1091551472 603system=system 604 605[system.cpu.istage2_mmu] 606type=ArmStage2MMU 607children=stage2_tlb 608eventq_index=0 609stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 610tlb=system.cpu.itb 611 612[system.cpu.istage2_mmu.stage2_tlb] 613type=ArmTLB 614children=walker 615eventq_index=0 616is_stage2=true 617size=32 618walker=system.cpu.istage2_mmu.stage2_tlb.walker 619 620[system.cpu.istage2_mmu.stage2_tlb.walker] 621type=ArmTableWalker 622clk_domain=system.cpu_clk_domain 623eventq_index=0 624is_stage2=true 625num_squash_per_cycle=2 626sys=system 627port=system.cpu.toL2Bus.slave[4] 628 629[system.cpu.itb] 630type=ArmTLB 631children=walker 632eventq_index=0 633is_stage2=false 634size=64 635walker=system.cpu.itb.walker 636 637[system.cpu.itb.walker] 638type=ArmTableWalker 639clk_domain=system.cpu_clk_domain 640eventq_index=0 641is_stage2=false 642num_squash_per_cycle=2 643sys=system 644port=system.cpu.toL2Bus.slave[2] 645 646[system.cpu.l2cache] 647type=BaseCache 648children=tags 649addr_ranges=0:18446744073709551615 650assoc=8 651clk_domain=system.cpu_clk_domain 652eventq_index=0 653forward_snoops=true 654hit_latency=20 655is_top_level=false 656max_miss_count=0 657mshrs=20 658prefetch_on_access=false 659prefetcher=Null 660response_latency=20 661sequential_access=false 662size=2097152 663system=system 664tags=system.cpu.l2cache.tags 665tgts_per_mshr=12 666two_queue=false 667write_buffers=8 668cpu_side=system.cpu.toL2Bus.master[0] 669mem_side=system.membus.slave[1] 670 671[system.cpu.l2cache.tags] 672type=LRU 673assoc=8 674block_size=64 675clk_domain=system.cpu_clk_domain 676eventq_index=0 677hit_latency=20 678sequential_access=false 679size=2097152 680 681[system.cpu.toL2Bus] 682type=CoherentBus 683clk_domain=system.cpu_clk_domain 684eventq_index=0 685header_cycles=1 686system=system 687use_default_range=false 688width=32 689master=system.cpu.l2cache.cpu_side 690slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 691 692[system.cpu.tracer] 693type=ExeTracer 694eventq_index=0 695 696[system.cpu.workload] 697type=LiveProcess 698cmd=parser 2.1.dict -batch 699cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 700egid=100 701env= 702errout=cerr 703euid=100 704eventq_index=0 705executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser 706gid=100 707input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 708max_stack_size=67108864 709output=cout 710pid=100 711ppid=99 712simpoint=114600000000 713system=system 714uid=100 715 716[system.cpu_clk_domain] 717type=SrcClockDomain 718clock=500 719domain_id=-1 720eventq_index=0 721init_perf_level=0 722voltage_domain=system.voltage_domain 723 724[system.dvfs_handler] 725type=DVFSHandler 726domains= 727enable=false 728eventq_index=0 729sys_clk_domain=system.clk_domain 730transition_latency=100000000 731 732[system.membus] 733type=CoherentBus 734clk_domain=system.clk_domain 735eventq_index=0 736header_cycles=1 737system=system 738use_default_range=false 739width=8 740master=system.physmem.port 741slave=system.system_port system.cpu.l2cache.mem_side 742 743[system.physmem] 744type=DRAMCtrl 745activation_limit=4 746addr_mapping=RoRaBaChCo 747banks_per_rank=8 748burst_length=8 749channels=1 750clk_domain=system.clk_domain 751conf_table_reported=true 752device_bus_width=8 753device_rowbuffer_size=1024 754devices_per_rank=8 755eventq_index=0 756in_addr_map=true 757max_accesses_per_row=16 758mem_sched_policy=frfcfs 759min_writes_per_switch=16 760null=false 761page_policy=open_adaptive 762range=0:134217727 763ranks_per_channel=2 764read_buffer_size=32 765static_backend_latency=10000 766static_frontend_latency=10000 767tBURST=5000 768tCK=1250 769tCL=13750 770tRAS=35000 771tRCD=13750 772tREFI=7800000 773tRFC=260000 774tRP=13750 775tRRD=6000 776tRTP=7500 777tRTW=2500 778tWR=15000 779tWTR=7500 780tXAW=30000 781write_buffer_size=64 782write_high_thresh_perc=85 783write_low_thresh_perc=50 784port=system.membus.master[0] 785 786[system.voltage_domain] 787type=VoltageDomain 788eventq_index=0 789voltage=1.000000 790 791