config.ini revision 10038
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90istage2_mmu=system.cpu.istage2_mmu 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysCCRegs=0 99numPhysFloatRegs=256 100numPhysIntRegs=256 101numROBEntries=192 102numRobs=1 103numThreads=1 104profile=0 105progress_interval=0 106renameToDecodeDelay=1 107renameToFetchDelay=1 108renameToIEWDelay=2 109renameToROBDelay=1 110renameWidth=8 111simpoint_start_insts= 112smtCommitPolicy=RoundRobin 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100 121squashWidth=8 122store_set_clear_period=250000 123switched_out=false 124system=system 125tracer=system.cpu.tracer 126trapLatency=13 127wbDepth=1 128wbWidth=8 129workload=system.cpu.workload 130dcache_port=system.cpu.dcache.cpu_side 131icache_port=system.cpu.icache.cpu_side 132 133[system.cpu.branchPred] 134type=BranchPredictor 135BTBEntries=4096 136BTBTagSize=16 137RASSize=16 138choiceCtrBits=2 139choicePredictorSize=8192 140eventq_index=0 141globalCtrBits=2 142globalPredictorSize=8192 143instShiftAmt=2 144localCtrBits=2 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu.dcache] 151type=BaseCache 152children=tags 153addr_ranges=0:18446744073709551615 154assoc=2 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157forward_snoops=true 158hit_latency=2 159is_top_level=true 160max_miss_count=0 161mshrs=4 162prefetch_on_access=false 163prefetcher=Null 164response_latency=2 165sequential_access=false 166size=262144 167system=system 168tags=system.cpu.dcache.tags 169tgts_per_mshr=20 170two_queue=false 171write_buffers=8 172cpu_side=system.cpu.dcache_port 173mem_side=system.cpu.toL2Bus.slave[1] 174 175[system.cpu.dcache.tags] 176type=LRU 177assoc=2 178block_size=64 179clk_domain=system.cpu_clk_domain 180eventq_index=0 181hit_latency=2 182sequential_access=false 183size=262144 184 185[system.cpu.dstage2_mmu] 186type=ArmStage2MMU 187children=stage2_tlb 188eventq_index=0 189stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 190tlb=system.cpu.dtb 191 192[system.cpu.dstage2_mmu.stage2_tlb] 193type=ArmTLB 194children=walker 195eventq_index=0 196is_stage2=true 197size=32 198walker=system.cpu.dstage2_mmu.stage2_tlb.walker 199 200[system.cpu.dstage2_mmu.stage2_tlb.walker] 201type=ArmTableWalker 202clk_domain=system.cpu_clk_domain 203eventq_index=0 204is_stage2=true 205num_squash_per_cycle=2 206sys=system 207port=system.cpu.toL2Bus.slave[5] 208 209[system.cpu.dtb] 210type=ArmTLB 211children=walker 212eventq_index=0 213is_stage2=false 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker 219clk_domain=system.cpu_clk_domain 220eventq_index=0 221is_stage2=false 222num_squash_per_cycle=2 223sys=system 224port=system.cpu.toL2Bus.slave[3] 225 226[system.cpu.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 230eventq_index=0 231 232[system.cpu.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu.fuPool.FUList0.opList 238 239[system.cpu.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242issueLat=1 243opClass=IntAlu 244opLat=1 245 246[system.cpu.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 252 253[system.cpu.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256issueLat=1 257opClass=IntMult 258opLat=3 259 260[system.cpu.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263issueLat=19 264opClass=IntDiv 265opLat=20 266 267[system.cpu.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 273 274[system.cpu.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277issueLat=1 278opClass=FloatAdd 279opLat=2 280 281[system.cpu.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284issueLat=1 285opClass=FloatCmp 286opLat=2 287 288[system.cpu.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291issueLat=1 292opClass=FloatCvt 293opLat=2 294 295[system.cpu.fuPool.FUList3] 296type=FUDesc 297children=opList0 opList1 opList2 298count=2 299eventq_index=0 300opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 301 302[system.cpu.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305issueLat=1 306opClass=FloatMult 307opLat=4 308 309[system.cpu.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 312issueLat=12 313opClass=FloatDiv 314opLat=12 315 316[system.cpu.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319issueLat=24 320opClass=FloatSqrt 321opLat=24 322 323[system.cpu.fuPool.FUList4] 324type=FUDesc 325children=opList 326count=0 327eventq_index=0 328opList=system.cpu.fuPool.FUList4.opList 329 330[system.cpu.fuPool.FUList4.opList] 331type=OpDesc 332eventq_index=0 333issueLat=1 334opClass=MemRead 335opLat=1 336 337[system.cpu.fuPool.FUList5] 338type=FUDesc 339children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 340count=4 341eventq_index=0 342opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 343 344[system.cpu.fuPool.FUList5.opList00] 345type=OpDesc 346eventq_index=0 347issueLat=1 348opClass=SimdAdd 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList01] 352type=OpDesc 353eventq_index=0 354issueLat=1 355opClass=SimdAddAcc 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList02] 359type=OpDesc 360eventq_index=0 361issueLat=1 362opClass=SimdAlu 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList03] 366type=OpDesc 367eventq_index=0 368issueLat=1 369opClass=SimdCmp 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList04] 373type=OpDesc 374eventq_index=0 375issueLat=1 376opClass=SimdCvt 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList05] 380type=OpDesc 381eventq_index=0 382issueLat=1 383opClass=SimdMisc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList06] 387type=OpDesc 388eventq_index=0 389issueLat=1 390opClass=SimdMult 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList07] 394type=OpDesc 395eventq_index=0 396issueLat=1 397opClass=SimdMultAcc 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList08] 401type=OpDesc 402eventq_index=0 403issueLat=1 404opClass=SimdShift 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList09] 408type=OpDesc 409eventq_index=0 410issueLat=1 411opClass=SimdShiftAcc 412opLat=1 413 414[system.cpu.fuPool.FUList5.opList10] 415type=OpDesc 416eventq_index=0 417issueLat=1 418opClass=SimdSqrt 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList11] 422type=OpDesc 423eventq_index=0 424issueLat=1 425opClass=SimdFloatAdd 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList12] 429type=OpDesc 430eventq_index=0 431issueLat=1 432opClass=SimdFloatAlu 433opLat=1 434 435[system.cpu.fuPool.FUList5.opList13] 436type=OpDesc 437eventq_index=0 438issueLat=1 439opClass=SimdFloatCmp 440opLat=1 441 442[system.cpu.fuPool.FUList5.opList14] 443type=OpDesc 444eventq_index=0 445issueLat=1 446opClass=SimdFloatCvt 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList15] 450type=OpDesc 451eventq_index=0 452issueLat=1 453opClass=SimdFloatDiv 454opLat=1 455 456[system.cpu.fuPool.FUList5.opList16] 457type=OpDesc 458eventq_index=0 459issueLat=1 460opClass=SimdFloatMisc 461opLat=1 462 463[system.cpu.fuPool.FUList5.opList17] 464type=OpDesc 465eventq_index=0 466issueLat=1 467opClass=SimdFloatMult 468opLat=1 469 470[system.cpu.fuPool.FUList5.opList18] 471type=OpDesc 472eventq_index=0 473issueLat=1 474opClass=SimdFloatMultAcc 475opLat=1 476 477[system.cpu.fuPool.FUList5.opList19] 478type=OpDesc 479eventq_index=0 480issueLat=1 481opClass=SimdFloatSqrt 482opLat=1 483 484[system.cpu.fuPool.FUList6] 485type=FUDesc 486children=opList 487count=0 488eventq_index=0 489opList=system.cpu.fuPool.FUList6.opList 490 491[system.cpu.fuPool.FUList6.opList] 492type=OpDesc 493eventq_index=0 494issueLat=1 495opClass=MemWrite 496opLat=1 497 498[system.cpu.fuPool.FUList7] 499type=FUDesc 500children=opList0 opList1 501count=4 502eventq_index=0 503opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 504 505[system.cpu.fuPool.FUList7.opList0] 506type=OpDesc 507eventq_index=0 508issueLat=1 509opClass=MemRead 510opLat=1 511 512[system.cpu.fuPool.FUList7.opList1] 513type=OpDesc 514eventq_index=0 515issueLat=1 516opClass=MemWrite 517opLat=1 518 519[system.cpu.fuPool.FUList8] 520type=FUDesc 521children=opList 522count=1 523eventq_index=0 524opList=system.cpu.fuPool.FUList8.opList 525 526[system.cpu.fuPool.FUList8.opList] 527type=OpDesc 528eventq_index=0 529issueLat=3 530opClass=IprAccess 531opLat=3 532 533[system.cpu.icache] 534type=BaseCache 535children=tags 536addr_ranges=0:18446744073709551615 537assoc=2 538clk_domain=system.cpu_clk_domain 539eventq_index=0 540forward_snoops=true 541hit_latency=2 542is_top_level=true 543max_miss_count=0 544mshrs=4 545prefetch_on_access=false 546prefetcher=Null 547response_latency=2 548sequential_access=false 549size=131072 550system=system 551tags=system.cpu.icache.tags 552tgts_per_mshr=20 553two_queue=false 554write_buffers=8 555cpu_side=system.cpu.icache_port 556mem_side=system.cpu.toL2Bus.slave[0] 557 558[system.cpu.icache.tags] 559type=LRU 560assoc=2 561block_size=64 562clk_domain=system.cpu_clk_domain 563eventq_index=0 564hit_latency=2 565sequential_access=false 566size=131072 567 568[system.cpu.interrupts] 569type=ArmInterrupts 570eventq_index=0 571 572[system.cpu.isa] 573type=ArmISA 574eventq_index=0 575fpsid=1090793632 576id_aa64afr0_el1=0 577id_aa64afr1_el1=0 578id_aa64dfr0_el1=1052678 579id_aa64dfr1_el1=0 580id_aa64isar0_el1=0 581id_aa64isar1_el1=0 582id_aa64mmfr0_el1=15728642 583id_aa64mmfr1_el1=0 584id_aa64pfr0_el1=17 585id_aa64pfr1_el1=0 586id_isar0=34607377 587id_isar1=34677009 588id_isar2=555950401 589id_isar3=17899825 590id_isar4=268501314 591id_isar5=0 592id_mmfr0=270536963 593id_mmfr1=0 594id_mmfr2=19070976 595id_mmfr3=34611729 596id_pfr0=49 597id_pfr1=4113 598midr=1091551472 599system=system 600 601[system.cpu.istage2_mmu] 602type=ArmStage2MMU 603children=stage2_tlb 604eventq_index=0 605stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 606tlb=system.cpu.itb 607 608[system.cpu.istage2_mmu.stage2_tlb] 609type=ArmTLB 610children=walker 611eventq_index=0 612is_stage2=true 613size=32 614walker=system.cpu.istage2_mmu.stage2_tlb.walker 615 616[system.cpu.istage2_mmu.stage2_tlb.walker] 617type=ArmTableWalker 618clk_domain=system.cpu_clk_domain 619eventq_index=0 620is_stage2=true 621num_squash_per_cycle=2 622sys=system 623port=system.cpu.toL2Bus.slave[4] 624 625[system.cpu.itb] 626type=ArmTLB 627children=walker 628eventq_index=0 629is_stage2=false 630size=64 631walker=system.cpu.itb.walker 632 633[system.cpu.itb.walker] 634type=ArmTableWalker 635clk_domain=system.cpu_clk_domain 636eventq_index=0 637is_stage2=false 638num_squash_per_cycle=2 639sys=system 640port=system.cpu.toL2Bus.slave[2] 641 642[system.cpu.l2cache] 643type=BaseCache 644children=tags 645addr_ranges=0:18446744073709551615 646assoc=8 647clk_domain=system.cpu_clk_domain 648eventq_index=0 649forward_snoops=true 650hit_latency=20 651is_top_level=false 652max_miss_count=0 653mshrs=20 654prefetch_on_access=false 655prefetcher=Null 656response_latency=20 657sequential_access=false 658size=2097152 659system=system 660tags=system.cpu.l2cache.tags 661tgts_per_mshr=12 662two_queue=false 663write_buffers=8 664cpu_side=system.cpu.toL2Bus.master[0] 665mem_side=system.membus.slave[1] 666 667[system.cpu.l2cache.tags] 668type=LRU 669assoc=8 670block_size=64 671clk_domain=system.cpu_clk_domain 672eventq_index=0 673hit_latency=20 674sequential_access=false 675size=2097152 676 677[system.cpu.toL2Bus] 678type=CoherentBus 679clk_domain=system.cpu_clk_domain 680eventq_index=0 681header_cycles=1 682system=system 683use_default_range=false 684width=32 685master=system.cpu.l2cache.cpu_side 686slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 687 688[system.cpu.tracer] 689type=ExeTracer 690eventq_index=0 691 692[system.cpu.workload] 693type=LiveProcess 694cmd=parser 2.1.dict -batch 695cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 696egid=100 697env= 698errout=cerr 699euid=100 700eventq_index=0 701executable=/dist/cpu2000/binaries/arm/linux/parser 702gid=100 703input=/dist/cpu2000/data/parser/mdred/input/parser.in 704max_stack_size=67108864 705output=cout 706pid=100 707ppid=99 708simpoint=114600000000 709system=system 710uid=100 711 712[system.cpu_clk_domain] 713type=SrcClockDomain 714clock=500 715eventq_index=0 716voltage_domain=system.voltage_domain 717 718[system.membus] 719type=CoherentBus 720clk_domain=system.clk_domain 721eventq_index=0 722header_cycles=1 723system=system 724use_default_range=false 725width=8 726master=system.physmem.port 727slave=system.system_port system.cpu.l2cache.mem_side 728 729[system.physmem] 730type=SimpleDRAM 731activation_limit=4 732addr_mapping=RaBaChCo 733banks_per_rank=8 734burst_length=8 735channels=1 736clk_domain=system.clk_domain 737conf_table_reported=true 738device_bus_width=8 739device_rowbuffer_size=1024 740devices_per_rank=8 741eventq_index=0 742in_addr_map=true 743mem_sched_policy=frfcfs 744null=false 745page_policy=open 746range=0:134217727 747ranks_per_channel=2 748read_buffer_size=32 749static_backend_latency=10000 750static_frontend_latency=10000 751tBURST=5000 752tCL=13750 753tRAS=35000 754tRCD=13750 755tREFI=7800000 756tRFC=300000 757tRP=13750 758tRRD=6250 759tWTR=7500 760tXAW=40000 761write_buffer_size=32 762write_high_thresh_perc=70 763write_low_thresh_perc=0 764port=system.membus.master[0] 765 766[system.voltage_domain] 767type=VoltageDomain 768eventq_index=0 769voltage=1.000000 770 771