config.ini revision 8660
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12memories=system.physmem 13num_work_ids=16 14physmem=system.physmem 15work_begin_ckpt_count=0 16work_begin_cpu_id_exit=-1 17work_begin_exit_count=0 18work_cpus_ckpt_count=0 19work_end_ckpt_count=0 20work_end_exit_count=0 21work_item_id=-1 22 23[system.cpu] 24type=DerivO3CPU 25children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 26BTBEntries=4096 27BTBTagSize=16 28LFSTSize=1024 29LQEntries=32 30LSQCheckLoads=true 31LSQDepCheckShift=4 32RASSize=16 33SQEntries=32 34SSITSize=1024 35activity=0 36backComSize=5 37cachePorts=200 38checker=Null 39choiceCtrBits=2 40choicePredictorSize=8192 41clock=500 42commitToDecodeDelay=1 43commitToFetchDelay=1 44commitToIEWDelay=1 45commitToRenameDelay=1 46commitWidth=8 47cpu_id=0 48decodeToFetchDelay=1 49decodeToRenameDelay=1 50decodeWidth=8 51defer_registration=false 52dispatchWidth=8 53do_checkpoint_insts=true 54do_statistics_insts=true 55dtb=system.cpu.dtb 56fetchToDecodeDelay=1 57fetchTrapLatency=1 58fetchWidth=8 59forwardComSize=5 60fuPool=system.cpu.fuPool 61function_trace=false 62function_trace_start=0 63globalCtrBits=2 64globalHistoryBits=13 65globalPredictorSize=8192 66iewToCommitDelay=1 67iewToDecodeDelay=1 68iewToFetchDelay=1 69iewToRenameDelay=1 70instShiftAmt=2 71issueToExecuteDelay=1 72issueWidth=8 73itb=system.cpu.itb 74localCtrBits=2 75localHistoryBits=11 76localHistoryTableSize=2048 77localPredictorSize=2048 78max_insts_all_threads=0 79max_insts_any_thread=0 80max_loads_all_threads=0 81max_loads_any_thread=0 82numIQEntries=64 83numPhysFloatRegs=256 84numPhysIntRegs=256 85numROBEntries=192 86numRobs=1 87numThreads=1 88phase=0 89predType=tournament 90progress_interval=0 91renameToDecodeDelay=1 92renameToFetchDelay=1 93renameToIEWDelay=2 94renameToROBDelay=1 95renameWidth=8 96smtCommitPolicy=RoundRobin 97smtFetchPolicy=SingleThread 98smtIQPolicy=Partitioned 99smtIQThreshold=100 100smtLSQPolicy=Partitioned 101smtLSQThreshold=100 102smtNumFetchingThreads=1 103smtROBPolicy=Partitioned 104smtROBThreshold=100 105squashWidth=8 106store_set_clear_period=250000 107system=system 108tracer=system.cpu.tracer 109trapLatency=13 110wbDepth=1 111wbWidth=8 112workload=system.cpu.workload 113dcache_port=system.cpu.dcache.cpu_side 114icache_port=system.cpu.icache.cpu_side 115 116[system.cpu.dcache] 117type=BaseCache 118addr_range=0:18446744073709551615 119assoc=2 120block_size=64 121forward_snoops=true 122hash_delay=1 123is_top_level=true 124latency=1000 125max_miss_count=0 126mshrs=10 127num_cpus=1 128prefetch_data_accesses_only=false 129prefetch_degree=1 130prefetch_latency=10000 131prefetch_on_access=false 132prefetch_past_page=false 133prefetch_policy=none 134prefetch_serial_squash=false 135prefetch_use_cpu_id=true 136prefetcher_size=100 137prioritizeRequests=false 138repl=Null 139size=262144 140subblock_size=0 141tgts_per_mshr=20 142trace_addr=0 143two_queue=false 144write_buffers=8 145cpu_side=system.cpu.dcache_port 146mem_side=system.cpu.toL2Bus.port[1] 147 148[system.cpu.dtb] 149type=ArmTLB 150size=64 151 152[system.cpu.fuPool] 153type=FUPool 154children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 155FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 156 157[system.cpu.fuPool.FUList0] 158type=FUDesc 159children=opList 160count=6 161opList=system.cpu.fuPool.FUList0.opList 162 163[system.cpu.fuPool.FUList0.opList] 164type=OpDesc 165issueLat=1 166opClass=IntAlu 167opLat=1 168 169[system.cpu.fuPool.FUList1] 170type=FUDesc 171children=opList0 opList1 172count=2 173opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 174 175[system.cpu.fuPool.FUList1.opList0] 176type=OpDesc 177issueLat=1 178opClass=IntMult 179opLat=3 180 181[system.cpu.fuPool.FUList1.opList1] 182type=OpDesc 183issueLat=19 184opClass=IntDiv 185opLat=20 186 187[system.cpu.fuPool.FUList2] 188type=FUDesc 189children=opList0 opList1 opList2 190count=4 191opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 192 193[system.cpu.fuPool.FUList2.opList0] 194type=OpDesc 195issueLat=1 196opClass=FloatAdd 197opLat=2 198 199[system.cpu.fuPool.FUList2.opList1] 200type=OpDesc 201issueLat=1 202opClass=FloatCmp 203opLat=2 204 205[system.cpu.fuPool.FUList2.opList2] 206type=OpDesc 207issueLat=1 208opClass=FloatCvt 209opLat=2 210 211[system.cpu.fuPool.FUList3] 212type=FUDesc 213children=opList0 opList1 opList2 214count=2 215opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 216 217[system.cpu.fuPool.FUList3.opList0] 218type=OpDesc 219issueLat=1 220opClass=FloatMult 221opLat=4 222 223[system.cpu.fuPool.FUList3.opList1] 224type=OpDesc 225issueLat=12 226opClass=FloatDiv 227opLat=12 228 229[system.cpu.fuPool.FUList3.opList2] 230type=OpDesc 231issueLat=24 232opClass=FloatSqrt 233opLat=24 234 235[system.cpu.fuPool.FUList4] 236type=FUDesc 237children=opList 238count=0 239opList=system.cpu.fuPool.FUList4.opList 240 241[system.cpu.fuPool.FUList4.opList] 242type=OpDesc 243issueLat=1 244opClass=MemRead 245opLat=1 246 247[system.cpu.fuPool.FUList5] 248type=FUDesc 249children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 250count=4 251opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 252 253[system.cpu.fuPool.FUList5.opList00] 254type=OpDesc 255issueLat=1 256opClass=SimdAdd 257opLat=1 258 259[system.cpu.fuPool.FUList5.opList01] 260type=OpDesc 261issueLat=1 262opClass=SimdAddAcc 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList02] 266type=OpDesc 267issueLat=1 268opClass=SimdAlu 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList03] 272type=OpDesc 273issueLat=1 274opClass=SimdCmp 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList04] 278type=OpDesc 279issueLat=1 280opClass=SimdCvt 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList05] 284type=OpDesc 285issueLat=1 286opClass=SimdMisc 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList06] 290type=OpDesc 291issueLat=1 292opClass=SimdMult 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList07] 296type=OpDesc 297issueLat=1 298opClass=SimdMultAcc 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList08] 302type=OpDesc 303issueLat=1 304opClass=SimdShift 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList09] 308type=OpDesc 309issueLat=1 310opClass=SimdShiftAcc 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList10] 314type=OpDesc 315issueLat=1 316opClass=SimdSqrt 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList11] 320type=OpDesc 321issueLat=1 322opClass=SimdFloatAdd 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList12] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatAlu 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList13] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatCmp 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList14] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatCvt 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList15] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatDiv 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList16] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatMisc 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList17] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMult 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList18] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMultAcc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList19] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatSqrt 371opLat=1 372 373[system.cpu.fuPool.FUList6] 374type=FUDesc 375children=opList 376count=0 377opList=system.cpu.fuPool.FUList6.opList 378 379[system.cpu.fuPool.FUList6.opList] 380type=OpDesc 381issueLat=1 382opClass=MemWrite 383opLat=1 384 385[system.cpu.fuPool.FUList7] 386type=FUDesc 387children=opList0 opList1 388count=4 389opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 390 391[system.cpu.fuPool.FUList7.opList0] 392type=OpDesc 393issueLat=1 394opClass=MemRead 395opLat=1 396 397[system.cpu.fuPool.FUList7.opList1] 398type=OpDesc 399issueLat=1 400opClass=MemWrite 401opLat=1 402 403[system.cpu.fuPool.FUList8] 404type=FUDesc 405children=opList 406count=1 407opList=system.cpu.fuPool.FUList8.opList 408 409[system.cpu.fuPool.FUList8.opList] 410type=OpDesc 411issueLat=3 412opClass=IprAccess 413opLat=3 414 415[system.cpu.icache] 416type=BaseCache 417addr_range=0:18446744073709551615 418assoc=2 419block_size=64 420forward_snoops=true 421hash_delay=1 422is_top_level=true 423latency=1000 424max_miss_count=0 425mshrs=10 426num_cpus=1 427prefetch_data_accesses_only=false 428prefetch_degree=1 429prefetch_latency=10000 430prefetch_on_access=false 431prefetch_past_page=false 432prefetch_policy=none 433prefetch_serial_squash=false 434prefetch_use_cpu_id=true 435prefetcher_size=100 436prioritizeRequests=false 437repl=Null 438size=131072 439subblock_size=0 440tgts_per_mshr=20 441trace_addr=0 442two_queue=false 443write_buffers=8 444cpu_side=system.cpu.icache_port 445mem_side=system.cpu.toL2Bus.port[0] 446 447[system.cpu.itb] 448type=ArmTLB 449size=64 450 451[system.cpu.l2cache] 452type=BaseCache 453addr_range=0:18446744073709551615 454assoc=2 455block_size=64 456forward_snoops=true 457hash_delay=1 458is_top_level=false 459latency=1000 460max_miss_count=0 461mshrs=10 462num_cpus=1 463prefetch_data_accesses_only=false 464prefetch_degree=1 465prefetch_latency=10000 466prefetch_on_access=false 467prefetch_past_page=false 468prefetch_policy=none 469prefetch_serial_squash=false 470prefetch_use_cpu_id=true 471prefetcher_size=100 472prioritizeRequests=false 473repl=Null 474size=2097152 475subblock_size=0 476tgts_per_mshr=5 477trace_addr=0 478two_queue=false 479write_buffers=8 480cpu_side=system.cpu.toL2Bus.port[2] 481mem_side=system.membus.port[1] 482 483[system.cpu.toL2Bus] 484type=Bus 485block_size=64 486bus_id=0 487clock=1000 488header_cycles=1 489use_default_range=false 490width=64 491port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 492 493[system.cpu.tracer] 494type=ExeTracer 495 496[system.cpu.workload] 497type=LiveProcess 498cmd=parser 2.1.dict -batch 499cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing 500egid=100 501env= 502errout=cerr 503euid=100 504executable=/dist/m5/cpu2000/binaries/arm/linux/parser 505gid=100 506input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in 507max_stack_size=67108864 508output=cout 509pid=100 510ppid=99 511simpoint=114600000000 512system=system 513uid=100 514 515[system.membus] 516type=Bus 517block_size=64 518bus_id=0 519clock=1000 520header_cycles=1 521use_default_range=false 522width=64 523port=system.physmem.port[0] system.cpu.l2cache.mem_side 524 525[system.physmem] 526type=PhysicalMemory 527file= 528latency=30000 529latency_var=0 530null=false 531range=0:134217727 532zero=false 533port=system.membus.port[0] 534 535