config.ini revision 7860
1[root] 2type=Root 3children=system 4dummy=0 5 6[system] 7type=System 8children=cpu membus physmem 9mem_mode=atomic 10physmem=system.physmem 11 12[system.cpu] 13type=DerivO3CPU 14children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 15BTBEntries=4096 16BTBTagSize=16 17LFSTSize=1024 18LQEntries=32 19RASSize=16 20SQEntries=32 21SSITSize=1024 22activity=0 23backComSize=5 24cachePorts=200 25checker=Null 26choiceCtrBits=2 27choicePredictorSize=8192 28clock=500 29commitToDecodeDelay=1 30commitToFetchDelay=1 31commitToIEWDelay=1 32commitToRenameDelay=1 33commitWidth=8 34cpu_id=0 35decodeToFetchDelay=1 36decodeToRenameDelay=1 37decodeWidth=8 38defer_registration=false 39dispatchWidth=8 40do_checkpoint_insts=true 41do_statistics_insts=true 42dtb=system.cpu.dtb 43fetchToDecodeDelay=1 44fetchTrapLatency=1 45fetchWidth=8 46forwardComSize=5 47fuPool=system.cpu.fuPool 48function_trace=false 49function_trace_start=0 50globalCtrBits=2 51globalHistoryBits=13 52globalPredictorSize=8192 53iewToCommitDelay=1 54iewToDecodeDelay=1 55iewToFetchDelay=1 56iewToRenameDelay=1 57instShiftAmt=2 58issueToExecuteDelay=1 59issueWidth=8 60itb=system.cpu.itb 61localCtrBits=2 62localHistoryBits=11 63localHistoryTableSize=2048 64localPredictorSize=2048 65max_insts_all_threads=0 66max_insts_any_thread=0 67max_loads_all_threads=0 68max_loads_any_thread=0 69numIQEntries=64 70numPhysFloatRegs=256 71numPhysIntRegs=256 72numROBEntries=192 73numRobs=1 74numThreads=1 75phase=0 76predType=tournament 77progress_interval=0 78renameToDecodeDelay=1 79renameToFetchDelay=1 80renameToIEWDelay=2 81renameToROBDelay=1 82renameWidth=8 83smtCommitPolicy=RoundRobin 84smtFetchPolicy=SingleThread 85smtIQPolicy=Partitioned 86smtIQThreshold=100 87smtLSQPolicy=Partitioned 88smtLSQThreshold=100 89smtNumFetchingThreads=1 90smtROBPolicy=Partitioned 91smtROBThreshold=100 92squashWidth=8 93system=system 94tracer=system.cpu.tracer 95trapLatency=13 96wbDepth=1 97wbWidth=8 98workload=system.cpu.workload 99dcache_port=system.cpu.dcache.cpu_side 100icache_port=system.cpu.icache.cpu_side 101 102[system.cpu.dcache] 103type=BaseCache 104addr_range=0:18446744073709551615 105assoc=2 106block_size=64 107forward_snoops=true 108hash_delay=1 109latency=1000 110max_miss_count=0 111mshrs=10 112num_cpus=1 113prefetch_data_accesses_only=false 114prefetch_degree=1 115prefetch_latency=10000 116prefetch_on_access=false 117prefetch_past_page=false 118prefetch_policy=none 119prefetch_serial_squash=false 120prefetch_use_cpu_id=true 121prefetcher_size=100 122prioritizeRequests=false 123repl=Null 124size=262144 125subblock_size=0 126tgts_per_mshr=20 127trace_addr=0 128two_queue=false 129write_buffers=8 130cpu_side=system.cpu.dcache_port 131mem_side=system.cpu.toL2Bus.port[1] 132 133[system.cpu.dtb] 134type=ArmTLB 135size=64 136 137[system.cpu.fuPool] 138type=FUPool 139children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 140FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 141 142[system.cpu.fuPool.FUList0] 143type=FUDesc 144children=opList 145count=6 146opList=system.cpu.fuPool.FUList0.opList 147 148[system.cpu.fuPool.FUList0.opList] 149type=OpDesc 150issueLat=1 151opClass=IntAlu 152opLat=1 153 154[system.cpu.fuPool.FUList1] 155type=FUDesc 156children=opList0 opList1 157count=2 158opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 159 160[system.cpu.fuPool.FUList1.opList0] 161type=OpDesc 162issueLat=1 163opClass=IntMult 164opLat=3 165 166[system.cpu.fuPool.FUList1.opList1] 167type=OpDesc 168issueLat=19 169opClass=IntDiv 170opLat=20 171 172[system.cpu.fuPool.FUList2] 173type=FUDesc 174children=opList0 opList1 opList2 175count=4 176opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 177 178[system.cpu.fuPool.FUList2.opList0] 179type=OpDesc 180issueLat=1 181opClass=FloatAdd 182opLat=2 183 184[system.cpu.fuPool.FUList2.opList1] 185type=OpDesc 186issueLat=1 187opClass=FloatCmp 188opLat=2 189 190[system.cpu.fuPool.FUList2.opList2] 191type=OpDesc 192issueLat=1 193opClass=FloatCvt 194opLat=2 195 196[system.cpu.fuPool.FUList3] 197type=FUDesc 198children=opList0 opList1 opList2 199count=2 200opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 201 202[system.cpu.fuPool.FUList3.opList0] 203type=OpDesc 204issueLat=1 205opClass=FloatMult 206opLat=4 207 208[system.cpu.fuPool.FUList3.opList1] 209type=OpDesc 210issueLat=12 211opClass=FloatDiv 212opLat=12 213 214[system.cpu.fuPool.FUList3.opList2] 215type=OpDesc 216issueLat=24 217opClass=FloatSqrt 218opLat=24 219 220[system.cpu.fuPool.FUList4] 221type=FUDesc 222children=opList 223count=0 224opList=system.cpu.fuPool.FUList4.opList 225 226[system.cpu.fuPool.FUList4.opList] 227type=OpDesc 228issueLat=1 229opClass=MemRead 230opLat=1 231 232[system.cpu.fuPool.FUList5] 233type=FUDesc 234children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 235count=4 236opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 237 238[system.cpu.fuPool.FUList5.opList00] 239type=OpDesc 240issueLat=1 241opClass=SimdAdd 242opLat=1 243 244[system.cpu.fuPool.FUList5.opList01] 245type=OpDesc 246issueLat=1 247opClass=SimdAddAcc 248opLat=1 249 250[system.cpu.fuPool.FUList5.opList02] 251type=OpDesc 252issueLat=1 253opClass=SimdAlu 254opLat=1 255 256[system.cpu.fuPool.FUList5.opList03] 257type=OpDesc 258issueLat=1 259opClass=SimdCmp 260opLat=1 261 262[system.cpu.fuPool.FUList5.opList04] 263type=OpDesc 264issueLat=1 265opClass=SimdCvt 266opLat=1 267 268[system.cpu.fuPool.FUList5.opList05] 269type=OpDesc 270issueLat=1 271opClass=SimdMisc 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList06] 275type=OpDesc 276issueLat=1 277opClass=SimdMult 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList07] 281type=OpDesc 282issueLat=1 283opClass=SimdMultAcc 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList08] 287type=OpDesc 288issueLat=1 289opClass=SimdShift 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList09] 293type=OpDesc 294issueLat=1 295opClass=SimdShiftAcc 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList10] 299type=OpDesc 300issueLat=1 301opClass=SimdSqrt 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList11] 305type=OpDesc 306issueLat=1 307opClass=SimdFloatAdd 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList12] 311type=OpDesc 312issueLat=1 313opClass=SimdFloatAlu 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList13] 317type=OpDesc 318issueLat=1 319opClass=SimdFloatCmp 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList14] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatCvt 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList15] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatDiv 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList16] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatMisc 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList17] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatMult 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList18] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatMultAcc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList19] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatSqrt 356opLat=1 357 358[system.cpu.fuPool.FUList6] 359type=FUDesc 360children=opList 361count=0 362opList=system.cpu.fuPool.FUList6.opList 363 364[system.cpu.fuPool.FUList6.opList] 365type=OpDesc 366issueLat=1 367opClass=MemWrite 368opLat=1 369 370[system.cpu.fuPool.FUList7] 371type=FUDesc 372children=opList0 opList1 373count=4 374opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 375 376[system.cpu.fuPool.FUList7.opList0] 377type=OpDesc 378issueLat=1 379opClass=MemRead 380opLat=1 381 382[system.cpu.fuPool.FUList7.opList1] 383type=OpDesc 384issueLat=1 385opClass=MemWrite 386opLat=1 387 388[system.cpu.fuPool.FUList8] 389type=FUDesc 390children=opList 391count=1 392opList=system.cpu.fuPool.FUList8.opList 393 394[system.cpu.fuPool.FUList8.opList] 395type=OpDesc 396issueLat=3 397opClass=IprAccess 398opLat=3 399 400[system.cpu.icache] 401type=BaseCache 402addr_range=0:18446744073709551615 403assoc=2 404block_size=64 405forward_snoops=true 406hash_delay=1 407latency=1000 408max_miss_count=0 409mshrs=10 410num_cpus=1 411prefetch_data_accesses_only=false 412prefetch_degree=1 413prefetch_latency=10000 414prefetch_on_access=false 415prefetch_past_page=false 416prefetch_policy=none 417prefetch_serial_squash=false 418prefetch_use_cpu_id=true 419prefetcher_size=100 420prioritizeRequests=false 421repl=Null 422size=131072 423subblock_size=0 424tgts_per_mshr=20 425trace_addr=0 426two_queue=false 427write_buffers=8 428cpu_side=system.cpu.icache_port 429mem_side=system.cpu.toL2Bus.port[0] 430 431[system.cpu.itb] 432type=ArmTLB 433size=64 434 435[system.cpu.l2cache] 436type=BaseCache 437addr_range=0:18446744073709551615 438assoc=2 439block_size=64 440forward_snoops=true 441hash_delay=1 442latency=1000 443max_miss_count=0 444mshrs=10 445num_cpus=1 446prefetch_data_accesses_only=false 447prefetch_degree=1 448prefetch_latency=10000 449prefetch_on_access=false 450prefetch_past_page=false 451prefetch_policy=none 452prefetch_serial_squash=false 453prefetch_use_cpu_id=true 454prefetcher_size=100 455prioritizeRequests=false 456repl=Null 457size=2097152 458subblock_size=0 459tgts_per_mshr=5 460trace_addr=0 461two_queue=false 462write_buffers=8 463cpu_side=system.cpu.toL2Bus.port[2] 464mem_side=system.membus.port[1] 465 466[system.cpu.toL2Bus] 467type=Bus 468block_size=64 469bus_id=0 470clock=1000 471header_cycles=1 472use_default_range=false 473width=64 474port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 475 476[system.cpu.tracer] 477type=ExeTracer 478 479[system.cpu.workload] 480type=LiveProcess 481cmd=parser 2.1.dict -batch 482cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing 483egid=100 484env= 485errout=cerr 486euid=100 487executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser 488gid=100 489input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in 490max_stack_size=67108864 491output=cout 492pid=100 493ppid=99 494simpoint=114600000000 495system=system 496uid=100 497 498[system.membus] 499type=Bus 500block_size=64 501bus_id=0 502clock=1000 503header_cycles=1 504use_default_range=false 505width=64 506port=system.physmem.port[0] system.cpu.l2cache.mem_side 507 508[system.physmem] 509type=PhysicalMemory 510file= 511latency=30000 512latency_var=0 513null=false 514range=0:134217727 515zero=false 516port=system.membus.port[0] 517 518