stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.370011 # Number of seconds simulated 4sim_ticks 370010840000 # Number of ticks simulated 5final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 564351 # Simulator instruction rate (inst/s) 8host_op_rate 993732 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1321716509 # Simulator tick rate (ticks/s) 10host_mem_usage 360832 # Number of bytes of host memory used 11host_seconds 279.95 # Real time elapsed on the host 12sim_insts 157988583 # Number of instructions simulated 13sim_ops 278192520 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory 20system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 444 # Number of system calls 38system.cpu.numCycles 740021680 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 157988583 # Number of instructions committed 42system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls 47system.cpu.num_int_insts 278186228 # number of integer instructions 48system.cpu.num_fp_insts 40 # number of float instructions 49system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read 50system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written 51system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 53system.cpu.num_mem_refs 122219139 # number of memory refs 54system.cpu.num_load_insts 90779388 # Number of load instructions 55system.cpu.num_store_insts 31439751 # Number of store instructions 56system.cpu.num_idle_cycles 0 # Number of idle cycles 57system.cpu.num_busy_cycles 740021680 # Number of busy cycles 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 24 # number of replacements 61system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use 62system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 66system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor 67system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits 74system.cpu.icache.overall_hits::total 217695401 # number of overall hits 75system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 76system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 77system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 78system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 79system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 80system.cpu.icache.overall_misses::total 808 # number of overall misses 81system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles 82system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles 83system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles 84system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles 85system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles 86system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles 87system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) 88system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) 89system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses 90system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses 91system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses 92system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses 93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 94system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 95system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 96system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 97system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 98system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency 100system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency 102system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency 103system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency 104system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency 105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111system.cpu.icache.fast_writes 0 # number of fast writes performed 112system.cpu.icache.cache_copies 0 # number of cache copies performed 113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 114system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 115system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 116system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 117system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 118system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles 120system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles 121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles 122system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles 123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles 124system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles 125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 128system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 130system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2062733 # number of replacements 139system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use 140system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. 141system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor 145system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits 149system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits 154system.cpu.dcache.overall_hits::total 120152372 # number of overall hits 155system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 162system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency 188system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency 189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency 190system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency 191system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency 192system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency 193system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency 194system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency 195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 201system.cpu.dcache.fast_writes 0 # number of fast writes performed 202system.cpu.dcache.cache_copies 0 # number of cache copies performed 203system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks 204system.cpu.dcache.writebacks::total 1437080 # number of writebacks 205system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 206system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 207system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 208system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 209system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 210system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 211system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 212system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles 214system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles 215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles 216system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles 217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles 218system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles 219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles 220system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles 221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 226system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 228system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency 230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 49212 # number of replacements 239system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use 240system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. 243system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor 245system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor 246system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor 247system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy 248system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy 249system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy 250system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy 251system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits 252system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits 253system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits 254system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits 255system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits 256system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits 257system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits 258system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits 259system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits 260system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits 261system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 262system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses 263system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses 264system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses 265system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses 266system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 267system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses 268system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses 269system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses 270system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses 271system.cpu.l2cache.overall_misses::total 76575 # number of overall misses 272system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles 273system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles 274system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles 275system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles 276system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles 277system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles 278system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles 279system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles 280system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles 281system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles 282system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles 283system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 284system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 285system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 286system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses) 287system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses) 288system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 289system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 290system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 291system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 292system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 293system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 294system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 295system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 296system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses 297system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses 298system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses 299system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses 300system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses 301system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 302system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses 303system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses 304system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 305system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses 306system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses 307system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 308system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 309system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 310system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency 311system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency 312system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 313system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency 314system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency 315system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 316system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency 317system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency 318system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 321system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 322system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.cpu.l2cache.fast_writes 0 # number of fast writes performed 325system.cpu.l2cache.cache_copies 0 # number of cache copies performed 326system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks 327system.cpu.l2cache.writebacks::total 29460 # number of writebacks 328system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 329system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses 330system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses 331system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses 332system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses 333system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 334system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses 335system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses 336system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 337system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses 338system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses 339system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles 340system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles 341system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles 342system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles 343system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles 344system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles 345system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles 346system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles 347system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles 348system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles 349system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles 350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses 352system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses 353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses 354system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses 355system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 356system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses 357system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses 358system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 359system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses 360system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses 361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 363system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 364system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 365system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 366system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 367system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 368system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 369system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 370system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 371system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 372system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 373 374---------- End Simulation Statistics ---------- 375