stats.txt revision 11731
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 0.366229 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 366229314500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711687Sandreas.hansson@arm.comhost_inst_rate 1002365 # Simulator instruction rate (inst/s) 811687Sandreas.hansson@arm.comhost_op_rate 1765004 # Simulator op (including micro ops) rate (op/s) 911687Sandreas.hansson@arm.comhost_tick_rate 2323557450 # Simulator tick rate (ticks/s) 1011687Sandreas.hansson@arm.comhost_mem_usage 412036 # Number of bytes of host memory used 1111687Sandreas.hansson@arm.comhost_seconds 157.62 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 157988548 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 278192465 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 1922944 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 6656 # Number of bytes written to this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 30046 # Number of read requests responded to by this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 104 # Number of write requests responded to by this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) 3311606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) 3411606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) 3511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) 3611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) 3711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) 3811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) 3911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 4111507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4211606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 4311507SCurtis.Dunham@arm.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 4411606Sandreas.sandberg@arm.comsystem.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 4511606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 4611507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 444 # Number of system calls 4711606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states 4811606Sandreas.sandberg@arm.comsystem.cpu.numCycles 732458629 # number of cpu cycles simulated 4911507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5011507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5111507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 157988548 # Number of instructions committed 5211507SCurtis.Dunham@arm.comsystem.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 5311507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 5411507SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 5511507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 8475189 # number of times a function call or return occured 5611507SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 5711507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 278169482 # number of integer instructions 5811507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 40 # number of float instructions 5911507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 6011507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 6111507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads 40 # number of times the floating registers were read 6211507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 26 # number of times the floating registers were written 6311507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 6411507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 6511507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 122219137 # number of memory refs 6611507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 90779385 # Number of load instructions 6711507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 31439752 # Number of store instructions 6811507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 6911606Sandreas.sandberg@arm.comsystem.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles 7011507SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 7111507SCurtis.Dunham@arm.comsystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 7211507SCurtis.Dunham@arm.comsystem.cpu.Branches 29309705 # Number of branches fetched 7311507SCurtis.Dunham@arm.comsystem.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 7411507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 7511507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 7611507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 7711507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 7811507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 7911507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 8011507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 8111687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction 8211507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 8311687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction 8411507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 8511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 8611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 8711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 8811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 8911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 9011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 9111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 9311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 9411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 9511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 9611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 9711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 9811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 9911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 10011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 10111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 10211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 10311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 10411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 10511687Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction 10611687Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction 10711687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction 10811687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction 10911507SCurtis.Dunham@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11011507SCurtis.Dunham@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11111507SCurtis.Dunham@arm.comsystem.cpu.op_class::total 278192465 # Class of executed instruction 11211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 11311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2062733 # number of replacements 11411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use 11511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 11611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 11711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 11811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. 11911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor 12011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy 12111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy 12211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 12311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 12411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id 12511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id 12611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 12711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 12811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 12911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 13011606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 13111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 13211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 13311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 13411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 13511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 13611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 13711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 13811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 120152370 # number of overall hits 13911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 14011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 14111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 14211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 14311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 14411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 14511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 14611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 2066829 # number of overall misses 14711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles 14811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles 14911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles 15011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles 15111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles 15211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles 15311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles 15411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles 15511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 15611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 15711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 15811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 15911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 16011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 16111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 16211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 16311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 16411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 16511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 16611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 16711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 16811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 16911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 17011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 17111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency 17211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency 17311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency 17411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency 17511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency 17611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency 17711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency 17811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency 17911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 18011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 18111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 18211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 18311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 18411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 18511507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks 18611507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2062482 # number of writebacks 18711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 18811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 18911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 19011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 19111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 19211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 19311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 19411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 19511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles 19611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles 19711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles 19811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles 19911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles 20011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles 20111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles 20211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles 20311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 20411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 20511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 20611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 20711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 20811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 20911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 21011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 21111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency 21211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency 21311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency 21411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency 21511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency 21611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency 21711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency 21811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency 21911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 22011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 24 # number of replacements 22111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use 22211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 22311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 22411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 22511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor 22711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy 22811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy 22911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 23011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 23111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 23211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 23311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 23411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 23511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 23611606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 23711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 23811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 23911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 24011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 24111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 24211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 217695356 # number of overall hits 24311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 24411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 24511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 24611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 24711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 24811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 808 # number of overall misses 24911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles 25011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles 25111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles 25211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles 25311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles 25411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles 25511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 25611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 25711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 25811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 25911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 26011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 26111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 26211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 26311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 26411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 26511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 26611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 26711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency 26811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency 26911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency 27011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency 27111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency 27211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency 27311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 27811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27911507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 24 # number of writebacks 28011507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 24 # number of writebacks 28111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 28211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 28311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 28411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 28511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 28611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 28711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles 28811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles 28911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles 29011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles 29111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles 29211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles 29311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 29411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 29511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 29711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 29811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 29911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency 30011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency 30111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency 30211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency 30311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency 30411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency 30511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 30611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 315 # number of replacements 30711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use 30811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks. 30911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks. 31011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks. 31111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor 31311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor 31411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor 31511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy 31611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy 31711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy 31811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy 31911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id 32011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 32111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 32211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 32311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id 32411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id 32511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id 32611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses 32711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses 32811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 32911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits 33011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits 33111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits 33211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits 33311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 33411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 33511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits 33611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits 33711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits 33811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits 33911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 34011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits 34111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits 34211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 34311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits 34411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 2037591 # number of overall hits 34511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 34611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 34711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses 34811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses 34911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses 35011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses 35111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 35211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses 35311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses 35411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 35511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses 35611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 30046 # number of overall misses 35711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles 35811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles 35911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles 36011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles 36111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles 36211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles 36311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles 36411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles 36511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles 36611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles 36711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles 36811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles 36911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) 37011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) 37111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) 37211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) 37311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 37411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 37511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) 37611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) 37711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) 37811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) 37911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 38011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 38111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 38211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 38311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 38411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 38511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses 38811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses 38911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses 39011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses 39111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 39211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses 39311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses 39411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 39511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses 39611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses 39711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency 39811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency 39911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency 40011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency 40111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 40211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 40311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency 40411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency 40511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency 40611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency 40711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency 40811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency 40911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 41211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 41311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 104 # number of writebacks 41611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 104 # number of writebacks 41711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 41811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 41911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses 42011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses 42111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses 42211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses 42311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 42411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses 42511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses 42611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 42711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses 42811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses 42911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles 43011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles 43111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles 43211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles 43311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles 43411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles 43511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles 43611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles 43711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles 43811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles 43911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles 44011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles 44111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 44211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 44311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses 44411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses 44511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses 44611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses 44711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 44811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses 44911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses 45011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 45111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses 45211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses 45311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency 45411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency 45511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency 45611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency 45711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 45811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 45911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency 46011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency 46111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency 46211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency 46311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency 46411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency 46511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. 46611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. 46711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 46811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. 46911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 47011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 47111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 47211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 47311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution 47411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution 47511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution 47611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 47711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 47811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution 47911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution 48011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) 48111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) 48211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) 48311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) 48411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) 48511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) 48611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 315 # Total snoops (count) 48711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) 48811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram 48911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram 49011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram 49111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 49211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram 49311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram 49411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 49511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 49611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 49711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 49811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram 49911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) 50011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 50111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 50211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 50311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 50411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 50511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. 50611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. 50711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 50811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 50911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 51011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 51111606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states 51211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 1022 # Transaction distribution 51311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 104 # Transaction distribution 51411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 14 # Transaction distribution 51511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 29024 # Transaction distribution 51611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 29024 # Transaction distribution 51711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution 51811606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) 51911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) 52011606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) 52111606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) 52211606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) 52311606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) 52411507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 52511570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 52611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 30046 # Request fanout histogram 52711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 52811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 52911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53011606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram 53111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 53211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 53311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 53411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 53511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 30046 # Request fanout histogram 53611606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) 53711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53811606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) 53911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 54011507SCurtis.Dunham@arm.com 54111507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 542