stats.txt revision 9583:c1a5a20cc1fa
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.066031 # Number of seconds simulated 4sim_ticks 66030660000 # Number of ticks simulated 5final_tick 66030660000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 55728 # Simulator instruction rate (inst/s) 8host_op_rate 98128 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23291229 # Simulator tick rate (ticks/s) 10host_mem_usage 430752 # Number of bytes of host memory used 11host_seconds 2835.00 # Real time elapsed on the host 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 64768 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1881920 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 64768 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 64768 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10176 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10176 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1012 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29405 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30417 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 159 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 159 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 980878 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28500700 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29481577 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 980878 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 980878 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 154110 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 154110 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 154110 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 980878 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28500700 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29635687 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30419 # Total number of read requests seen 38system.physmem.writeReqs 159 # Total number of write requests seen 39system.physmem.cpureqs 30579 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1946688 # Total number of bytes read from memory 41system.physmem.bytesWritten 10176 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1946688 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 10176 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 38 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1880 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1951 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1941 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1894 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 66030647000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30419 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 159 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 29848 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 96 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 127system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 159system.physmem.totQLat 12950000 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 610712500 # Sum of mem lat for all requests 161system.physmem.totBusLat 151905000 # Total cycles spent in databus access 162system.physmem.totBankLat 445857500 # Total cycles spent in bank access 163system.physmem.avgQLat 426.25 # Average queueing delay per request 164system.physmem.avgBankLat 14675.54 # Average bank access latency per request 165system.physmem.avgBusLat 5000.00 # Average bus latency per request 166system.physmem.avgMemAccLat 20101.79 # Average memory access latency 167system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.23 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.01 # Average read queue length over time 174system.physmem.avgWrQLen 9.37 # Average write queue length over time 175system.physmem.readRowHits 29124 # Number of row buffer hits during reads 176system.physmem.writeRowHits 74 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 95.86 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 46.54 # Row buffer hit rate for writes 179system.physmem.avgGap 2159416.80 # Average gap between requests 180system.cpu.branchPred.lookups 34530822 # Number of BP lookups 181system.cpu.branchPred.condPredicted 34530822 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 911360 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 24729253 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 24630321 # Number of BTB hits 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 186system.cpu.branchPred.BTBHitPct 99.599939 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 189system.cpu.workload.num_syscalls 444 # Number of system calls 190system.cpu.numCycles 132061321 # number of cpu cycles simulated 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 193system.cpu.fetch.icacheStallCycles 26640465 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 185644154 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 34530822 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 24630321 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 56512430 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 6116130 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 43661882 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 168 # Number of stall cycles due to pending traps 202system.cpu.fetch.CacheLines 25987124 # Number of cache lines fetched 203system.cpu.fetch.IcacheSquashes 190736 # Number of outstanding Icache misses that were squashed 204system.cpu.fetch.rateDist::samples 131984046 # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::mean 2.483688 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::stdev 3.326165 # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::0 78029555 59.12% 59.12% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::1 1995729 1.51% 60.63% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::2 2956074 2.24% 62.87% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::3 3928612 2.98% 65.85% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::4 7800232 5.91% 71.76% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::5 4757812 3.60% 75.36% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::6 2739309 2.08% 77.44% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::7 1526136 1.16% 78.60% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::8 28250587 21.40% 100.00% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::total 131984046 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.branchRate 0.261476 # Number of branch fetches per cycle 222system.cpu.fetch.rate 1.405742 # Number of inst fetches per cycle 223system.cpu.decode.IdleCycles 37482972 # Number of cycles decode is idle 224system.cpu.decode.BlockedCycles 35916557 # Number of cycles decode is blocked 225system.cpu.decode.RunCycles 44772529 # Number of cycles decode is running 226system.cpu.decode.UnblockCycles 8642915 # Number of cycles decode is unblocking 227system.cpu.decode.SquashCycles 5169073 # Number of cycles decode is squashing 228system.cpu.decode.DecodedInsts 324582822 # Number of instructions handled by decode 229system.cpu.rename.SquashCycles 5169073 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 43046448 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 8564916 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 9080 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 47588733 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 27605796 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 320159922 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 237 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 45758 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 25753634 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers 240system.cpu.rename.RenamedOperands 322185741 # Number of destination operands rename has renamed 241system.cpu.rename.RenameLookups 849178580 # Number of register rename lookups that rename has made 242system.cpu.rename.int_rename_lookups 849176902 # Number of integer rename lookups 243system.cpu.rename.fp_rename_lookups 1678 # Number of floating rename lookups 244system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 245system.cpu.rename.UndoneMaps 42972994 # Number of HB maps that are undone due to squashing 246system.cpu.rename.serializingInsts 471 # count of serializing insts renamed 247system.cpu.rename.tempSerializingInsts 465 # count of temporary serializing insts renamed 248system.cpu.rename.skidInsts 62311011 # count of insts added to the skid buffer 249system.cpu.memDep0.insertedLoads 102521831 # Number of loads inserted to the mem dependence unit. 250system.cpu.memDep0.insertedStores 35289955 # Number of stores inserted to the mem dependence unit. 251system.cpu.memDep0.conflictingLoads 39590581 # Number of conflicting loads. 252system.cpu.memDep0.conflictingStores 5948018 # Number of conflicting stores. 253system.cpu.iq.iqInstsAdded 315836203 # Number of instructions added to the IQ (excludes non-spec) 254system.cpu.iq.iqNonSpecInstsAdded 1692 # Number of non-speculative instructions added to the IQ 255system.cpu.iq.iqInstsIssued 302241523 # Number of instructions issued 256system.cpu.iq.iqSquashedInstsIssued 114427 # Number of squashed instructions issued 257system.cpu.iq.iqSquashedInstsExamined 37009178 # Number of squashed instructions iterated over during squash; mainly for profiling 258system.cpu.iq.iqSquashedOperandsExamined 54193553 # Number of squashed operands that are examined and possibly removed from graph 259system.cpu.iq.iqSquashedNonSpecRemoved 1247 # Number of squashed non-spec instructions that were removed 260system.cpu.iq.issued_per_cycle::samples 131984046 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::mean 2.289985 # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::stdev 1.700189 # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::0 24578568 18.62% 18.62% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::1 23258852 17.62% 36.24% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::2 25861899 19.59% 55.84% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::3 25827751 19.57% 75.41% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::4 18939781 14.35% 89.76% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::5 8317897 6.30% 96.06% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::6 4131388 3.13% 99.19% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::7 904597 0.69% 99.88% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::8 163313 0.12% 100.00% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::total 131984046 # Number of insts issued each cycle 277system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 278system.cpu.iq.fu_full::IntAlu 38531 1.97% 1.97% # attempts to use FU when none available 279system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 280system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 307system.cpu.iq.fu_full::MemRead 1832245 93.51% 95.48% # attempts to use FU when none available 308system.cpu.iq.fu_full::MemWrite 88531 4.52% 100.00% # attempts to use FU when none available 309system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 310system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 311system.cpu.iq.FU_type_0::No_OpClass 31281 0.01% 0.01% # Type of FU issued 312system.cpu.iq.FU_type_0::IntAlu 171212053 56.65% 56.66% # Type of FU issued 313system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.66% # Type of FU issued 314system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.66% # Type of FU issued 315system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.66% # Type of FU issued 316system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.66% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.66% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.66% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.66% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued 341system.cpu.iq.FU_type_0::MemRead 97762843 32.35% 89.00% # Type of FU issued 342system.cpu.iq.FU_type_0::MemWrite 33235315 11.00% 100.00% # Type of FU issued 343system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 344system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 345system.cpu.iq.FU_type_0::total 302241523 # Type of FU issued 346system.cpu.iq.rate 2.288645 # Inst issue rate 347system.cpu.iq.fu_busy_cnt 1959307 # FU busy when requested 348system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) 349system.cpu.iq.int_inst_queue_reads 738540324 # Number of integer instruction queue reads 350system.cpu.iq.int_inst_queue_writes 352878782 # Number of integer instruction queue writes 351system.cpu.iq.int_inst_queue_wakeup_accesses 299597425 # Number of integer instruction queue wakeup accesses 352system.cpu.iq.fp_inst_queue_reads 502 # Number of floating instruction queue reads 353system.cpu.iq.fp_inst_queue_writes 804 # Number of floating instruction queue writes 354system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses 355system.cpu.iq.int_alu_accesses 304169320 # Number of integer alu accesses 356system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses 357system.cpu.iew.lsq.thread0.forwLoads 54003142 # Number of loads that had data forwarded from stores 358system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 359system.cpu.iew.lsq.thread0.squashedLoads 11742446 # Number of loads squashed 360system.cpu.iew.lsq.thread0.ignoredResponses 27574 # Number of memory responses ignored because the instruction is squashed 361system.cpu.iew.lsq.thread0.memOrderViolation 33469 # Number of memory ordering violations 362system.cpu.iew.lsq.thread0.squashedStores 3850203 # Number of stores squashed 363system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 364system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 365system.cpu.iew.lsq.thread0.rescheduledLoads 3240 # Number of loads that were rescheduled 366system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked 367system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 368system.cpu.iew.iewSquashCycles 5169073 # Number of cycles IEW is squashing 369system.cpu.iew.iewBlockCycles 1760712 # Number of cycles IEW is blocking 370system.cpu.iew.iewUnblockCycles 159375 # Number of cycles IEW is unblocking 371system.cpu.iew.iewDispatchedInsts 315837895 # Number of instructions dispatched to IQ 372system.cpu.iew.iewDispSquashedInsts 196193 # Number of squashed instructions skipped by dispatch 373system.cpu.iew.iewDispLoadInsts 102521831 # Number of dispatched load instructions 374system.cpu.iew.iewDispStoreInsts 35289955 # Number of dispatched store instructions 375system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions 376system.cpu.iew.iewIQFullEvents 3161 # Number of times the IQ has become full, causing a stall 377system.cpu.iew.iewLSQFullEvents 73375 # Number of times the LSQ has become full, causing a stall 378system.cpu.iew.memOrderViolationEvents 33469 # Number of memory order violations 379system.cpu.iew.predictedTakenIncorrect 522333 # Number of branches that were predicted taken incorrectly 380system.cpu.iew.predictedNotTakenIncorrect 446338 # Number of branches that were predicted not taken incorrectly 381system.cpu.iew.branchMispredicts 968671 # Number of branch mispredicts detected at execute 382system.cpu.iew.iewExecutedInsts 300624260 # Number of executed instructions 383system.cpu.iew.iewExecLoadInsts 97295381 # Number of load instructions executed 384system.cpu.iew.iewExecSquashedInsts 1617263 # Number of squashed instructions skipped in execute 385system.cpu.iew.exec_swp 0 # number of swp insts executed 386system.cpu.iew.exec_nop 0 # number of nop insts executed 387system.cpu.iew.exec_refs 130311532 # number of memory reference insts executed 388system.cpu.iew.exec_branches 30892471 # Number of branches executed 389system.cpu.iew.exec_stores 33016151 # Number of stores executed 390system.cpu.iew.exec_rate 2.276399 # Inst execution rate 391system.cpu.iew.wb_sent 300027844 # cumulative count of insts sent to commit 392system.cpu.iew.wb_count 299597573 # cumulative count of insts written-back 393system.cpu.iew.wb_producers 219555050 # num instructions producing a value 394system.cpu.iew.wb_consumers 298061824 # num instructions consuming a value 395system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 396system.cpu.iew.wb_rate 2.268625 # insts written-back per cycle 397system.cpu.iew.wb_fanout 0.736609 # average fanout of values written-back 398system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 399system.cpu.commit.commitSquashedInsts 37658416 # The number of squashed insts skipped by commit 400system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 401system.cpu.commit.branchMispredicts 911380 # The number of times a branch was mispredicted 402system.cpu.commit.committed_per_cycle::samples 126814973 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::mean 2.193688 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::stdev 2.964855 # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::0 58216662 45.91% 45.91% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::1 19288284 15.21% 61.12% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::2 11866550 9.36% 70.47% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::3 9593635 7.57% 78.04% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::4 1717867 1.35% 79.39% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::5 2074758 1.64% 81.03% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::6 1297787 1.02% 82.05% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::7 717245 0.57% 82.62% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::8 22042185 17.38% 100.00% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::total 126814973 # Number of insts commited each cycle 419system.cpu.commit.committedInsts 157988547 # Number of instructions committed 420system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 421system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 422system.cpu.commit.refs 122219137 # Number of memory references committed 423system.cpu.commit.loads 90779385 # Number of loads committed 424system.cpu.commit.membars 0 # Number of memory barriers committed 425system.cpu.commit.branches 29309705 # Number of branches committed 426system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 427system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. 428system.cpu.commit.function_calls 0 # Number of function calls committed. 429system.cpu.commit.bw_lim_events 22042185 # number cycles where commit BW limit reached 430system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 431system.cpu.rob.rob_reads 420623668 # The number of ROB reads 432system.cpu.rob.rob_writes 636875907 # The number of ROB writes 433system.cpu.timesIdled 13847 # Number of times that the entire CPU went into an idle state and unscheduled itself 434system.cpu.idleCycles 77275 # Total number of cycles that the CPU has spent unscheduled due to idling 435system.cpu.committedInsts 157988547 # Number of Instructions Simulated 436system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated 438system.cpu.cpi 0.835892 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 0.835892 # CPI: Total CPI of All Threads 440system.cpu.ipc 1.196327 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 1.196327 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 592882448 # number of integer regfile reads 443system.cpu.int_regfile_writes 300260228 # number of integer regfile writes 444system.cpu.fp_regfile_reads 139 # number of floating regfile reads 445system.cpu.fp_regfile_writes 69 # number of floating regfile writes 446system.cpu.misc_regfile_reads 192732445 # number of misc regfile reads 447system.cpu.misc_regfile_writes 1 # number of misc regfile writes 448system.cpu.icache.replacements 62 # number of replacements 449system.cpu.icache.tagsinuse 833.765098 # Cycle average of tags in use 450system.cpu.icache.total_refs 25985776 # Total number of references to valid blocks. 451system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. 452system.cpu.icache.avg_refs 25253.426628 # Average number of references to valid blocks. 453system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 454system.cpu.icache.occ_blocks::cpu.inst 833.765098 # Average occupied blocks per requestor 455system.cpu.icache.occ_percent::cpu.inst 0.407112 # Average percentage of cache occupancy 456system.cpu.icache.occ_percent::total 0.407112 # Average percentage of cache occupancy 457system.cpu.icache.ReadReq_hits::cpu.inst 25985776 # number of ReadReq hits 458system.cpu.icache.ReadReq_hits::total 25985776 # number of ReadReq hits 459system.cpu.icache.demand_hits::cpu.inst 25985776 # number of demand (read+write) hits 460system.cpu.icache.demand_hits::total 25985776 # number of demand (read+write) hits 461system.cpu.icache.overall_hits::cpu.inst 25985776 # number of overall hits 462system.cpu.icache.overall_hits::total 25985776 # number of overall hits 463system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses 464system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses 465system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses 466system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses 467system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses 468system.cpu.icache.overall_misses::total 1348 # number of overall misses 469system.cpu.icache.ReadReq_miss_latency::cpu.inst 66423500 # number of ReadReq miss cycles 470system.cpu.icache.ReadReq_miss_latency::total 66423500 # number of ReadReq miss cycles 471system.cpu.icache.demand_miss_latency::cpu.inst 66423500 # number of demand (read+write) miss cycles 472system.cpu.icache.demand_miss_latency::total 66423500 # number of demand (read+write) miss cycles 473system.cpu.icache.overall_miss_latency::cpu.inst 66423500 # number of overall miss cycles 474system.cpu.icache.overall_miss_latency::total 66423500 # number of overall miss cycles 475system.cpu.icache.ReadReq_accesses::cpu.inst 25987124 # number of ReadReq accesses(hits+misses) 476system.cpu.icache.ReadReq_accesses::total 25987124 # number of ReadReq accesses(hits+misses) 477system.cpu.icache.demand_accesses::cpu.inst 25987124 # number of demand (read+write) accesses 478system.cpu.icache.demand_accesses::total 25987124 # number of demand (read+write) accesses 479system.cpu.icache.overall_accesses::cpu.inst 25987124 # number of overall (read+write) accesses 480system.cpu.icache.overall_accesses::total 25987124 # number of overall (read+write) accesses 481system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 482system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 483system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 484system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 485system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 486system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses 487system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49275.593472 # average ReadReq miss latency 488system.cpu.icache.ReadReq_avg_miss_latency::total 49275.593472 # average ReadReq miss latency 489system.cpu.icache.demand_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency 490system.cpu.icache.demand_avg_miss_latency::total 49275.593472 # average overall miss latency 491system.cpu.icache.overall_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency 492system.cpu.icache.overall_avg_miss_latency::total 49275.593472 # average overall miss latency 493system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked 494system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 496system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 # average number of cycles each access was blocked 498system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.icache.fast_writes 0 # number of fast writes performed 500system.cpu.icache.cache_copies 0 # number of cache copies performed 501system.cpu.icache.ReadReq_mshr_hits::cpu.inst 318 # number of ReadReq MSHR hits 502system.cpu.icache.ReadReq_mshr_hits::total 318 # number of ReadReq MSHR hits 503system.cpu.icache.demand_mshr_hits::cpu.inst 318 # number of demand (read+write) MSHR hits 504system.cpu.icache.demand_mshr_hits::total 318 # number of demand (read+write) MSHR hits 505system.cpu.icache.overall_mshr_hits::cpu.inst 318 # number of overall MSHR hits 506system.cpu.icache.overall_mshr_hits::total 318 # number of overall MSHR hits 507system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses 508system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 509system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses 510system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses 511system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses 512system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses 513system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51809000 # number of ReadReq MSHR miss cycles 514system.cpu.icache.ReadReq_mshr_miss_latency::total 51809000 # number of ReadReq MSHR miss cycles 515system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51809000 # number of demand (read+write) MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::total 51809000 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51809000 # number of overall MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::total 51809000 # number of overall MSHR miss cycles 519system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 520system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 521system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 522system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 523system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 524system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 525system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50300 # average ReadReq mshr miss latency 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50300 # average ReadReq mshr miss latency 527system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency 529system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency 531system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.l2cache.replacements 466 # number of replacements 533system.cpu.l2cache.tagsinuse 20794.050693 # Cycle average of tags in use 534system.cpu.l2cache.total_refs 4028842 # Total number of references to valid blocks. 535system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. 536system.cpu.l2cache.avg_refs 132.545138 # Average number of references to valid blocks. 537system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 538system.cpu.l2cache.occ_blocks::writebacks 19862.572081 # Average occupied blocks per requestor 539system.cpu.l2cache.occ_blocks::cpu.inst 688.563421 # Average occupied blocks per requestor 540system.cpu.l2cache.occ_blocks::cpu.data 242.915191 # Average occupied blocks per requestor 541system.cpu.l2cache.occ_percent::writebacks 0.606158 # Average percentage of cache occupancy 542system.cpu.l2cache.occ_percent::cpu.inst 0.021013 # Average percentage of cache occupancy 543system.cpu.l2cache.occ_percent::cpu.data 0.007413 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::total 0.634584 # Average percentage of cache occupancy 545system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 546system.cpu.l2cache.ReadReq_hits::cpu.data 1993511 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::total 1993528 # number of ReadReq hits 548system.cpu.l2cache.Writeback_hits::writebacks 2066502 # number of Writeback hits 549system.cpu.l2cache.Writeback_hits::total 2066502 # number of Writeback hits 550system.cpu.l2cache.ReadExReq_hits::cpu.data 53260 # number of ReadExReq hits 551system.cpu.l2cache.ReadExReq_hits::total 53260 # number of ReadExReq hits 552system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 553system.cpu.l2cache.demand_hits::cpu.data 2046771 # number of demand (read+write) hits 554system.cpu.l2cache.demand_hits::total 2046788 # number of demand (read+write) hits 555system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 556system.cpu.l2cache.overall_hits::cpu.data 2046771 # number of overall hits 557system.cpu.l2cache.overall_hits::total 2046788 # number of overall hits 558system.cpu.l2cache.ReadReq_misses::cpu.inst 1012 # number of ReadReq misses 559system.cpu.l2cache.ReadReq_misses::cpu.data 407 # number of ReadReq misses 560system.cpu.l2cache.ReadReq_misses::total 1419 # number of ReadReq misses 561system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 562system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 563system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses 564system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses 565system.cpu.l2cache.demand_misses::cpu.inst 1012 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::cpu.data 29407 # number of demand (read+write) misses 567system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.inst 1012 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.data 29407 # number of overall misses 570system.cpu.l2cache.overall_misses::total 30419 # number of overall misses 571system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50601000 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20149000 # number of ReadReq miss cycles 573system.cpu.l2cache.ReadReq_miss_latency::total 70750000 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220932500 # number of ReadExReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::total 1220932500 # number of ReadExReq miss cycles 576system.cpu.l2cache.demand_miss_latency::cpu.inst 50601000 # number of demand (read+write) miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.data 1241081500 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::total 1291682500 # number of demand (read+write) miss cycles 579system.cpu.l2cache.overall_miss_latency::cpu.inst 50601000 # number of overall miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.data 1241081500 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::total 1291682500 # number of overall miss cycles 582system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.ReadReq_accesses::cpu.data 1993918 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::total 1994947 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.Writeback_accesses::writebacks 2066502 # number of Writeback accesses(hits+misses) 586system.cpu.l2cache.Writeback_accesses::total 2066502 # number of Writeback accesses(hits+misses) 587system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 588system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 589system.cpu.l2cache.ReadExReq_accesses::cpu.data 82260 # number of ReadExReq accesses(hits+misses) 590system.cpu.l2cache.ReadExReq_accesses::total 82260 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses 592system.cpu.l2cache.demand_accesses::cpu.data 2076178 # number of demand (read+write) accesses 593system.cpu.l2cache.demand_accesses::total 2077207 # number of demand (read+write) accesses 594system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses 595system.cpu.l2cache.overall_accesses::cpu.data 2076178 # number of overall (read+write) accesses 596system.cpu.l2cache.overall_accesses::total 2077207 # number of overall (read+write) accesses 597system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983479 # miss rate for ReadReq accesses 598system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000204 # miss rate for ReadReq accesses 599system.cpu.l2cache.ReadReq_miss_rate::total 0.000711 # miss rate for ReadReq accesses 600system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 601system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 602system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352541 # miss rate for ReadExReq accesses 603system.cpu.l2cache.ReadExReq_miss_rate::total 0.352541 # miss rate for ReadExReq accesses 604system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983479 # miss rate for demand accesses 605system.cpu.l2cache.demand_miss_rate::cpu.data 0.014164 # miss rate for demand accesses 606system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 607system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983479 # miss rate for overall accesses 608system.cpu.l2cache.overall_miss_rate::cpu.data 0.014164 # miss rate for overall accesses 609system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses 610system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50000.988142 # average ReadReq miss latency 611system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49506.142506 # average ReadReq miss latency 612system.cpu.l2cache.ReadReq_avg_miss_latency::total 49859.055673 # average ReadReq miss latency 613system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42101.120690 # average ReadExReq miss latency 614system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42101.120690 # average ReadExReq miss latency 615system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50000.988142 # average overall miss latency 616system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42203.607984 # average overall miss latency 617system.cpu.l2cache.demand_avg_miss_latency::total 42463.016536 # average overall miss latency 618system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50000.988142 # average overall miss latency 619system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42203.607984 # average overall miss latency 620system.cpu.l2cache.overall_avg_miss_latency::total 42463.016536 # average overall miss latency 621system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 622system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 623system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 624system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 625system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 626system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 627system.cpu.l2cache.fast_writes 0 # number of fast writes performed 628system.cpu.l2cache.cache_copies 0 # number of cache copies performed 629system.cpu.l2cache.writebacks::writebacks 159 # number of writebacks 630system.cpu.l2cache.writebacks::total 159 # number of writebacks 631system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1012 # number of ReadReq MSHR misses 632system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 407 # number of ReadReq MSHR misses 633system.cpu.l2cache.ReadReq_mshr_misses::total 1419 # number of ReadReq MSHR misses 634system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 635system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 636system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses 637system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses 638system.cpu.l2cache.demand_mshr_misses::cpu.inst 1012 # number of demand (read+write) MSHR misses 639system.cpu.l2cache.demand_mshr_misses::cpu.data 29407 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.demand_mshr_misses::total 30419 # number of demand (read+write) MSHR misses 641system.cpu.l2cache.overall_mshr_misses::cpu.inst 1012 # number of overall MSHR misses 642system.cpu.l2cache.overall_mshr_misses::cpu.data 29407 # number of overall MSHR misses 643system.cpu.l2cache.overall_mshr_misses::total 30419 # number of overall MSHR misses 644system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38046308 # number of ReadReq MSHR miss cycles 645system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15112341 # number of ReadReq MSHR miss cycles 646system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53158649 # number of ReadReq MSHR miss cycles 647system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 648system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 649system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 863152212 # number of ReadExReq MSHR miss cycles 650system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 863152212 # number of ReadExReq MSHR miss cycles 651system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38046308 # number of demand (read+write) MSHR miss cycles 652system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 878264553 # number of demand (read+write) MSHR miss cycles 653system.cpu.l2cache.demand_mshr_miss_latency::total 916310861 # number of demand (read+write) MSHR miss cycles 654system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38046308 # number of overall MSHR miss cycles 655system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 878264553 # number of overall MSHR miss cycles 656system.cpu.l2cache.overall_mshr_miss_latency::total 916310861 # number of overall MSHR miss cycles 657system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for ReadReq accesses 658system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000204 # mshr miss rate for ReadReq accesses 659system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000711 # mshr miss rate for ReadReq accesses 660system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 661system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352541 # mshr miss rate for ReadExReq accesses 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352541 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for demand accesses 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014164 # mshr miss rate for demand accesses 666system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 667system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for overall accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014164 # mshr miss rate for overall accesses 669system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses 670system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37595.166008 # average ReadReq mshr miss latency 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.058968 # average ReadReq mshr miss latency 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37462.050035 # average ReadReq mshr miss latency 673system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 674system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29763.869379 # average ReadExReq mshr miss latency 676system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.869379 # average ReadExReq mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37595.166008 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29865.833067 # average overall mshr miss latency 679system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30122.977777 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37595.166008 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29865.833067 # average overall mshr miss latency 682system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30122.977777 # average overall mshr miss latency 683system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 684system.cpu.dcache.replacements 2072079 # number of replacements 685system.cpu.dcache.tagsinuse 4072.467231 # Cycle average of tags in use 686system.cpu.dcache.total_refs 71962219 # Total number of references to valid blocks. 687system.cpu.dcache.sampled_refs 2076175 # Sample count of references to valid blocks. 688system.cpu.dcache.avg_refs 34.660960 # Average number of references to valid blocks. 689system.cpu.dcache.warmup_cycle 21183795000 # Cycle when the warmup percentage was hit. 690system.cpu.dcache.occ_blocks::cpu.data 4072.467231 # Average occupied blocks per requestor 691system.cpu.dcache.occ_percent::cpu.data 0.994255 # Average percentage of cache occupancy 692system.cpu.dcache.occ_percent::total 0.994255 # Average percentage of cache occupancy 693system.cpu.dcache.ReadReq_hits::cpu.data 40620741 # number of ReadReq hits 694system.cpu.dcache.ReadReq_hits::total 40620741 # number of ReadReq hits 695system.cpu.dcache.WriteReq_hits::cpu.data 31341471 # number of WriteReq hits 696system.cpu.dcache.WriteReq_hits::total 31341471 # number of WriteReq hits 697system.cpu.dcache.demand_hits::cpu.data 71962212 # number of demand (read+write) hits 698system.cpu.dcache.demand_hits::total 71962212 # number of demand (read+write) hits 699system.cpu.dcache.overall_hits::cpu.data 71962212 # number of overall hits 700system.cpu.dcache.overall_hits::total 71962212 # number of overall hits 701system.cpu.dcache.ReadReq_misses::cpu.data 2625931 # number of ReadReq misses 702system.cpu.dcache.ReadReq_misses::total 2625931 # number of ReadReq misses 703system.cpu.dcache.WriteReq_misses::cpu.data 98281 # number of WriteReq misses 704system.cpu.dcache.WriteReq_misses::total 98281 # number of WriteReq misses 705system.cpu.dcache.demand_misses::cpu.data 2724212 # number of demand (read+write) misses 706system.cpu.dcache.demand_misses::total 2724212 # number of demand (read+write) misses 707system.cpu.dcache.overall_misses::cpu.data 2724212 # number of overall misses 708system.cpu.dcache.overall_misses::total 2724212 # number of overall misses 709system.cpu.dcache.ReadReq_miss_latency::cpu.data 31328626500 # number of ReadReq miss cycles 710system.cpu.dcache.ReadReq_miss_latency::total 31328626500 # number of ReadReq miss cycles 711system.cpu.dcache.WriteReq_miss_latency::cpu.data 2110180998 # number of WriteReq miss cycles 712system.cpu.dcache.WriteReq_miss_latency::total 2110180998 # number of WriteReq miss cycles 713system.cpu.dcache.demand_miss_latency::cpu.data 33438807498 # number of demand (read+write) miss cycles 714system.cpu.dcache.demand_miss_latency::total 33438807498 # number of demand (read+write) miss cycles 715system.cpu.dcache.overall_miss_latency::cpu.data 33438807498 # number of overall miss cycles 716system.cpu.dcache.overall_miss_latency::total 33438807498 # number of overall miss cycles 717system.cpu.dcache.ReadReq_accesses::cpu.data 43246672 # number of ReadReq accesses(hits+misses) 718system.cpu.dcache.ReadReq_accesses::total 43246672 # number of ReadReq accesses(hits+misses) 719system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 720system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 721system.cpu.dcache.demand_accesses::cpu.data 74686424 # number of demand (read+write) accesses 722system.cpu.dcache.demand_accesses::total 74686424 # number of demand (read+write) accesses 723system.cpu.dcache.overall_accesses::cpu.data 74686424 # number of overall (read+write) accesses 724system.cpu.dcache.overall_accesses::total 74686424 # number of overall (read+write) accesses 725system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060720 # miss rate for ReadReq accesses 726system.cpu.dcache.ReadReq_miss_rate::total 0.060720 # miss rate for ReadReq accesses 727system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 728system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses 729system.cpu.dcache.demand_miss_rate::cpu.data 0.036475 # miss rate for demand accesses 730system.cpu.dcache.demand_miss_rate::total 0.036475 # miss rate for demand accesses 731system.cpu.dcache.overall_miss_rate::cpu.data 0.036475 # miss rate for overall accesses 732system.cpu.dcache.overall_miss_rate::total 0.036475 # miss rate for overall accesses 733system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.483512 # average ReadReq miss latency 734system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.483512 # average ReadReq miss latency 735system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21470.894659 # average WriteReq miss latency 736system.cpu.dcache.WriteReq_avg_miss_latency::total 21470.894659 # average WriteReq miss latency 737system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency 738system.cpu.dcache.demand_avg_miss_latency::total 12274.671537 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency 740system.cpu.dcache.overall_avg_miss_latency::total 12274.671537 # average overall miss latency 741system.cpu.dcache.blocked_cycles::no_mshrs 32091 # number of cycles access was blocked 742system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.dcache.blocked::no_mshrs 9458 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.393001 # average number of cycles each access was blocked 746system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.dcache.fast_writes 0 # number of fast writes performed 748system.cpu.dcache.cache_copies 0 # number of cache copies performed 749system.cpu.dcache.writebacks::writebacks 2066502 # number of writebacks 750system.cpu.dcache.writebacks::total 2066502 # number of writebacks 751system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631907 # number of ReadReq MSHR hits 752system.cpu.dcache.ReadReq_mshr_hits::total 631907 # number of ReadReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16126 # number of WriteReq MSHR hits 754system.cpu.dcache.WriteReq_mshr_hits::total 16126 # number of WriteReq MSHR hits 755system.cpu.dcache.demand_mshr_hits::cpu.data 648033 # number of demand (read+write) MSHR hits 756system.cpu.dcache.demand_mshr_hits::total 648033 # number of demand (read+write) MSHR hits 757system.cpu.dcache.overall_mshr_hits::cpu.data 648033 # number of overall MSHR hits 758system.cpu.dcache.overall_mshr_hits::total 648033 # number of overall MSHR hits 759system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994024 # number of ReadReq MSHR misses 760system.cpu.dcache.ReadReq_mshr_misses::total 1994024 # number of ReadReq MSHR misses 761system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82155 # number of WriteReq MSHR misses 762system.cpu.dcache.WriteReq_mshr_misses::total 82155 # number of WriteReq MSHR misses 763system.cpu.dcache.demand_mshr_misses::cpu.data 2076179 # number of demand (read+write) MSHR misses 764system.cpu.dcache.demand_mshr_misses::total 2076179 # number of demand (read+write) MSHR misses 765system.cpu.dcache.overall_mshr_misses::cpu.data 2076179 # number of overall MSHR misses 766system.cpu.dcache.overall_mshr_misses::total 2076179 # number of overall MSHR misses 767system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982252000 # number of ReadReq MSHR miss cycles 768system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982252000 # number of ReadReq MSHR miss cycles 769system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1835038498 # number of WriteReq MSHR miss cycles 770system.cpu.dcache.WriteReq_mshr_miss_latency::total 1835038498 # number of WriteReq MSHR miss cycles 771system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23817290498 # number of demand (read+write) MSHR miss cycles 772system.cpu.dcache.demand_mshr_miss_latency::total 23817290498 # number of demand (read+write) MSHR miss cycles 773system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817290498 # number of overall MSHR miss cycles 774system.cpu.dcache.overall_mshr_miss_latency::total 23817290498 # number of overall MSHR miss cycles 775system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046108 # mshr miss rate for ReadReq accesses 776system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046108 # mshr miss rate for ReadReq accesses 777system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses 778system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses 779system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for demand accesses 780system.cpu.dcache.demand_mshr_miss_rate::total 0.027799 # mshr miss rate for demand accesses 781system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for overall accesses 782system.cpu.dcache.overall_mshr_miss_rate::total 0.027799 # mshr miss rate for overall accesses 783system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.065909 # average ReadReq mshr miss latency 784system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.065909 # average ReadReq mshr miss latency 785system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22336.297219 # average WriteReq mshr miss latency 786system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22336.297219 # average WriteReq mshr miss latency 787system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency 788system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency 789system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency 790system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency 791system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 792 793---------- End Simulation Statistics ---------- 794