stats.txt revision 8807:35e77c938919
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.070098 # Number of seconds simulated 4sim_ticks 70097938500 # Number of ticks simulated 5final_tick 70097938500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 110386 # Simulator instruction rate (inst/s) 8host_tick_rate 27814669 # Simulator tick rate (ticks/s) 9host_mem_usage 379416 # Number of bytes of host memory used 10host_seconds 2520.18 # Real time elapsed on the host 11sim_insts 278192519 # Number of instructions simulated 12system.physmem.bytes_read 3896128 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 65152 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 892416 # Number of bytes written to this memory 15system.physmem.num_reads 60877 # Number of read requests responded to by this memory 16system.physmem.num_writes 13944 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 55581207 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 929442 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 12730988 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 68312194 # Total bandwidth to/from this memory (bytes/s) 22system.cpu.workload.num_syscalls 444 # Number of system calls 23system.cpu.numCycles 140195878 # number of cpu cycles simulated 24system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 25system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 26system.cpu.BPredUnit.lookups 37928407 # Number of BP lookups 27system.cpu.BPredUnit.condPredicted 37928407 # Number of conditional branches predicted 28system.cpu.BPredUnit.condIncorrect 1334678 # Number of conditional branches incorrect 29system.cpu.BPredUnit.BTBLookups 33548417 # Number of BTB lookups 30system.cpu.BPredUnit.BTBHits 33040245 # Number of BTB hits 31system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 32system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 33system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 34system.cpu.fetch.icacheStallCycles 29060209 # Number of cycles fetch is stalled on an Icache miss 35system.cpu.fetch.Insts 203598338 # Number of instructions fetch has processed 36system.cpu.fetch.Branches 37928407 # Number of branches that fetch encountered 37system.cpu.fetch.predictedBranches 33040245 # Number of branches that fetch has predicted taken 38system.cpu.fetch.Cycles 63274026 # Number of cycles fetch has run and was not squashing or blocked 39system.cpu.fetch.SquashCycles 10249926 # Number of cycles fetch has spent squashing 40system.cpu.fetch.BlockedCycles 38189577 # Number of cycles fetch has spent blocked 41system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 42system.cpu.fetch.PendingTrapStallCycles 77 # Number of stall cycles due to pending traps 43system.cpu.fetch.CacheLines 28245503 # Number of cache lines fetched 44system.cpu.fetch.IcacheSquashes 214193 # Number of outstanding Icache misses that were squashed 45system.cpu.fetch.rateDist::samples 139407654 # Number of instructions fetched each cycle (Total) 46system.cpu.fetch.rateDist::mean 2.577879 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::stdev 3.292775 # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::0 78584615 56.37% 56.37% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::1 3556242 2.55% 58.92% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::2 2802198 2.01% 60.93% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::3 4529245 3.25% 64.18% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::4 6913485 4.96% 69.14% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::5 5169478 3.71% 72.85% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::6 7697084 5.52% 78.37% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::7 4298531 3.08% 81.45% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::8 25856776 18.55% 100.00% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::total 139407654 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.branchRate 0.270539 # Number of branch fetches per cycle 63system.cpu.fetch.rate 1.452242 # Number of inst fetches per cycle 64system.cpu.decode.IdleCycles 41988791 # Number of cycles decode is idle 65system.cpu.decode.BlockedCycles 28417024 # Number of cycles decode is blocked 66system.cpu.decode.RunCycles 52030953 # Number of cycles decode is running 67system.cpu.decode.UnblockCycles 8087139 # Number of cycles decode is unblocking 68system.cpu.decode.SquashCycles 8883747 # Number of cycles decode is squashing 69system.cpu.decode.DecodedInsts 355040007 # Number of instructions handled by decode 70system.cpu.rename.SquashCycles 8883747 # Number of cycles rename is squashing 71system.cpu.rename.IdleCycles 48483810 # Number of cycles rename is idle 72system.cpu.rename.BlockCycles 4810408 # Number of cycles rename is blocking 73system.cpu.rename.serializeStallCycles 9079 # count of cycles rename stalled for serializing inst 74system.cpu.rename.RunCycles 52929871 # Number of cycles rename is running 75system.cpu.rename.UnblockCycles 24290739 # Number of cycles rename is unblocking 76system.cpu.rename.RenamedInsts 350051728 # Number of instructions processed by rename 77system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full 78system.cpu.rename.IQFullEvents 103496 # Number of times rename has blocked due to IQ full 79system.cpu.rename.LSQFullEvents 20366187 # Number of times rename has blocked due to LSQ full 80system.cpu.rename.RenamedOperands 314282471 # Number of destination operands rename has renamed 81system.cpu.rename.RenameLookups 860902327 # Number of register rename lookups that rename has made 82system.cpu.rename.int_rename_lookups 860897388 # Number of integer rename lookups 83system.cpu.rename.fp_rename_lookups 4939 # Number of floating rename lookups 84system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed 85system.cpu.rename.UndoneMaps 65938279 # Number of HB maps that are undone due to squashing 86system.cpu.rename.serializingInsts 478 # count of serializing insts renamed 87system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed 88system.cpu.rename.skidInsts 57634584 # count of insts added to the skid buffer 89system.cpu.memDep0.insertedLoads 112617334 # Number of loads inserted to the mem dependence unit. 90system.cpu.memDep0.insertedStores 37601195 # Number of stores inserted to the mem dependence unit. 91system.cpu.memDep0.conflictingLoads 47838969 # Number of conflicting loads. 92system.cpu.memDep0.conflictingStores 8379867 # Number of conflicting stores. 93system.cpu.iq.iqInstsAdded 343415839 # Number of instructions added to the IQ (excludes non-spec) 94system.cpu.iq.iqNonSpecInstsAdded 2328 # Number of non-speculative instructions added to the IQ 95system.cpu.iq.iqInstsIssued 316096096 # Number of instructions issued 96system.cpu.iq.iqSquashedInstsIssued 78808 # Number of squashed instructions issued 97system.cpu.iq.iqSquashedInstsExamined 65029362 # Number of squashed instructions iterated over during squash; mainly for profiling 98system.cpu.iq.iqSquashedOperandsExamined 92942153 # Number of squashed operands that are examined and possibly removed from graph 99system.cpu.iq.iqSquashedNonSpecRemoved 1882 # Number of squashed non-spec instructions that were removed 100system.cpu.iq.issued_per_cycle::samples 139407654 # Number of insts issued each cycle 101system.cpu.iq.issued_per_cycle::mean 2.267423 # Number of insts issued each cycle 102system.cpu.iq.issued_per_cycle::stdev 1.745481 # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::0 32098361 23.02% 23.02% # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::1 17868067 12.82% 35.84% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::2 24417482 17.52% 53.36% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::3 32093883 23.02% 76.38% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::4 18421218 13.21% 89.59% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::5 9527374 6.83% 96.43% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::6 3128162 2.24% 98.67% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::7 1804154 1.29% 99.96% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::8 48953 0.04% 100.00% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::total 139407654 # Number of insts issued each cycle 117system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 118system.cpu.iq.fu_full::IntAlu 25731 1.31% 1.31% # attempts to use FU when none available 119system.cpu.iq.fu_full::IntMult 0 0.00% 1.31% # attempts to use FU when none available 120system.cpu.iq.fu_full::IntDiv 0 0.00% 1.31% # attempts to use FU when none available 121system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.31% # attempts to use FU when none available 122system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.31% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.31% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatMult 0 0.00% 1.31% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.31% # attempts to use FU when none available 126system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.31% # attempts to use FU when none available 127system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.31% # attempts to use FU when none available 128system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.31% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.31% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.31% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.31% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.31% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdMult 0 0.00% 1.31% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.31% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdShift 0 0.00% 1.31% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.31% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.31% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.31% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.31% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.31% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.31% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.31% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.31% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.31% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.31% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.31% # attempts to use FU when none available 147system.cpu.iq.fu_full::MemRead 1863505 95.00% 96.31% # attempts to use FU when none available 148system.cpu.iq.fu_full::MemWrite 72393 3.69% 100.00% # attempts to use FU when none available 149system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 150system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 151system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued 152system.cpu.iq.FU_type_0::IntAlu 180196286 57.01% 57.01% # Type of FU issued 153system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued 154system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued 155system.cpu.iq.FU_type_0::FloatAdd 342 0.00% 57.01% # Type of FU issued 156system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued 160system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued 161system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued 162system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued 181system.cpu.iq.FU_type_0::MemRead 101438567 32.09% 89.10% # Type of FU issued 182system.cpu.iq.FU_type_0::MemWrite 34444190 10.90% 100.00% # Type of FU issued 183system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 184system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 185system.cpu.iq.FU_type_0::total 316096096 # Type of FU issued 186system.cpu.iq.rate 2.254675 # Inst issue rate 187system.cpu.iq.fu_busy_cnt 1961629 # FU busy when requested 188system.cpu.iq.fu_busy_rate 0.006206 # FU busy rate (busy events/executed inst) 189system.cpu.iq.int_inst_queue_reads 773638738 # Number of integer instruction queue reads 190system.cpu.iq.int_inst_queue_writes 408477370 # Number of integer instruction queue writes 191system.cpu.iq.int_inst_queue_wakeup_accesses 312370165 # Number of integer instruction queue wakeup accesses 192system.cpu.iq.fp_inst_queue_reads 1545 # Number of floating instruction queue reads 193system.cpu.iq.fp_inst_queue_writes 3169 # Number of floating instruction queue writes 194system.cpu.iq.fp_inst_queue_wakeup_accesses 656 # Number of floating instruction queue wakeup accesses 195system.cpu.iq.int_alu_accesses 318040246 # Number of integer alu accesses 196system.cpu.iq.fp_alu_accesses 768 # Number of floating point alu accesses 197system.cpu.iew.lsq.thread0.forwLoads 52318776 # Number of loads that had data forwarded from stores 198system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 199system.cpu.iew.lsq.thread0.squashedLoads 21837946 # Number of loads squashed 200system.cpu.iew.lsq.thread0.ignoredResponses 139826 # Number of memory responses ignored because the instruction is squashed 201system.cpu.iew.lsq.thread0.memOrderViolation 33737 # Number of memory ordering violations 202system.cpu.iew.lsq.thread0.squashedStores 6161444 # Number of stores squashed 203system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 204system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 205system.cpu.iew.lsq.thread0.rescheduledLoads 3258 # Number of loads that were rescheduled 206system.cpu.iew.lsq.thread0.cacheBlocked 3821 # Number of times an access to memory failed due to the cache being blocked 207system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 208system.cpu.iew.iewSquashCycles 8883747 # Number of cycles IEW is squashing 209system.cpu.iew.iewBlockCycles 984872 # Number of cycles IEW is blocking 210system.cpu.iew.iewUnblockCycles 88741 # Number of cycles IEW is unblocking 211system.cpu.iew.iewDispatchedInsts 343418167 # Number of instructions dispatched to IQ 212system.cpu.iew.iewDispSquashedInsts 39651 # Number of squashed instructions skipped by dispatch 213system.cpu.iew.iewDispLoadInsts 112617334 # Number of dispatched load instructions 214system.cpu.iew.iewDispStoreInsts 37601195 # Number of dispatched store instructions 215system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions 216system.cpu.iew.iewIQFullEvents 1341 # Number of times the IQ has become full, causing a stall 217system.cpu.iew.iewLSQFullEvents 42673 # Number of times the LSQ has become full, causing a stall 218system.cpu.iew.memOrderViolationEvents 33737 # Number of memory order violations 219system.cpu.iew.predictedTakenIncorrect 1237180 # Number of branches that were predicted taken incorrectly 220system.cpu.iew.predictedNotTakenIncorrect 215729 # Number of branches that were predicted not taken incorrectly 221system.cpu.iew.branchMispredicts 1452909 # Number of branch mispredicts detected at execute 222system.cpu.iew.iewExecutedInsts 313907375 # Number of executed instructions 223system.cpu.iew.iewExecLoadInsts 100815222 # Number of load instructions executed 224system.cpu.iew.iewExecSquashedInsts 2188721 # Number of squashed instructions skipped in execute 225system.cpu.iew.exec_swp 0 # number of swp insts executed 226system.cpu.iew.exec_nop 0 # number of nop insts executed 227system.cpu.iew.exec_refs 134855811 # number of memory reference insts executed 228system.cpu.iew.exec_branches 31730666 # Number of branches executed 229system.cpu.iew.exec_stores 34040589 # Number of stores executed 230system.cpu.iew.exec_rate 2.239063 # Inst execution rate 231system.cpu.iew.wb_sent 313087219 # cumulative count of insts sent to commit 232system.cpu.iew.wb_count 312370821 # cumulative count of insts written-back 233system.cpu.iew.wb_producers 231825034 # num instructions producing a value 234system.cpu.iew.wb_consumers 317282535 # num instructions consuming a value 235system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 236system.cpu.iew.wb_rate 2.228103 # insts written-back per cycle 237system.cpu.iew.wb_fanout 0.730658 # average fanout of values written-back 238system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 239system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions 240system.cpu.commit.commitSquashedInsts 65229233 # The number of squashed insts skipped by commit 241system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards 242system.cpu.commit.branchMispredicts 1334689 # The number of times a branch was mispredicted 243system.cpu.commit.committed_per_cycle::samples 130523907 # Number of insts commited each cycle 244system.cpu.commit.committed_per_cycle::mean 2.131353 # Number of insts commited each cycle 245system.cpu.commit.committed_per_cycle::stdev 2.650695 # Number of insts commited each cycle 246system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::0 49374885 37.83% 37.83% # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::1 24990571 19.15% 56.97% # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::2 17165469 13.15% 70.13% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::3 12454302 9.54% 79.67% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::4 3472302 2.66% 82.33% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::5 3453203 2.65% 84.97% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::6 2713996 2.08% 87.05% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::7 1124527 0.86% 87.91% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::8 15774652 12.09% 100.00% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::total 130523907 # Number of insts commited each cycle 260system.cpu.commit.count 278192519 # Number of instructions committed 261system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 262system.cpu.commit.refs 122219139 # Number of memory references committed 263system.cpu.commit.loads 90779388 # Number of loads committed 264system.cpu.commit.membars 0 # Number of memory barriers committed 265system.cpu.commit.branches 29309710 # Number of branches committed 266system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 267system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. 268system.cpu.commit.function_calls 0 # Number of function calls committed. 269system.cpu.commit.bw_lim_events 15774652 # number cycles where commit BW limit reached 270system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 271system.cpu.rob.rob_reads 458171007 # The number of ROB reads 272system.cpu.rob.rob_writes 695745355 # The number of ROB writes 273system.cpu.timesIdled 23904 # Number of times that the entire CPU went into an idle state and unscheduled itself 274system.cpu.idleCycles 788224 # Total number of cycles that the CPU has spent unscheduled due to idling 275system.cpu.committedInsts 278192519 # Number of Instructions Simulated 276system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated 277system.cpu.cpi 0.503953 # CPI: Cycles Per Instruction 278system.cpu.cpi_total 0.503953 # CPI: Total CPI of All Threads 279system.cpu.ipc 1.984313 # IPC: Instructions Per Cycle 280system.cpu.ipc_total 1.984313 # IPC: Total IPC of All Threads 281system.cpu.int_regfile_reads 554439426 # number of integer regfile reads 282system.cpu.int_regfile_writes 279882097 # number of integer regfile writes 283system.cpu.fp_regfile_reads 791 # number of floating regfile reads 284system.cpu.fp_regfile_writes 562 # number of floating regfile writes 285system.cpu.misc_regfile_reads 200975844 # number of misc regfile reads 286system.cpu.icache.replacements 62 # number of replacements 287system.cpu.icache.tagsinuse 823.089414 # Cycle average of tags in use 288system.cpu.icache.total_refs 28244206 # Total number of references to valid blocks. 289system.cpu.icache.sampled_refs 1023 # Sample count of references to valid blocks. 290system.cpu.icache.avg_refs 27609.194526 # Average number of references to valid blocks. 291system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 292system.cpu.icache.occ_blocks::0 823.089414 # Average occupied blocks per context 293system.cpu.icache.occ_percent::0 0.401899 # Average percentage of cache occupancy 294system.cpu.icache.ReadReq_hits 28244206 # number of ReadReq hits 295system.cpu.icache.demand_hits 28244206 # number of demand (read+write) hits 296system.cpu.icache.overall_hits 28244206 # number of overall hits 297system.cpu.icache.ReadReq_misses 1297 # number of ReadReq misses 298system.cpu.icache.demand_misses 1297 # number of demand (read+write) misses 299system.cpu.icache.overall_misses 1297 # number of overall misses 300system.cpu.icache.ReadReq_miss_latency 46884000 # number of ReadReq miss cycles 301system.cpu.icache.demand_miss_latency 46884000 # number of demand (read+write) miss cycles 302system.cpu.icache.overall_miss_latency 46884000 # number of overall miss cycles 303system.cpu.icache.ReadReq_accesses 28245503 # number of ReadReq accesses(hits+misses) 304system.cpu.icache.demand_accesses 28245503 # number of demand (read+write) accesses 305system.cpu.icache.overall_accesses 28245503 # number of overall (read+write) accesses 306system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses 307system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses 308system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses 309system.cpu.icache.ReadReq_avg_miss_latency 36148.033924 # average ReadReq miss latency 310system.cpu.icache.demand_avg_miss_latency 36148.033924 # average overall miss latency 311system.cpu.icache.overall_avg_miss_latency 36148.033924 # average overall miss latency 312system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 313system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 314system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 315system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 316system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 317system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 318system.cpu.icache.fast_writes 0 # number of fast writes performed 319system.cpu.icache.cache_copies 0 # number of cache copies performed 320system.cpu.icache.writebacks 0 # number of writebacks 321system.cpu.icache.ReadReq_mshr_hits 273 # number of ReadReq MSHR hits 322system.cpu.icache.demand_mshr_hits 273 # number of demand (read+write) MSHR hits 323system.cpu.icache.overall_mshr_hits 273 # number of overall MSHR hits 324system.cpu.icache.ReadReq_mshr_misses 1024 # number of ReadReq MSHR misses 325system.cpu.icache.demand_mshr_misses 1024 # number of demand (read+write) MSHR misses 326system.cpu.icache.overall_mshr_misses 1024 # number of overall MSHR misses 327system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 328system.cpu.icache.ReadReq_mshr_miss_latency 36044000 # number of ReadReq MSHR miss cycles 329system.cpu.icache.demand_mshr_miss_latency 36044000 # number of demand (read+write) MSHR miss cycles 330system.cpu.icache.overall_mshr_miss_latency 36044000 # number of overall MSHR miss cycles 331system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 332system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses 333system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses 334system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses 335system.cpu.icache.ReadReq_avg_mshr_miss_latency 35199.218750 # average ReadReq mshr miss latency 336system.cpu.icache.demand_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency 337system.cpu.icache.overall_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency 338system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 339system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 340system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 341system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 342system.cpu.dcache.replacements 2072801 # number of replacements 343system.cpu.dcache.tagsinuse 4073.016957 # Cycle average of tags in use 344system.cpu.dcache.total_refs 77487718 # Total number of references to valid blocks. 345system.cpu.dcache.sampled_refs 2076897 # Sample count of references to valid blocks. 346system.cpu.dcache.avg_refs 37.309370 # Average number of references to valid blocks. 347system.cpu.dcache.warmup_cycle 23652058000 # Cycle when the warmup percentage was hit. 348system.cpu.dcache.occ_blocks::0 4073.016957 # Average occupied blocks per context 349system.cpu.dcache.occ_percent::0 0.994389 # Average percentage of cache occupancy 350system.cpu.dcache.ReadReq_hits 46133976 # number of ReadReq hits 351system.cpu.dcache.WriteReq_hits 31353733 # number of WriteReq hits 352system.cpu.dcache.demand_hits 77487709 # number of demand (read+write) hits 353system.cpu.dcache.overall_hits 77487709 # number of overall hits 354system.cpu.dcache.ReadReq_misses 2288597 # number of ReadReq misses 355system.cpu.dcache.WriteReq_misses 86018 # number of WriteReq misses 356system.cpu.dcache.demand_misses 2374615 # number of demand (read+write) misses 357system.cpu.dcache.overall_misses 2374615 # number of overall misses 358system.cpu.dcache.ReadReq_miss_latency 13760644500 # number of ReadReq miss cycles 359system.cpu.dcache.WriteReq_miss_latency 1501321288 # number of WriteReq miss cycles 360system.cpu.dcache.demand_miss_latency 15261965788 # number of demand (read+write) miss cycles 361system.cpu.dcache.overall_miss_latency 15261965788 # number of overall miss cycles 362system.cpu.dcache.ReadReq_accesses 48422573 # number of ReadReq accesses(hits+misses) 363system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) 364system.cpu.dcache.demand_accesses 79862324 # number of demand (read+write) accesses 365system.cpu.dcache.overall_accesses 79862324 # number of overall (read+write) accesses 366system.cpu.dcache.ReadReq_miss_rate 0.047263 # miss rate for ReadReq accesses 367system.cpu.dcache.WriteReq_miss_rate 0.002736 # miss rate for WriteReq accesses 368system.cpu.dcache.demand_miss_rate 0.029734 # miss rate for demand accesses 369system.cpu.dcache.overall_miss_rate 0.029734 # miss rate for overall accesses 370system.cpu.dcache.ReadReq_avg_miss_latency 6012.698828 # average ReadReq miss latency 371system.cpu.dcache.WriteReq_avg_miss_latency 17453.571206 # average WriteReq miss latency 372system.cpu.dcache.demand_avg_miss_latency 6427.132730 # average overall miss latency 373system.cpu.dcache.overall_avg_miss_latency 6427.132730 # average overall miss latency 374system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 377system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 378system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 379system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 380system.cpu.dcache.fast_writes 0 # number of fast writes performed 381system.cpu.dcache.cache_copies 0 # number of cache copies performed 382system.cpu.dcache.writebacks 1880524 # number of writebacks 383system.cpu.dcache.ReadReq_mshr_hits 293812 # number of ReadReq MSHR hits 384system.cpu.dcache.WriteReq_mshr_hits 3902 # number of WriteReq MSHR hits 385system.cpu.dcache.demand_mshr_hits 297714 # number of demand (read+write) MSHR hits 386system.cpu.dcache.overall_mshr_hits 297714 # number of overall MSHR hits 387system.cpu.dcache.ReadReq_mshr_misses 1994785 # number of ReadReq MSHR misses 388system.cpu.dcache.WriteReq_mshr_misses 82116 # number of WriteReq MSHR misses 389system.cpu.dcache.demand_mshr_misses 2076901 # number of demand (read+write) MSHR misses 390system.cpu.dcache.overall_mshr_misses 2076901 # number of overall MSHR misses 391system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 392system.cpu.dcache.ReadReq_mshr_miss_latency 5560782500 # number of ReadReq MSHR miss cycles 393system.cpu.dcache.WriteReq_mshr_miss_latency 1157739288 # number of WriteReq MSHR miss cycles 394system.cpu.dcache.demand_mshr_miss_latency 6718521788 # number of demand (read+write) MSHR miss cycles 395system.cpu.dcache.overall_mshr_miss_latency 6718521788 # number of overall MSHR miss cycles 396system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 397system.cpu.dcache.ReadReq_mshr_miss_rate 0.041195 # mshr miss rate for ReadReq accesses 398system.cpu.dcache.WriteReq_mshr_miss_rate 0.002612 # mshr miss rate for WriteReq accesses 399system.cpu.dcache.demand_mshr_miss_rate 0.026006 # mshr miss rate for demand accesses 400system.cpu.dcache.overall_mshr_miss_rate 0.026006 # mshr miss rate for overall accesses 401system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2787.660074 # average ReadReq mshr miss latency 402system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14098.827123 # average WriteReq mshr miss latency 403system.cpu.dcache.demand_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency 404system.cpu.dcache.overall_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency 405system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 406system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 407system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 408system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 409system.cpu.l2cache.replacements 33248 # number of replacements 410system.cpu.l2cache.tagsinuse 18948.902283 # Cycle average of tags in use 411system.cpu.l2cache.total_refs 3764067 # Total number of references to valid blocks. 412system.cpu.l2cache.sampled_refs 61254 # Sample count of references to valid blocks. 413system.cpu.l2cache.avg_refs 61.450142 # Average number of references to valid blocks. 414system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 415system.cpu.l2cache.occ_blocks::0 6031.150094 # Average occupied blocks per context 416system.cpu.l2cache.occ_blocks::1 12917.752189 # Average occupied blocks per context 417system.cpu.l2cache.occ_percent::0 0.184056 # Average percentage of cache occupancy 418system.cpu.l2cache.occ_percent::1 0.394219 # Average percentage of cache occupancy 419system.cpu.l2cache.ReadReq_hits 1964318 # number of ReadReq hits 420system.cpu.l2cache.Writeback_hits 1880524 # number of Writeback hits 421system.cpu.l2cache.ReadExReq_hits 52728 # number of ReadExReq hits 422system.cpu.l2cache.demand_hits 2017046 # number of demand (read+write) hits 423system.cpu.l2cache.overall_hits 2017046 # number of overall hits 424system.cpu.l2cache.ReadReq_misses 31362 # number of ReadReq misses 425system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses 426system.cpu.l2cache.ReadExReq_misses 29515 # number of ReadExReq misses 427system.cpu.l2cache.demand_misses 60877 # number of demand (read+write) misses 428system.cpu.l2cache.overall_misses 60877 # number of overall misses 429system.cpu.l2cache.ReadReq_miss_latency 1071112000 # number of ReadReq miss cycles 430system.cpu.l2cache.ReadExReq_miss_latency 1006258500 # number of ReadExReq miss cycles 431system.cpu.l2cache.demand_miss_latency 2077370500 # number of demand (read+write) miss cycles 432system.cpu.l2cache.overall_miss_latency 2077370500 # number of overall miss cycles 433system.cpu.l2cache.ReadReq_accesses 1995680 # number of ReadReq accesses(hits+misses) 434system.cpu.l2cache.Writeback_accesses 1880524 # number of Writeback accesses(hits+misses) 435system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) 436system.cpu.l2cache.ReadExReq_accesses 82243 # number of ReadExReq accesses(hits+misses) 437system.cpu.l2cache.demand_accesses 2077923 # number of demand (read+write) accesses 438system.cpu.l2cache.overall_accesses 2077923 # number of overall (read+write) accesses 439system.cpu.l2cache.ReadReq_miss_rate 0.015715 # miss rate for ReadReq accesses 440system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 441system.cpu.l2cache.ReadExReq_miss_rate 0.358876 # miss rate for ReadExReq accesses 442system.cpu.l2cache.demand_miss_rate 0.029297 # miss rate for demand accesses 443system.cpu.l2cache.overall_miss_rate 0.029297 # miss rate for overall accesses 444system.cpu.l2cache.ReadReq_avg_miss_latency 34153.179006 # average ReadReq miss latency 445system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.122141 # average ReadExReq miss latency 446system.cpu.l2cache.demand_avg_miss_latency 34124.061632 # average overall miss latency 447system.cpu.l2cache.overall_avg_miss_latency 34124.061632 # average overall miss latency 448system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 453system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 454system.cpu.l2cache.fast_writes 0 # number of fast writes performed 455system.cpu.l2cache.cache_copies 0 # number of cache copies performed 456system.cpu.l2cache.writebacks 13944 # number of writebacks 457system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 458system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 459system.cpu.l2cache.ReadReq_mshr_misses 31362 # number of ReadReq MSHR misses 460system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses 461system.cpu.l2cache.ReadExReq_mshr_misses 29515 # number of ReadExReq MSHR misses 462system.cpu.l2cache.demand_mshr_misses 60877 # number of demand (read+write) MSHR misses 463system.cpu.l2cache.overall_mshr_misses 60877 # number of overall MSHR misses 464system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 465system.cpu.l2cache.ReadReq_mshr_miss_latency 972890000 # number of ReadReq MSHR miss cycles 466system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles 467system.cpu.l2cache.ReadExReq_mshr_miss_latency 914988000 # number of ReadExReq MSHR miss cycles 468system.cpu.l2cache.demand_mshr_miss_latency 1887878000 # number of demand (read+write) MSHR miss cycles 469system.cpu.l2cache.overall_mshr_miss_latency 1887878000 # number of overall MSHR miss cycles 470system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 471system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015715 # mshr miss rate for ReadReq accesses 472system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 473system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358876 # mshr miss rate for ReadExReq accesses 474system.cpu.l2cache.demand_mshr_miss_rate 0.029297 # mshr miss rate for demand accesses 475system.cpu.l2cache.overall_mshr_miss_rate 0.029297 # mshr miss rate for overall accesses 476system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.299662 # average ReadReq mshr miss latency 477system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency 478system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.779265 # average ReadExReq mshr miss latency 479system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency 480system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency 481system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 482system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 483system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 484system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 485 486---------- End Simulation Statistics ---------- 487