stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.361489 # Number of seconds simulated 4sim_ticks 361488530000 # Number of ticks simulated 5final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 653861 # Simulator instruction rate (inst/s) 8host_op_rate 653888 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 969395755 # Simulator tick rate (ticks/s) 10host_mem_usage 365508 # Number of bytes of host memory used 11host_seconds 372.90 # Real time elapsed on the host 12sim_insts 243825150 # Number of instructions simulated 13sim_ops 243835265 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 998592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 2762444 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 1036 # Transaction distribution 32system.membus.trans_dist::ReadResp 1036 # Transaction distribution 33system.membus.trans_dist::ReadExReq 14567 # Transaction distribution 34system.membus.trans_dist::ReadExResp 14567 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 998592 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 43system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 45system.cpu.workload.num_syscalls 443 # Number of system calls 46system.cpu.numCycles 722977060 # number of cpu cycles simulated 47system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 48system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 49system.cpu.committedInsts 243825150 # Number of instructions committed 50system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed 51system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses 52system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses 53system.cpu.num_func_calls 4252956 # number of times a function call or return occured 54system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls 55system.cpu.num_int_insts 194726494 # number of integer instructions 56system.cpu.num_fp_insts 11630 # number of float instructions 57system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read 58system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written 59system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read 60system.cpu.num_fp_register_writes 90 # number of times the floating registers were written 61system.cpu.num_mem_refs 105711441 # number of memory refs 62system.cpu.num_load_insts 82803521 # Number of load instructions 63system.cpu.num_store_insts 22907920 # Number of store instructions 64system.cpu.num_idle_cycles 0 # Number of idle cycles 65system.cpu.num_busy_cycles 722977060 # Number of busy cycles 66system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 67system.cpu.idle_fraction 0 # Percentage of idle cycles 68system.cpu.icache.replacements 25 # number of replacements 69system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use 70system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. 71system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. 72system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. 73system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor 75system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy 76system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy 77system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits 78system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits 79system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits 80system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits 81system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits 82system.cpu.icache.overall_hits::total 244420617 # number of overall hits 83system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses 84system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses 85system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses 86system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses 87system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses 88system.cpu.icache.overall_misses::total 882 # number of overall misses 89system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles 90system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles 91system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles 92system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles 93system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles 94system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles 95system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) 96system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) 97system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses 98system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses 99system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses 100system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses 101system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 102system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 103system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 104system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 105system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 106system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 107system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency 108system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency 109system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 110system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency 111system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency 112system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency 113system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 116system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 117system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119system.cpu.icache.fast_writes 0 # number of fast writes performed 120system.cpu.icache.cache_copies 0 # number of cache copies performed 121system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses 122system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses 123system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses 124system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses 125system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses 126system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses 127system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles 128system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles 129system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles 130system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles 131system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles 132system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles 133system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 134system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 135system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 136system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 137system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 138system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 139system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency 140system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency 141system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 142system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 143system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency 144system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency 145system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 146system.cpu.l2cache.replacements 0 # number of replacements 147system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use 148system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. 149system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. 150system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. 151system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 152system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor 153system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor 154system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor 155system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy 156system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy 157system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy 158system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy 159system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 160system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits 161system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits 162system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits 163system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits 164system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits 165system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits 166system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 167system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits 168system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits 169system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 170system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits 171system.cpu.l2cache.overall_hits::total 924850 # number of overall hits 172system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses 173system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses 174system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses 175system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses 176system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses 177system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses 178system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses 179system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses 180system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses 181system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses 182system.cpu.l2cache.overall_misses::total 15603 # number of overall misses 183system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles 184system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles 185system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles 186system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles 187system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles 188system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles 189system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles 190system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles 191system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles 192system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles 193system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles 194system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) 195system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) 196system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) 197system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) 198system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) 199system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) 200system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) 201system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses 202system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses 203system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses 204system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses 205system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses 206system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses 207system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses 208system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses 209system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses 210system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses 211system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses 212system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses 213system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses 214system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses 215system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses 216system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses 217system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses 218system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 219system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 220system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 221system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 222system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 223system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 224system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 225system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 226system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 227system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 228system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 229system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 230system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 231system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 232system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 233system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 234system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 235system.cpu.l2cache.fast_writes 0 # number of fast writes performed 236system.cpu.l2cache.cache_copies 0 # number of cache copies performed 237system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses 238system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses 239system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses 240system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses 241system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses 242system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses 243system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses 244system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 245system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses 246system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses 247system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses 248system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles 249system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles 250system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles 251system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles 252system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles 253system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles 254system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles 255system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles 256system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles 257system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles 258system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles 259system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses 260system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses 261system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses 262system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses 263system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses 264system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses 265system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses 266system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses 267system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses 268system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses 269system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses 270system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 271system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 272system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 273system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 274system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 275system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 276system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 277system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 278system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 279system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 280system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 281system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 282system.cpu.dcache.replacements 935475 # number of replacements 283system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use 284system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. 285system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. 286system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. 287system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. 288system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor 289system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy 290system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy 291system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits 292system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits 293system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits 294system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits 295system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits 296system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits 297system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits 298system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits 299system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits 300system.cpu.dcache.overall_hits::total 104182817 # number of overall hits 301system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses 302system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses 303system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses 304system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses 305system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses 306system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses 307system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses 308system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses 309system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses 310system.cpu.dcache.overall_misses::total 939567 # number of overall misses 311system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles 312system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles 313system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles 314system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles 315system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles 316system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles 317system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles 318system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles 319system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles 320system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles 321system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) 322system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) 323system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) 324system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) 325system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) 326system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) 327system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses 328system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses 329system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses 330system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses 331system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses 332system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses 333system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses 334system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses 335system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses 336system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses 337system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses 338system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses 339system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses 340system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses 341system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency 342system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency 343system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency 344system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency 345system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency 346system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency 347system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 348system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency 349system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency 350system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency 351system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 352system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 353system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 354system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 355system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 356system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 357system.cpu.dcache.fast_writes 0 # number of fast writes performed 358system.cpu.dcache.cache_copies 0 # number of cache copies performed 359system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks 360system.cpu.dcache.writebacks::total 935266 # number of writebacks 361system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses 362system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses 363system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses 364system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses 365system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses 366system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses 367system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses 368system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses 369system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses 370system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses 371system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles 372system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles 373system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles 374system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles 375system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles 376system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles 377system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles 378system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles 379system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles 380system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles 381system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses 382system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses 383system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses 384system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses 385system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses 386system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses 387system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses 388system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses 389system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses 390system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses 391system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency 392system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency 393system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency 394system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency 395system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency 396system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency 397system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 398system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 399system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency 400system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency 401system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 402system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) 403system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution 404system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution 405system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution 406system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution 407system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution 408system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes) 409system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes) 410system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes) 411system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes) 412system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes) 413system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes) 414system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) 415system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 416system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) 417system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 418system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) 419system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 420system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) 421system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 422 423---------- End Simulation Statistics ---------- 424