stats.txt revision 9988:0b2e590c85be
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026911 # Number of seconds simulated 4sim_ticks 26911413000 # Number of ticks simulated 5final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 116759 # Simulator instruction rate (inst/s) 8host_op_rate 117598 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34685583 # Simulator tick rate (ticks/s) 10host_mem_usage 427272 # Number of bytes of host memory used 11host_seconds 775.87 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory 16system.physmem.bytes_read::total 993152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 15518 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 987 # Per bank write bursts 43system.physmem.perBankRdBursts::1 886 # Per bank write bursts 44system.physmem.perBankRdBursts::2 942 # Per bank write bursts 45system.physmem.perBankRdBursts::3 1028 # Per bank write bursts 46system.physmem.perBankRdBursts::4 1050 # Per bank write bursts 47system.physmem.perBankRdBursts::5 1105 # Per bank write bursts 48system.physmem.perBankRdBursts::6 1078 # Per bank write bursts 49system.physmem.perBankRdBursts::7 1080 # Per bank write bursts 50system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 51system.physmem.perBankRdBursts::9 959 # Per bank write bursts 52system.physmem.perBankRdBursts::10 938 # Per bank write bursts 53system.physmem.perBankRdBursts::11 899 # Per bank write bursts 54system.physmem.perBankRdBursts::12 904 # Per bank write bursts 55system.physmem.perBankRdBursts::13 865 # Per bank write bursts 56system.physmem.perBankRdBursts::14 877 # Per bank write bursts 57system.physmem.perBankRdBursts::15 896 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 26911220500 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 15518 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 155system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation 264system.physmem.totQLat 103760250 # Total ticks spent queuing 265system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers 267system.physmem.totBankLat 175780000 # Total ticks spent accessing banks 268system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst 269system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 271system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.29 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 282system.physmem.readRowHits 14899 # Number of row buffer hits during reads 283system.physmem.writeRowHits 0 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 286system.physmem.avgGap 1734193.87 # Average gap between requests 287system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined 288system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state 289system.membus.throughput 36904491 # Throughput (bytes/s) 290system.membus.trans_dist::ReadReq 980 # Transaction distribution 291system.membus.trans_dist::ReadResp 980 # Transaction distribution 292system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 293system.membus.trans_dist::UpgradeResp 1 # Transaction distribution 294system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 295system.membus.trans_dist::ReadExResp 14538 # Transaction distribution 296system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) 297system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) 298system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) 299system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) 300system.membus.data_through_bus 993152 # Total data (bytes) 301system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 302system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) 303system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 304system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) 305system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 306system.cpu.branchPred.lookups 26686306 # Number of BP lookups 307system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted 308system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect 309system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups 310system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits 311system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 312system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage 313system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. 314system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. 315system.cpu.dtb.inst_hits 0 # ITB inst hits 316system.cpu.dtb.inst_misses 0 # ITB inst misses 317system.cpu.dtb.read_hits 0 # DTB read hits 318system.cpu.dtb.read_misses 0 # DTB read misses 319system.cpu.dtb.write_hits 0 # DTB write hits 320system.cpu.dtb.write_misses 0 # DTB write misses 321system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 322system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 323system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 324system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 325system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 326system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 327system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 328system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 329system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 330system.cpu.dtb.read_accesses 0 # DTB read accesses 331system.cpu.dtb.write_accesses 0 # DTB write accesses 332system.cpu.dtb.inst_accesses 0 # ITB inst accesses 333system.cpu.dtb.hits 0 # DTB hits 334system.cpu.dtb.misses 0 # DTB misses 335system.cpu.dtb.accesses 0 # DTB accesses 336system.cpu.itb.inst_hits 0 # ITB inst hits 337system.cpu.itb.inst_misses 0 # ITB inst misses 338system.cpu.itb.read_hits 0 # DTB read hits 339system.cpu.itb.read_misses 0 # DTB read misses 340system.cpu.itb.write_hits 0 # DTB write hits 341system.cpu.itb.write_misses 0 # DTB write misses 342system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 343system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 344system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 345system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 346system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 347system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 348system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 349system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 350system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 351system.cpu.itb.read_accesses 0 # DTB read accesses 352system.cpu.itb.write_accesses 0 # DTB write accesses 353system.cpu.itb.inst_accesses 0 # ITB inst accesses 354system.cpu.itb.hits 0 # DTB hits 355system.cpu.itb.misses 0 # DTB misses 356system.cpu.itb.accesses 0 # DTB accesses 357system.cpu.workload.num_syscalls 442 # Number of system calls 358system.cpu.numCycles 53822827 # number of cpu cycles simulated 359system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 360system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 361system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss 362system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed 363system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered 364system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken 365system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked 366system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing 367system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked 368system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 369system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps 370system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR 371system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched 372system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed 373system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle 391system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle 392system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle 393system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked 394system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running 395system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking 396system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing 397system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch 398system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction 399system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode 400system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode 401system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing 402system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle 403system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking 404system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst 405system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running 406system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking 407system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename 408system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full 409system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full 410system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full 411system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers 412system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed 413system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made 414system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups 415system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups 416system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed 417system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing 418system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed 419system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed 420system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer 421system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. 422system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. 423system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. 424system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. 425system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) 426system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ 427system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued 428system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued 429system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling 430system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph 431system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed 432system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle 449system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 450system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available 451system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available 452system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available 453system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available 454system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available 455system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available 456system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available 479system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available 480system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 482system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 483system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 484system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued 485system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued 486system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued 488system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued 489system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued 490system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued 491system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued 492system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued 513system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued 514system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued 515system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 516system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 517system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued 518system.cpu.iq.rate 1.953956 # Inst issue rate 519system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested 520system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) 521system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads 522system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes 523system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses 524system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads 525system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes 526system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses 527system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses 528system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses 529system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores 530system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 531system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed 532system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed 533system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations 534system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed 535system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 536system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 537system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 538system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked 539system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 540system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing 541system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking 542system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking 543system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ 544system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch 545system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions 546system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions 547system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions 548system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall 549system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall 550system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations 551system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly 552system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly 553system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute 554system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions 555system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed 556system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute 557system.cpu.iew.exec_swp 0 # number of swp insts executed 558system.cpu.iew.exec_nop 12696 # number of nop insts executed 559system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed 560system.cpu.iew.exec_branches 21326762 # Number of branches executed 561system.cpu.iew.exec_stores 5056823 # Number of stores executed 562system.cpu.iew.exec_rate 1.935827 # Inst execution rate 563system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit 564system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back 565system.cpu.iew.wb_producers 62249009 # num instructions producing a value 566system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value 567system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 568system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle 569system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back 570system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 571system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit 572system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 573system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted 574system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle 591system.cpu.commit.committedInsts 90602407 # Number of instructions committed 592system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed 593system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 594system.cpu.commit.refs 27318810 # Number of memory references committed 595system.cpu.commit.loads 22573966 # Number of loads committed 596system.cpu.commit.membars 3888 # Number of memory barriers committed 597system.cpu.commit.branches 18732304 # Number of branches committed 598system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 599system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. 600system.cpu.commit.function_calls 56148 # Number of function calls committed. 601system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached 602system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 603system.cpu.rob.rob_reads 162447241 # The number of ROB reads 604system.cpu.rob.rob_writes 240306728 # The number of ROB writes 605system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself 606system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling 607system.cpu.committedInsts 90589798 # Number of Instructions Simulated 608system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated 609system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated 610system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction 611system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads 612system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle 613system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads 614system.cpu.int_regfile_reads 495604527 # number of integer regfile reads 615system.cpu.int_regfile_writes 120552200 # number of integer regfile writes 616system.cpu.fp_regfile_reads 148 # number of floating regfile reads 617system.cpu.fp_regfile_writes 360 # number of floating regfile writes 618system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads 619system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 620system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) 621system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution 628system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) 629system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) 630system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) 631system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) 632system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) 633system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) 634system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) 635system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) 636system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) 637system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) 638system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) 639system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 640system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) 641system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) 642system.cpu.icache.tags.replacements 3 # number of replacements 643system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use 644system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. 645system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. 646system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. 647system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 648system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor 649system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy 650system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy 651system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits 652system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits 653system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits 654system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits 655system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits 656system.cpu.icache.overall_hits::total 13844401 # number of overall hits 657system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses 658system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses 659system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses 660system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses 661system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses 662system.cpu.icache.overall_misses::total 991 # number of overall misses 663system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles 664system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles 665system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles 666system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles 667system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles 668system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles 669system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) 670system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) 671system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses 672system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses 673system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses 674system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses 675system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses 676system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses 677system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses 678system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses 679system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses 680system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses 681system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency 682system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency 683system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency 684system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency 685system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency 686system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency 687system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked 688system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 690system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked 692system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu.icache.fast_writes 0 # number of fast writes performed 694system.cpu.icache.cache_copies 0 # number of cache copies performed 695system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits 696system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits 697system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits 698system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits 699system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits 700system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits 701system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses 702system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses 703system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses 704system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses 705system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses 706system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses 707system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51712250 # number of ReadReq MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_latency::total 51712250 # number of ReadReq MSHR miss cycles 709system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51712250 # number of demand (read+write) MSHR miss cycles 710system.cpu.icache.demand_mshr_miss_latency::total 51712250 # number of demand (read+write) MSHR miss cycles 711system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51712250 # number of overall MSHR miss cycles 712system.cpu.icache.overall_mshr_miss_latency::total 51712250 # number of overall MSHR miss cycles 713system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses 714system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses 715system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses 716system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 717system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses 718system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 719system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170 # average ReadReq mshr miss latency 720system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70165.875170 # average ReadReq mshr miss latency 721system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency 722system.cpu.icache.demand_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency 723system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency 724system.cpu.icache.overall_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency 725system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 726system.cpu.l2cache.tags.replacements 0 # number of replacements 727system.cpu.l2cache.tags.tagsinuse 10730.950237 # Cycle average of tags in use 728system.cpu.l2cache.tags.total_refs 1831391 # Total number of references to valid blocks. 729system.cpu.l2cache.tags.sampled_refs 15501 # Sample count of references to valid blocks. 730system.cpu.l2cache.tags.avg_refs 118.146636 # Average number of references to valid blocks. 731system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 732system.cpu.l2cache.tags.occ_blocks::writebacks 9880.493814 # Average occupied blocks per requestor 733system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.630242 # Average occupied blocks per requestor 734system.cpu.l2cache.tags.occ_blocks::cpu.data 231.826182 # Average occupied blocks per requestor 735system.cpu.l2cache.tags.occ_percent::writebacks 0.301529 # Average percentage of cache occupancy 736system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy 737system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy 738system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy 739system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits 741system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits 742system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits 743system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits 744system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 745system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 746system.cpu.l2cache.ReadExReq_hits::cpu.data 29162 # number of ReadExReq hits 747system.cpu.l2cache.ReadExReq_hits::total 29162 # number of ReadExReq hits 748system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 749system.cpu.l2cache.demand_hits::cpu.data 932780 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::total 932804 # number of demand (read+write) hits 751system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits 752system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits 753system.cpu.l2cache.overall_hits::total 932804 # number of overall hits 754system.cpu.l2cache.ReadReq_misses::cpu.inst 711 # number of ReadReq misses 755system.cpu.l2cache.ReadReq_misses::cpu.data 280 # number of ReadReq misses 756system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses 757system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 758system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 759system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 760system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 761system.cpu.l2cache.demand_misses::cpu.inst 711 # number of demand (read+write) misses 762system.cpu.l2cache.demand_misses::cpu.data 14818 # number of demand (read+write) misses 763system.cpu.l2cache.demand_misses::total 15529 # number of demand (read+write) misses 764system.cpu.l2cache.overall_misses::cpu.inst 711 # number of overall misses 765system.cpu.l2cache.overall_misses::cpu.data 14818 # number of overall misses 766system.cpu.l2cache.overall_misses::total 15529 # number of overall misses 767system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50729000 # number of ReadReq miss cycles 768system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21404500 # number of ReadReq miss cycles 769system.cpu.l2cache.ReadReq_miss_latency::total 72133500 # number of ReadReq miss cycles 770system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962429750 # number of ReadExReq miss cycles 771system.cpu.l2cache.ReadExReq_miss_latency::total 962429750 # number of ReadExReq miss cycles 772system.cpu.l2cache.demand_miss_latency::cpu.inst 50729000 # number of demand (read+write) miss cycles 773system.cpu.l2cache.demand_miss_latency::cpu.data 983834250 # number of demand (read+write) miss cycles 774system.cpu.l2cache.demand_miss_latency::total 1034563250 # number of demand (read+write) miss cycles 775system.cpu.l2cache.overall_miss_latency::cpu.inst 50729000 # number of overall miss cycles 776system.cpu.l2cache.overall_miss_latency::cpu.data 983834250 # number of overall miss cycles 777system.cpu.l2cache.overall_miss_latency::total 1034563250 # number of overall miss cycles 778system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) 779system.cpu.l2cache.ReadReq_accesses::cpu.data 903898 # number of ReadReq accesses(hits+misses) 780system.cpu.l2cache.ReadReq_accesses::total 904633 # number of ReadReq accesses(hits+misses) 781system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) 782system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) 783system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 784system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 785system.cpu.l2cache.ReadExReq_accesses::cpu.data 43700 # number of ReadExReq accesses(hits+misses) 786system.cpu.l2cache.ReadExReq_accesses::total 43700 # number of ReadExReq accesses(hits+misses) 787system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses 788system.cpu.l2cache.demand_accesses::cpu.data 947598 # number of demand (read+write) accesses 789system.cpu.l2cache.demand_accesses::total 948333 # number of demand (read+write) accesses 790system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses 791system.cpu.l2cache.overall_accesses::cpu.data 947598 # number of overall (read+write) accesses 792system.cpu.l2cache.overall_accesses::total 948333 # number of overall (read+write) accesses 793system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967347 # miss rate for ReadReq accesses 794system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000310 # miss rate for ReadReq accesses 795system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses 796system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 797system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 798system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332677 # miss rate for ReadExReq accesses 799system.cpu.l2cache.ReadExReq_miss_rate::total 0.332677 # miss rate for ReadExReq accesses 800system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967347 # miss rate for demand accesses 801system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses 802system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses 803system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967347 # miss rate for overall accesses 804system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses 805system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses 806system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71348.804501 # average ReadReq miss latency 807system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76444.642857 # average ReadReq miss latency 808system.cpu.l2cache.ReadReq_avg_miss_latency::total 72788.597376 # average ReadReq miss latency 809system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66200.973311 # average ReadExReq miss latency 810system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66200.973311 # average ReadExReq miss latency 811system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency 812system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency 813system.cpu.l2cache.demand_avg_miss_latency::total 66621.369695 # average overall miss latency 814system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency 815system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency 816system.cpu.l2cache.overall_avg_miss_latency::total 66621.369695 # average overall miss latency 817system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 818system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 819system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 820system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 821system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 822system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 823system.cpu.l2cache.fast_writes 0 # number of fast writes performed 824system.cpu.l2cache.cache_copies 0 # number of cache copies performed 825system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 826system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 827system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 828system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 829system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 830system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 831system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 832system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 833system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits 834system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses 835system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 270 # number of ReadReq MSHR misses 836system.cpu.l2cache.ReadReq_mshr_misses::total 980 # number of ReadReq MSHR misses 837system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 838system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 839system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 840system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 841system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses 842system.cpu.l2cache.demand_mshr_misses::cpu.data 14808 # number of demand (read+write) MSHR misses 843system.cpu.l2cache.demand_mshr_misses::total 15518 # number of demand (read+write) MSHR misses 844system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses 845system.cpu.l2cache.overall_mshr_misses::cpu.data 14808 # number of overall MSHR misses 846system.cpu.l2cache.overall_mshr_misses::total 15518 # number of overall MSHR misses 847system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41786750 # number of ReadReq MSHR miss cycles 848system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17438000 # number of ReadReq MSHR miss cycles 849system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59224750 # number of ReadReq MSHR miss cycles 850system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 851system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 852system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780053750 # number of ReadExReq MSHR miss cycles 853system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780053750 # number of ReadExReq MSHR miss cycles 854system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41786750 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797491750 # number of demand (read+write) MSHR miss cycles 856system.cpu.l2cache.demand_mshr_miss_latency::total 839278500 # number of demand (read+write) MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41786750 # number of overall MSHR miss cycles 858system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797491750 # number of overall MSHR miss cycles 859system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses 861system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses 862system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses 863system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 864system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 865system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses 867system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses 868system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses 869system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses 870system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses 871system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses 872system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency 874system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency 875system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency 876system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 877system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency 886system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 887system.cpu.dcache.tags.replacements 943502 # number of replacements 888system.cpu.dcache.tags.tagsinuse 3671.733270 # Cycle average of tags in use 889system.cpu.dcache.tags.total_refs 28144425 # Total number of references to valid blocks. 890system.cpu.dcache.tags.sampled_refs 947598 # Sample count of references to valid blocks. 891system.cpu.dcache.tags.avg_refs 29.700807 # Average number of references to valid blocks. 892system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. 893system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor 894system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy 895system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy 896system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits 897system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits 898system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits 899system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits 900system.cpu.dcache.LoadLockedReq_hits::cpu.data 3913 # number of LoadLockedReq hits 901system.cpu.dcache.LoadLockedReq_hits::total 3913 # number of LoadLockedReq hits 902system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 903system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 904system.cpu.dcache.demand_hits::cpu.data 28136618 # number of demand (read+write) hits 905system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits 906system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits 907system.cpu.dcache.overall_hits::total 28136618 # number of overall hits 908system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses 909system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses 910system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses 911system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses 912system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses 913system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses 914system.cpu.dcache.demand_misses::cpu.data 1376116 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 1376116 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 1376116 # number of overall misses 917system.cpu.dcache.overall_misses::total 1376116 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 13894448479 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 13894448479 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458649331 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles 924system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles 925system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles 926system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles 927system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles 928system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) 929system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) 930system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 931system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 932system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3920 # number of LoadLockedReq accesses(hits+misses) 933system.cpu.dcache.LoadLockedReq_accesses::total 3920 # number of LoadLockedReq accesses(hits+misses) 934system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 935system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 936system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses 937system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses 938system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses 939system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses 940system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses 941system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses 942system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses 943system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses 944system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses 945system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses 946system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses 947system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses 948system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses 949system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses 950system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency 951system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency 952system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency 953system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency 954system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency 955system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency 956system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency 957system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency 958system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency 959system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency 960system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked 961system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 962system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked 963system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 964system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked 965system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 966system.cpu.dcache.fast_writes 0 # number of fast writes performed 967system.cpu.dcache.cache_copies 0 # number of cache copies performed 968system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks 969system.cpu.dcache.writebacks::total 942892 # number of writebacks 970system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits 971system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits 972system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits 973system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits 974system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits 975system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits 976system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits 977system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits 978system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits 979system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits 980system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses 981system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses 982system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses 983system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses 984system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses 985system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses 986system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses 987system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses 988system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles 989system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles 990system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles 991system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles 992system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles 993system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles 994system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles 995system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles 996system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses 997system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses 998system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses 999system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses 1000system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses 1001system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses 1002system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses 1003system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency 1005system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency 1006system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency 1007system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency 1008system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency 1009system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency 1010system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency 1011system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency 1012system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013 1014---------- End Simulation Statistics ---------- 1015