stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026877 # Number of seconds simulated 4sim_ticks 26876770500 # Number of ticks simulated 5final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 124105 # Simulator instruction rate (inst/s) 8host_op_rate 124996 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36820237 # Simulator tick rate (ticks/s) 10host_mem_usage 379416 # Number of bytes of host memory used 11host_seconds 729.95 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992448 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 15507 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 992448 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 26876578500 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 15507 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation 189system.physmem.totQLat 33774250 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests 191system.physmem.totBusLat 77535000 # Total cycles spent in databus access 192system.physmem.totBankLat 180097500 # Total cycles spent in bank access 193system.physmem.avgQLat 2178.00 # Average queueing delay per request 194system.physmem.avgBankLat 11613.95 # Average bank access latency per request 195system.physmem.avgBusLat 5000.00 # Average bus latency per request 196system.physmem.avgMemAccLat 18791.95 # Average memory access latency 197system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s 198system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 0.29 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.01 # Average read queue length over time 204system.physmem.avgWrQLen 0.00 # Average write queue length over time 205system.physmem.readRowHits 15228 # Number of row buffer hits during reads 206system.physmem.writeRowHits 0 # Number of row buffer hits during writes 207system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 209system.physmem.avgGap 1733190.08 # Average gap between requests 210system.membus.throughput 36925865 # Throughput (bytes/s) 211system.membus.trans_dist::ReadReq 969 # Transaction distribution 212system.membus.trans_dist::ReadResp 969 # Transaction distribution 213system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 214system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 215system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 216system.membus.trans_dist::ReadExResp 14538 # Transaction distribution 217system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes) 218system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes) 219system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes) 220system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes) 221system.membus.data_through_bus 992448 # Total data (bytes) 222system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 223system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks) 224system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 225system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks) 226system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 227system.cpu.branchPred.lookups 26679971 # Number of BP lookups 228system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted 229system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect 230system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups 231system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits 232system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 233system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage 234system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target. 235system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions. 236system.cpu.dtb.inst_hits 0 # ITB inst hits 237system.cpu.dtb.inst_misses 0 # ITB inst misses 238system.cpu.dtb.read_hits 0 # DTB read hits 239system.cpu.dtb.read_misses 0 # DTB read misses 240system.cpu.dtb.write_hits 0 # DTB write hits 241system.cpu.dtb.write_misses 0 # DTB write misses 242system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 243system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 244system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 245system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 246system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 247system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 248system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 249system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 250system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 251system.cpu.dtb.read_accesses 0 # DTB read accesses 252system.cpu.dtb.write_accesses 0 # DTB write accesses 253system.cpu.dtb.inst_accesses 0 # ITB inst accesses 254system.cpu.dtb.hits 0 # DTB hits 255system.cpu.dtb.misses 0 # DTB misses 256system.cpu.dtb.accesses 0 # DTB accesses 257system.cpu.itb.inst_hits 0 # ITB inst hits 258system.cpu.itb.inst_misses 0 # ITB inst misses 259system.cpu.itb.read_hits 0 # DTB read hits 260system.cpu.itb.read_misses 0 # DTB read misses 261system.cpu.itb.write_hits 0 # DTB write hits 262system.cpu.itb.write_misses 0 # DTB write misses 263system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 265system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 266system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 267system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 268system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 269system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 270system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 271system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 272system.cpu.itb.read_accesses 0 # DTB read accesses 273system.cpu.itb.write_accesses 0 # DTB write accesses 274system.cpu.itb.inst_accesses 0 # ITB inst accesses 275system.cpu.itb.hits 0 # DTB hits 276system.cpu.itb.misses 0 # DTB misses 277system.cpu.itb.accesses 0 # DTB accesses 278system.cpu.workload.num_syscalls 442 # Number of system calls 279system.cpu.numCycles 53753542 # number of cpu cycles simulated 280system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 281system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 282system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss 283system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed 284system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered 285system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken 286system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked 287system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing 288system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked 289system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 290system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps 291system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR 292system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched 293system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed 294system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle 312system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle 313system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle 314system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked 315system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running 316system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking 317system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing 318system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch 319system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction 320system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode 321system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode 322system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle 324system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking 325system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename 329system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full 330system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full 331system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full 332system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers 333system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed 334system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made 335system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups 336system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups 337system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed 338system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing 339system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed 340system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed 341system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer 342system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit. 343system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit. 344system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads. 345system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores. 346system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec) 347system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ 348system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued 349system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued 350system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling 351system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph 352system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed 353system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle 370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 371system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 405system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued 434system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued 435system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued 436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued 439system.cpu.iq.rate 1.956050 # Inst issue rate 440system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested 441system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst) 442system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads 443system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes 444system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses 445system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads 446system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes 447system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses 448system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses 449system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses 450system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores 451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 452system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed 453system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed 454system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations 455system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed 456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 458system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 459system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked 460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 461system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing 462system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking 463system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking 464system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ 465system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch 466system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions 467system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions 468system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions 469system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall 470system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall 471system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations 472system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly 473system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly 474system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute 475system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions 476system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute 478system.cpu.iew.exec_swp 0 # number of swp insts executed 479system.cpu.iew.exec_nop 12698 # number of nop insts executed 480system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed 481system.cpu.iew.exec_branches 21325081 # Number of branches executed 482system.cpu.iew.exec_stores 5056078 # Number of stores executed 483system.cpu.iew.exec_rate 1.937862 # Inst execution rate 484system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit 485system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back 486system.cpu.iew.wb_producers 62239721 # num instructions producing a value 487system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value 488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 489system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back 491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 492system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit 493system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 494system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle 512system.cpu.commit.committedInsts 90602407 # Number of instructions committed 513system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 27318810 # Number of memory references committed 516system.cpu.commit.loads 22573966 # Number of loads committed 517system.cpu.commit.membars 3888 # Number of memory barriers committed 518system.cpu.commit.branches 18732304 # Number of branches committed 519system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 520system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. 521system.cpu.commit.function_calls 56148 # Number of function calls committed. 522system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached 523system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 524system.cpu.rob.rob_reads 162415559 # The number of ROB reads 525system.cpu.rob.rob_writes 240257118 # The number of ROB writes 526system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself 527system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling 528system.cpu.committedInsts 90589798 # Number of Instructions Simulated 529system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated 530system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated 531system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction 532system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads 533system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle 534system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads 535system.cpu.int_regfile_reads 495496517 # number of integer regfile reads 536system.cpu.int_regfile_writes 120533542 # number of integer regfile writes 537system.cpu.fp_regfile_reads 149 # number of floating regfile reads 538system.cpu.fp_regfile_writes 362 # number of floating regfile writes 539system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads 540system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 541system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s) 542system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution 549system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes) 550system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes) 556system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) 557system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks) 558system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) 559system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks) 560system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 561system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks) 562system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) 563system.cpu.icache.replacements 4 # number of replacements 564system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use 565system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks. 566system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks. 567system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks. 568system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 569system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor 570system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy 571system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy 572system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits 573system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits 574system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits 575system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits 576system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits 577system.cpu.icache.overall_hits::total 13838883 # number of overall hits 578system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses 579system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses 580system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses 581system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses 582system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses 583system.cpu.icache.overall_misses::total 984 # number of overall misses 584system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles 585system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles 586system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles 587system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles 588system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles 589system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles 590system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses) 591system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses) 592system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses 593system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses 594system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses 595system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses 596system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses 597system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses 598system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses 599system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses 600system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses 601system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses 602system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency 603system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency 604system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency 605system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency 606system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency 607system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency 608system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked 609system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 610system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked 611system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked 613system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 614system.cpu.icache.fast_writes 0 # number of fast writes performed 615system.cpu.icache.cache_copies 0 # number of cache copies performed 616system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits 617system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits 618system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits 619system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits 620system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits 621system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits 622system.cpu.icache.ReadReq_mshr_misses::cpu.inst 730 # number of ReadReq MSHR misses 623system.cpu.icache.ReadReq_mshr_misses::total 730 # number of ReadReq MSHR misses 624system.cpu.icache.demand_mshr_misses::cpu.inst 730 # number of demand (read+write) MSHR misses 625system.cpu.icache.demand_mshr_misses::total 730 # number of demand (read+write) MSHR misses 626system.cpu.icache.overall_mshr_misses::cpu.inst 730 # number of overall MSHR misses 627system.cpu.icache.overall_mshr_misses::total 730 # number of overall MSHR misses 628system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49961500 # number of ReadReq MSHR miss cycles 629system.cpu.icache.ReadReq_mshr_miss_latency::total 49961500 # number of ReadReq MSHR miss cycles 630system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49961500 # number of demand (read+write) MSHR miss cycles 631system.cpu.icache.demand_mshr_miss_latency::total 49961500 # number of demand (read+write) MSHR miss cycles 632system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49961500 # number of overall MSHR miss cycles 633system.cpu.icache.overall_mshr_miss_latency::total 49961500 # number of overall MSHR miss cycles 634system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses 635system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses 636system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses 637system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 638system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses 639system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 640system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68440.410959 # average ReadReq mshr miss latency 641system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68440.410959 # average ReadReq mshr miss latency 642system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency 643system.cpu.icache.demand_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency 644system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency 645system.cpu.icache.overall_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency 646system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 647system.cpu.l2cache.replacements 0 # number of replacements 648system.cpu.l2cache.tagsinuse 10730.679646 # Cycle average of tags in use 649system.cpu.l2cache.total_refs 1831381 # Total number of references to valid blocks. 650system.cpu.l2cache.sampled_refs 15490 # Sample count of references to valid blocks. 651system.cpu.l2cache.avg_refs 118.229890 # Average number of references to valid blocks. 652system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 653system.cpu.l2cache.occ_blocks::writebacks 9888.279908 # Average occupied blocks per requestor 654system.cpu.l2cache.occ_blocks::cpu.inst 613.185142 # Average occupied blocks per requestor 655system.cpu.l2cache.occ_blocks::cpu.data 229.214596 # Average occupied blocks per requestor 656system.cpu.l2cache.occ_percent::writebacks 0.301766 # Average percentage of cache occupancy 657system.cpu.l2cache.occ_percent::cpu.inst 0.018713 # Average percentage of cache occupancy 658system.cpu.l2cache.occ_percent::cpu.data 0.006995 # Average percentage of cache occupancy 659system.cpu.l2cache.occ_percent::total 0.327474 # Average percentage of cache occupancy 660system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits 661system.cpu.l2cache.ReadReq_hits::cpu.data 903579 # number of ReadReq hits 662system.cpu.l2cache.ReadReq_hits::total 903605 # number of ReadReq hits 663system.cpu.l2cache.Writeback_hits::writebacks 942920 # number of Writeback hits 664system.cpu.l2cache.Writeback_hits::total 942920 # number of Writeback hits 665system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 666system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 667system.cpu.l2cache.ReadExReq_hits::cpu.data 29237 # number of ReadExReq hits 668system.cpu.l2cache.ReadExReq_hits::total 29237 # number of ReadExReq hits 669system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits 670system.cpu.l2cache.demand_hits::cpu.data 932816 # number of demand (read+write) hits 671system.cpu.l2cache.demand_hits::total 932842 # number of demand (read+write) hits 672system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits 673system.cpu.l2cache.overall_hits::cpu.data 932816 # number of overall hits 674system.cpu.l2cache.overall_hits::total 932842 # number of overall hits 675system.cpu.l2cache.ReadReq_misses::cpu.inst 701 # number of ReadReq misses 676system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses 677system.cpu.l2cache.ReadReq_misses::total 980 # number of ReadReq misses 678system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 679system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 680system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 681system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 682system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses 684system.cpu.l2cache.demand_misses::total 15518 # number of demand (read+write) misses 685system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses 686system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses 687system.cpu.l2cache.overall_misses::total 15518 # number of overall misses 688system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48961500 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19173000 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadReq_miss_latency::total 68134500 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 895149000 # number of ReadExReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::total 895149000 # number of ReadExReq miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.inst 48961500 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.data 914322000 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::total 963283500 # number of demand (read+write) miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.inst 48961500 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.data 914322000 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::total 963283500 # number of overall miss cycles 699system.cpu.l2cache.ReadReq_accesses::cpu.inst 727 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadReq_accesses::cpu.data 903858 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadReq_accesses::total 904585 # number of ReadReq accesses(hits+misses) 702system.cpu.l2cache.Writeback_accesses::writebacks 942920 # number of Writeback accesses(hits+misses) 703system.cpu.l2cache.Writeback_accesses::total 942920 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 705system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 706system.cpu.l2cache.ReadExReq_accesses::cpu.data 43775 # number of ReadExReq accesses(hits+misses) 707system.cpu.l2cache.ReadExReq_accesses::total 43775 # number of ReadExReq accesses(hits+misses) 708system.cpu.l2cache.demand_accesses::cpu.inst 727 # number of demand (read+write) accesses 709system.cpu.l2cache.demand_accesses::cpu.data 947633 # number of demand (read+write) accesses 710system.cpu.l2cache.demand_accesses::total 948360 # number of demand (read+write) accesses 711system.cpu.l2cache.overall_accesses::cpu.inst 727 # number of overall (read+write) accesses 712system.cpu.l2cache.overall_accesses::cpu.data 947633 # number of overall (read+write) accesses 713system.cpu.l2cache.overall_accesses::total 948360 # number of overall (read+write) accesses 714system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964237 # miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses 717system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses 718system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses 719system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332107 # miss rate for ReadExReq accesses 720system.cpu.l2cache.ReadExReq_miss_rate::total 0.332107 # miss rate for ReadExReq accesses 721system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964237 # miss rate for demand accesses 722system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses 723system.cpu.l2cache.demand_miss_rate::total 0.016363 # miss rate for demand accesses 724system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964237 # miss rate for overall accesses 725system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses 726system.cpu.l2cache.overall_miss_rate::total 0.016363 # miss rate for overall accesses 727system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69845.221113 # average ReadReq miss latency 728system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68720.430108 # average ReadReq miss latency 729system.cpu.l2cache.ReadReq_avg_miss_latency::total 69525 # average ReadReq miss latency 730system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61573.049938 # average ReadExReq miss latency 731system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61573.049938 # average ReadExReq miss latency 732system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency 733system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency 734system.cpu.l2cache.demand_avg_miss_latency::total 62075.235211 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency 736system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency 737system.cpu.l2cache.overall_avg_miss_latency::total 62075.235211 # average overall miss latency 738system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 740system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 741system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 742system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 743system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 744system.cpu.l2cache.fast_writes 0 # number of fast writes performed 745system.cpu.l2cache.cache_copies 0 # number of cache copies performed 746system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 747system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 748system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 749system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 750system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 751system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 752system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 753system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 754system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits 755system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 700 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses 758system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 759system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 760system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 761system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 762system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses 763system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses 764system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses 766system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses 767system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses 768system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40240750 # number of ReadReq MSHR miss cycles 769system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15233500 # number of ReadReq MSHR miss cycles 770system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55474250 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 772system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714861250 # number of ReadExReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles 775system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::total 770335500 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40240750 # number of overall MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730094750 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::total 770335500 # number of overall MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses 785system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57248.968008 # average ReadReq mshr miss latency 797system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 798system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 799system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency 807system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu.dcache.replacements 943537 # number of replacements 809system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use 810system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks. 811system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks. 812system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks. 813system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit. 814system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor 815system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy 816system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy 817system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits 818system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits 819system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # number of WriteReq hits 820system.cpu.dcache.WriteReq_hits::total 4532751 # number of WriteReq hits 821system.cpu.dcache.LoadLockedReq_hits::cpu.data 3906 # number of LoadLockedReq hits 822system.cpu.dcache.LoadLockedReq_hits::total 3906 # number of LoadLockedReq hits 823system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 824system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 825system.cpu.dcache.demand_hits::cpu.data 28130292 # number of demand (read+write) hits 826system.cpu.dcache.demand_hits::total 28130292 # number of demand (read+write) hits 827system.cpu.dcache.overall_hits::cpu.data 28130292 # number of overall hits 828system.cpu.dcache.overall_hits::total 28130292 # number of overall hits 829system.cpu.dcache.ReadReq_misses::cpu.data 1173737 # number of ReadReq misses 830system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses 831system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses 832system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses 833system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses 834system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses 835system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses 836system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses 837system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses 838system.cpu.dcache.overall_misses::total 1375967 # number of overall misses 839system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles 840system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles 841system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # number of WriteReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::total 7842358356 # number of WriteReq miss cycles 843system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 236000 # number of LoadLockedReq miss cycles 844system.cpu.dcache.LoadLockedReq_miss_latency::total 236000 # number of LoadLockedReq miss cycles 845system.cpu.dcache.demand_miss_latency::cpu.data 21730040356 # number of demand (read+write) miss cycles 846system.cpu.dcache.demand_miss_latency::total 21730040356 # number of demand (read+write) miss cycles 847system.cpu.dcache.overall_miss_latency::cpu.data 21730040356 # number of overall miss cycles 848system.cpu.dcache.overall_miss_latency::total 21730040356 # number of overall miss cycles 849system.cpu.dcache.ReadReq_accesses::cpu.data 24771278 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.ReadReq_accesses::total 24771278 # number of ReadReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 853system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses) 854system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses) 855system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 856system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 857system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses 858system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses 859system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses 860system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses 861system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses 862system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses 863system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses 864system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses 865system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses 866system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses 867system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses 868system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses 869system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses 870system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses 871system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency 872system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency 873system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency 874system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency 875system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency 876system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency 877system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency 878system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency 879system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency 880system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency 881system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked 882system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 883system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked 884system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 885system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked 886system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 887system.cpu.dcache.fast_writes 0 # number of fast writes performed 888system.cpu.dcache.cache_copies 0 # number of cache copies performed 889system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks 890system.cpu.dcache.writebacks::total 942920 # number of writebacks 891system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits 892system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits 893system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits 894system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits 895system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits 896system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits 897system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits 898system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits 899system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits 900system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits 901system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses 902system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses 903system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses 905system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses 906system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses 907system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses 908system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses 909system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles 910system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles 917system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses 918system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses 922system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses 923system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses 924system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses 925system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency 927system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency 929system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency 931system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency 933system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 934 935---------- End Simulation Statistics ---------- 936