stats.txt revision 9312:e05e1b69ebf2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025283 # Number of seconds simulated 4sim_ticks 25283397500 # Number of ticks simulated 5final_tick 25283397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 115178 # Simulator instruction rate (inst/s) 8host_op_rate 116005 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32142506 # Simulator tick rate (ticks/s) 10host_mem_usage 365228 # Number of bytes of host memory used 11host_seconds 786.60 # Real time elapsed on the host 12sim_insts 90599358 # Number of instructions simulated 13sim_ops 91249911 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45760 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory 16system.physmem.bytes_read::total 993280 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45760 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45760 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 715 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1809883 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 37475976 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 39285859 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1809883 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1809883 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1809883 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 37475976 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 39285859 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 15520 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 993280 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 993280 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 998 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 943 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 934 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 25283243500 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 15520 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 9030 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 6257 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 43058501 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 270142501 # Sum of mem lat for all requests 169system.physmem.totBusLat 62080000 # Total cycles spent in databus access 170system.physmem.totBankLat 165004000 # Total cycles spent in bank access 171system.physmem.avgQLat 2774.39 # Average queueing delay per request 172system.physmem.avgBankLat 10631.70 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 17406.09 # Average memory access latency 175system.physmem.avgRdBW 39.29 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 39.29 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.25 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.01 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 15094 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 1629074.97 # Average gap between requests 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 196system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 197system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 198system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 199system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 200system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 201system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 202system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 203system.cpu.dtb.read_accesses 0 # DTB read accesses 204system.cpu.dtb.write_accesses 0 # DTB write accesses 205system.cpu.dtb.inst_accesses 0 # ITB inst accesses 206system.cpu.dtb.hits 0 # DTB hits 207system.cpu.dtb.misses 0 # DTB misses 208system.cpu.dtb.accesses 0 # DTB accesses 209system.cpu.itb.inst_hits 0 # ITB inst hits 210system.cpu.itb.inst_misses 0 # ITB inst misses 211system.cpu.itb.read_hits 0 # DTB read hits 212system.cpu.itb.read_misses 0 # DTB read misses 213system.cpu.itb.write_hits 0 # DTB write hits 214system.cpu.itb.write_misses 0 # DTB write misses 215system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 216system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 217system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 218system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 219system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 220system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 221system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 222system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 442 # Number of system calls 231system.cpu.numCycles 50566796 # number of cpu cycles simulated 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.BPredUnit.lookups 26827710 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 22074051 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 888543 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 11563656 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 11363946 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 71231 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 482 # Number of incorrect RAS predictions. 242system.cpu.fetch.icacheStallCycles 14348377 # Number of cycles fetch is stalled on an Icache miss 243system.cpu.fetch.Insts 128701471 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 26827710 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 11435177 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 24213451 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 4809546 # Number of cycles fetch has spent squashing 248system.cpu.fetch.BlockedCycles 8060195 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 250system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps 251system.cpu.fetch.CacheLines 14028280 # Number of cache lines fetched 252system.cpu.fetch.IcacheSquashes 377661 # Number of outstanding Icache misses that were squashed 253system.cpu.fetch.rateDist::samples 50539595 # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::mean 2.565225 # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::stdev 3.255897 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::0 26364164 52.17% 52.17% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::1 3431492 6.79% 58.96% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::2 2034951 4.03% 62.98% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::3 1571856 3.11% 66.09% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::4 1677128 3.32% 69.41% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::5 2962722 5.86% 75.27% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::6 1482816 2.93% 78.21% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::7 1106293 2.19% 80.40% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::8 9908173 19.60% 100.00% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::total 50539595 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.branchRate 0.530540 # Number of branch fetches per cycle 271system.cpu.fetch.rate 2.545177 # Number of inst fetches per cycle 272system.cpu.decode.IdleCycles 16886092 # Number of cycles decode is idle 273system.cpu.decode.BlockedCycles 6166490 # Number of cycles decode is blocked 274system.cpu.decode.RunCycles 22746907 # Number of cycles decode is running 275system.cpu.decode.UnblockCycles 831459 # Number of cycles decode is unblocking 276system.cpu.decode.SquashCycles 3908647 # Number of cycles decode is squashing 277system.cpu.decode.BranchResolved 4474881 # Number of times decode resolved a branch 278system.cpu.decode.BranchMispred 9055 # Number of times decode detected a branch misprediction 279system.cpu.decode.DecodedInsts 126903101 # Number of instructions handled by decode 280system.cpu.decode.SquashedInsts 43084 # Number of squashed instructions handled by decode 281system.cpu.rename.SquashCycles 3908647 # Number of cycles rename is squashing 282system.cpu.rename.IdleCycles 18602269 # Number of cycles rename is idle 283system.cpu.rename.BlockCycles 1370571 # Number of cycles rename is blocking 284system.cpu.rename.serializeStallCycles 152009 # count of cycles rename stalled for serializing inst 285system.cpu.rename.RunCycles 21842488 # Number of cycles rename is running 286system.cpu.rename.UnblockCycles 4663611 # Number of cycles rename is unblocking 287system.cpu.rename.RenamedInsts 123722180 # Number of instructions processed by rename 288system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 289system.cpu.rename.IQFullEvents 282360 # Number of times rename has blocked due to IQ full 290system.cpu.rename.LSQFullEvents 3941818 # Number of times rename has blocked due to LSQ full 291system.cpu.rename.RenamedOperands 144182082 # Number of destination operands rename has renamed 292system.cpu.rename.RenameLookups 538941570 # Number of register rename lookups that rename has made 293system.cpu.rename.int_rename_lookups 538934983 # Number of integer rename lookups 294system.cpu.rename.fp_rename_lookups 6587 # Number of floating rename lookups 295system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed 296system.cpu.rename.UndoneMaps 36752600 # Number of HB maps that are undone due to squashing 297system.cpu.rename.serializingInsts 6474 # count of serializing insts renamed 298system.cpu.rename.tempSerializingInsts 6472 # count of temporary serializing insts renamed 299system.cpu.rename.skidInsts 10800172 # count of insts added to the skid buffer 300system.cpu.memDep0.insertedLoads 29574364 # Number of loads inserted to the mem dependence unit. 301system.cpu.memDep0.insertedStores 5545202 # Number of stores inserted to the mem dependence unit. 302system.cpu.memDep0.conflictingLoads 2016944 # Number of conflicting loads. 303system.cpu.memDep0.conflictingStores 1216593 # Number of conflicting stores. 304system.cpu.iq.iqInstsAdded 118465493 # Number of instructions added to the IQ (excludes non-spec) 305system.cpu.iq.iqNonSpecInstsAdded 10340 # Number of non-speculative instructions added to the IQ 306system.cpu.iq.iqInstsIssued 105556460 # Number of instructions issued 307system.cpu.iq.iqSquashedInstsIssued 69311 # Number of squashed instructions issued 308system.cpu.iq.iqSquashedInstsExamined 27028341 # Number of squashed instructions iterated over during squash; mainly for profiling 309system.cpu.iq.iqSquashedOperandsExamined 66448905 # Number of squashed operands that are examined and possibly removed from graph 310system.cpu.iq.iqSquashedNonSpecRemoved 210 # Number of squashed non-spec instructions that were removed 311system.cpu.iq.issued_per_cycle::samples 50539595 # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::mean 2.088589 # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::stdev 1.960694 # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::0 13663948 27.04% 27.04% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::1 10566811 20.91% 47.94% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::2 7991493 15.81% 63.76% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::3 6436117 12.73% 76.49% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::4 4858269 9.61% 86.10% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::5 3518110 6.96% 93.07% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::6 2381435 4.71% 97.78% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::7 601220 1.19% 98.97% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::8 522192 1.03% 100.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::total 50539595 # Number of insts issued each cycle 328system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 329system.cpu.iq.fu_full::IntAlu 142805 18.40% 18.40% # attempts to use FU when none available 330system.cpu.iq.fu_full::IntMult 27 0.00% 18.40% # attempts to use FU when none available 331system.cpu.iq.fu_full::IntDiv 0 0.00% 18.40% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.40% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.40% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.40% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatMult 0 0.00% 18.40% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.40% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.40% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.40% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.40% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.40% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.40% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.40% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.40% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdMult 0 0.00% 18.40% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.40% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdShift 0 0.00% 18.40% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.40% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.40% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.40% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.40% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.40% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.40% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.40% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.40% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.40% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.40% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.40% # attempts to use FU when none available 358system.cpu.iq.fu_full::MemRead 357317 46.04% 64.44% # attempts to use FU when none available 359system.cpu.iq.fu_full::MemWrite 276029 35.56% 100.00% # attempts to use FU when none available 360system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 361system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 362system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 363system.cpu.iq.FU_type_0::IntAlu 74650431 70.72% 70.72% # Type of FU issued 364system.cpu.iq.FU_type_0::IntMult 10952 0.01% 70.73% # Type of FU issued 365system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued 367system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued 368system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.73% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatCvt 213 0.00% 70.73% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatMisc 258 0.00% 70.73% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.73% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued 392system.cpu.iq.FU_type_0::MemRead 25757662 24.40% 95.13% # Type of FU issued 393system.cpu.iq.FU_type_0::MemWrite 5136941 4.87% 100.00% # Type of FU issued 394system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 395system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 396system.cpu.iq.FU_type_0::total 105556460 # Type of FU issued 397system.cpu.iq.rate 2.087466 # Inst issue rate 398system.cpu.iq.fu_busy_cnt 776178 # FU busy when requested 399system.cpu.iq.fu_busy_rate 0.007353 # FU busy rate (busy events/executed inst) 400system.cpu.iq.int_inst_queue_reads 262497002 # Number of integer instruction queue reads 401system.cpu.iq.int_inst_queue_writes 145505542 # Number of integer instruction queue writes 402system.cpu.iq.int_inst_queue_wakeup_accesses 102811583 # Number of integer instruction queue wakeup accesses 403system.cpu.iq.fp_inst_queue_reads 1002 # Number of floating instruction queue reads 404system.cpu.iq.fp_inst_queue_writes 1425 # Number of floating instruction queue writes 405system.cpu.iq.fp_inst_queue_wakeup_accesses 429 # Number of floating instruction queue wakeup accesses 406system.cpu.iq.int_alu_accesses 106332135 # Number of integer alu accesses 407system.cpu.iq.fp_alu_accesses 503 # Number of floating point alu accesses 408system.cpu.iew.lsq.thread0.forwLoads 448933 # Number of loads that had data forwarded from stores 409system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 410system.cpu.iew.lsq.thread0.squashedLoads 6998486 # Number of loads squashed 411system.cpu.iew.lsq.thread0.ignoredResponses 7563 # Number of memory responses ignored because the instruction is squashed 412system.cpu.iew.lsq.thread0.memOrderViolation 3836 # Number of memory ordering violations 413system.cpu.iew.lsq.thread0.squashedStores 798446 # Number of stores squashed 414system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 415system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 416system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 417system.cpu.iew.lsq.thread0.cacheBlocked 13664 # Number of times an access to memory failed due to the cache being blocked 418system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 419system.cpu.iew.iewSquashCycles 3908647 # Number of cycles IEW is squashing 420system.cpu.iew.iewBlockCycles 40058 # Number of cycles IEW is blocking 421system.cpu.iew.iewUnblockCycles 10147 # Number of cycles IEW is unblocking 422system.cpu.iew.iewDispatchedInsts 118488563 # Number of instructions dispatched to IQ 423system.cpu.iew.iewDispSquashedInsts 346139 # Number of squashed instructions skipped by dispatch 424system.cpu.iew.iewDispLoadInsts 29574364 # Number of dispatched load instructions 425system.cpu.iew.iewDispStoreInsts 5545202 # Number of dispatched store instructions 426system.cpu.iew.iewDispNonSpecInsts 6435 # Number of dispatched non-speculative instructions 427system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall 428system.cpu.iew.iewLSQFullEvents 113 # Number of times the LSQ has become full, causing a stall 429system.cpu.iew.memOrderViolationEvents 3836 # Number of memory order violations 430system.cpu.iew.predictedTakenIncorrect 475714 # Number of branches that were predicted taken incorrectly 431system.cpu.iew.predictedNotTakenIncorrect 478249 # Number of branches that were predicted not taken incorrectly 432system.cpu.iew.branchMispredicts 953963 # Number of branch mispredicts detected at execute 433system.cpu.iew.iewExecutedInsts 104402584 # Number of executed instructions 434system.cpu.iew.iewExecLoadInsts 25308083 # Number of load instructions executed 435system.cpu.iew.iewExecSquashedInsts 1153876 # Number of squashed instructions skipped in execute 436system.cpu.iew.exec_swp 0 # number of swp insts executed 437system.cpu.iew.exec_nop 12730 # number of nop insts executed 438system.cpu.iew.exec_refs 30381749 # number of memory reference insts executed 439system.cpu.iew.exec_branches 21354330 # Number of branches executed 440system.cpu.iew.exec_stores 5073666 # Number of stores executed 441system.cpu.iew.exec_rate 2.064647 # Inst execution rate 442system.cpu.iew.wb_sent 103125475 # cumulative count of insts sent to commit 443system.cpu.iew.wb_count 102812012 # cumulative count of insts written-back 444system.cpu.iew.wb_producers 62190160 # num instructions producing a value 445system.cpu.iew.wb_consumers 104171478 # num instructions consuming a value 446system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 447system.cpu.iew.wb_rate 2.033192 # insts written-back per cycle 448system.cpu.iew.wb_fanout 0.596998 # average fanout of values written-back 449system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 450system.cpu.commit.commitSquashedInsts 27226534 # The number of squashed insts skipped by commit 451system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards 452system.cpu.commit.branchMispredicts 879646 # The number of times a branch was mispredicted 453system.cpu.commit.committed_per_cycle::samples 46630949 # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::mean 1.957123 # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::stdev 2.526822 # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::0 16429146 35.23% 35.23% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::1 13384342 28.70% 63.93% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::2 4483579 9.62% 73.55% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::3 3865779 8.29% 81.84% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::4 1521076 3.26% 85.10% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::5 802170 1.72% 86.82% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::6 837343 1.80% 88.62% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::7 265641 0.57% 89.19% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::8 5041873 10.81% 100.00% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::total 46630949 # Number of insts commited each cycle 470system.cpu.commit.committedInsts 90611967 # Number of instructions committed 471system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed 472system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 473system.cpu.commit.refs 27322634 # Number of memory references committed 474system.cpu.commit.loads 22575878 # Number of loads committed 475system.cpu.commit.membars 3888 # Number of memory barriers committed 476system.cpu.commit.branches 18734216 # Number of branches committed 477system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 478system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. 479system.cpu.commit.function_calls 56148 # Number of function calls committed. 480system.cpu.commit.bw_lim_events 5041873 # number cycles where commit BW limit reached 481system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 482system.cpu.rob.rob_reads 160072396 # The number of ROB reads 483system.cpu.rob.rob_writes 240909016 # The number of ROB writes 484system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself 485system.cpu.idleCycles 27201 # Total number of cycles that the CPU has spent unscheduled due to idling 486system.cpu.committedInsts 90599358 # Number of Instructions Simulated 487system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated 488system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated 489system.cpu.cpi 0.558136 # CPI: Cycles Per Instruction 490system.cpu.cpi_total 0.558136 # CPI: Total CPI of All Threads 491system.cpu.ipc 1.791677 # IPC: Instructions Per Cycle 492system.cpu.ipc_total 1.791677 # IPC: Total IPC of All Threads 493system.cpu.int_regfile_reads 496271114 # number of integer regfile reads 494system.cpu.int_regfile_writes 120718739 # number of integer regfile writes 495system.cpu.fp_regfile_reads 209 # number of floating regfile reads 496system.cpu.fp_regfile_writes 557 # number of floating regfile writes 497system.cpu.misc_regfile_reads 182190391 # number of misc regfile reads 498system.cpu.misc_regfile_writes 11608 # number of misc regfile writes 499system.cpu.icache.replacements 3 # number of replacements 500system.cpu.icache.tagsinuse 643.406523 # Cycle average of tags in use 501system.cpu.icache.total_refs 14027306 # Total number of references to valid blocks. 502system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks. 503system.cpu.icache.avg_refs 18853.905914 # Average number of references to valid blocks. 504system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 505system.cpu.icache.occ_blocks::cpu.inst 643.406523 # Average occupied blocks per requestor 506system.cpu.icache.occ_percent::cpu.inst 0.314163 # Average percentage of cache occupancy 507system.cpu.icache.occ_percent::total 0.314163 # Average percentage of cache occupancy 508system.cpu.icache.ReadReq_hits::cpu.inst 14027306 # number of ReadReq hits 509system.cpu.icache.ReadReq_hits::total 14027306 # number of ReadReq hits 510system.cpu.icache.demand_hits::cpu.inst 14027306 # number of demand (read+write) hits 511system.cpu.icache.demand_hits::total 14027306 # number of demand (read+write) hits 512system.cpu.icache.overall_hits::cpu.inst 14027306 # number of overall hits 513system.cpu.icache.overall_hits::total 14027306 # number of overall hits 514system.cpu.icache.ReadReq_misses::cpu.inst 974 # number of ReadReq misses 515system.cpu.icache.ReadReq_misses::total 974 # number of ReadReq misses 516system.cpu.icache.demand_misses::cpu.inst 974 # number of demand (read+write) misses 517system.cpu.icache.demand_misses::total 974 # number of demand (read+write) misses 518system.cpu.icache.overall_misses::cpu.inst 974 # number of overall misses 519system.cpu.icache.overall_misses::total 974 # number of overall misses 520system.cpu.icache.ReadReq_miss_latency::cpu.inst 30438500 # number of ReadReq miss cycles 521system.cpu.icache.ReadReq_miss_latency::total 30438500 # number of ReadReq miss cycles 522system.cpu.icache.demand_miss_latency::cpu.inst 30438500 # number of demand (read+write) miss cycles 523system.cpu.icache.demand_miss_latency::total 30438500 # number of demand (read+write) miss cycles 524system.cpu.icache.overall_miss_latency::cpu.inst 30438500 # number of overall miss cycles 525system.cpu.icache.overall_miss_latency::total 30438500 # number of overall miss cycles 526system.cpu.icache.ReadReq_accesses::cpu.inst 14028280 # number of ReadReq accesses(hits+misses) 527system.cpu.icache.ReadReq_accesses::total 14028280 # number of ReadReq accesses(hits+misses) 528system.cpu.icache.demand_accesses::cpu.inst 14028280 # number of demand (read+write) accesses 529system.cpu.icache.demand_accesses::total 14028280 # number of demand (read+write) accesses 530system.cpu.icache.overall_accesses::cpu.inst 14028280 # number of overall (read+write) accesses 531system.cpu.icache.overall_accesses::total 14028280 # number of overall (read+write) accesses 532system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses 533system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses 534system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses 535system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses 536system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses 537system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses 538system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31251.026694 # average ReadReq miss latency 539system.cpu.icache.ReadReq_avg_miss_latency::total 31251.026694 # average ReadReq miss latency 540system.cpu.icache.demand_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency 541system.cpu.icache.demand_avg_miss_latency::total 31251.026694 # average overall miss latency 542system.cpu.icache.overall_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency 543system.cpu.icache.overall_avg_miss_latency::total 31251.026694 # average overall miss latency 544system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 545system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 546system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 547system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 548system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 549system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 550system.cpu.icache.fast_writes 0 # number of fast writes performed 551system.cpu.icache.cache_copies 0 # number of cache copies performed 552system.cpu.icache.ReadReq_mshr_hits::cpu.inst 230 # number of ReadReq MSHR hits 553system.cpu.icache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits 554system.cpu.icache.demand_mshr_hits::cpu.inst 230 # number of demand (read+write) MSHR hits 555system.cpu.icache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits 556system.cpu.icache.overall_mshr_hits::cpu.inst 230 # number of overall MSHR hits 557system.cpu.icache.overall_mshr_hits::total 230 # number of overall MSHR hits 558system.cpu.icache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses 559system.cpu.icache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses 560system.cpu.icache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses 561system.cpu.icache.demand_mshr_misses::total 744 # number of demand (read+write) MSHR misses 562system.cpu.icache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses 563system.cpu.icache.overall_mshr_misses::total 744 # number of overall MSHR misses 564system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24024500 # number of ReadReq MSHR miss cycles 565system.cpu.icache.ReadReq_mshr_miss_latency::total 24024500 # number of ReadReq MSHR miss cycles 566system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24024500 # number of demand (read+write) MSHR miss cycles 567system.cpu.icache.demand_mshr_miss_latency::total 24024500 # number of demand (read+write) MSHR miss cycles 568system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24024500 # number of overall MSHR miss cycles 569system.cpu.icache.overall_mshr_miss_latency::total 24024500 # number of overall MSHR miss cycles 570system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses 572system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses 573system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 574system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses 575system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 576system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32290.994624 # average ReadReq mshr miss latency 577system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32290.994624 # average ReadReq mshr miss latency 578system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32290.994624 # average overall mshr miss latency 579system.cpu.icache.demand_avg_mshr_miss_latency::total 32290.994624 # average overall mshr miss latency 580system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32290.994624 # average overall mshr miss latency 581system.cpu.icache.overall_avg_mshr_miss_latency::total 32290.994624 # average overall mshr miss latency 582system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 583system.cpu.dcache.replacements 943584 # number of replacements 584system.cpu.dcache.tagsinuse 3642.676555 # Cycle average of tags in use 585system.cpu.dcache.total_refs 28382023 # Total number of references to valid blocks. 586system.cpu.dcache.sampled_refs 947680 # Sample count of references to valid blocks. 587system.cpu.dcache.avg_refs 29.948952 # Average number of references to valid blocks. 588system.cpu.dcache.warmup_cycle 8082482000 # Cycle when the warmup percentage was hit. 589system.cpu.dcache.occ_blocks::cpu.data 3642.676555 # Average occupied blocks per requestor 590system.cpu.dcache.occ_percent::cpu.data 0.889325 # Average percentage of cache occupancy 591system.cpu.dcache.occ_percent::total 0.889325 # Average percentage of cache occupancy 592system.cpu.dcache.ReadReq_hits::cpu.data 23788332 # number of ReadReq hits 593system.cpu.dcache.ReadReq_hits::total 23788332 # number of ReadReq hits 594system.cpu.dcache.WriteReq_hits::cpu.data 4582046 # number of WriteReq hits 595system.cpu.dcache.WriteReq_hits::total 4582046 # number of WriteReq hits 596system.cpu.dcache.LoadLockedReq_hits::cpu.data 5846 # number of LoadLockedReq hits 597system.cpu.dcache.LoadLockedReq_hits::total 5846 # number of LoadLockedReq hits 598system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits 599system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits 600system.cpu.dcache.demand_hits::cpu.data 28370378 # number of demand (read+write) hits 601system.cpu.dcache.demand_hits::total 28370378 # number of demand (read+write) hits 602system.cpu.dcache.overall_hits::cpu.data 28370378 # number of overall hits 603system.cpu.dcache.overall_hits::total 28370378 # number of overall hits 604system.cpu.dcache.ReadReq_misses::cpu.data 1007938 # number of ReadReq misses 605system.cpu.dcache.ReadReq_misses::total 1007938 # number of ReadReq misses 606system.cpu.dcache.WriteReq_misses::cpu.data 152935 # number of WriteReq misses 607system.cpu.dcache.WriteReq_misses::total 152935 # number of WriteReq misses 608system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses 609system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses 610system.cpu.dcache.demand_misses::cpu.data 1160873 # number of demand (read+write) misses 611system.cpu.dcache.demand_misses::total 1160873 # number of demand (read+write) misses 612system.cpu.dcache.overall_misses::cpu.data 1160873 # number of overall misses 613system.cpu.dcache.overall_misses::total 1160873 # number of overall misses 614system.cpu.dcache.ReadReq_miss_latency::cpu.data 4150084000 # number of ReadReq miss cycles 615system.cpu.dcache.ReadReq_miss_latency::total 4150084000 # number of ReadReq miss cycles 616system.cpu.dcache.WriteReq_miss_latency::cpu.data 2674625065 # number of WriteReq miss cycles 617system.cpu.dcache.WriteReq_miss_latency::total 2674625065 # number of WriteReq miss cycles 618system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118000 # number of LoadLockedReq miss cycles 619system.cpu.dcache.LoadLockedReq_miss_latency::total 118000 # number of LoadLockedReq miss cycles 620system.cpu.dcache.demand_miss_latency::cpu.data 6824709065 # number of demand (read+write) miss cycles 621system.cpu.dcache.demand_miss_latency::total 6824709065 # number of demand (read+write) miss cycles 622system.cpu.dcache.overall_miss_latency::cpu.data 6824709065 # number of overall miss cycles 623system.cpu.dcache.overall_miss_latency::total 6824709065 # number of overall miss cycles 624system.cpu.dcache.ReadReq_accesses::cpu.data 24796270 # number of ReadReq accesses(hits+misses) 625system.cpu.dcache.ReadReq_accesses::total 24796270 # number of ReadReq accesses(hits+misses) 626system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 627system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 628system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5854 # number of LoadLockedReq accesses(hits+misses) 629system.cpu.dcache.LoadLockedReq_accesses::total 5854 # number of LoadLockedReq accesses(hits+misses) 630system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) 631system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) 632system.cpu.dcache.demand_accesses::cpu.data 29531251 # number of demand (read+write) accesses 633system.cpu.dcache.demand_accesses::total 29531251 # number of demand (read+write) accesses 634system.cpu.dcache.overall_accesses::cpu.data 29531251 # number of overall (read+write) accesses 635system.cpu.dcache.overall_accesses::total 29531251 # number of overall (read+write) accesses 636system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040649 # miss rate for ReadReq accesses 637system.cpu.dcache.ReadReq_miss_rate::total 0.040649 # miss rate for ReadReq accesses 638system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032299 # miss rate for WriteReq accesses 639system.cpu.dcache.WriteReq_miss_rate::total 0.032299 # miss rate for WriteReq accesses 640system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001367 # miss rate for LoadLockedReq accesses 641system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001367 # miss rate for LoadLockedReq accesses 642system.cpu.dcache.demand_miss_rate::cpu.data 0.039310 # miss rate for demand accesses 643system.cpu.dcache.demand_miss_rate::total 0.039310 # miss rate for demand accesses 644system.cpu.dcache.overall_miss_rate::cpu.data 0.039310 # miss rate for overall accesses 645system.cpu.dcache.overall_miss_rate::total 0.039310 # miss rate for overall accesses 646system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4117.400078 # average ReadReq miss latency 647system.cpu.dcache.ReadReq_avg_miss_latency::total 4117.400078 # average ReadReq miss latency 648system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17488.639389 # average WriteReq miss latency 649system.cpu.dcache.WriteReq_avg_miss_latency::total 17488.639389 # average WriteReq miss latency 650system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14750 # average LoadLockedReq miss latency 651system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14750 # average LoadLockedReq miss latency 652system.cpu.dcache.demand_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency 653system.cpu.dcache.demand_avg_miss_latency::total 5878.945470 # average overall miss latency 654system.cpu.dcache.overall_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency 655system.cpu.dcache.overall_avg_miss_latency::total 5878.945470 # average overall miss latency 656system.cpu.dcache.blocked_cycles::no_mshrs 12644 # number of cycles access was blocked 657system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked 659system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.939561 # average number of cycles each access was blocked 661system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.dcache.fast_writes 0 # number of fast writes performed 663system.cpu.dcache.cache_copies 0 # number of cache copies performed 664system.cpu.dcache.writebacks::writebacks 942946 # number of writebacks 665system.cpu.dcache.writebacks::total 942946 # number of writebacks 666system.cpu.dcache.ReadReq_mshr_hits::cpu.data 94900 # number of ReadReq MSHR hits 667system.cpu.dcache.ReadReq_mshr_hits::total 94900 # number of ReadReq MSHR hits 668system.cpu.dcache.WriteReq_mshr_hits::cpu.data 118293 # number of WriteReq MSHR hits 669system.cpu.dcache.WriteReq_mshr_hits::total 118293 # number of WriteReq MSHR hits 670system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits 671system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits 672system.cpu.dcache.demand_mshr_hits::cpu.data 213193 # number of demand (read+write) MSHR hits 673system.cpu.dcache.demand_mshr_hits::total 213193 # number of demand (read+write) MSHR hits 674system.cpu.dcache.overall_mshr_hits::cpu.data 213193 # number of overall MSHR hits 675system.cpu.dcache.overall_mshr_hits::total 213193 # number of overall MSHR hits 676system.cpu.dcache.ReadReq_mshr_misses::cpu.data 913038 # number of ReadReq MSHR misses 677system.cpu.dcache.ReadReq_mshr_misses::total 913038 # number of ReadReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::cpu.data 34642 # number of WriteReq MSHR misses 679system.cpu.dcache.WriteReq_mshr_misses::total 34642 # number of WriteReq MSHR misses 680system.cpu.dcache.demand_mshr_misses::cpu.data 947680 # number of demand (read+write) MSHR misses 681system.cpu.dcache.demand_mshr_misses::total 947680 # number of demand (read+write) MSHR misses 682system.cpu.dcache.overall_mshr_misses::cpu.data 947680 # number of overall MSHR misses 683system.cpu.dcache.overall_mshr_misses::total 947680 # number of overall MSHR misses 684system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1880090500 # number of ReadReq MSHR miss cycles 685system.cpu.dcache.ReadReq_mshr_miss_latency::total 1880090500 # number of ReadReq MSHR miss cycles 686system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 538394011 # number of WriteReq MSHR miss cycles 687system.cpu.dcache.WriteReq_mshr_miss_latency::total 538394011 # number of WriteReq MSHR miss cycles 688system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2418484511 # number of demand (read+write) MSHR miss cycles 689system.cpu.dcache.demand_mshr_miss_latency::total 2418484511 # number of demand (read+write) MSHR miss cycles 690system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2418484511 # number of overall MSHR miss cycles 691system.cpu.dcache.overall_mshr_miss_latency::total 2418484511 # number of overall MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036822 # mshr miss rate for ReadReq accesses 693system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036822 # mshr miss rate for ReadReq accesses 694system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007316 # mshr miss rate for WriteReq accesses 695system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007316 # mshr miss rate for WriteReq accesses 696system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032091 # mshr miss rate for demand accesses 697system.cpu.dcache.demand_mshr_miss_rate::total 0.032091 # mshr miss rate for demand accesses 698system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032091 # mshr miss rate for overall accesses 699system.cpu.dcache.overall_mshr_miss_rate::total 0.032091 # mshr miss rate for overall accesses 700system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2059.159093 # average ReadReq mshr miss latency 701system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2059.159093 # average ReadReq mshr miss latency 702system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15541.654956 # average WriteReq mshr miss latency 703system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15541.654956 # average WriteReq mshr miss latency 704system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2552.005435 # average overall mshr miss latency 705system.cpu.dcache.demand_avg_mshr_miss_latency::total 2552.005435 # average overall mshr miss latency 706system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2552.005435 # average overall mshr miss latency 707system.cpu.dcache.overall_avg_mshr_miss_latency::total 2552.005435 # average overall mshr miss latency 708system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 709system.cpu.l2cache.replacements 0 # number of replacements 710system.cpu.l2cache.tagsinuse 10470.960701 # Cycle average of tags in use 711system.cpu.l2cache.total_refs 1840613 # Total number of references to valid blocks. 712system.cpu.l2cache.sampled_refs 15503 # Sample count of references to valid blocks. 713system.cpu.l2cache.avg_refs 118.726247 # Average number of references to valid blocks. 714system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 715system.cpu.l2cache.occ_blocks::writebacks 9615.271069 # Average occupied blocks per requestor 716system.cpu.l2cache.occ_blocks::cpu.inst 626.227168 # Average occupied blocks per requestor 717system.cpu.l2cache.occ_blocks::cpu.data 229.462463 # Average occupied blocks per requestor 718system.cpu.l2cache.occ_percent::writebacks 0.293435 # Average percentage of cache occupancy 719system.cpu.l2cache.occ_percent::cpu.inst 0.019111 # Average percentage of cache occupancy 720system.cpu.l2cache.occ_percent::cpu.data 0.007003 # Average percentage of cache occupancy 721system.cpu.l2cache.occ_percent::total 0.319548 # Average percentage of cache occupancy 722system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits 723system.cpu.l2cache.ReadReq_hits::cpu.data 912759 # number of ReadReq hits 724system.cpu.l2cache.ReadReq_hits::total 912786 # number of ReadReq hits 725system.cpu.l2cache.Writeback_hits::writebacks 942946 # number of Writeback hits 726system.cpu.l2cache.Writeback_hits::total 942946 # number of Writeback hits 727system.cpu.l2cache.ReadExReq_hits::cpu.data 20105 # number of ReadExReq hits 728system.cpu.l2cache.ReadExReq_hits::total 20105 # number of ReadExReq hits 729system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits 730system.cpu.l2cache.demand_hits::cpu.data 932864 # number of demand (read+write) hits 731system.cpu.l2cache.demand_hits::total 932891 # number of demand (read+write) hits 732system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits 733system.cpu.l2cache.overall_hits::cpu.data 932864 # number of overall hits 734system.cpu.l2cache.overall_hits::total 932891 # number of overall hits 735system.cpu.l2cache.ReadReq_misses::cpu.inst 717 # number of ReadReq misses 736system.cpu.l2cache.ReadReq_misses::cpu.data 278 # number of ReadReq misses 737system.cpu.l2cache.ReadReq_misses::total 995 # number of ReadReq misses 738system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 739system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 740system.cpu.l2cache.demand_misses::cpu.inst 717 # number of demand (read+write) misses 741system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses 742system.cpu.l2cache.demand_misses::total 15533 # number of demand (read+write) misses 743system.cpu.l2cache.overall_misses::cpu.inst 717 # number of overall misses 744system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses 745system.cpu.l2cache.overall_misses::total 15533 # number of overall misses 746system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23240500 # number of ReadReq miss cycles 747system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9566500 # number of ReadReq miss cycles 748system.cpu.l2cache.ReadReq_miss_latency::total 32807000 # number of ReadReq miss cycles 749system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 335686000 # number of ReadExReq miss cycles 750system.cpu.l2cache.ReadExReq_miss_latency::total 335686000 # number of ReadExReq miss cycles 751system.cpu.l2cache.demand_miss_latency::cpu.inst 23240500 # number of demand (read+write) miss cycles 752system.cpu.l2cache.demand_miss_latency::cpu.data 345252500 # number of demand (read+write) miss cycles 753system.cpu.l2cache.demand_miss_latency::total 368493000 # number of demand (read+write) miss cycles 754system.cpu.l2cache.overall_miss_latency::cpu.inst 23240500 # number of overall miss cycles 755system.cpu.l2cache.overall_miss_latency::cpu.data 345252500 # number of overall miss cycles 756system.cpu.l2cache.overall_miss_latency::total 368493000 # number of overall miss cycles 757system.cpu.l2cache.ReadReq_accesses::cpu.inst 744 # number of ReadReq accesses(hits+misses) 758system.cpu.l2cache.ReadReq_accesses::cpu.data 913037 # number of ReadReq accesses(hits+misses) 759system.cpu.l2cache.ReadReq_accesses::total 913781 # number of ReadReq accesses(hits+misses) 760system.cpu.l2cache.Writeback_accesses::writebacks 942946 # number of Writeback accesses(hits+misses) 761system.cpu.l2cache.Writeback_accesses::total 942946 # number of Writeback accesses(hits+misses) 762system.cpu.l2cache.ReadExReq_accesses::cpu.data 34643 # number of ReadExReq accesses(hits+misses) 763system.cpu.l2cache.ReadExReq_accesses::total 34643 # number of ReadExReq accesses(hits+misses) 764system.cpu.l2cache.demand_accesses::cpu.inst 744 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::cpu.data 947680 # number of demand (read+write) accesses 766system.cpu.l2cache.demand_accesses::total 948424 # number of demand (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.inst 744 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::cpu.data 947680 # number of overall (read+write) accesses 769system.cpu.l2cache.overall_accesses::total 948424 # number of overall (read+write) accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963710 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses 773system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419652 # miss rate for ReadExReq accesses 774system.cpu.l2cache.ReadExReq_miss_rate::total 0.419652 # miss rate for ReadExReq accesses 775system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963710 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::total 0.016378 # miss rate for demand accesses 778system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963710 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::total 0.016378 # miss rate for overall accesses 781system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32413.528591 # average ReadReq miss latency 782system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34411.870504 # average ReadReq miss latency 783system.cpu.l2cache.ReadReq_avg_miss_latency::total 32971.859296 # average ReadReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 23090.246251 # average ReadExReq miss latency 785system.cpu.l2cache.ReadExReq_avg_miss_latency::total 23090.246251 # average ReadExReq miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32413.528591 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::cpu.data 23302.679536 # average overall miss latency 788system.cpu.l2cache.demand_avg_miss_latency::total 23723.234404 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32413.528591 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::cpu.data 23302.679536 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::total 23723.234404 # average overall miss latency 792system.cpu.l2cache.blocked_cycles::no_mshrs 27 # number of cycles access was blocked 793system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 795system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked 797system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 798system.cpu.l2cache.fast_writes 0 # number of fast writes performed 799system.cpu.l2cache.cache_copies 0 # number of cache copies performed 800system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 801system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits 802system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits 803system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 804system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 805system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 806system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 807system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 808system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits 809system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 715 # number of ReadReq MSHR misses 810system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses 811system.cpu.l2cache.ReadReq_mshr_misses::total 982 # number of ReadReq MSHR misses 812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 814system.cpu.l2cache.demand_mshr_misses::cpu.inst 715 # number of demand (read+write) MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.overall_mshr_misses::cpu.inst 715 # number of overall MSHR misses 818system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses 820system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20653050 # number of ReadReq MSHR miss cycles 821system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8351373 # number of ReadReq MSHR miss cycles 822system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29004423 # number of ReadReq MSHR miss cycles 823system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 284430809 # number of ReadExReq MSHR miss cycles 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 284430809 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20653050 # number of demand (read+write) MSHR miss cycles 826system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 292782182 # number of demand (read+write) MSHR miss cycles 827system.cpu.l2cache.demand_mshr_miss_latency::total 313435232 # number of demand (read+write) MSHR miss cycles 828system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20653050 # number of overall MSHR miss cycles 829system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 292782182 # number of overall MSHR miss cycles 830system.cpu.l2cache.overall_mshr_miss_latency::total 313435232 # number of overall MSHR miss cycles 831system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for ReadReq accesses 832system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001075 # mshr miss rate for ReadReq accesses 834system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419652 # mshr miss rate for ReadExReq accesses 835system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419652 # mshr miss rate for ReadExReq accesses 836system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for demand accesses 837system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses 838system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses 839system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for overall accesses 840system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses 841system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses 842system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28885.384615 # average ReadReq mshr miss latency 843system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31278.550562 # average ReadReq mshr miss latency 844system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29536.072301 # average ReadReq mshr miss latency 845system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19564.644999 # average ReadExReq mshr miss latency 846system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19564.644999 # average ReadExReq mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency 849system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency 853system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 854 855---------- End Simulation Statistics ---------- 856