stats.txt revision 11336:b318499f676c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058179 # Number of seconds simulated 4sim_ticks 58178990500 # Number of ticks simulated 5final_tick 58178990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 122973 # Simulator instruction rate (inst/s) 8host_op_rate 123585 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 78976040 # Simulator tick rate (ticks/s) 10host_mem_usage 539340 # Number of bytes of host memory used 11host_seconds 736.67 # Real time elapsed on the host 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44864 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 57344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 923968 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1026176 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44864 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44864 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 10880 # Number of bytes written to this memory 23system.physmem.bytes_written::total 10880 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 701 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 896 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 14437 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 16034 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 170 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 170 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 771137 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 985648 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 15881472 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 17638257 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 771137 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 771137 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 187009 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 187009 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 187009 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 771137 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 985648 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 15881472 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17825266 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 16035 # Number of read requests accepted 44system.physmem.writeReqs 170 # Number of write requests accepted 45system.physmem.readBursts 16035 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 170 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1017600 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue 49system.physmem.bytesWritten 9088 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1026240 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10880 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 1166 # Per bank write bursts 56system.physmem.perBankRdBursts::1 919 # Per bank write bursts 57system.physmem.perBankRdBursts::2 953 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1033 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1062 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1116 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1091 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1089 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts 65system.physmem.perBankRdBursts::10 937 # Per bank write bursts 66system.physmem.perBankRdBursts::11 900 # Per bank write bursts 67system.physmem.perBankRdBursts::12 906 # Per bank write bursts 68system.physmem.perBankRdBursts::13 899 # Per bank write bursts 69system.physmem.perBankRdBursts::14 910 # Per bank write bursts 70system.physmem.perBankRdBursts::15 933 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7 # Per bank write bursts 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts 73system.physmem.perBankWrBursts::2 12 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4 # Per bank write bursts 75system.physmem.perBankWrBursts::4 3 # Per bank write bursts 76system.physmem.perBankWrBursts::5 12 # Per bank write bursts 77system.physmem.perBankWrBursts::6 37 # Per bank write bursts 78system.physmem.perBankWrBursts::7 2 # Per bank write bursts 79system.physmem.perBankWrBursts::8 2 # Per bank write bursts 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7 # Per bank write bursts 84system.physmem.perBankWrBursts::13 12 # Per bank write bursts 85system.physmem.perBankWrBursts::14 33 # Per bank write bursts 86system.physmem.perBankWrBursts::15 1 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 58178982000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 16035 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 170 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 10985 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2530 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 393 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 293 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 1792 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 572.928571 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 339.689561 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 430.205419 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 476 26.56% 26.56% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 210 11.72% 38.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 97 5.41% 43.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 63 3.52% 47.21% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 46 2.57% 49.78% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 57 3.18% 52.96% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 50 2.79% 55.75% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 48 2.68% 58.43% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 745 41.57% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 1792 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 1980.250000 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 75.328493 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 5451.280656 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 17.750000 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 17.736929 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 0.707107 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 7 87.50% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 228system.physmem.totQLat 173529353 # Total ticks spent queuing 229system.physmem.totMemAccLat 471654353 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 79500000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 10913.11 # Average queueing delay per DRAM burst 232system.physmem.avgBusLat 4999.69 # Average bus latency per DRAM burst 233system.physmem.avgMemAccLat 29661.93 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 17.49 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 17.64 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.14 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 20.26 # Average write queue length when enqueuing 244system.physmem.readRowHits 14205 # Number of row buffer hits during reads 245system.physmem.writeRowHits 45 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 27.11 # Row buffer hit rate for writes 248system.physmem.avgGap 3590187.10 # Average gap between requests 249system.physmem.pageHitRate 88.69 # Row buffer hit rate, read and write combined 250system.physmem_0.actEnergy 7794360 # Energy for activate commands per rank (pJ) 251system.physmem_0.preEnergy 4252875 # Energy for precharge commands per rank (pJ) 252system.physmem_0.readEnergy 65746200 # Energy for read commands per rank (pJ) 253system.physmem_0.writeEnergy 498960 # Energy for write commands per rank (pJ) 254system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) 255system.physmem_0.actBackEnergy 2649738195 # Energy for active background per rank (pJ) 256system.physmem_0.preBackEnergy 32583140250 # Energy for precharge background per rank (pJ) 257system.physmem_0.totalEnergy 39111131160 # Total energy per rank (pJ) 258system.physmem_0.averagePower 672.253743 # Core power per rank (mW) 259system.physmem_0.memoryStateTime::IDLE 54193285294 # Time in different power states 260system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states 261system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 262system.physmem_0.memoryStateTime::ACT 2043128456 # Time in different power states 263system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 264system.physmem_1.actEnergy 5753160 # Energy for activate commands per rank (pJ) 265system.physmem_1.preEnergy 3139125 # Energy for precharge commands per rank (pJ) 266system.physmem_1.readEnergy 58273800 # Energy for read commands per rank (pJ) 267system.physmem_1.writeEnergy 421200 # Energy for write commands per rank (pJ) 268system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) 269system.physmem_1.actBackEnergy 2342596545 # Energy for active background per rank (pJ) 270system.physmem_1.preBackEnergy 32852562750 # Energy for precharge background per rank (pJ) 271system.physmem_1.totalEnergy 39062706900 # Total energy per rank (pJ) 272system.physmem_1.averagePower 671.421412 # Core power per rank (mW) 273system.physmem_1.memoryStateTime::IDLE 54644034494 # Time in different power states 274system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states 275system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 276system.physmem_1.memoryStateTime::ACT 1592379256 # Time in different power states 277system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 278system.cpu.branchPred.lookups 28257760 # Number of BP lookups 279system.cpu.branchPred.condPredicted 23279733 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 837848 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 11842330 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 11784674 # Number of BTB hits 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 284system.cpu.branchPred.BTBHitPct 99.513136 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 75804 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. 287system.cpu_clk_domain.clock 500 # Clock period in ticks 288system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 297system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 298system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 299system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 300system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 306system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 307system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 308system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 309system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 310system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 312system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 313system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 314system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 315system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 316system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 317system.cpu.dtb.walker.walks 0 # Table walker walks requested 318system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.inst_hits 0 # ITB inst hits 326system.cpu.dtb.inst_misses 0 # ITB inst misses 327system.cpu.dtb.read_hits 0 # DTB read hits 328system.cpu.dtb.read_misses 0 # DTB read misses 329system.cpu.dtb.write_hits 0 # DTB write hits 330system.cpu.dtb.write_misses 0 # DTB write misses 331system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.dtb.read_accesses 0 # DTB read accesses 341system.cpu.dtb.write_accesses 0 # DTB write accesses 342system.cpu.dtb.inst_accesses 0 # ITB inst accesses 343system.cpu.dtb.hits 0 # DTB hits 344system.cpu.dtb.misses 0 # DTB misses 345system.cpu.dtb.accesses 0 # DTB accesses 346system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 355system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 356system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 357system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 358system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 359system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 360system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 375system.cpu.itb.walker.walks 0 # Table walker walks requested 376system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.inst_hits 0 # ITB inst hits 384system.cpu.itb.inst_misses 0 # ITB inst misses 385system.cpu.itb.read_hits 0 # DTB read hits 386system.cpu.itb.read_misses 0 # DTB read misses 387system.cpu.itb.write_hits 0 # DTB write hits 388system.cpu.itb.write_misses 0 # DTB write misses 389system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 390system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 391system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 392system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 393system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 394system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 395system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 396system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.itb.read_accesses 0 # DTB read accesses 399system.cpu.itb.write_accesses 0 # DTB write accesses 400system.cpu.itb.inst_accesses 0 # ITB inst accesses 401system.cpu.itb.hits 0 # DTB hits 402system.cpu.itb.misses 0 # DTB misses 403system.cpu.itb.accesses 0 # DTB accesses 404system.cpu.workload.num_syscalls 442 # Number of system calls 405system.cpu.numCycles 116357982 # number of cpu cycles simulated 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.fetch.icacheStallCycles 748703 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 134988401 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 28257760 # Number of branches that fetch encountered 411system.cpu.fetch.predictedBranches 11860478 # Number of branches that fetch has predicted taken 412system.cpu.fetch.Cycles 114715121 # Number of cycles fetch has run and was not squashing or blocked 413system.cpu.fetch.SquashCycles 1679113 # Number of cycles fetch has spent squashing 414system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 415system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR 416system.cpu.fetch.CacheLines 32302514 # Number of cache lines fetched 417system.cpu.fetch.IcacheSquashes 574 # Number of outstanding Icache misses that were squashed 418system.cpu.fetch.rateDist::samples 116305190 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::mean 1.165894 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::0 58733287 50.50% 50.50% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::1 13942631 11.99% 62.49% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::2 9230901 7.94% 70.42% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::3 34398371 29.58% 100.00% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::total 116305190 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.branchRate 0.242852 # Number of branch fetches per cycle 431system.cpu.fetch.rate 1.160113 # Number of inst fetches per cycle 432system.cpu.decode.IdleCycles 8839704 # Number of cycles decode is idle 433system.cpu.decode.BlockedCycles 64044923 # Number of cycles decode is blocked 434system.cpu.decode.RunCycles 33035218 # Number of cycles decode is running 435system.cpu.decode.UnblockCycles 9558027 # Number of cycles decode is unblocking 436system.cpu.decode.SquashCycles 827318 # Number of cycles decode is squashing 437system.cpu.decode.BranchResolved 4101316 # Number of times decode resolved a branch 438system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction 439system.cpu.decode.DecodedInsts 114430969 # Number of instructions handled by decode 440system.cpu.decode.SquashedInsts 1996281 # Number of squashed instructions handled by decode 441system.cpu.rename.SquashCycles 827318 # Number of cycles rename is squashing 442system.cpu.rename.IdleCycles 15281065 # Number of cycles rename is idle 443system.cpu.rename.BlockCycles 49888125 # Number of cycles rename is blocking 444system.cpu.rename.serializeStallCycles 109559 # count of cycles rename stalled for serializing inst 445system.cpu.rename.RunCycles 35425090 # Number of cycles rename is running 446system.cpu.rename.UnblockCycles 14774033 # Number of cycles rename is unblocking 447system.cpu.rename.RenamedInsts 110899108 # Number of instructions processed by rename 448system.cpu.rename.SquashedInsts 1414941 # Number of squashed instructions processed by rename 449system.cpu.rename.ROBFullEvents 11132282 # Number of times rename has blocked due to ROB full 450system.cpu.rename.IQFullEvents 1143663 # Number of times rename has blocked due to IQ full 451system.cpu.rename.LQFullEvents 1527047 # Number of times rename has blocked due to LQ full 452system.cpu.rename.SQFullEvents 487517 # Number of times rename has blocked due to SQ full 453system.cpu.rename.RenamedOperands 129956871 # Number of destination operands rename has renamed 454system.cpu.rename.RenameLookups 483273963 # Number of register rename lookups that rename has made 455system.cpu.rename.int_rename_lookups 119474159 # Number of integer rename lookups 456system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups 457system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 458system.cpu.rename.UndoneMaps 22643952 # Number of HB maps that are undone due to squashing 459system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed 460system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed 461system.cpu.rename.skidInsts 21508074 # count of insts added to the skid buffer 462system.cpu.memDep0.insertedLoads 26812702 # Number of loads inserted to the mem dependence unit. 463system.cpu.memDep0.insertedStores 5350076 # Number of stores inserted to the mem dependence unit. 464system.cpu.memDep0.conflictingLoads 518927 # Number of conflicting loads. 465system.cpu.memDep0.conflictingStores 253927 # Number of conflicting stores. 466system.cpu.iq.iqInstsAdded 109691489 # Number of instructions added to the IQ (excludes non-spec) 467system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ 468system.cpu.iq.iqInstsIssued 101389067 # Number of instructions issued 469system.cpu.iq.iqSquashedInstsIssued 1075877 # Number of squashed instructions issued 470system.cpu.iq.iqSquashedInstsExamined 18658707 # Number of squashed instructions iterated over during squash; mainly for profiling 471system.cpu.iq.iqSquashedOperandsExamined 41691247 # Number of squashed operands that are examined and possibly removed from graph 472system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed 473system.cpu.iq.issued_per_cycle::samples 116305190 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::mean 0.871750 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::stdev 0.989327 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::0 54664640 47.00% 47.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::1 31360805 26.96% 73.97% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::2 22009670 18.92% 92.89% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::3 7071691 6.08% 98.97% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::4 1198071 1.03% 100.00% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::total 116305190 # Number of insts issued each cycle 490system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::IntAlu 9787073 48.68% 48.68% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available 494system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.68% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.68% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatMult 0 0.00% 48.68% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.68% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.68% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.68% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.68% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.68% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.68% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.68% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.68% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMult 0 0.00% 48.68% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.68% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdShift 0 0.00% 48.68% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.68% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.68% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.68% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.68% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.68% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.68% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.68% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available 520system.cpu.iq.fu_full::MemRead 9614641 47.82% 96.50% # attempts to use FU when none available 521system.cpu.iq.fu_full::MemWrite 704123 3.50% 100.00% # attempts to use FU when none available 522system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 523system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 524system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 525system.cpu.iq.FU_type_0::IntAlu 71985140 71.00% 71.00% # Type of FU issued 526system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued 527system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 528system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 554system.cpu.iq.FU_type_0::MemRead 24343416 24.01% 95.02% # Type of FU issued 555system.cpu.iq.FU_type_0::MemWrite 5049618 4.98% 100.00% # Type of FU issued 556system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::total 101389067 # Type of FU issued 559system.cpu.iq.rate 0.871355 # Inst issue rate 560system.cpu.iq.fu_busy_cnt 20105900 # FU busy when requested 561system.cpu.iq.fu_busy_rate 0.198304 # FU busy rate (busy events/executed inst) 562system.cpu.iq.int_inst_queue_reads 340264641 # Number of integer instruction queue reads 563system.cpu.iq.int_inst_queue_writes 128359131 # Number of integer instruction queue writes 564system.cpu.iq.int_inst_queue_wakeup_accesses 99626279 # Number of integer instruction queue wakeup accesses 565system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 566system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes 567system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses 568system.cpu.iq.int_alu_accesses 121494727 # Number of integer alu accesses 569system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses 570system.cpu.iew.lsq.thread0.forwLoads 289423 # Number of loads that had data forwarded from stores 571system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 572system.cpu.iew.lsq.thread0.squashedLoads 4336791 # Number of loads squashed 573system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed 574system.cpu.iew.lsq.thread0.memOrderViolation 1348 # Number of memory ordering violations 575system.cpu.iew.lsq.thread0.squashedStores 605232 # Number of stores squashed 576system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 577system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 578system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled 579system.cpu.iew.lsq.thread0.cacheBlocked 130606 # Number of times an access to memory failed due to the cache being blocked 580system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 581system.cpu.iew.iewSquashCycles 827318 # Number of cycles IEW is squashing 582system.cpu.iew.iewBlockCycles 8114310 # Number of cycles IEW is blocking 583system.cpu.iew.iewUnblockCycles 683997 # Number of cycles IEW is unblocking 584system.cpu.iew.iewDispatchedInsts 109712406 # Number of instructions dispatched to IQ 585system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 586system.cpu.iew.iewDispLoadInsts 26812702 # Number of dispatched load instructions 587system.cpu.iew.iewDispStoreInsts 5350076 # Number of dispatched store instructions 588system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions 589system.cpu.iew.iewIQFullEvents 178818 # Number of times the IQ has become full, causing a stall 590system.cpu.iew.iewLSQFullEvents 342272 # Number of times the LSQ has become full, causing a stall 591system.cpu.iew.memOrderViolationEvents 1348 # Number of memory order violations 592system.cpu.iew.predictedTakenIncorrect 436595 # Number of branches that were predicted taken incorrectly 593system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly 594system.cpu.iew.branchMispredicts 849476 # Number of branch mispredicts detected at execute 595system.cpu.iew.iewExecutedInsts 100127969 # Number of executed instructions 596system.cpu.iew.iewExecLoadInsts 23806710 # Number of load instructions executed 597system.cpu.iew.iewExecSquashedInsts 1261098 # Number of squashed instructions skipped in execute 598system.cpu.iew.exec_swp 0 # number of swp insts executed 599system.cpu.iew.exec_nop 12669 # number of nop insts executed 600system.cpu.iew.exec_refs 28724643 # number of memory reference insts executed 601system.cpu.iew.exec_branches 20624882 # Number of branches executed 602system.cpu.iew.exec_stores 4917933 # Number of stores executed 603system.cpu.iew.exec_rate 0.860517 # Inst execution rate 604system.cpu.iew.wb_sent 99711034 # cumulative count of insts sent to commit 605system.cpu.iew.wb_count 99626392 # cumulative count of insts written-back 606system.cpu.iew.wb_producers 59704097 # num instructions producing a value 607system.cpu.iew.wb_consumers 95546076 # num instructions consuming a value 608system.cpu.iew.wb_rate 0.856206 # insts written-back per cycle 609system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back 610system.cpu.commit.commitSquashedInsts 17384953 # The number of squashed insts skipped by commit 611system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 612system.cpu.commit.branchMispredicts 825610 # The number of times a branch was mispredicted 613system.cpu.commit.committed_per_cycle::samples 113612998 # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::mean 0.801437 # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::stdev 1.737923 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::0 77188479 67.94% 67.94% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::1 18612991 16.38% 84.32% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::2 7152574 6.30% 90.62% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::3 3468909 3.05% 93.67% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::4 1644585 1.45% 95.12% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::5 541952 0.48% 95.60% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::6 704226 0.62% 96.22% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::7 178939 0.16% 96.37% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::8 4120343 3.63% 100.00% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::total 113612998 # Number of insts commited each cycle 630system.cpu.commit.committedInsts 90602408 # Number of instructions committed 631system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 632system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 633system.cpu.commit.refs 27220755 # Number of memory references committed 634system.cpu.commit.loads 22475911 # Number of loads committed 635system.cpu.commit.membars 3888 # Number of memory barriers committed 636system.cpu.commit.branches 18732305 # Number of branches committed 637system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 638system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 639system.cpu.commit.function_calls 56148 # Number of function calls committed. 640system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 641system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 642system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 643system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 644system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 645system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 670system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 671system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 672system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 673system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 675system.cpu.commit.bw_lim_events 4120343 # number cycles where commit BW limit reached 676system.cpu.rob.rob_reads 217925513 # The number of ROB reads 677system.cpu.rob.rob_writes 219569964 # The number of ROB writes 678system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself 679system.cpu.idleCycles 52792 # Total number of cycles that the CPU has spent unscheduled due to idling 680system.cpu.committedInsts 90589799 # Number of Instructions Simulated 681system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 682system.cpu.cpi 1.284449 # CPI: Cycles Per Instruction 683system.cpu.cpi_total 1.284449 # CPI: Total CPI of All Threads 684system.cpu.ipc 0.778544 # IPC: Instructions Per Cycle 685system.cpu.ipc_total 0.778544 # IPC: Total IPC of All Threads 686system.cpu.int_regfile_reads 108112150 # number of integer regfile reads 687system.cpu.int_regfile_writes 58701199 # number of integer regfile writes 688system.cpu.fp_regfile_reads 58 # number of floating regfile reads 689system.cpu.fp_regfile_writes 93 # number of floating regfile writes 690system.cpu.cc_regfile_reads 369067542 # number of cc regfile reads 691system.cpu.cc_regfile_writes 58693892 # number of cc regfile writes 692system.cpu.misc_regfile_reads 28415154 # number of misc regfile reads 693system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 694system.cpu.dcache.tags.replacements 5470195 # number of replacements 695system.cpu.dcache.tags.tagsinuse 511.784912 # Cycle average of tags in use 696system.cpu.dcache.tags.total_refs 18253010 # Total number of references to valid blocks. 697system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. 698system.cpu.dcache.tags.avg_refs 3.336499 # Average number of references to valid blocks. 699system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. 700system.cpu.dcache.tags.occ_blocks::cpu.data 511.784912 # Average occupied blocks per requestor 701system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy 702system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy 703system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 704system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id 705system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 706system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 707system.cpu.dcache.tags.tag_accesses 61911209 # Number of tag accesses 708system.cpu.dcache.tags.data_accesses 61911209 # Number of data accesses 709system.cpu.dcache.ReadReq_hits::cpu.data 13890997 # number of ReadReq hits 710system.cpu.dcache.ReadReq_hits::total 13890997 # number of ReadReq hits 711system.cpu.dcache.WriteReq_hits::cpu.data 4353726 # number of WriteReq hits 712system.cpu.dcache.WriteReq_hits::total 4353726 # number of WriteReq hits 713system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 714system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 715system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 716system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits 717system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 718system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 719system.cpu.dcache.demand_hits::cpu.data 18244723 # number of demand (read+write) hits 720system.cpu.dcache.demand_hits::total 18244723 # number of demand (read+write) hits 721system.cpu.dcache.overall_hits::cpu.data 18245245 # number of overall hits 722system.cpu.dcache.overall_hits::total 18245245 # number of overall hits 723system.cpu.dcache.ReadReq_misses::cpu.data 9585970 # number of ReadReq misses 724system.cpu.dcache.ReadReq_misses::total 9585970 # number of ReadReq misses 725system.cpu.dcache.WriteReq_misses::cpu.data 381255 # number of WriteReq misses 726system.cpu.dcache.WriteReq_misses::total 381255 # number of WriteReq misses 727system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 728system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 729system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 730system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 731system.cpu.dcache.demand_misses::cpu.data 9967225 # number of demand (read+write) misses 732system.cpu.dcache.demand_misses::total 9967225 # number of demand (read+write) misses 733system.cpu.dcache.overall_misses::cpu.data 9967232 # number of overall misses 734system.cpu.dcache.overall_misses::total 9967232 # number of overall misses 735system.cpu.dcache.ReadReq_miss_latency::cpu.data 88736242500 # number of ReadReq miss cycles 736system.cpu.dcache.ReadReq_miss_latency::total 88736242500 # number of ReadReq miss cycles 737system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002302858 # number of WriteReq miss cycles 738system.cpu.dcache.WriteReq_miss_latency::total 4002302858 # number of WriteReq miss cycles 739system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles 740system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles 741system.cpu.dcache.demand_miss_latency::cpu.data 92738545358 # number of demand (read+write) miss cycles 742system.cpu.dcache.demand_miss_latency::total 92738545358 # number of demand (read+write) miss cycles 743system.cpu.dcache.overall_miss_latency::cpu.data 92738545358 # number of overall miss cycles 744system.cpu.dcache.overall_miss_latency::total 92738545358 # number of overall miss cycles 745system.cpu.dcache.ReadReq_accesses::cpu.data 23476967 # number of ReadReq accesses(hits+misses) 746system.cpu.dcache.ReadReq_accesses::total 23476967 # number of ReadReq accesses(hits+misses) 747system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 748system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 749system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 750system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 751system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 752system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 753system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 754system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 755system.cpu.dcache.demand_accesses::cpu.data 28211948 # number of demand (read+write) accesses 756system.cpu.dcache.demand_accesses::total 28211948 # number of demand (read+write) accesses 757system.cpu.dcache.overall_accesses::cpu.data 28212477 # number of overall (read+write) accesses 758system.cpu.dcache.overall_accesses::total 28212477 # number of overall (read+write) accesses 759system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408314 # miss rate for ReadReq accesses 760system.cpu.dcache.ReadReq_miss_rate::total 0.408314 # miss rate for ReadReq accesses 761system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080519 # miss rate for WriteReq accesses 762system.cpu.dcache.WriteReq_miss_rate::total 0.080519 # miss rate for WriteReq accesses 763system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 764system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 765system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 766system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 767system.cpu.dcache.demand_miss_rate::cpu.data 0.353298 # miss rate for demand accesses 768system.cpu.dcache.demand_miss_rate::total 0.353298 # miss rate for demand accesses 769system.cpu.dcache.overall_miss_rate::cpu.data 0.353292 # miss rate for overall accesses 770system.cpu.dcache.overall_miss_rate::total 0.353292 # miss rate for overall accesses 771system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.887149 # average ReadReq miss latency 772system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.887149 # average ReadReq miss latency 773system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887 # average WriteReq miss latency 774system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887 # average WriteReq miss latency 775system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency 776system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency 777system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.349541 # average overall miss latency 778system.cpu.dcache.demand_avg_miss_latency::total 9304.349541 # average overall miss latency 779system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.343007 # average overall miss latency 780system.cpu.dcache.overall_avg_miss_latency::total 9304.343007 # average overall miss latency 781system.cpu.dcache.blocked_cycles::no_mshrs 330007 # number of cycles access was blocked 782system.cpu.dcache.blocked_cycles::no_targets 109189 # number of cycles access was blocked 783system.cpu.dcache.blocked::no_mshrs 121421 # number of cycles access was blocked 784system.cpu.dcache.blocked::no_targets 12842 # number of cycles access was blocked 785system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717874 # average number of cycles each access was blocked 786system.cpu.dcache.avg_blocked_cycles::no_targets 8.502492 # average number of cycles each access was blocked 787system.cpu.dcache.fast_writes 0 # number of fast writes performed 788system.cpu.dcache.cache_copies 0 # number of cache copies performed 789system.cpu.dcache.writebacks::writebacks 5470195 # number of writebacks 790system.cpu.dcache.writebacks::total 5470195 # number of writebacks 791system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337753 # number of ReadReq MSHR hits 792system.cpu.dcache.ReadReq_mshr_hits::total 4337753 # number of ReadReq MSHR hits 793system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158766 # number of WriteReq MSHR hits 794system.cpu.dcache.WriteReq_mshr_hits::total 158766 # number of WriteReq MSHR hits 795system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 796system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 797system.cpu.dcache.demand_mshr_hits::cpu.data 4496519 # number of demand (read+write) MSHR hits 798system.cpu.dcache.demand_mshr_hits::total 4496519 # number of demand (read+write) MSHR hits 799system.cpu.dcache.overall_mshr_hits::cpu.data 4496519 # number of overall MSHR hits 800system.cpu.dcache.overall_mshr_hits::total 4496519 # number of overall MSHR hits 801system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248217 # number of ReadReq MSHR misses 802system.cpu.dcache.ReadReq_mshr_misses::total 5248217 # number of ReadReq MSHR misses 803system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222489 # number of WriteReq MSHR misses 804system.cpu.dcache.WriteReq_mshr_misses::total 222489 # number of WriteReq MSHR misses 805system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 806system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 807system.cpu.dcache.demand_mshr_misses::cpu.data 5470706 # number of demand (read+write) MSHR misses 808system.cpu.dcache.demand_mshr_misses::total 5470706 # number of demand (read+write) MSHR misses 809system.cpu.dcache.overall_mshr_misses::cpu.data 5470710 # number of overall MSHR misses 810system.cpu.dcache.overall_mshr_misses::total 5470710 # number of overall MSHR misses 811system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43257355500 # number of ReadReq MSHR miss cycles 812system.cpu.dcache.ReadReq_mshr_miss_latency::total 43257355500 # number of ReadReq MSHR miss cycles 813system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285854739 # number of WriteReq MSHR miss cycles 814system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285854739 # number of WriteReq MSHR miss cycles 815system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles 816system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45543210239 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 45543210239 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45543424739 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 45543424739 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223547 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223547 # mshr miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses 825system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 826system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 827system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193915 # mshr miss rate for demand accesses 828system.cpu.dcache.demand_mshr_miss_rate::total 0.193915 # mshr miss rate for demand accesses 829system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses 830system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses 831system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.295526 # average ReadReq mshr miss latency 832system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.295526 # average ReadReq mshr miss latency 833system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374 # average WriteReq mshr miss latency 834system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374 # average WriteReq mshr miss latency 835system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 836system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 837system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.923737 # average overall mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.923737 # average overall mshr miss latency 839system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.956859 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.956859 # average overall mshr miss latency 841system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 842system.cpu.icache.tags.replacements 452 # number of replacements 843system.cpu.icache.tags.tagsinuse 428.759642 # Cycle average of tags in use 844system.cpu.icache.tags.total_refs 32301343 # Total number of references to valid blocks. 845system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. 846system.cpu.icache.tags.avg_refs 35457.017563 # Average number of references to valid blocks. 847system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 848system.cpu.icache.tags.occ_blocks::cpu.inst 428.759642 # Average occupied blocks per requestor 849system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy 850system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy 851system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 852system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 853system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id 854system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id 855system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id 856system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id 857system.cpu.icache.tags.tag_accesses 64605911 # Number of tag accesses 858system.cpu.icache.tags.data_accesses 64605911 # Number of data accesses 859system.cpu.icache.ReadReq_hits::cpu.inst 32301343 # number of ReadReq hits 860system.cpu.icache.ReadReq_hits::total 32301343 # number of ReadReq hits 861system.cpu.icache.demand_hits::cpu.inst 32301343 # number of demand (read+write) hits 862system.cpu.icache.demand_hits::total 32301343 # number of demand (read+write) hits 863system.cpu.icache.overall_hits::cpu.inst 32301343 # number of overall hits 864system.cpu.icache.overall_hits::total 32301343 # number of overall hits 865system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses 866system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses 867system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses 868system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses 869system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses 870system.cpu.icache.overall_misses::total 1157 # number of overall misses 871system.cpu.icache.ReadReq_miss_latency::cpu.inst 61697981 # number of ReadReq miss cycles 872system.cpu.icache.ReadReq_miss_latency::total 61697981 # number of ReadReq miss cycles 873system.cpu.icache.demand_miss_latency::cpu.inst 61697981 # number of demand (read+write) miss cycles 874system.cpu.icache.demand_miss_latency::total 61697981 # number of demand (read+write) miss cycles 875system.cpu.icache.overall_miss_latency::cpu.inst 61697981 # number of overall miss cycles 876system.cpu.icache.overall_miss_latency::total 61697981 # number of overall miss cycles 877system.cpu.icache.ReadReq_accesses::cpu.inst 32302500 # number of ReadReq accesses(hits+misses) 878system.cpu.icache.ReadReq_accesses::total 32302500 # number of ReadReq accesses(hits+misses) 879system.cpu.icache.demand_accesses::cpu.inst 32302500 # number of demand (read+write) accesses 880system.cpu.icache.demand_accesses::total 32302500 # number of demand (read+write) accesses 881system.cpu.icache.overall_accesses::cpu.inst 32302500 # number of overall (read+write) accesses 882system.cpu.icache.overall_accesses::total 32302500 # number of overall (read+write) accesses 883system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 885system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 886system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 887system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 888system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275 # average ReadReq miss latency 890system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275 # average ReadReq miss latency 891system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency 892system.cpu.icache.demand_avg_miss_latency::total 53325.826275 # average overall miss latency 893system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency 894system.cpu.icache.overall_avg_miss_latency::total 53325.826275 # average overall miss latency 895system.cpu.icache.blocked_cycles::no_mshrs 18986 # number of cycles access was blocked 896system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked 897system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked 898system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 899system.cpu.icache.avg_blocked_cycles::no_mshrs 84.382222 # average number of cycles each access was blocked 900system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked 901system.cpu.icache.fast_writes 0 # number of fast writes performed 902system.cpu.icache.cache_copies 0 # number of cache copies performed 903system.cpu.icache.writebacks::writebacks 452 # number of writebacks 904system.cpu.icache.writebacks::total 452 # number of writebacks 905system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits 906system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits 907system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits 908system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits 909system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits 910system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits 911system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses 912system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses 913system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses 914system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses 915system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses 916system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses 917system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50324485 # number of ReadReq MSHR miss cycles 918system.cpu.icache.ReadReq_mshr_miss_latency::total 50324485 # number of ReadReq MSHR miss cycles 919system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50324485 # number of demand (read+write) MSHR miss cycles 920system.cpu.icache.demand_mshr_miss_latency::total 50324485 # number of demand (read+write) MSHR miss cycles 921system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50324485 # number of overall MSHR miss cycles 922system.cpu.icache.overall_mshr_miss_latency::total 50324485 # number of overall MSHR miss cycles 923system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 924system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 925system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 926system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 927system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 928system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 929system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360 # average ReadReq mshr miss latency 930system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360 # average ReadReq mshr miss latency 931system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency 932system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency 933system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency 934system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency 935system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 936system.cpu.l2cache.prefetcher.num_hwpf_issued 4981576 # number of hwpf issued 937system.cpu.l2cache.prefetcher.pfIdentified 5296807 # number of prefetch candidates identified 938system.cpu.l2cache.prefetcher.pfBufferHit 274066 # number of redundant prefetches already in prefetch queue 939system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 940system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 941system.cpu.l2cache.prefetcher.pfSpanPage 14075593 # number of prefetches not generated due to page crossing 942system.cpu.l2cache.tags.replacements 236 # number of replacements 943system.cpu.l2cache.tags.tagsinuse 11228.158132 # Cycle average of tags in use 944system.cpu.l2cache.tags.total_refs 5318864 # Total number of references to valid blocks. 945system.cpu.l2cache.tags.sampled_refs 14906 # Sample count of references to valid blocks. 946system.cpu.l2cache.tags.avg_refs 356.827050 # Average number of references to valid blocks. 947system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 948system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538 # Average occupied blocks per requestor 949system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 163.435594 # Average occupied blocks per requestor 950system.cpu.l2cache.tags.occ_percent::writebacks 0.675337 # Average percentage of cache occupancy 951system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009975 # Average percentage of cache occupancy 952system.cpu.l2cache.tags.occ_percent::total 0.685312 # Average percentage of cache occupancy 953system.cpu.l2cache.tags.occ_task_id_blocks::1022 176 # Occupied blocks per task id 954system.cpu.l2cache.tags.occ_task_id_blocks::1024 14494 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1022::4 160 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 960system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3697 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9309 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1024::4 890 # Occupied blocks per task id 964system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010742 # Percentage of cache occupancy per task id 965system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884644 # Percentage of cache occupancy per task id 966system.cpu.l2cache.tags.tag_accesses 180495153 # Number of tag accesses 967system.cpu.l2cache.tags.data_accesses 180495153 # Number of data accesses 968system.cpu.l2cache.WritebackDirty_hits::writebacks 5450602 # number of WritebackDirty hits 969system.cpu.l2cache.WritebackDirty_hits::total 5450602 # number of WritebackDirty hits 970system.cpu.l2cache.WritebackClean_hits::writebacks 17129 # number of WritebackClean hits 971system.cpu.l2cache.WritebackClean_hits::total 17129 # number of WritebackClean hits 972system.cpu.l2cache.ReadExReq_hits::cpu.data 226024 # number of ReadExReq hits 973system.cpu.l2cache.ReadExReq_hits::total 226024 # number of ReadExReq hits 974system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 209 # number of ReadCleanReq hits 975system.cpu.l2cache.ReadCleanReq_hits::total 209 # number of ReadCleanReq hits 976system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243596 # number of ReadSharedReq hits 977system.cpu.l2cache.ReadSharedReq_hits::total 5243596 # number of ReadSharedReq hits 978system.cpu.l2cache.demand_hits::cpu.inst 209 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.data 5469620 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::total 5469829 # number of demand (read+write) hits 981system.cpu.l2cache.overall_hits::cpu.inst 209 # number of overall hits 982system.cpu.l2cache.overall_hits::cpu.data 5469620 # number of overall hits 983system.cpu.l2cache.overall_hits::total 5469829 # number of overall hits 984system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 985system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 986system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses 987system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses 988system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 703 # number of ReadCleanReq misses 989system.cpu.l2cache.ReadCleanReq_misses::total 703 # number of ReadCleanReq misses 990system.cpu.l2cache.ReadSharedReq_misses::cpu.data 588 # number of ReadSharedReq misses 991system.cpu.l2cache.ReadSharedReq_misses::total 588 # number of ReadSharedReq misses 992system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses 993system.cpu.l2cache.demand_misses::cpu.data 1087 # number of demand (read+write) misses 994system.cpu.l2cache.demand_misses::total 1790 # number of demand (read+write) misses 995system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses 996system.cpu.l2cache.overall_misses::cpu.data 1087 # number of overall misses 997system.cpu.l2cache.overall_misses::total 1790 # number of overall misses 998system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60500 # number of UpgradeReq miss cycles 999system.cpu.l2cache.UpgradeReq_miss_latency::total 60500 # number of UpgradeReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41219500 # number of ReadExReq miss cycles 1001system.cpu.l2cache.ReadExReq_miss_latency::total 41219500 # number of ReadExReq miss cycles 1002system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48001500 # number of ReadCleanReq miss cycles 1003system.cpu.l2cache.ReadCleanReq_miss_latency::total 48001500 # number of ReadCleanReq miss cycles 1004system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40148500 # number of ReadSharedReq miss cycles 1005system.cpu.l2cache.ReadSharedReq_miss_latency::total 40148500 # number of ReadSharedReq miss cycles 1006system.cpu.l2cache.demand_miss_latency::cpu.inst 48001500 # number of demand (read+write) miss cycles 1007system.cpu.l2cache.demand_miss_latency::cpu.data 81368000 # number of demand (read+write) miss cycles 1008system.cpu.l2cache.demand_miss_latency::total 129369500 # number of demand (read+write) miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.inst 48001500 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::cpu.data 81368000 # number of overall miss cycles 1011system.cpu.l2cache.overall_miss_latency::total 129369500 # number of overall miss cycles 1012system.cpu.l2cache.WritebackDirty_accesses::writebacks 5450602 # number of WritebackDirty accesses(hits+misses) 1013system.cpu.l2cache.WritebackDirty_accesses::total 5450602 # number of WritebackDirty accesses(hits+misses) 1014system.cpu.l2cache.WritebackClean_accesses::writebacks 17129 # number of WritebackClean accesses(hits+misses) 1015system.cpu.l2cache.WritebackClean_accesses::total 17129 # number of WritebackClean accesses(hits+misses) 1016system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 1017system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 1018system.cpu.l2cache.ReadExReq_accesses::cpu.data 226523 # number of ReadExReq accesses(hits+misses) 1019system.cpu.l2cache.ReadExReq_accesses::total 226523 # number of ReadExReq accesses(hits+misses) 1020system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses) 1021system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses) 1022system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244184 # number of ReadSharedReq accesses(hits+misses) 1023system.cpu.l2cache.ReadSharedReq_accesses::total 5244184 # number of ReadSharedReq accesses(hits+misses) 1024system.cpu.l2cache.demand_accesses::cpu.inst 912 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 5470707 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 5471619 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.inst 912 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.data 5470707 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::total 5471619 # number of overall (read+write) accesses 1030system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1031system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1032system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002203 # miss rate for ReadExReq accesses 1033system.cpu.l2cache.ReadExReq_miss_rate::total 0.002203 # miss rate for ReadExReq accesses 1034system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.770833 # miss rate for ReadCleanReq accesses 1035system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.770833 # miss rate for ReadCleanReq accesses 1036system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses 1037system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses 1038system.cpu.l2cache.demand_miss_rate::cpu.inst 0.770833 # miss rate for demand accesses 1039system.cpu.l2cache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses 1040system.cpu.l2cache.demand_miss_rate::total 0.000327 # miss rate for demand accesses 1041system.cpu.l2cache.overall_miss_rate::cpu.inst 0.770833 # miss rate for overall accesses 1042system.cpu.l2cache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses 1043system.cpu.l2cache.overall_miss_rate::total 0.000327 # miss rate for overall accesses 1044system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency 1045system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency 1046system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82604.208417 # average ReadExReq miss latency 1047system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82604.208417 # average ReadExReq miss latency 1048system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68280.938834 # average ReadCleanReq miss latency 1049system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68280.938834 # average ReadCleanReq miss latency 1050system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68279.761905 # average ReadSharedReq miss latency 1051system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68279.761905 # average ReadSharedReq miss latency 1052system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency 1053system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency 1054system.cpu.l2cache.demand_avg_miss_latency::total 72273.463687 # average overall miss latency 1055system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency 1056system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency 1057system.cpu.l2cache.overall_avg_miss_latency::total 72273.463687 # average overall miss latency 1058system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1060system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1061system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1062system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1063system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1064system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1065system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1066system.cpu.l2cache.writebacks::writebacks 170 # number of writebacks 1067system.cpu.l2cache.writebacks::total 170 # number of writebacks 1068system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1069system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1070system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1071system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1072system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits 1073system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits 1074system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1075system.cpu.l2cache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits 1076system.cpu.l2cache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits 1077system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1078system.cpu.l2cache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits 1079system.cpu.l2cache.overall_mshr_hits::total 191 # number of overall MSHR hits 1080system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316176 # number of HardPFReq MSHR misses 1081system.cpu.l2cache.HardPFReq_mshr_misses::total 316176 # number of HardPFReq MSHR misses 1082system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 1083system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 1084system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1085system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1086system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 702 # number of ReadCleanReq MSHR misses 1087system.cpu.l2cache.ReadCleanReq_mshr_misses::total 702 # number of ReadCleanReq MSHR misses 1088system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 556 # number of ReadSharedReq MSHR misses 1089system.cpu.l2cache.ReadSharedReq_mshr_misses::total 556 # number of ReadSharedReq MSHR misses 1090system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses 1091system.cpu.l2cache.demand_mshr_misses::cpu.data 897 # number of demand (read+write) MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::total 1599 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.data 897 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316176 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::total 317775 # number of overall MSHR misses 1097system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of HardPFReq MSHR miss cycles 1098system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 851895298 # number of HardPFReq MSHR miss cycles 1099system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42500 # number of UpgradeReq MSHR miss cycles 1100system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42500 # number of UpgradeReq MSHR miss cycles 1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32684500 # number of ReadExReq MSHR miss cycles 1102system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32684500 # number of ReadExReq MSHR miss cycles 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43736000 # number of ReadCleanReq MSHR miss cycles 1104system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43736000 # number of ReadCleanReq MSHR miss cycles 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35150000 # number of ReadSharedReq MSHR miss cycles 1106system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35150000 # number of ReadSharedReq MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43736000 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67834500 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::total 111570500 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43736000 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67834500 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::total 963465798 # number of overall MSHR miss cycles 1114system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1115system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1116system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1117system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses 1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses 1120system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for ReadCleanReq accesses 1121system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.769737 # mshr miss rate for ReadCleanReq accesses 1122system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000106 # mshr miss rate for ReadSharedReq accesses 1123system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000106 # mshr miss rate for ReadSharedReq accesses 1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for demand accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for demand accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::total 0.000292 # mshr miss rate for demand accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for overall accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::total 0.058077 # mshr miss rate for overall accesses 1131system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average HardPFReq mshr miss latency 1132system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.370534 # average HardPFReq mshr miss latency 1133system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency 1134system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency 1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607 # average ReadExReq mshr miss latency 1136system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607 # average ReadExReq mshr miss latency 1137system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302 # average ReadCleanReq mshr miss latency 1138system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302 # average ReadCleanReq mshr miss latency 1139system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460 # average ReadSharedReq mshr miss latency 1140system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460 # average ReadSharedReq mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3031.911881 # average overall mshr miss latency 1148system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1149system.cpu.toL2Bus.snoop_filter.tot_requests 10942269 # Total number of requests made to the snoop filter. 1150system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470664 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1151system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1152system.cpu.toL2Bus.snoop_filter.tot_snoops 303004 # Total number of snoops made to the snoop filter. 1153system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302696 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1154system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1155system.cpu.toL2Bus.trans_dist::ReadResp 5245095 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::WritebackDirty 5450772 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WritebackClean 20045 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::CleanEvict 1323 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::HardPFReq 318050 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::ReadExReq 226523 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::ReadExResp 226523 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244184 # Transaction distribution 1167system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2275 # Packet count per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16411619 # Packet count per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_count::total 16413894 # Packet count per connected master and slave (bytes) 1170system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87232 # Cumulative packet size per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700217984 # Cumulative packet size per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size::total 700305216 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.snoops 319547 # Total snoops (count) 1174system.cpu.toL2Bus.snoop_fanout::samples 5791165 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::mean 0.052881 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::stdev 0.224033 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::0 5485231 94.72% 94.72% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::1 305626 5.28% 99.99% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::total 5791165 # Request fanout histogram 1185system.cpu.toL2Bus.reqLayer0.occupancy 10941781515 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 1187system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1188system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1189system.cpu.toL2Bus.respLayer0.occupancy 1367498 # Layer occupancy (ticks) 1190system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1191system.cpu.toL2Bus.respLayer1.occupancy 8206066491 # Layer occupancy (ticks) 1192system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 1193system.membus.trans_dist::ReadResp 15694 # Transaction distribution 1194system.membus.trans_dist::WritebackDirty 170 # Transaction distribution 1195system.membus.trans_dist::CleanEvict 58 # Transaction distribution 1196system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 1197system.membus.trans_dist::ReadExReq 340 # Transaction distribution 1198system.membus.trans_dist::ReadExResp 340 # Transaction distribution 1199system.membus.trans_dist::ReadSharedReq 15695 # Transaction distribution 1200system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32301 # Packet count per connected master and slave (bytes) 1201system.membus.pkt_count::total 32301 # Packet count per connected master and slave (bytes) 1202system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1037056 # Cumulative packet size per connected master and slave (bytes) 1203system.membus.pkt_size::total 1037056 # Cumulative packet size per connected master and slave (bytes) 1204system.membus.snoops 0 # Total snoops (count) 1205system.membus.snoop_fanout::samples 16267 # Request fanout histogram 1206system.membus.snoop_fanout::mean 0 # Request fanout histogram 1207system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1208system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1209system.membus.snoop_fanout::0 16267 100.00% 100.00% # Request fanout histogram 1210system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1211system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1212system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1213system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1214system.membus.snoop_fanout::total 16267 # Request fanout histogram 1215system.membus.reqLayer0.occupancy 26872796 # Layer occupancy (ticks) 1216system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1217system.membus.respLayer1.occupancy 83907066 # Layer occupancy (ticks) 1218system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1219 1220---------- End Simulation Statistics ---------- 1221