stats.txt revision 10242:cb4e86c17767
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026894 # Number of seconds simulated 4sim_ticks 26894328500 # Number of ticks simulated 5final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 165934 # Simulator instruction rate (inst/s) 8host_op_rate 167125 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49262466 # Simulator tick rate (ticks/s) 10host_mem_usage 394132 # Number of bytes of host memory used 11host_seconds 545.94 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91240351 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory 18system.physmem.bytes_read::total 992640 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 15510 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 987 # Per bank write bursts 45system.physmem.perBankRdBursts::1 885 # Per bank write bursts 46system.physmem.perBankRdBursts::2 942 # Per bank write bursts 47system.physmem.perBankRdBursts::3 1029 # Per bank write bursts 48system.physmem.perBankRdBursts::4 1048 # Per bank write bursts 49system.physmem.perBankRdBursts::5 1105 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1078 # Per bank write bursts 51system.physmem.perBankRdBursts::7 1080 # Per bank write bursts 52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 53system.physmem.perBankRdBursts::9 957 # Per bank write bursts 54system.physmem.perBankRdBursts::10 936 # Per bank write bursts 55system.physmem.perBankRdBursts::11 899 # Per bank write bursts 56system.physmem.perBankRdBursts::12 905 # Per bank write bursts 57system.physmem.perBankRdBursts::13 863 # Per bank write bursts 58system.physmem.perBankRdBursts::14 876 # Per bank write bursts 59system.physmem.perBankRdBursts::15 896 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 26894128500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15510 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation 203system.physmem.totQLat 88775250 # Total ticks spent queuing 204system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.29 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14143 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 1733986.36 # Average gap between requests 224system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states 226system.physmem.memoryStateTime::REF 898040000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 36908897 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 972 # Transaction distribution 232system.membus.trans_dist::ReadResp 972 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 1 # Transaction distribution 235system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 236system.membus.trans_dist::ReadExResp 14538 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes) 239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 992640 # Total data (bytes) 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 243system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks) 244system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 245system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks) 246system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 247system.cpu_clk_domain.clock 500 # Clock period in ticks 248system.cpu.branchPred.lookups 27364118 # Number of BP lookups 249system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 254system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions. 257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 265system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 267system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 268system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 269system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 270system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 271system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 272system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 273system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 274system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 275system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 276system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 277system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 278system.cpu.dtb.inst_hits 0 # ITB inst hits 279system.cpu.dtb.inst_misses 0 # ITB inst misses 280system.cpu.dtb.read_hits 0 # DTB read hits 281system.cpu.dtb.read_misses 0 # DTB read misses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dtb.read_accesses 0 # DTB read accesses 294system.cpu.dtb.write_accesses 0 # DTB write accesses 295system.cpu.dtb.inst_accesses 0 # ITB inst accesses 296system.cpu.dtb.hits 0 # DTB hits 297system.cpu.dtb.misses 0 # DTB misses 298system.cpu.dtb.accesses 0 # DTB accesses 299system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 300system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 301system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 302system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 303system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 304system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 305system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 307system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 308system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 309system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 310system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 311system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 312system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 313system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 314system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 315system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 316system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 317system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 318system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 319system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 320system.cpu.itb.inst_hits 0 # ITB inst hits 321system.cpu.itb.inst_misses 0 # ITB inst misses 322system.cpu.itb.read_hits 0 # DTB read hits 323system.cpu.itb.read_misses 0 # DTB read misses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 327system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 328system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 329system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 330system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 331system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 332system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 333system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 442 # Number of system calls 342system.cpu.numCycles 53788658 # number of cpu cycles simulated 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 345system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing 351system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked 352system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 353system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps 354system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR 355system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched 356system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed 357system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle 375system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle 376system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle 377system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked 378system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running 379system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking 380system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing 381system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch 382system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction 383system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode 384system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode 385system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing 386system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle 387system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking 388system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst 389system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running 390system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking 391system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename 392system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full 393system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full 394system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full 395system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full 396system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers 397system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed 398system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made 399system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups 400system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups 401system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed 402system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing 403system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed 404system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed 405system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer 406system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit. 407system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit. 408system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads. 409system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores. 410system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec) 411system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ 412system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued 413system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued 414system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling 415system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph 416system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed 417system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle 434system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available 465system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 468system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 469system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued 470system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued 471system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued 498system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued 499system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued 503system.cpu.iq.rate 1.969822 # Inst issue rate 504system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested 505system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst) 506system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads 507system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes 508system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses 509system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads 510system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes 511system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses 512system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses 513system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses 514system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores 515system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 516system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed 517system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed 518system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations 519system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed 520system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 521system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 522system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 523system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked 524system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 525system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing 526system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking 527system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking 528system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ 529system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch 530system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions 531system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions 532system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions 533system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall 534system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall 535system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations 536system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly 537system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly 538system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute 539system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions 540system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed 541system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute 542system.cpu.iew.exec_swp 0 # number of swp insts executed 543system.cpu.iew.exec_nop 12732 # number of nop insts executed 544system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed 545system.cpu.iew.exec_branches 21526378 # Number of branches executed 546system.cpu.iew.exec_stores 5070820 # Number of stores executed 547system.cpu.iew.exec_rate 1.951233 # Inst execution rate 548system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit 549system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back 550system.cpu.iew.wb_producers 62672484 # num instructions producing a value 551system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value 552system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 553system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle 554system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back 555system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 556system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit 557system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 558system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted 559system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle 576system.cpu.commit.committedInsts 90602407 # Number of instructions committed 577system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed 578system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 579system.cpu.commit.refs 27318810 # Number of memory references committed 580system.cpu.commit.loads 22573966 # Number of loads committed 581system.cpu.commit.membars 3888 # Number of memory barriers committed 582system.cpu.commit.branches 18732304 # Number of branches committed 583system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 584system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. 585system.cpu.commit.function_calls 56148 # Number of function calls committed. 586system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 587system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction 588system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction 589system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction 616system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction 617system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 619system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 620system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction 621system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached 622system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 623system.cpu.rob.rob_reads 164461990 # The number of ROB reads 624system.cpu.rob.rob_writes 245943119 # The number of ROB writes 625system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself 626system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling 627system.cpu.committedInsts 90589798 # Number of Instructions Simulated 628system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated 629system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction 630system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads 631system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle 632system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads 633system.cpu.int_regfile_reads 499033245 # number of integer regfile reads 634system.cpu.int_regfile_writes 121427335 # number of integer regfile writes 635system.cpu.fp_regfile_reads 166 # number of floating regfile reads 636system.cpu.fp_regfile_writes 402 # number of floating regfile writes 637system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads 638system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 639system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s) 640system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution 641system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution 647system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes) 648system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes) 654system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) 655system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks) 656system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) 657system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks) 658system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 659system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks) 660system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) 661system.cpu.icache.tags.replacements 3 # number of replacements 662system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use 663system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks. 664system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks. 665system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks. 666system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor 668system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy 669system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 672system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 673system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id 675system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id 676system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses 677system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses 678system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits 679system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits 680system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits 681system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits 682system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits 683system.cpu.icache.overall_hits::total 14155509 # number of overall hits 684system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses 685system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses 686system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses 687system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses 688system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses 689system.cpu.icache.overall_misses::total 995 # number of overall misses 690system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles 691system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles 692system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles 693system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles 694system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles 695system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles 696system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses) 697system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses) 698system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses 699system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses 700system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses 701system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses 702system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses 703system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses 704system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses 705system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses 706system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses 707system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses 708system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency 709system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency 710system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency 711system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency 712system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency 713system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency 714system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked 715system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 716system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked 717system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked 719system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 720system.cpu.icache.fast_writes 0 # number of fast writes performed 721system.cpu.icache.cache_copies 0 # number of cache copies performed 722system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits 723system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits 724system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits 725system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits 726system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits 727system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits 728system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses 729system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses 730system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses 731system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses 732system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses 733system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses 734system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles 735system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles 740system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses 741system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses 742system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses 743system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses 744system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses 745system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses 746system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency 748system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency 750system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency 752system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.l2cache.tags.replacements 0 # number of replacements 754system.cpu.l2cache.tags.tagsinuse 10751.524012 # Cycle average of tags in use 755system.cpu.l2cache.tags.total_refs 1834202 # Total number of references to valid blocks. 756system.cpu.l2cache.tags.sampled_refs 15494 # Sample count of references to valid blocks. 757system.cpu.l2cache.tags.avg_refs 118.381438 # Average number of references to valid blocks. 758system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.l2cache.tags.occ_blocks::writebacks 9904.575959 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.inst 617.996997 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_blocks::cpu.data 228.951056 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_percent::writebacks 0.302264 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018860 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.data 0.006987 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::total 0.328110 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_task_id_blocks::1024 15494 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1306 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13614 # Occupied blocks per task id 772system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472839 # Percentage of cache occupancy per task id 773system.cpu.l2cache.tags.tag_accesses 15186331 # Number of tag accesses 774system.cpu.l2cache.tags.data_accesses 15186331 # Number of data accesses 775system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits 776system.cpu.l2cache.ReadReq_hits::cpu.data 906402 # number of ReadReq hits 777system.cpu.l2cache.ReadReq_hits::total 906426 # number of ReadReq hits 778system.cpu.l2cache.Writeback_hits::writebacks 942895 # number of Writeback hits 779system.cpu.l2cache.Writeback_hits::total 942895 # number of Writeback hits 780system.cpu.l2cache.ReadExReq_hits::cpu.data 26395 # number of ReadExReq hits 781system.cpu.l2cache.ReadExReq_hits::total 26395 # number of ReadExReq hits 782system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 783system.cpu.l2cache.demand_hits::cpu.data 932797 # number of demand (read+write) hits 784system.cpu.l2cache.demand_hits::total 932821 # number of demand (read+write) hits 785system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits 786system.cpu.l2cache.overall_hits::cpu.data 932797 # number of overall hits 787system.cpu.l2cache.overall_hits::total 932821 # number of overall hits 788system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses 789system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses 790system.cpu.l2cache.ReadReq_misses::total 983 # number of ReadReq misses 791system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 792system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 793system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 794system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 795system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses 796system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses 797system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses 798system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses 799system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses 800system.cpu.l2cache.overall_misses::total 15521 # number of overall misses 801system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49834500 # number of ReadReq miss cycles 802system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21050250 # number of ReadReq miss cycles 803system.cpu.l2cache.ReadReq_miss_latency::total 70884750 # number of ReadReq miss cycles 804system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 978125750 # number of ReadExReq miss cycles 805system.cpu.l2cache.ReadExReq_miss_latency::total 978125750 # number of ReadExReq miss cycles 806system.cpu.l2cache.demand_miss_latency::cpu.inst 49834500 # number of demand (read+write) miss cycles 807system.cpu.l2cache.demand_miss_latency::cpu.data 999176000 # number of demand (read+write) miss cycles 808system.cpu.l2cache.demand_miss_latency::total 1049010500 # number of demand (read+write) miss cycles 809system.cpu.l2cache.overall_miss_latency::cpu.inst 49834500 # number of overall miss cycles 810system.cpu.l2cache.overall_miss_latency::cpu.data 999176000 # number of overall miss cycles 811system.cpu.l2cache.overall_miss_latency::total 1049010500 # number of overall miss cycles 812system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses) 813system.cpu.l2cache.ReadReq_accesses::cpu.data 906678 # number of ReadReq accesses(hits+misses) 814system.cpu.l2cache.ReadReq_accesses::total 907409 # number of ReadReq accesses(hits+misses) 815system.cpu.l2cache.Writeback_accesses::writebacks 942895 # number of Writeback accesses(hits+misses) 816system.cpu.l2cache.Writeback_accesses::total 942895 # number of Writeback accesses(hits+misses) 817system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 818system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 819system.cpu.l2cache.ReadExReq_accesses::cpu.data 40933 # number of ReadExReq accesses(hits+misses) 820system.cpu.l2cache.ReadExReq_accesses::total 40933 # number of ReadExReq accesses(hits+misses) 821system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses 822system.cpu.l2cache.demand_accesses::cpu.data 947611 # number of demand (read+write) accesses 823system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses 824system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses 825system.cpu.l2cache.overall_accesses::cpu.data 947611 # number of overall (read+write) accesses 826system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses 827system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses 828system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses 829system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses 830system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 831system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 832system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.355166 # miss rate for ReadExReq accesses 833system.cpu.l2cache.ReadExReq_miss_rate::total 0.355166 # miss rate for ReadExReq accesses 834system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses 835system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses 836system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses 837system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses 838system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses 839system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses 840system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70487.270156 # average ReadReq miss latency 841system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76269.021739 # average ReadReq miss latency 842system.cpu.l2cache.ReadReq_avg_miss_latency::total 72110.630722 # average ReadReq miss latency 843system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67280.626634 # average ReadExReq miss latency 844system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67280.626634 # average ReadExReq miss latency 845system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency 846system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency 847system.cpu.l2cache.demand_avg_miss_latency::total 67586.527930 # average overall miss latency 848system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency 849system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency 850system.cpu.l2cache.overall_avg_miss_latency::total 67586.527930 # average overall miss latency 851system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 852system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 853system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 854system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 855system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 856system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 857system.cpu.l2cache.fast_writes 0 # number of fast writes performed 858system.cpu.l2cache.cache_copies 0 # number of cache copies performed 859system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 860system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 861system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 862system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 863system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 864system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 865system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 866system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 867system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits 868system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses 869system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses 870system.cpu.l2cache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses 871system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 872system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 875system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses 876system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses 879system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses 880system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses 881system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40933250 # number of ReadReq MSHR miss cycles 882system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17118000 # number of ReadReq MSHR miss cycles 883system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58051250 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 885system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 886system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles 887system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles 888system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles 889system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles 892system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles 894system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses 895system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses 896system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses 897system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 898system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 899system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses 900system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses 901system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses 907system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency 910system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 911system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency 913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency 920system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 921system.cpu.dcache.tags.replacements 943515 # number of replacements 922system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use 923system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks. 924system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks. 925system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks. 926system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit. 927system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor 928system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy 929system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy 930system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 931system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id 932system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id 934system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 935system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses 936system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses 937system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits 938system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits 939system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits 940system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits 941system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits 942system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits 943system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 944system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 945system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits 946system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits 947system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits 948system.cpu.dcache.overall_hits::total 28221779 # number of overall hits 949system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses 950system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses 951system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses 952system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses 953system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses 954system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses 955system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses 956system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses 957system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses 958system.cpu.dcache.overall_misses::total 1359651 # number of overall misses 959system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles 960system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles 961system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles 962system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles 963system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles 964system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles 965system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles 966system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles 967system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles 968system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles 969system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses) 970system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses) 971system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 972system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 973system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) 974system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) 975system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 976system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 977system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses 978system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses 979system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses 980system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses 981system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses 982system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses 983system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses 984system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses 985system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses 986system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses 987system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses 988system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses 989system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses 990system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses 991system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency 992system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency 993system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency 994system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency 995system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency 996system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency 997system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency 998system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency 999system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency 1000system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency 1001system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked 1002system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1003system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked 1004system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1005system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked 1006system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1007system.cpu.dcache.fast_writes 0 # number of fast writes performed 1008system.cpu.dcache.cache_copies 0 # number of cache copies performed 1009system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks 1010system.cpu.dcache.writebacks::total 942895 # number of writebacks 1011system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits 1012system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits 1013system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits 1014system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits 1015system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits 1016system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits 1017system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits 1018system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits 1019system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits 1020system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits 1021system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses 1022system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses 1023system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses 1024system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses 1025system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses 1026system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses 1027system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses 1028system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses 1029system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles 1030system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles 1031system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles 1032system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles 1033system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles 1034system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles 1035system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles 1036system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles 1037system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses 1038system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses 1039system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses 1040system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses 1041system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses 1042system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses 1043system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses 1044system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses 1045system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency 1046system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency 1047system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency 1048system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency 1049system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency 1050system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency 1051system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency 1052system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency 1053system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1054 1055---------- End Simulation Statistics ---------- 1056