simout revision 11298:e535b95573c0
110086Snilay@cs.wisc.edugem5 Simulator System. http://gem5.org 210086Snilay@cs.wisc.edugem5 is copyrighted software; use the --copyright option for details. 310086Snilay@cs.wisc.edu 410086Snilay@cs.wisc.edugem5 compiled Jan 17 2016 20:30:24 510086Snilay@cs.wisc.edugem5 started Jan 17 2016 20:30:38 610086Snilay@cs.wisc.edugem5 executing on zizzer, pid 47389 710086Snilay@cs.wisc.educommand line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic 810086Snilay@cs.wisc.edu 910086Snilay@cs.wisc.eduGlobal frequency set at 2000000000 ticks per second 1010086Snilay@cs.wisc.eduinfo: No kernel set for full system simulation. Assuming you know what you're doing 1110086Snilay@cs.wisc.edu 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 1210086Snilay@cs.wisc.edu 1310086Snilay@cs.wisc.edu 0: system.t1000.htod: Real-time clock set to 1230768000 1410086Snilay@cs.wisc.eduinfo: Entering event queue @ 0. Starting simulation... 1510086Snilay@cs.wisc.eduinfo: Ignoring write to SPARC ERROR regsiter 1610086Snilay@cs.wisc.eduinfo: Ignoring write to SPARC ERROR regsiter 1710086Snilay@cs.wisc.eduExiting @ tick 4467555024 because m5_exit instruction encountered 1810086Snilay@cs.wisc.edu