config.json revision 11946:8eb1f2595a92
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "rom": { 9 "range": "1099243192320:1099251580927", 10 "latency": 60, 11 "name": "rom", 12 "p_state_clk_gate_min": 2, 13 "eventq_index": 0, 14 "p_state_clk_gate_bins": 20, 15 "default_p_state": "UNDEFINED", 16 "clk_domain": "system.clk_domain", 17 "latency_var": 0, 18 "bandwidth": "0.000000", 19 "conf_table_reported": true, 20 "cxx_class": "SimpleMemory", 21 "p_state_clk_gate_max": 2000000000, 22 "path": "system.rom", 23 "null": false, 24 "type": "SimpleMemory", 25 "port": { 26 "peer": "system.membus.master[3]", 27 "role": "SLAVE" 28 }, 29 "in_addr_map": true 30 }, 31 "bridge": { 32 "ranges": [ 33 "133412421632:133412421639", 34 "134217728000:554050781183", 35 "644245094400:652835028991", 36 "725849473024:1095485095935", 37 "1099255955456:1099255955463" 38 ], 39 "slave": { 40 "peer": "system.membus.master[2]", 41 "role": "SLAVE" 42 }, 43 "name": "bridge", 44 "p_state_clk_gate_min": 2, 45 "p_state_clk_gate_bins": 20, 46 "cxx_class": "Bridge", 47 "req_size": 16, 48 "clk_domain": "system.clk_domain", 49 "delay": 100, 50 "eventq_index": 0, 51 "master": { 52 "peer": "system.iobus.slave[0]", 53 "role": "MASTER" 54 }, 55 "default_p_state": "UNDEFINED", 56 "p_state_clk_gate_max": 2000000000, 57 "path": "system.bridge", 58 "resp_size": 16, 59 "type": "Bridge" 60 }, 61 "iobus": { 62 "forward_latency": 1, 63 "slave": { 64 "peer": [ 65 "system.bridge.master" 66 ], 67 "role": "SLAVE" 68 }, 69 "name": "iobus", 70 "p_state_clk_gate_min": 2, 71 "p_state_clk_gate_bins": 20, 72 "cxx_class": "NoncoherentXBar", 73 "clk_domain": "system.clk_domain", 74 "width": 16, 75 "eventq_index": 0, 76 "master": { 77 "peer": [ 78 "system.t1000.fake_clk.pio", 79 "system.t1000.fake_membnks.pio", 80 "system.t1000.fake_l2_1.pio", 81 "system.t1000.fake_l2_2.pio", 82 "system.t1000.fake_l2_3.pio", 83 "system.t1000.fake_l2_4.pio", 84 "system.t1000.fake_l2esr_1.pio", 85 "system.t1000.fake_l2esr_2.pio", 86 "system.t1000.fake_l2esr_3.pio", 87 "system.t1000.fake_l2esr_4.pio", 88 "system.t1000.fake_ssi.pio", 89 "system.t1000.fake_jbi.pio", 90 "system.t1000.puart0.pio", 91 "system.t1000.hvuart.pio", 92 "system.disk0.pio" 93 ], 94 "role": "MASTER" 95 }, 96 "response_latency": 2, 97 "default_p_state": "UNDEFINED", 98 "p_state_clk_gate_max": 2000000000, 99 "path": "system.iobus", 100 "type": "NoncoherentXBar", 101 "use_default_range": false, 102 "frontend_latency": 2 103 }, 104 "t1000": { 105 "htod": { 106 "name": "htod", 107 "p_state_clk_gate_min": 2, 108 "pio": { 109 "peer": "system.membus.master[1]", 110 "role": "SLAVE" 111 }, 112 "p_state_clk_gate_bins": 20, 113 "cxx_class": "DumbTOD", 114 "pio_latency": 200, 115 "clk_domain": "system.clk_domain", 116 "system": "system", 117 "eventq_index": 0, 118 "time": "Thu Jan 1 00:00:00 2009", 119 "default_p_state": "UNDEFINED", 120 "p_state_clk_gate_max": 2000000000, 121 "path": "system.t1000.htod", 122 "pio_addr": 1099255906296, 123 "type": "DumbTOD" 124 }, 125 "puart0": { 126 "name": "puart0", 127 "p_state_clk_gate_min": 2, 128 "pio": { 129 "peer": "system.iobus.master[12]", 130 "role": "SLAVE" 131 }, 132 "p_state_clk_gate_bins": 20, 133 "cxx_class": "Uart8250", 134 "pio_latency": 200, 135 "clk_domain": "system.clk_domain", 136 "system": "system", 137 "terminal": "system.t1000.pterm", 138 "platform": "system.t1000", 139 "eventq_index": 0, 140 "default_p_state": "UNDEFINED", 141 "p_state_clk_gate_max": 2000000000, 142 "path": "system.t1000.puart0", 143 "pio_addr": 133412421632, 144 "type": "Uart8250" 145 }, 146 "fake_membnks": { 147 "pio": { 148 "peer": "system.iobus.master[1]", 149 "role": "SLAVE" 150 }, 151 "ret_data64": 0, 152 "fake_mem": false, 153 "clk_domain": "system.clk_domain", 154 "cxx_class": "IsaFake", 155 "pio_addr": 648540061696, 156 "update_data": false, 157 "warn_access": "", 158 "pio_latency": 200, 159 "system": "system", 160 "eventq_index": 0, 161 "default_p_state": "UNDEFINED", 162 "p_state_clk_gate_max": 2000000000, 163 "type": "IsaFake", 164 "p_state_clk_gate_min": 2, 165 "ret_data32": 4294967295, 166 "path": "system.t1000.fake_membnks", 167 "ret_data16": 65535, 168 "ret_data8": 255, 169 "name": "fake_membnks", 170 "ret_bad_addr": false, 171 "pio_size": 16384, 172 "p_state_clk_gate_bins": 20 173 }, 174 "cxx_class": "T1000", 175 "fake_jbi": { 176 "pio": { 177 "peer": "system.iobus.master[11]", 178 "role": "SLAVE" 179 }, 180 "ret_data64": 18446744073709551615, 181 "fake_mem": false, 182 "clk_domain": "system.clk_domain", 183 "cxx_class": "IsaFake", 184 "pio_addr": 549755813888, 185 "update_data": false, 186 "warn_access": "", 187 "pio_latency": 200, 188 "system": "system", 189 "eventq_index": 0, 190 "default_p_state": "UNDEFINED", 191 "p_state_clk_gate_max": 2000000000, 192 "type": "IsaFake", 193 "p_state_clk_gate_min": 2, 194 "ret_data32": 4294967295, 195 "path": "system.t1000.fake_jbi", 196 "ret_data16": 65535, 197 "ret_data8": 255, 198 "name": "fake_jbi", 199 "ret_bad_addr": false, 200 "pio_size": 4294967296, 201 "p_state_clk_gate_bins": 20 202 }, 203 "intrctrl": "system.intrctrl", 204 "fake_l2esr_2": { 205 "pio": { 206 "peer": "system.iobus.master[7]", 207 "role": "SLAVE" 208 }, 209 "ret_data64": 0, 210 "fake_mem": false, 211 "clk_domain": "system.clk_domain", 212 "cxx_class": "IsaFake", 213 "pio_addr": 734439407680, 214 "update_data": true, 215 "warn_access": "", 216 "pio_latency": 200, 217 "system": "system", 218 "eventq_index": 0, 219 "default_p_state": "UNDEFINED", 220 "p_state_clk_gate_max": 2000000000, 221 "type": "IsaFake", 222 "p_state_clk_gate_min": 2, 223 "ret_data32": 4294967295, 224 "path": "system.t1000.fake_l2esr_2", 225 "ret_data16": 65535, 226 "ret_data8": 255, 227 "name": "fake_l2esr_2", 228 "ret_bad_addr": false, 229 "pio_size": 8, 230 "p_state_clk_gate_bins": 20 231 }, 232 "system": "system", 233 "eventq_index": 0, 234 "hterm": { 235 "name": "hterm", 236 "output": true, 237 "number": 0, 238 "intr_control": "system.intrctrl", 239 "eventq_index": 0, 240 "cxx_class": "Terminal", 241 "path": "system.t1000.hterm", 242 "type": "Terminal", 243 "port": 3456 244 }, 245 "type": "T1000", 246 "fake_l2_4": { 247 "pio": { 248 "peer": "system.iobus.master[5]", 249 "role": "SLAVE" 250 }, 251 "ret_data64": 1, 252 "fake_mem": false, 253 "clk_domain": "system.clk_domain", 254 "cxx_class": "IsaFake", 255 "pio_addr": 725849473216, 256 "update_data": true, 257 "warn_access": "", 258 "pio_latency": 200, 259 "system": "system", 260 "eventq_index": 0, 261 "default_p_state": "UNDEFINED", 262 "p_state_clk_gate_max": 2000000000, 263 "type": "IsaFake", 264 "p_state_clk_gate_min": 2, 265 "ret_data32": 4294967295, 266 "path": "system.t1000.fake_l2_4", 267 "ret_data16": 65535, 268 "ret_data8": 255, 269 "name": "fake_l2_4", 270 "ret_bad_addr": false, 271 "pio_size": 8, 272 "p_state_clk_gate_bins": 20 273 }, 274 "fake_l2_1": { 275 "pio": { 276 "peer": "system.iobus.master[2]", 277 "role": "SLAVE" 278 }, 279 "ret_data64": 1, 280 "fake_mem": false, 281 "clk_domain": "system.clk_domain", 282 "cxx_class": "IsaFake", 283 "pio_addr": 725849473024, 284 "update_data": true, 285 "warn_access": "", 286 "pio_latency": 200, 287 "system": "system", 288 "eventq_index": 0, 289 "default_p_state": "UNDEFINED", 290 "p_state_clk_gate_max": 2000000000, 291 "type": "IsaFake", 292 "p_state_clk_gate_min": 2, 293 "ret_data32": 4294967295, 294 "path": "system.t1000.fake_l2_1", 295 "ret_data16": 65535, 296 "ret_data8": 255, 297 "name": "fake_l2_1", 298 "ret_bad_addr": false, 299 "pio_size": 8, 300 "p_state_clk_gate_bins": 20 301 }, 302 "fake_l2_2": { 303 "pio": { 304 "peer": "system.iobus.master[3]", 305 "role": "SLAVE" 306 }, 307 "ret_data64": 1, 308 "fake_mem": false, 309 "clk_domain": "system.clk_domain", 310 "cxx_class": "IsaFake", 311 "pio_addr": 725849473088, 312 "update_data": true, 313 "warn_access": "", 314 "pio_latency": 200, 315 "system": "system", 316 "eventq_index": 0, 317 "default_p_state": "UNDEFINED", 318 "p_state_clk_gate_max": 2000000000, 319 "type": "IsaFake", 320 "p_state_clk_gate_min": 2, 321 "ret_data32": 4294967295, 322 "path": "system.t1000.fake_l2_2", 323 "ret_data16": 65535, 324 "ret_data8": 255, 325 "name": "fake_l2_2", 326 "ret_bad_addr": false, 327 "pio_size": 8, 328 "p_state_clk_gate_bins": 20 329 }, 330 "fake_l2_3": { 331 "pio": { 332 "peer": "system.iobus.master[4]", 333 "role": "SLAVE" 334 }, 335 "ret_data64": 1, 336 "fake_mem": false, 337 "clk_domain": "system.clk_domain", 338 "cxx_class": "IsaFake", 339 "pio_addr": 725849473152, 340 "update_data": true, 341 "warn_access": "", 342 "pio_latency": 200, 343 "system": "system", 344 "eventq_index": 0, 345 "default_p_state": "UNDEFINED", 346 "p_state_clk_gate_max": 2000000000, 347 "type": "IsaFake", 348 "p_state_clk_gate_min": 2, 349 "ret_data32": 4294967295, 350 "path": "system.t1000.fake_l2_3", 351 "ret_data16": 65535, 352 "ret_data8": 255, 353 "name": "fake_l2_3", 354 "ret_bad_addr": false, 355 "pio_size": 8, 356 "p_state_clk_gate_bins": 20 357 }, 358 "pterm": { 359 "name": "pterm", 360 "output": true, 361 "number": 0, 362 "intr_control": "system.intrctrl", 363 "eventq_index": 0, 364 "cxx_class": "Terminal", 365 "path": "system.t1000.pterm", 366 "type": "Terminal", 367 "port": 3456 368 }, 369 "path": "system.t1000", 370 "iob": { 371 "name": "iob", 372 "p_state_clk_gate_min": 2, 373 "pio": { 374 "peer": "system.membus.master[0]", 375 "role": "SLAVE" 376 }, 377 "p_state_clk_gate_bins": 20, 378 "cxx_class": "Iob", 379 "pio_latency": 2, 380 "clk_domain": "system.clk_domain", 381 "system": "system", 382 "platform": "system.t1000", 383 "eventq_index": 0, 384 "default_p_state": "UNDEFINED", 385 "p_state_clk_gate_max": 2000000000, 386 "path": "system.t1000.iob", 387 "type": "Iob" 388 }, 389 "hvuart": { 390 "name": "hvuart", 391 "p_state_clk_gate_min": 2, 392 "pio": { 393 "peer": "system.iobus.master[13]", 394 "role": "SLAVE" 395 }, 396 "p_state_clk_gate_bins": 20, 397 "cxx_class": "Uart8250", 398 "pio_latency": 200, 399 "clk_domain": "system.clk_domain", 400 "system": "system", 401 "terminal": "system.t1000.hterm", 402 "platform": "system.t1000", 403 "eventq_index": 0, 404 "default_p_state": "UNDEFINED", 405 "p_state_clk_gate_max": 2000000000, 406 "path": "system.t1000.hvuart", 407 "pio_addr": 1099255955456, 408 "type": "Uart8250" 409 }, 410 "name": "t1000", 411 "fake_l2esr_3": { 412 "pio": { 413 "peer": "system.iobus.master[8]", 414 "role": "SLAVE" 415 }, 416 "ret_data64": 0, 417 "fake_mem": false, 418 "clk_domain": "system.clk_domain", 419 "cxx_class": "IsaFake", 420 "pio_addr": 734439407744, 421 "update_data": true, 422 "warn_access": "", 423 "pio_latency": 200, 424 "system": "system", 425 "eventq_index": 0, 426 "default_p_state": "UNDEFINED", 427 "p_state_clk_gate_max": 2000000000, 428 "type": "IsaFake", 429 "p_state_clk_gate_min": 2, 430 "ret_data32": 4294967295, 431 "path": "system.t1000.fake_l2esr_3", 432 "ret_data16": 65535, 433 "ret_data8": 255, 434 "name": "fake_l2esr_3", 435 "ret_bad_addr": false, 436 "pio_size": 8, 437 "p_state_clk_gate_bins": 20 438 }, 439 "fake_ssi": { 440 "pio": { 441 "peer": "system.iobus.master[10]", 442 "role": "SLAVE" 443 }, 444 "ret_data64": 18446744073709551615, 445 "fake_mem": false, 446 "clk_domain": "system.clk_domain", 447 "cxx_class": "IsaFake", 448 "pio_addr": 1095216660480, 449 "update_data": false, 450 "warn_access": "", 451 "pio_latency": 200, 452 "system": "system", 453 "eventq_index": 0, 454 "default_p_state": "UNDEFINED", 455 "p_state_clk_gate_max": 2000000000, 456 "type": "IsaFake", 457 "p_state_clk_gate_min": 2, 458 "ret_data32": 4294967295, 459 "path": "system.t1000.fake_ssi", 460 "ret_data16": 65535, 461 "ret_data8": 255, 462 "name": "fake_ssi", 463 "ret_bad_addr": false, 464 "pio_size": 268435456, 465 "p_state_clk_gate_bins": 20 466 }, 467 "fake_l2esr_1": { 468 "pio": { 469 "peer": "system.iobus.master[6]", 470 "role": "SLAVE" 471 }, 472 "ret_data64": 0, 473 "fake_mem": false, 474 "clk_domain": "system.clk_domain", 475 "cxx_class": "IsaFake", 476 "pio_addr": 734439407616, 477 "update_data": true, 478 "warn_access": "", 479 "pio_latency": 200, 480 "system": "system", 481 "eventq_index": 0, 482 "default_p_state": "UNDEFINED", 483 "p_state_clk_gate_max": 2000000000, 484 "type": "IsaFake", 485 "p_state_clk_gate_min": 2, 486 "ret_data32": 4294967295, 487 "path": "system.t1000.fake_l2esr_1", 488 "ret_data16": 65535, 489 "ret_data8": 255, 490 "name": "fake_l2esr_1", 491 "ret_bad_addr": false, 492 "pio_size": 8, 493 "p_state_clk_gate_bins": 20 494 }, 495 "fake_l2esr_4": { 496 "pio": { 497 "peer": "system.iobus.master[9]", 498 "role": "SLAVE" 499 }, 500 "ret_data64": 0, 501 "fake_mem": false, 502 "clk_domain": "system.clk_domain", 503 "cxx_class": "IsaFake", 504 "pio_addr": 734439407808, 505 "update_data": true, 506 "warn_access": "", 507 "pio_latency": 200, 508 "system": "system", 509 "eventq_index": 0, 510 "default_p_state": "UNDEFINED", 511 "p_state_clk_gate_max": 2000000000, 512 "type": "IsaFake", 513 "p_state_clk_gate_min": 2, 514 "ret_data32": 4294967295, 515 "path": "system.t1000.fake_l2esr_4", 516 "ret_data16": 65535, 517 "ret_data8": 255, 518 "name": "fake_l2esr_4", 519 "ret_bad_addr": false, 520 "pio_size": 8, 521 "p_state_clk_gate_bins": 20 522 }, 523 "fake_clk": { 524 "pio": { 525 "peer": "system.iobus.master[0]", 526 "role": "SLAVE" 527 }, 528 "ret_data64": 18446744073709551615, 529 "fake_mem": false, 530 "clk_domain": "system.clk_domain", 531 "cxx_class": "IsaFake", 532 "pio_addr": 644245094400, 533 "update_data": false, 534 "warn_access": "", 535 "pio_latency": 200, 536 "system": "system", 537 "eventq_index": 0, 538 "default_p_state": "UNDEFINED", 539 "p_state_clk_gate_max": 2000000000, 540 "type": "IsaFake", 541 "p_state_clk_gate_min": 2, 542 "ret_data32": 4294967295, 543 "path": "system.t1000.fake_clk", 544 "ret_data16": 65535, 545 "ret_data8": 255, 546 "name": "fake_clk", 547 "ret_bad_addr": false, 548 "pio_size": 4294967296, 549 "p_state_clk_gate_bins": 20 550 } 551 }, 552 "partition_desc_addr": 133445976064, 553 "symbolfile": "", 554 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 555 "thermal_model": null, 556 "hypervisor_addr": 1099243257856, 557 "mem_ranges": [ 558 "1048576:68157439", 559 "2147483648:2415919103" 560 ], 561 "cxx_class": "SparcSystem", 562 "work_begin_cpu_id_exit": -1, 563 "load_offset": 0, 564 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 565 "work_end_ckpt_count": 0, 566 "work_begin_exit_count": 0, 567 "openboot_addr": 1099243716608, 568 "p_state_clk_gate_min": 2, 569 "nvram_addr": 133429198848, 570 "memories": [ 571 "system.hypervisor_desc", 572 "system.nvram", 573 "system.partition_desc", 574 "system.physmem0", 575 "system.physmem1", 576 "system.rom" 577 ], 578 "work_begin_ckpt_count": 0, 579 "partition_desc": { 580 "range": "133445976064:133445984255", 581 "latency": 60, 582 "name": "partition_desc", 583 "p_state_clk_gate_min": 2, 584 "eventq_index": 0, 585 "p_state_clk_gate_bins": 20, 586 "default_p_state": "UNDEFINED", 587 "clk_domain": "system.clk_domain", 588 "latency_var": 0, 589 "bandwidth": "0.000000", 590 "conf_table_reported": true, 591 "cxx_class": "SimpleMemory", 592 "p_state_clk_gate_max": 2000000000, 593 "path": "system.partition_desc", 594 "null": false, 595 "type": "SimpleMemory", 596 "port": { 597 "peer": "system.membus.master[6]", 598 "role": "SLAVE" 599 }, 600 "in_addr_map": true 601 }, 602 "clk_domain": { 603 "name": "clk_domain", 604 "clock": [ 605 2 606 ], 607 "init_perf_level": 0, 608 "voltage_domain": "system.voltage_domain", 609 "eventq_index": 0, 610 "cxx_class": "SrcClockDomain", 611 "path": "system.clk_domain", 612 "type": "SrcClockDomain", 613 "domain_id": -1 614 }, 615 "hypervisor_desc": { 616 "range": "133446500352:133446508543", 617 "latency": 60, 618 "name": "hypervisor_desc", 619 "p_state_clk_gate_min": 2, 620 "eventq_index": 0, 621 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659 "p_state_clk_gate_max": 2000000000, 660 "type": "IsaFake", 661 "p_state_clk_gate_min": 2, 662 "ret_data32": 4294967295, 663 "path": "system.membus.badaddr_responder", 664 "ret_data16": 65535, 665 "ret_data8": 255, 666 "name": "badaddr_responder", 667 "ret_bad_addr": true, 668 "pio_size": 8, 669 "p_state_clk_gate_bins": 20 670 }, 671 "forward_latency": 4, 672 "clk_domain": "system.clk_domain", 673 "width": 16, 674 "eventq_index": 0, 675 "default_p_state": "UNDEFINED", 676 "p_state_clk_gate_max": 2000000000, 677 "master": { 678 "peer": [ 679 "system.t1000.iob.pio", 680 "system.t1000.htod.pio", 681 "system.bridge.slave", 682 "system.rom.port", 683 "system.nvram.port", 684 "system.hypervisor_desc.port", 685 "system.partition_desc.port", 686 "system.physmem0.port", 687 "system.physmem1.port" 688 ], 689 "role": "MASTER" 690 }, 691 "type": "CoherentXBar", 692 "frontend_latency": 3, 693 "slave": { 694 "peer": [ 695 "system.system_port", 696 "system.cpu.icache_port", 697 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