config.ini revision 11946:8eb1f2595a92
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=200000000 9time_sync_spin_threshold=200000 10 11[system] 12type=SparcSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20hypervisor_addr=1099243257856 21hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin 22hypervisor_desc=system.hypervisor_desc 23hypervisor_desc_addr=133446500352 24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin 25init_param=0 26kernel= 27kernel_addr_check=true 28load_addr_mask=1099511627775 29load_offset=0 30mem_mode=atomic 31mem_ranges=1048576:68157439 2147483648:2415919103 32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom 33mmap_using_noreserve=false 34multi_thread=false 35num_work_ids=16 36nvram=system.nvram 37nvram_addr=133429198848 38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1 39openboot_addr=1099243716608 40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin 41p_state_clk_gate_bins=20 42p_state_clk_gate_max=2000000000 43p_state_clk_gate_min=2 44partition_desc=system.partition_desc 45partition_desc_addr=133445976064 46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin 47readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh 48reset_addr=1099243192320 49reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin 50rom=system.rom 51symbolfile= 52thermal_components= 53thermal_model=Null 54work_begin_ckpt_count=0 55work_begin_cpu_id_exit=-1 56work_begin_exit_count=0 57work_cpus_ckpt_count=0 58work_end_ckpt_count=0 59work_end_exit_count=0 60work_item_id=-1 61system_port=system.membus.slave[0] 62 63[system.bridge] 64type=Bridge 65clk_domain=system.clk_domain 66default_p_state=UNDEFINED 67delay=100 68eventq_index=0 69p_state_clk_gate_bins=20 70p_state_clk_gate_max=2000000000 71p_state_clk_gate_min=2 72ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 73req_size=16 74resp_size=16 75master=system.iobus.slave[0] 76slave=system.membus.master[2] 77 78[system.clk_domain] 79type=SrcClockDomain 80clock=2 81domain_id=-1 82eventq_index=0 83init_perf_level=0 84voltage_domain=system.voltage_domain 85 86[system.cpu] 87type=AtomicSimpleCPU 88children=dtb interrupts isa itb tracer 89branchPred=Null 90checker=Null 91clk_domain=system.cpu_clk_domain 92cpu_id=0 93default_p_state=UNDEFINED 94do_checkpoint_insts=true 95do_quiesce=true 96do_statistics_insts=true 97dtb=system.cpu.dtb 98eventq_index=0 99fastmem=false 100function_trace=false 101function_trace_start=0 102interrupts=system.cpu.interrupts 103isa=system.cpu.isa 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109numThreads=1 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=2000000000 112p_state_clk_gate_min=2 113profile=0 114progress_interval=0 115simpoint_start_insts= 116simulate_data_stalls=false 117simulate_inst_stalls=false 118socket_id=0 119switched_out=false 120system=system 121tracer=system.cpu.tracer 122width=1 123workload= 124dcache_port=system.membus.slave[2] 125icache_port=system.membus.slave[1] 126 127[system.cpu.dtb] 128type=SparcTLB 129eventq_index=0 130size=64 131 132[system.cpu.interrupts] 133type=SparcInterrupts 134eventq_index=0 135 136[system.cpu.isa] 137type=SparcISA 138eventq_index=0 139 140[system.cpu.itb] 141type=SparcTLB 142eventq_index=0 143size=64 144 145[system.cpu.tracer] 146type=ExeTracer 147eventq_index=0 148 149[system.cpu_clk_domain] 150type=SrcClockDomain 151clock=2 152domain_id=-1 153eventq_index=0 154init_perf_level=0 155voltage_domain=system.voltage_domain 156 157[system.disk0] 158type=MmDisk 159children=image 160clk_domain=system.clk_domain 161default_p_state=UNDEFINED 162eventq_index=0 163image=system.disk0.image 164p_state_clk_gate_bins=20 165p_state_clk_gate_max=2000000000 166p_state_clk_gate_min=2 167pio_addr=134217728000 168pio_latency=200 169system=system 170pio=system.iobus.master[14] 171 172[system.disk0.image] 173type=CowDiskImage 174children=child 175child=system.disk0.image.child 176eventq_index=0 177image_file= 178read_only=false 179table_size=65536 180 181[system.disk0.image.child] 182type=RawDiskImage 183eventq_index=0 184image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2 185read_only=true 186 187[system.dvfs_handler] 188type=DVFSHandler 189domains= 190enable=false 191eventq_index=0 192sys_clk_domain=system.clk_domain 193transition_latency=200000 194 195[system.hypervisor_desc] 196type=SimpleMemory 197bandwidth=0.000000 198clk_domain=system.clk_domain 199conf_table_reported=true 200default_p_state=UNDEFINED 201eventq_index=0 202in_addr_map=true 203latency=60 204latency_var=0 205null=false 206p_state_clk_gate_bins=20 207p_state_clk_gate_max=2000000000 208p_state_clk_gate_min=2 209range=133446500352:133446508543 210port=system.membus.master[5] 211 212[system.intrctrl] 213type=IntrControl 214eventq_index=0 215sys=system 216 217[system.iobus] 218type=NoncoherentXBar 219clk_domain=system.clk_domain 220default_p_state=UNDEFINED 221eventq_index=0 222forward_latency=1 223frontend_latency=2 224p_state_clk_gate_bins=20 225p_state_clk_gate_max=2000000000 226p_state_clk_gate_min=2 227response_latency=2 228use_default_range=false 229width=16 230master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 231slave=system.bridge.master 232 233[system.membus] 234type=CoherentXBar 235children=badaddr_responder 236clk_domain=system.clk_domain 237default_p_state=UNDEFINED 238eventq_index=0 239forward_latency=4 240frontend_latency=3 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=2000000000 243p_state_clk_gate_min=2 244point_of_coherency=true 245response_latency=2 246snoop_filter=Null 247snoop_response_latency=4 248system=system 249use_default_range=false 250width=16 251default=system.membus.badaddr_responder.pio 252master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port 253slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 254 255[system.membus.badaddr_responder] 256type=IsaFake 257clk_domain=system.clk_domain 258default_p_state=UNDEFINED 259eventq_index=0 260fake_mem=false 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=2000000000 263p_state_clk_gate_min=2 264pio_addr=0 265pio_latency=200 266pio_size=8 267ret_bad_addr=true 268ret_data16=65535 269ret_data32=4294967295 270ret_data64=18446744073709551615 271ret_data8=255 272system=system 273update_data=false 274warn_access= 275pio=system.membus.default 276 277[system.nvram] 278type=SimpleMemory 279bandwidth=0.000000 280clk_domain=system.clk_domain 281conf_table_reported=true 282default_p_state=UNDEFINED 283eventq_index=0 284in_addr_map=true 285latency=60 286latency_var=0 287null=false 288p_state_clk_gate_bins=20 289p_state_clk_gate_max=2000000000 290p_state_clk_gate_min=2 291range=133429198848:133429207039 292port=system.membus.master[4] 293 294[system.partition_desc] 295type=SimpleMemory 296bandwidth=0.000000 297clk_domain=system.clk_domain 298conf_table_reported=true 299default_p_state=UNDEFINED 300eventq_index=0 301in_addr_map=true 302latency=60 303latency_var=0 304null=false 305p_state_clk_gate_bins=20 306p_state_clk_gate_max=2000000000 307p_state_clk_gate_min=2 308range=133445976064:133445984255 309port=system.membus.master[6] 310 311[system.physmem0] 312type=SimpleMemory 313bandwidth=0.000000 314clk_domain=system.clk_domain 315conf_table_reported=true 316default_p_state=UNDEFINED 317eventq_index=0 318in_addr_map=true 319latency=60 320latency_var=0 321null=false 322p_state_clk_gate_bins=20 323p_state_clk_gate_max=2000000000 324p_state_clk_gate_min=2 325range=1048576:68157439 326port=system.membus.master[7] 327 328[system.physmem1] 329type=SimpleMemory 330bandwidth=0.000000 331clk_domain=system.clk_domain 332conf_table_reported=true 333default_p_state=UNDEFINED 334eventq_index=0 335in_addr_map=true 336latency=60 337latency_var=0 338null=false 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=2000000000 341p_state_clk_gate_min=2 342range=2147483648:2415919103 343port=system.membus.master[8] 344 345[system.rom] 346type=SimpleMemory 347bandwidth=0.000000 348clk_domain=system.clk_domain 349conf_table_reported=true 350default_p_state=UNDEFINED 351eventq_index=0 352in_addr_map=true 353latency=60 354latency_var=0 355null=false 356p_state_clk_gate_bins=20 357p_state_clk_gate_max=2000000000 358p_state_clk_gate_min=2 359range=1099243192320:1099251580927 360port=system.membus.master[3] 361 362[system.t1000] 363type=T1000 364children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 365eventq_index=0 366intrctrl=system.intrctrl 367system=system 368 369[system.t1000.fake_clk] 370type=IsaFake 371clk_domain=system.clk_domain 372default_p_state=UNDEFINED 373eventq_index=0 374fake_mem=false 375p_state_clk_gate_bins=20 376p_state_clk_gate_max=2000000000 377p_state_clk_gate_min=2 378pio_addr=644245094400 379pio_latency=200 380pio_size=4294967296 381ret_bad_addr=false 382ret_data16=65535 383ret_data32=4294967295 384ret_data64=18446744073709551615 385ret_data8=255 386system=system 387update_data=false 388warn_access= 389pio=system.iobus.master[0] 390 391[system.t1000.fake_jbi] 392type=IsaFake 393clk_domain=system.clk_domain 394default_p_state=UNDEFINED 395eventq_index=0 396fake_mem=false 397p_state_clk_gate_bins=20 398p_state_clk_gate_max=2000000000 399p_state_clk_gate_min=2 400pio_addr=549755813888 401pio_latency=200 402pio_size=4294967296 403ret_bad_addr=false 404ret_data16=65535 405ret_data32=4294967295 406ret_data64=18446744073709551615 407ret_data8=255 408system=system 409update_data=false 410warn_access= 411pio=system.iobus.master[11] 412 413[system.t1000.fake_l2_1] 414type=IsaFake 415clk_domain=system.clk_domain 416default_p_state=UNDEFINED 417eventq_index=0 418fake_mem=false 419p_state_clk_gate_bins=20 420p_state_clk_gate_max=2000000000 421p_state_clk_gate_min=2 422pio_addr=725849473024 423pio_latency=200 424pio_size=8 425ret_bad_addr=false 426ret_data16=65535 427ret_data32=4294967295 428ret_data64=1 429ret_data8=255 430system=system 431update_data=true 432warn_access= 433pio=system.iobus.master[2] 434 435[system.t1000.fake_l2_2] 436type=IsaFake 437clk_domain=system.clk_domain 438default_p_state=UNDEFINED 439eventq_index=0 440fake_mem=false 441p_state_clk_gate_bins=20 442p_state_clk_gate_max=2000000000 443p_state_clk_gate_min=2 444pio_addr=725849473088 445pio_latency=200 446pio_size=8 447ret_bad_addr=false 448ret_data16=65535 449ret_data32=4294967295 450ret_data64=1 451ret_data8=255 452system=system 453update_data=true 454warn_access= 455pio=system.iobus.master[3] 456 457[system.t1000.fake_l2_3] 458type=IsaFake 459clk_domain=system.clk_domain 460default_p_state=UNDEFINED 461eventq_index=0 462fake_mem=false 463p_state_clk_gate_bins=20 464p_state_clk_gate_max=2000000000 465p_state_clk_gate_min=2 466pio_addr=725849473152 467pio_latency=200 468pio_size=8 469ret_bad_addr=false 470ret_data16=65535 471ret_data32=4294967295 472ret_data64=1 473ret_data8=255 474system=system 475update_data=true 476warn_access= 477pio=system.iobus.master[4] 478 479[system.t1000.fake_l2_4] 480type=IsaFake 481clk_domain=system.clk_domain 482default_p_state=UNDEFINED 483eventq_index=0 484fake_mem=false 485p_state_clk_gate_bins=20 486p_state_clk_gate_max=2000000000 487p_state_clk_gate_min=2 488pio_addr=725849473216 489pio_latency=200 490pio_size=8 491ret_bad_addr=false 492ret_data16=65535 493ret_data32=4294967295 494ret_data64=1 495ret_data8=255 496system=system 497update_data=true 498warn_access= 499pio=system.iobus.master[5] 500 501[system.t1000.fake_l2esr_1] 502type=IsaFake 503clk_domain=system.clk_domain 504default_p_state=UNDEFINED 505eventq_index=0 506fake_mem=false 507p_state_clk_gate_bins=20 508p_state_clk_gate_max=2000000000 509p_state_clk_gate_min=2 510pio_addr=734439407616 511pio_latency=200 512pio_size=8 513ret_bad_addr=false 514ret_data16=65535 515ret_data32=4294967295 516ret_data64=0 517ret_data8=255 518system=system 519update_data=true 520warn_access= 521pio=system.iobus.master[6] 522 523[system.t1000.fake_l2esr_2] 524type=IsaFake 525clk_domain=system.clk_domain 526default_p_state=UNDEFINED 527eventq_index=0 528fake_mem=false 529p_state_clk_gate_bins=20 530p_state_clk_gate_max=2000000000 531p_state_clk_gate_min=2 532pio_addr=734439407680 533pio_latency=200 534pio_size=8 535ret_bad_addr=false 536ret_data16=65535 537ret_data32=4294967295 538ret_data64=0 539ret_data8=255 540system=system 541update_data=true 542warn_access= 543pio=system.iobus.master[7] 544 545[system.t1000.fake_l2esr_3] 546type=IsaFake 547clk_domain=system.clk_domain 548default_p_state=UNDEFINED 549eventq_index=0 550fake_mem=false 551p_state_clk_gate_bins=20 552p_state_clk_gate_max=2000000000 553p_state_clk_gate_min=2 554pio_addr=734439407744 555pio_latency=200 556pio_size=8 557ret_bad_addr=false 558ret_data16=65535 559ret_data32=4294967295 560ret_data64=0 561ret_data8=255 562system=system 563update_data=true 564warn_access= 565pio=system.iobus.master[8] 566 567[system.t1000.fake_l2esr_4] 568type=IsaFake 569clk_domain=system.clk_domain 570default_p_state=UNDEFINED 571eventq_index=0 572fake_mem=false 573p_state_clk_gate_bins=20 574p_state_clk_gate_max=2000000000 575p_state_clk_gate_min=2 576pio_addr=734439407808 577pio_latency=200 578pio_size=8 579ret_bad_addr=false 580ret_data16=65535 581ret_data32=4294967295 582ret_data64=0 583ret_data8=255 584system=system 585update_data=true 586warn_access= 587pio=system.iobus.master[9] 588 589[system.t1000.fake_membnks] 590type=IsaFake 591clk_domain=system.clk_domain 592default_p_state=UNDEFINED 593eventq_index=0 594fake_mem=false 595p_state_clk_gate_bins=20 596p_state_clk_gate_max=2000000000 597p_state_clk_gate_min=2 598pio_addr=648540061696 599pio_latency=200 600pio_size=16384 601ret_bad_addr=false 602ret_data16=65535 603ret_data32=4294967295 604ret_data64=0 605ret_data8=255 606system=system 607update_data=false 608warn_access= 609pio=system.iobus.master[1] 610 611[system.t1000.fake_ssi] 612type=IsaFake 613clk_domain=system.clk_domain 614default_p_state=UNDEFINED 615eventq_index=0 616fake_mem=false 617p_state_clk_gate_bins=20 618p_state_clk_gate_max=2000000000 619p_state_clk_gate_min=2 620pio_addr=1095216660480 621pio_latency=200 622pio_size=268435456 623ret_bad_addr=false 624ret_data16=65535 625ret_data32=4294967295 626ret_data64=18446744073709551615 627ret_data8=255 628system=system 629update_data=false 630warn_access= 631pio=system.iobus.master[10] 632 633[system.t1000.hterm] 634type=Terminal 635eventq_index=0 636intr_control=system.intrctrl 637number=0 638output=true 639port=3456 640 641[system.t1000.htod] 642type=DumbTOD 643clk_domain=system.clk_domain 644default_p_state=UNDEFINED 645eventq_index=0 646p_state_clk_gate_bins=20 647p_state_clk_gate_max=2000000000 648p_state_clk_gate_min=2 649pio_addr=1099255906296 650pio_latency=200 651system=system 652time=Thu Jan 1 00:00:00 2009 653pio=system.membus.master[1] 654 655[system.t1000.hvuart] 656type=Uart8250 657clk_domain=system.clk_domain 658default_p_state=UNDEFINED 659eventq_index=0 660p_state_clk_gate_bins=20 661p_state_clk_gate_max=2000000000 662p_state_clk_gate_min=2 663pio_addr=1099255955456 664pio_latency=200 665platform=system.t1000 666system=system 667terminal=system.t1000.hterm 668pio=system.iobus.master[13] 669 670[system.t1000.iob] 671type=Iob 672clk_domain=system.clk_domain 673default_p_state=UNDEFINED 674eventq_index=0 675p_state_clk_gate_bins=20 676p_state_clk_gate_max=2000000000 677p_state_clk_gate_min=2 678pio_latency=2 679platform=system.t1000 680system=system 681pio=system.membus.master[0] 682 683[system.t1000.pterm] 684type=Terminal 685eventq_index=0 686intr_control=system.intrctrl 687number=0 688output=true 689port=3456 690 691[system.t1000.puart0] 692type=Uart8250 693clk_domain=system.clk_domain 694default_p_state=UNDEFINED 695eventq_index=0 696p_state_clk_gate_bins=20 697p_state_clk_gate_max=2000000000 698p_state_clk_gate_min=2 699pio_addr=133412421632 700pio_latency=200 701platform=system.t1000 702system=system 703terminal=system.t1000.pterm 704pio=system.iobus.master[12] 705 706[system.voltage_domain] 707type=VoltageDomain 708eventq_index=0 709voltage=1.000000 710 711