stats.txt revision 10645
18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
310645Snilay@cs.wisc.edusim_seconds                                  5.305853                       # Number of seconds simulated
410645Snilay@cs.wisc.edusim_ticks                                5305853045500                       # Number of ticks simulated
510645Snilay@cs.wisc.edufinal_tick                               5305853045500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
710645Snilay@cs.wisc.eduhost_inst_rate                                 145601                       # Simulator instruction rate (inst/s)
810645Snilay@cs.wisc.eduhost_op_rate                                   279059                       # Simulator op (including micro ops) rate (op/s)
910645Snilay@cs.wisc.eduhost_tick_rate                             7202357719                       # Simulator tick rate (ticks/s)
1010645Snilay@cs.wisc.eduhost_mem_usage                                 842312                       # Number of bytes of host memory used
1110645Snilay@cs.wisc.eduhost_seconds                                   736.68                       # Real time elapsed on the host
1210645Snilay@cs.wisc.edusim_insts                                   107261903                       # Number of instructions simulated
1310645Snilay@cs.wisc.edusim_ops                                     205578304                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1610645Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11415232                       # Number of bytes read from this memory
1710645Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total           11415232                       # Number of bytes read from this memory
1810645Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9161984                       # Number of bytes written to this memory
1910645Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total         9161984                       # Number of bytes written to this memory
2010645Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0       178363                       # Number of read requests responded to by this memory
2110645Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total              178363                       # Number of read requests responded to by this memory
2210645Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0       143156                       # Number of write requests responded to by this memory
2310645Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total             143156                       # Number of write requests responded to by this memory
2410645Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2151441                       # Total read bandwidth from this memory (bytes/s)
2510645Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::total               2151441                       # Total read bandwidth from this memory (bytes/s)
2610645Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1726769                       # Write bandwidth from this memory (bytes/s)
2710645Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::total              1726769                       # Write bandwidth from this memory (bytes/s)
2810645Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::ruby.dir_cntrl0      3878211                       # Total bandwidth to/from this memory (bytes/s)
2910645Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::total              3878211                       # Total bandwidth to/from this memory (bytes/s)
3010645Snilay@cs.wisc.edusystem.mem_ctrls.readReqs                      178363                       # Number of read requests accepted
3110645Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs                     143156                       # Number of write requests accepted
3210645Snilay@cs.wisc.edusystem.mem_ctrls.readBursts                    178363                       # Number of DRAM read bursts, including those serviced by the write queue
3310645Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts                   143156                       # Number of DRAM write bursts, including those merged in the write queue
3410645Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM               11360576                       # Total number of bytes read from DRAM
3510645Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ                   54656                       # Total number of bytes read from write queue
3610645Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten                 9153536                       # Total number of bytes written to DRAM
3710645Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys                11415232                       # Total read bytes from the system interface side
3810645Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys              9161984                       # Total written bytes from the system interface side
3910645Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ                    854                       # Number of DRAM read bursts serviced by the write queue
4010645Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts                   108                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4210645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0             10856                       # Per bank write bursts
4310645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1             10881                       # Per bank write bursts
4410645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2             10729                       # Per bank write bursts
4510645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3             11226                       # Per bank write bursts
4610645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4             11595                       # Per bank write bursts
4710645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5             12060                       # Per bank write bursts
4810645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6             11357                       # Per bank write bursts
4910645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7             10544                       # Per bank write bursts
5010645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8             10640                       # Per bank write bursts
5110645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9             10408                       # Per bank write bursts
5210645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10            10338                       # Per bank write bursts
5310645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11            14247                       # Per bank write bursts
5410645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12            10851                       # Per bank write bursts
5510645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13            10291                       # Per bank write bursts
5610645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14            10803                       # Per bank write bursts
5710645Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15            10683                       # Per bank write bursts
5810645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0              8741                       # Per bank write bursts
5910645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1              8453                       # Per bank write bursts
6010645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2              8515                       # Per bank write bursts
6110645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3              9195                       # Per bank write bursts
6210645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4              9530                       # Per bank write bursts
6310645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5              9557                       # Per bank write bursts
6410645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6              9142                       # Per bank write bursts
6510645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7              8665                       # Per bank write bursts
6610645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8              8844                       # Per bank write bursts
6710645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9              8855                       # Per bank write bursts
6810645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10             8455                       # Per bank write bursts
6910645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11             9314                       # Per bank write bursts
7010645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12             8873                       # Per bank write bursts
7110645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13             8616                       # Per bank write bursts
7210645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14             9161                       # Per bank write bursts
7310645Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15             9108                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7610645Snilay@cs.wisc.edusystem.mem_ctrls.totGap                  5305852911000                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8310645Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6                178363                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9010645Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6               143156                       # Write request sizes (log2)
9110645Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0                  177440                       # What read queue length does an incoming req see
9210645Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                      69                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13810645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15                   2057                       # What write queue length does an incoming req see
13910645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16                   2808                       # What write queue length does an incoming req see
14010645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17                   8578                       # What write queue length does an incoming req see
14110645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18                   9141                       # What write queue length does an incoming req see
14210645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19                   8600                       # What write queue length does an incoming req see
14310645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20                   9229                       # What write queue length does an incoming req see
14410645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21                   9219                       # What write queue length does an incoming req see
14510645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                   8361                       # What write queue length does an incoming req see
14610645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                   9057                       # What write queue length does an incoming req see
14710645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24                   9077                       # What write queue length does an incoming req see
14810645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25                   8449                       # What write queue length does an incoming req see
14910645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26                   8526                       # What write queue length does an incoming req see
15010645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27                   8348                       # What write queue length does an incoming req see
15110645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                   8471                       # What write queue length does an incoming req see
15210645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                   8060                       # What write queue length does an incoming req see
15310645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                   8092                       # What write queue length does an incoming req see
15410645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                   8178                       # What write queue length does an incoming req see
15510645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                   7986                       # What write queue length does an incoming req see
15610645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                    125                       # What write queue length does an incoming req see
15710645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                    114                       # What write queue length does an incoming req see
15810645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                    101                       # What write queue length does an incoming req see
15910645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                     94                       # What write queue length does an incoming req see
16010645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37                     84                       # What write queue length does an incoming req see
16110645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                     73                       # What write queue length does an incoming req see
16210645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                     59                       # What write queue length does an incoming req see
16310628Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::40                     51                       # What write queue length does an incoming req see
16410645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                     33                       # What write queue length does an incoming req see
16510645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                     27                       # What write queue length does an incoming req see
16610645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                     19                       # What write queue length does an incoming req see
16710645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      9                       # What write queue length does an incoming req see
16810645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      3                       # What write queue length does an incoming req see
16910645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      2                       # What write queue length does an incoming req see
17010645Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      2                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18710645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples        60721                       # Bytes accessed per row activation
18810645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean    337.841076                       # Bytes accessed per row activation
18910645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean   199.411090                       # Bytes accessed per row activation
19010645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev   344.057801                       # Bytes accessed per row activation
19110645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127        20489     33.74%     33.74% # Bytes accessed per row activation
19210645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255        14673     24.16%     57.91% # Bytes accessed per row activation
19310645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383         6364     10.48%     68.39% # Bytes accessed per row activation
19410645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511         3396      5.59%     73.98% # Bytes accessed per row activation
19510645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639         2745      4.52%     78.50% # Bytes accessed per row activation
19610645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767         1826      3.01%     81.51% # Bytes accessed per row activation
19710645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895         1362      2.24%     83.75% # Bytes accessed per row activation
19810645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023         1430      2.36%     86.11% # Bytes accessed per row activation
19910645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151         8436     13.89%    100.00% # Bytes accessed per row activation
20010645Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total        60721                       # Bytes accessed per row activation
20110645Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples         7928                       # Reads before turning the bus around for writes
20210645Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      22.388118                       # Reads before turning the bus around for writes
20310645Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev    317.537098                       # Reads before turning the bus around for writes
20410645Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::0-1023         7922     99.92%     99.92% # Reads before turning the bus around for writes
20510526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::1024-2047            2      0.03%     99.95% # Reads before turning the bus around for writes
20610526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::2048-3071            2      0.03%     99.97% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20910645Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total          7928                       # Reads before turning the bus around for writes
21010645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples         7928                       # Writes before turning the bus around for reads
21110645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean      18.040363                       # Writes before turning the bus around for reads
21210645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean     17.696882                       # Writes before turning the bus around for reads
21310645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      3.983964                       # Writes before turning the bus around for reads
21410645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16             5814     73.34%     73.34% # Writes before turning the bus around for reads
21510645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::17               14      0.18%     73.51% # Writes before turning the bus around for reads
21610645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18              181      2.28%     75.79% # Writes before turning the bus around for reads
21710645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19               14      0.18%     75.97% # Writes before turning the bus around for reads
21810645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::20               36      0.45%     76.43% # Writes before turning the bus around for reads
21910645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::21              489      6.17%     82.59% # Writes before turning the bus around for reads
22010645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::22              149      1.88%     84.47% # Writes before turning the bus around for reads
22110645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::23               53      0.67%     85.14% # Writes before turning the bus around for reads
22210645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::24              653      8.24%     93.38% # Writes before turning the bus around for reads
22310645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::25              113      1.43%     94.80% # Writes before turning the bus around for reads
22410645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::26                3      0.04%     94.84% # Writes before turning the bus around for reads
22510645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::27               13      0.16%     95.01% # Writes before turning the bus around for reads
22610645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::28              312      3.94%     98.94% # Writes before turning the bus around for reads
22710645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::29                4      0.05%     98.99% # Writes before turning the bus around for reads
22810645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::30               10      0.13%     99.12% # Writes before turning the bus around for reads
22910645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::31                5      0.06%     99.18% # Writes before turning the bus around for reads
23010645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::32                9      0.11%     99.29% # Writes before turning the bus around for reads
23110645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::33                9      0.11%     99.41% # Writes before turning the bus around for reads
23210645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::34                2      0.03%     99.43% # Writes before turning the bus around for reads
23310645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::35                3      0.04%     99.47% # Writes before turning the bus around for reads
23410645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::36                4      0.05%     99.52% # Writes before turning the bus around for reads
23510645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::37                5      0.06%     99.58% # Writes before turning the bus around for reads
23610645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::38                2      0.03%     99.61% # Writes before turning the bus around for reads
23710645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::39                3      0.04%     99.65% # Writes before turning the bus around for reads
23810645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::40                6      0.08%     99.72% # Writes before turning the bus around for reads
23910645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::41                2      0.03%     99.75% # Writes before turning the bus around for reads
24010645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::42                1      0.01%     99.76% # Writes before turning the bus around for reads
24110645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::43                3      0.04%     99.80% # Writes before turning the bus around for reads
24210645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::44                6      0.08%     99.87% # Writes before turning the bus around for reads
24310645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::45                2      0.03%     99.90% # Writes before turning the bus around for reads
24410645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::46                1      0.01%     99.91% # Writes before turning the bus around for reads
24510645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.92% # Writes before turning the bus around for reads
24610645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::48                1      0.01%     99.94% # Writes before turning the bus around for reads
24710645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::49                2      0.03%     99.96% # Writes before turning the bus around for reads
24810645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::51                3      0.04%    100.00% # Writes before turning the bus around for reads
24910645Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total          7928                       # Writes before turning the bus around for reads
25010645Snilay@cs.wisc.edusystem.mem_ctrls.totQLat                   1963253998                       # Total ticks spent queuing
25110645Snilay@cs.wisc.edusystem.mem_ctrls.totMemAccLat              5291547748                       # Total ticks spent from burst creation until serviced by the DRAM
25210645Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat                  887545000                       # Total ticks spent in databus transfers
25310645Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat                     11060.03                       # Average queueing delay per DRAM burst
25410526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25510645Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat                29810.03                       # Average memory access latency per DRAM burst
25610628Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBW                         2.14                       # Average DRAM read bandwidth in MiByte/s
25710645Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBW                         1.73                       # Average achieved write bandwidth in MiByte/s
25810645Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBWSys                      2.15                       # Average system read bandwidth in MiByte/s
25910645Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBWSys                      1.73                       # Average system write bandwidth in MiByte/s
26010526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
26110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
26210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26310526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26510645Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen                      24.94                       # Average write queue length when enqueuing
26610645Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits                   141459                       # Number of row buffer hits during reads
26710645Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits                  118352                       # Number of row buffer hits during writes
26810645Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate                 79.69                       # Row buffer hit rate for reads
26910628Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate                82.74                       # Row buffer hit rate for writes
27010645Snilay@cs.wisc.edusystem.mem_ctrls.avgGap                   16502455.25                       # Average gap between requests
27110645Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate                    81.05                       # Row buffer hit rate, read and write combined
27210645Snilay@cs.wisc.edusystem.mem_ctrls_0.actEnergy                231139440                       # Energy for activate commands per rank (pJ)
27310645Snilay@cs.wisc.edusystem.mem_ctrls_0.preEnergy                126117750                       # Energy for precharge commands per rank (pJ)
27410645Snilay@cs.wisc.edusystem.mem_ctrls_0.readEnergy               696134400                       # Energy for read commands per rank (pJ)
27510645Snilay@cs.wisc.edusystem.mem_ctrls_0.writeEnergy              465251040                       # Energy for write commands per rank (pJ)
27610645Snilay@cs.wisc.edusystem.mem_ctrls_0.refreshEnergy         346552109280                       # Energy for refresh commands per rank (pJ)
27710645Snilay@cs.wisc.edusystem.mem_ctrls_0.actBackEnergy         149731396200                       # Energy for active background per rank (pJ)
27810645Snilay@cs.wisc.edusystem.mem_ctrls_0.preBackEnergy         3052164794250                       # Energy for precharge background per rank (pJ)
27910645Snilay@cs.wisc.edusystem.mem_ctrls_0.totalEnergy           3549966942360                       # Total energy per rank (pJ)
28010645Snilay@cs.wisc.edusystem.mem_ctrls_0.averagePower            669.066980                       # Core power per rank (mW)
28110645Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::IDLE 5077378950000                       # Time in different power states
28210645Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::REF  177173880000                       # Time in different power states
28310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
28410645Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::ACT   51294057500                       # Time in different power states
28510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
28610645Snilay@cs.wisc.edusystem.mem_ctrls_1.actEnergy                227911320                       # Energy for activate commands per rank (pJ)
28710645Snilay@cs.wisc.edusystem.mem_ctrls_1.preEnergy                124356375                       # Energy for precharge commands per rank (pJ)
28810645Snilay@cs.wisc.edusystem.mem_ctrls_1.readEnergy               688428000                       # Energy for read commands per rank (pJ)
28910645Snilay@cs.wisc.edusystem.mem_ctrls_1.writeEnergy              461544480                       # Energy for write commands per rank (pJ)
29010645Snilay@cs.wisc.edusystem.mem_ctrls_1.refreshEnergy         346552109280                       # Energy for refresh commands per rank (pJ)
29110645Snilay@cs.wisc.edusystem.mem_ctrls_1.actBackEnergy         149042883510                       # Energy for active background per rank (pJ)
29210645Snilay@cs.wisc.edusystem.mem_ctrls_1.preBackEnergy         3052768752750                       # Energy for precharge background per rank (pJ)
29310645Snilay@cs.wisc.edusystem.mem_ctrls_1.totalEnergy           3549865985715                       # Total energy per rank (pJ)
29410645Snilay@cs.wisc.edusystem.mem_ctrls_1.averagePower            669.047952                       # Core power per rank (mW)
29510645Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::IDLE 5078391595500                       # Time in different power states
29610645Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::REF  177173880000                       # Time in different power states
29710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
29810645Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::ACT   50287445500                       # Time in different power states
29910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
30010315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
30110036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
30210645Snilay@cs.wisc.edusystem.cpu0.numCycles                     10611706091                       # number of cpu cycles simulated
3038968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
3048968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
30510645Snilay@cs.wisc.edusystem.cpu0.committedInsts                   59111887                       # Number of instructions committed
30610645Snilay@cs.wisc.edusystem.cpu0.committedOps                    113456709                       # Number of ops (including micro ops) committed
30710645Snilay@cs.wisc.edusystem.cpu0.num_int_alu_accesses            106426265                       # Number of integer alu accesses
30810645Snilay@cs.wisc.edusystem.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
30910645Snilay@cs.wisc.edusystem.cpu0.num_func_calls                    1016173                       # number of times a function call or return occured
31010645Snilay@cs.wisc.edusystem.cpu0.num_conditional_control_insts     10055603                       # number of instructions that are conditional controls
31110645Snilay@cs.wisc.edusystem.cpu0.num_int_insts                   106426265                       # number of integer instructions
31210645Snilay@cs.wisc.edusystem.cpu0.num_fp_insts                           48                       # number of float instructions
31310645Snilay@cs.wisc.edusystem.cpu0.num_int_register_reads          200823032                       # number of times the integer registers were read
31410645Snilay@cs.wisc.edusystem.cpu0.num_int_register_writes          90335124                       # number of times the integer registers were written
31510645Snilay@cs.wisc.edusystem.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
3168968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
31710645Snilay@cs.wisc.edusystem.cpu0.num_cc_register_reads            61044422                       # number of times the CC registers were read
31810645Snilay@cs.wisc.edusystem.cpu0.num_cc_register_writes           44109295                       # number of times the CC registers were written
31910645Snilay@cs.wisc.edusystem.cpu0.num_mem_refs                     12452626                       # number of memory refs
32010645Snilay@cs.wisc.edusystem.cpu0.num_load_insts                    7522002                       # Number of load instructions
32110645Snilay@cs.wisc.edusystem.cpu0.num_store_insts                   4930624                       # Number of store instructions
32210645Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles              10088968020.334099                       # Number of idle cycles
32310645Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles              522738070.665901                       # Number of busy cycles
32410645Snilay@cs.wisc.edusystem.cpu0.not_idle_fraction                0.049261                       # Percentage of non-idle cycles
32510645Snilay@cs.wisc.edusystem.cpu0.idle_fraction                    0.950739                       # Percentage of idle cycles
32610645Snilay@cs.wisc.edusystem.cpu0.Branches                         11433567                       # Number of branches fetched
32710645Snilay@cs.wisc.edusystem.cpu0.op_class::No_OpClass               130284      0.11%      0.11% # Class of executed instruction
32810645Snilay@cs.wisc.edusystem.cpu0.op_class::IntAlu                100735872     88.79%     88.90% # Class of executed instruction
32910645Snilay@cs.wisc.edusystem.cpu0.op_class::IntMult                   86129      0.08%     88.98% # Class of executed instruction
33010645Snilay@cs.wisc.edusystem.cpu0.op_class::IntDiv                    56904      0.05%     89.03% # Class of executed instruction
33110645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatAdd                      0      0.00%     89.03% # Class of executed instruction
33210645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCmp                      0      0.00%     89.03% # Class of executed instruction
33310645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCvt                     16      0.00%     89.03% # Class of executed instruction
33410645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatMult                     0      0.00%     89.03% # Class of executed instruction
33510645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatDiv                      0      0.00%     89.03% # Class of executed instruction
33610645Snilay@cs.wisc.edusystem.cpu0.op_class::FloatSqrt                     0      0.00%     89.03% # Class of executed instruction
33710645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAdd                       0      0.00%     89.03% # Class of executed instruction
33810645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAddAcc                    0      0.00%     89.03% # Class of executed instruction
33910645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAlu                       0      0.00%     89.03% # Class of executed instruction
34010645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCmp                       0      0.00%     89.03% # Class of executed instruction
34110645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCvt                       0      0.00%     89.03% # Class of executed instruction
34210645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMisc                      0      0.00%     89.03% # Class of executed instruction
34310645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMult                      0      0.00%     89.03% # Class of executed instruction
34410645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMultAcc                   0      0.00%     89.03% # Class of executed instruction
34510645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShift                     0      0.00%     89.03% # Class of executed instruction
34610645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.03% # Class of executed instruction
34710645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdSqrt                      0      0.00%     89.03% # Class of executed instruction
34810645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.03% # Class of executed instruction
34910645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.03% # Class of executed instruction
35010645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.03% # Class of executed instruction
35110645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.03% # Class of executed instruction
35210645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.03% # Class of executed instruction
35310645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.03% # Class of executed instruction
35410645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMult                 0      0.00%     89.03% # Class of executed instruction
35510645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.03% # Class of executed instruction
35610645Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.03% # Class of executed instruction
35710645Snilay@cs.wisc.edusystem.cpu0.op_class::MemRead                 7517799      6.63%     95.65% # Class of executed instruction
35810645Snilay@cs.wisc.edusystem.cpu0.op_class::MemWrite                4930624      4.35%    100.00% # Class of executed instruction
35910220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
36010220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
36110645Snilay@cs.wisc.edusystem.cpu0.op_class::total                 113457628                       # Class of executed instruction
3628968SN/Asystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
3638968SN/Asystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
36410036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
36510645Snilay@cs.wisc.edusystem.cpu1.numCycles                     10608768454                       # number of cpu cycles simulated
3668968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
3678968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
36810645Snilay@cs.wisc.edusystem.cpu1.committedInsts                   48150016                       # Number of instructions committed
36910645Snilay@cs.wisc.edusystem.cpu1.committedOps                     92121595                       # Number of ops (including micro ops) committed
37010645Snilay@cs.wisc.edusystem.cpu1.num_int_alu_accesses             88447961                       # Number of integer alu accesses
37110645Snilay@cs.wisc.edusystem.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
37210645Snilay@cs.wisc.edusystem.cpu1.num_func_calls                    1752470                       # number of times a function call or return occured
37310645Snilay@cs.wisc.edusystem.cpu1.num_conditional_control_insts      8220366                       # number of instructions that are conditional controls
37410645Snilay@cs.wisc.edusystem.cpu1.num_int_insts                    88447961                       # number of integer instructions
37510645Snilay@cs.wisc.edusystem.cpu1.num_fp_insts                           48                       # number of float instructions
37610645Snilay@cs.wisc.edusystem.cpu1.num_int_register_reads          171418684                       # number of times the integer registers were read
37710645Snilay@cs.wisc.edusystem.cpu1.num_int_register_writes          73201141                       # number of times the integer registers were written
37810645Snilay@cs.wisc.edusystem.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
3798968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
38010645Snilay@cs.wisc.edusystem.cpu1.num_cc_register_reads            50927854                       # number of times the CC registers were read
38110645Snilay@cs.wisc.edusystem.cpu1.num_cc_register_writes           32747914                       # number of times the CC registers were written
38210645Snilay@cs.wisc.edusystem.cpu1.num_mem_refs                     14125904                       # number of memory refs
38310645Snilay@cs.wisc.edusystem.cpu1.num_load_insts                    9133896                       # Number of load instructions
38410645Snilay@cs.wisc.edusystem.cpu1.num_store_insts                   4992008                       # Number of store instructions
38510645Snilay@cs.wisc.edusystem.cpu1.num_idle_cycles              10273983246.713898                       # Number of idle cycles
38610645Snilay@cs.wisc.edusystem.cpu1.num_busy_cycles              334785207.286102                       # Number of busy cycles
38710645Snilay@cs.wisc.edusystem.cpu1.not_idle_fraction                0.031557                       # Percentage of non-idle cycles
38810645Snilay@cs.wisc.edusystem.cpu1.idle_fraction                    0.968443                       # Percentage of idle cycles
38910645Snilay@cs.wisc.edusystem.cpu1.Branches                         10582274                       # Number of branches fetched
39010645Snilay@cs.wisc.edusystem.cpu1.op_class::No_OpClass               169782      0.18%      0.18% # Class of executed instruction
39110645Snilay@cs.wisc.edusystem.cpu1.op_class::IntAlu                 77660292     84.30%     84.49% # Class of executed instruction
39210645Snilay@cs.wisc.edusystem.cpu1.op_class::IntMult                   98483      0.11%     84.59% # Class of executed instruction
39310645Snilay@cs.wisc.edusystem.cpu1.op_class::IntDiv                    71910      0.08%     84.67% # Class of executed instruction
39410645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatAdd                      0      0.00%     84.67% # Class of executed instruction
39510645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCmp                      0      0.00%     84.67% # Class of executed instruction
39610645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCvt                     16      0.00%     84.67% # Class of executed instruction
39710645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatMult                     0      0.00%     84.67% # Class of executed instruction
39810645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatDiv                      0      0.00%     84.67% # Class of executed instruction
39910645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatSqrt                     0      0.00%     84.67% # Class of executed instruction
40010645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAdd                       0      0.00%     84.67% # Class of executed instruction
40110645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAddAcc                    0      0.00%     84.67% # Class of executed instruction
40210645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAlu                       0      0.00%     84.67% # Class of executed instruction
40310645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCmp                       0      0.00%     84.67% # Class of executed instruction
40410645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCvt                       0      0.00%     84.67% # Class of executed instruction
40510645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMisc                      0      0.00%     84.67% # Class of executed instruction
40610645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMult                      0      0.00%     84.67% # Class of executed instruction
40710645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMultAcc                   0      0.00%     84.67% # Class of executed instruction
40810645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShift                     0      0.00%     84.67% # Class of executed instruction
40910645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.67% # Class of executed instruction
41010645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdSqrt                      0      0.00%     84.67% # Class of executed instruction
41110645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.67% # Class of executed instruction
41210645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.67% # Class of executed instruction
41310645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.67% # Class of executed instruction
41410645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.67% # Class of executed instruction
41510645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.67% # Class of executed instruction
41610645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.67% # Class of executed instruction
41710645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMult                 0      0.00%     84.67% # Class of executed instruction
41810645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.67% # Class of executed instruction
41910645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.67% # Class of executed instruction
42010645Snilay@cs.wisc.edusystem.cpu1.op_class::MemRead                 9129755      9.91%     94.58% # Class of executed instruction
42110645Snilay@cs.wisc.edusystem.cpu1.op_class::MemWrite                4992008      5.42%    100.00% # Class of executed instruction
42210220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
42310220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
42410645Snilay@cs.wisc.edusystem.cpu1.op_class::total                  92122246                       # Class of executed instruction
4258968SN/Asystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
4268968SN/Asystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
42710645Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq               857753                       # Transaction distribution
42810645Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp              857753                       # Transaction distribution
42910645Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteReq               36065                       # Transaction distribution
43010645Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteResp              36065                       # Transaction distribution
43110645Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageReq              1791                       # Transaction distribution
43210645Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageResp             1791                       # Transaction distribution
43310645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1702                       # Packet count per connected master and slave (bytes)
43410645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1646                       # Packet count per connected master and slave (bytes)
43510645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3348                       # Packet count per connected master and slave (bytes)
43610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
43710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5758                       # Packet count per connected master and slave (bytes)
43810560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
43910645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          968                       # Packet count per connected master and slave (bytes)
44010645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           66                       # Packet count per connected master and slave (bytes)
44110628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
44210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
44310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
44410645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          964                       # Packet count per connected master and slave (bytes)
44510560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
44610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
44710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14814                       # Packet count per connected master and slave (bytes)
44810645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       742772                       # Packet count per connected master and slave (bytes)
44910645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          158                       # Packet count per connected master and slave (bytes)
45010560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
45110645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1702492                       # Packet count per connected master and slave (bytes)
45210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
45310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
45410645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5284                       # Packet count per connected master and slave (bytes)
45510560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
45610645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          396                       # Packet count per connected master and slave (bytes)
45710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           28                       # Packet count per connected master and slave (bytes)
45810628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
45910645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        30942                       # Packet count per connected master and slave (bytes)
46010645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          384                       # Packet count per connected master and slave (bytes)
46110645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31030                       # Packet count per connected master and slave (bytes)
46210645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12448                       # Packet count per connected master and slave (bytes)
46310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
46410560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
46510560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
46610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
46710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           76                       # Packet count per connected master and slave (bytes)
46810645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4614                       # Packet count per connected master and slave (bytes)
46910645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        85378                       # Packet count per connected master and slave (bytes)
47010645Snilay@cs.wisc.edusystem.iobus.pkt_count::total                 1791218                       # Packet count per connected master and slave (bytes)
47110645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3404                       # Cumulative packet size per connected master and slave (bytes)
47210645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
47310645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6696                       # Cumulative packet size per connected master and slave (bytes)
47410560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
47510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3266                       # Cumulative packet size per connected master and slave (bytes)
47610560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
47710645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          484                       # Cumulative packet size per connected master and slave (bytes)
47810645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           33                       # Cumulative packet size per connected master and slave (bytes)
47910628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
48010560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
48110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
48210645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1928                       # Cumulative packet size per connected master and slave (bytes)
48310560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
48410560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
48510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7407                       # Cumulative packet size per connected master and slave (bytes)
48610645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1485538                       # Cumulative packet size per connected master and slave (bytes)
48710645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          316                       # Cumulative packet size per connected master and slave (bytes)
48810560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
48910645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1970762                       # Cumulative packet size per connected master and slave (bytes)
49010560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
49210645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3394                       # Cumulative packet size per connected master and slave (bytes)
49310560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
49410645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          198                       # Cumulative packet size per connected master and slave (bytes)
49510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           14                       # Cumulative packet size per connected master and slave (bytes)
49610628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49710645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15471                       # Cumulative packet size per connected master and slave (bytes)
49810645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          768                       # Cumulative packet size per connected master and slave (bytes)
49910645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15515                       # Cumulative packet size per connected master and slave (bytes)
50010645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6224                       # Cumulative packet size per connected master and slave (bytes)
50110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50210560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50310560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50410560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
50510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          152                       # Cumulative packet size per connected master and slave (bytes)
50610645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9225                       # Cumulative packet size per connected master and slave (bytes)
50710645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        51075                       # Cumulative packet size per connected master and slave (bytes)
50810645Snilay@cs.wisc.edusystem.iobus.pkt_size::total                  2028533                       # Cumulative packet size per connected master and slave (bytes)
50910628Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy                50000                       # Layer occupancy (ticks)
51010560Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
51110645Snilay@cs.wisc.edusystem.iobus.reqLayer1.occupancy                 7000                       # Layer occupancy (ticks)
51210560Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
51310645Snilay@cs.wisc.edusystem.iobus.reqLayer2.occupancy             10224000                       # Layer occupancy (ticks)
51410560Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
51510645Snilay@cs.wisc.edusystem.iobus.reqLayer3.occupancy               143500                       # Layer occupancy (ticks)
51610560Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
51710645Snilay@cs.wisc.edusystem.iobus.reqLayer4.occupancy              1064000                       # Layer occupancy (ticks)
51810560Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
51910645Snilay@cs.wisc.edusystem.iobus.reqLayer5.occupancy                97500                       # Layer occupancy (ticks)
52010560Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
52110645Snilay@cs.wisc.edusystem.iobus.reqLayer6.occupancy                56000                       # Layer occupancy (ticks)
52210560Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
52310645Snilay@cs.wisc.edusystem.iobus.reqLayer7.occupancy             20660000                       # Layer occupancy (ticks)
52410560Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
52510560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.occupancy            700937500                       # Layer occupancy (ticks)
52610560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
52710645Snilay@cs.wisc.edusystem.iobus.reqLayer9.occupancy              1276000                       # Layer occupancy (ticks)
52810560Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
52910645Snilay@cs.wisc.edusystem.iobus.reqLayer10.occupancy            31144500                       # Layer occupancy (ticks)
53010560Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
53110645Snilay@cs.wisc.edusystem.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
53210560Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
53310645Snilay@cs.wisc.edusystem.iobus.reqLayer13.occupancy            23664000                       # Layer occupancy (ticks)
53410560Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
53510645Snilay@cs.wisc.edusystem.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
53610560Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
53710645Snilay@cs.wisc.edusystem.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
53810560Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
53910560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
54010560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
54110645Snilay@cs.wisc.edusystem.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
54210560Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
54310645Snilay@cs.wisc.edusystem.iobus.reqLayer18.occupancy           468374820                       # Layer occupancy (ticks)
54410560Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
54510645Snilay@cs.wisc.edusystem.iobus.reqLayer19.occupancy             7594080                       # Layer occupancy (ticks)
54610560Sandreas.hansson@arm.comsystem.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
54710645Snilay@cs.wisc.edusystem.iobus.reqLayer21.occupancy             1329500                       # Layer occupancy (ticks)
54810560Sandreas.hansson@arm.comsystem.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
54910645Snilay@cs.wisc.edusystem.iobus.respLayer0.occupancy             2404400                       # Layer occupancy (ticks)
55010560Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
55110645Snilay@cs.wisc.edusystem.iobus.respLayer2.occupancy          2023552000                       # Layer occupancy (ticks)
55210560Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
55310645Snilay@cs.wisc.edusystem.iobus.respLayer4.occupancy            60655000                       # Layer occupancy (ticks)
55410560Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
55510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
55710560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
55810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
55910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
56010560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
56110560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
56210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
56310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
56410560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
56510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
56610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
56710560Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
56810560Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
56910560Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
57010645Snilay@cs.wisc.edusystem.ruby.delayHist::samples               10895286                       # delay histogram for all message
57110645Snilay@cs.wisc.edusystem.ruby.delayHist::mean                  0.442462                       # delay histogram for all message
57210645Snilay@cs.wisc.edusystem.ruby.delayHist::stdev                 1.830078                       # delay histogram for all message
57310645Snilay@cs.wisc.edusystem.ruby.delayHist                    |    10293202     94.47%     94.47% |        1309      0.01%     94.49% |      600320      5.51%    100.00% |         166      0.00%    100.00% |         230      0.00%    100.00% |          12      0.00%    100.00% |          47      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
57410645Snilay@cs.wisc.edusystem.ruby.delayHist::total                 10895286                       # delay histogram for all message
57510560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size            1                      
57610560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket            9                      
57710645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples    152835093                      
57810645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean       1.000166                      
57910645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean      1.000115                      
58010645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::stdev      0.012900                      
58110645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152809657     99.98%     99.98% |       25436      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58210645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total     152835093                      
58310560Sandreas.hansson@arm.comsystem.ruby.latency_hist::bucket_size             256                      
58410560Sandreas.hansson@arm.comsystem.ruby.latency_hist::max_bucket             2559                      
58510645Snilay@cs.wisc.edusystem.ruby.latency_hist::samples           152835092                      
58610645Snilay@cs.wisc.edusystem.ruby.latency_hist::mean               3.434217                      
58710645Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean              3.107238                      
58810645Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev              5.763379                      
58910645Snilay@cs.wisc.edusystem.ruby.latency_hist                 |   152826007     99.99%     99.99% |        6324      0.00%    100.00% |        2683      0.00%    100.00% |          40      0.00%    100.00% |          37      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59010645Snilay@cs.wisc.edusystem.ruby.latency_hist::total             152835092                      
59110560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size            1                      
59210560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket            9                      
59310645Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples       150173515                      
59410560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::mean                  3                      
59510560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::gmean          3.000000                      
59610645Snilay@cs.wisc.edusystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   150173515    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59710645Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total         150173515                      
59810560Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::bucket_size          256                      
59910560Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::max_bucket         2559                      
60010645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples        2661577                      
60110645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean         27.933965                      
60210645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean        22.542647                      
60310645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev        36.007083                      
60410645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist            |     2652492     99.66%     99.66% |        6324      0.24%     99.90% |        2683      0.10%    100.00% |          40      0.00%    100.00% |          37      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
60510645Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total          2661577                      
60610645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_hits     11100819                       # Number of cache demand hits
60710645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_misses       532265                       # Number of cache demand misses
60810645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     11633084                       # Number of cache demand accesses
60910645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_hits     68582952                       # Number of cache demand hits
61010645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_misses       323144                       # Number of cache demand misses
61110645Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_accesses     68906096                       # Number of cache demand accesses
61210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
61310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
61410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
61510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
61610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
61710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
61810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
61910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
62010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
62110628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.fully_busy_cycles            15                       # cycles for which number of transistions == max transitions
62210645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_hits     12795048                       # Number of cache demand hits
62310645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_misses      1313851                       # Number of cache demand misses
62410645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_accesses     14108899                       # Number of cache demand accesses
62510645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_hits     57694696                       # Number of cache demand hits
62610645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_misses       492317                       # Number of cache demand misses
62710645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_accesses     58187013                       # Number of cache demand accesses
62810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
62910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
63010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
63110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
63210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
63310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
63410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
63510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
63610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
63710645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.fully_busy_cycles             7                       # cycles for which number of transistions == max transitions
63810645Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_hits      2434372                       # Number of cache demand hits
63910645Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_misses       227205                       # Number of cache demand misses
64010645Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_accesses      2661577                       # Number of cache demand accesses
64110628Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.fully_busy_cycles             1                       # cycles for which number of transistions == max transitions
64210560Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
64310645Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized     0.029987                      
64410645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::0       855409                      
64510645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Request_Control::2        42371                      
64610645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::1       883866                      
64710645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::1       509923                      
64810645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::2       507294                      
64910645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::0       298509                      
65010645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::1          176                      
65110645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::0       170526                      
65210645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::0      6843272                      
65310645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Request_Control::2       338968                      
65410645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::1     63638352                      
65510645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::1      4079384                      
65610645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::2      4058352                      
65710645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     21492648                      
65810645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        12672                      
65910645Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      1364208                      
66010645Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized     0.057152                      
66110645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::0      1806168                      
66210645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Request_Control::2        40332                      
66310645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::1      1830141                      
66410645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::1      1256659                      
66510645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::2      1255808                      
66610645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::0       276119                      
66710645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::1          194                      
66810645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::0       942229                      
66910645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::0     14449344                      
67010645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Request_Control::2       322656                      
67110645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::1    131770152                      
67210645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::1     10053272                      
67310645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::2     10046464                      
67410645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::0     19880568                      
67510645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        13968                      
67610645Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::0      7537832                      
67710645Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized     0.091505                      
67810645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::0      2839493                      
67910645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Request_Control::2        81198                      
68010645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::1      2891200                      
68110645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::1      1848800                      
68210645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::2      1763102                      
68310645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::0       574628                      
68410645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::1          370                      
68510645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::0      1112755                      
68610645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::0     22715944                      
68710645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Request_Control::2       649584                      
68810645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::1    208166400                      
68910645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::1     14790400                      
69010645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::2     14104816                      
69110645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     41373216                      
69210645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        26640                      
69310645Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      8902040                      
69410645Snilay@cs.wisc.edusystem.ruby.network.routers3.percent_links_utilized     0.006812                      
69510645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Control::0       177916                      
69610645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Data::1       276580                      
69710645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Control::1       130228                      
69810645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Writeback_Control::0        47545                      
69910560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
70010645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Control::0      1423328                      
70110645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Data::1     19913760                      
70210645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Control::1      1041824                      
70310645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380360                      
70410560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
70510628Sandreas.hansson@arm.comsystem.ruby.network.routers4.percent_links_utilized     0.000239                      
70610645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Response_Data::1          809                      
70710645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Writeback_Control::0        47545                      
70810560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
70910645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Response_Data::1        58248                      
71010645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380360                      
71110560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
71210560Sandreas.hansson@arm.comsystem.ruby.network.routers5.percent_links_utilized            0                      
71310645Snilay@cs.wisc.edusystem.ruby.network.routers6.percent_links_utilized     0.030950                      
71410645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Control::0      2839493                      
71510645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Request_Control::2        82703                      
71610645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Data::1      2941298                      
71710645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::1      1872805                      
71810645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::2      1763102                      
71910645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::0       574628                      
72010645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::1          370                      
72110645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Control::0      1160300                      
72210560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
72310645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Control::0     22715944                      
72410645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Request_Control::2       661624                      
72510645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Data::1    211773456                      
72610645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::1     14982440                      
72710645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::2     14104816                      
72810645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     41373216                      
72910645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        26640                      
73010645Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9282400                      
73110560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
73210645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Control         8518479                      
73310645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Request_Control       246604                      
73410645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Data      8823894                      
73510645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Control     10907721                      
73610645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Data      1724994                      
73710645Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Control      3621108                      
73810645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Control         68147832                      
73910645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Request_Control      1972832                      
74010645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Data    635320368                      
74110645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Control     87261768                      
74210645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Data    124199568                      
74310645Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Control     28968864                      
74410645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization     0.038287                      
74510645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        42371                      
74610645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1       843260                      
74710645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1       494161                      
74810645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       338968                      
74910645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1     60714720                      
75010645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      3953288                      
75110645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization     0.021686                      
75210645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::0       855409                      
75310645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        40606                      
75410645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        15762                      
75510645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2       507294                      
75610645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       298509                      
75710645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          176                      
75810645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       170526                      
75910645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::0      6843272                      
76010645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2923632                      
76110645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       126096                      
76210645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      4058352                      
76310645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     21492648                      
76410645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        12672                      
76510645Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      1364208                      
76610645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization     0.082198                      
76710645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        40332                      
76810645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1      1796167                      
76910645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1      1239377                      
77010645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       322656                      
77110645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1    129324024                      
77210645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      9915016                      
77310645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization     0.032106                      
77410645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Control::0      1806168                      
77510645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        33974                      
77610645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        17282                      
77710645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2      1255808                      
77810645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       276119                      
77910645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          194                      
78010645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       942229                      
78110645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Control::0     14449344                      
78210645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2446128                      
78310645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       138256                      
78410645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2     10046464                      
78510645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     19880568                      
78610645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        13968                      
78710645Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      7537832                      
78810645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization     0.059676                      
78910645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Control::0      2661577                      
79010645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       203207                      
79110645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       123979                      
79210645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1763102                      
79310645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       574628                      
79410645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          370                      
79510645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1112755                      
79610645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21292616                      
79710645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     14630904                      
79810645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1       991832                      
79910645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14104816                      
80010645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41373216                      
80110645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        26640                      
80210645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      8902040                      
80310645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization     0.123335                      
80410645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::0       177916                      
80510645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2        81198                      
80610645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2687993                      
80710645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1724821                      
80810645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1423328                      
80910645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       649584                      
81010645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    193535496                      
81110645Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     13798568                      
81210645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.link_utilization     0.005284                      
81310645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Control::0       177916                      
81410645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1        97855                      
81510645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        15288                      
81610645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47545                      
81710645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1423328                      
81810645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7045560                      
81910645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       122304                      
82010645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380360                      
82110645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.link_utilization     0.008341                      
82210645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Data::1       178725                      
82310645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Control::1       114940                      
8249978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
82510645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     12868200                      
82610645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       919520                      
8279978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82810526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000255                      
82910645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_count.Response_Data::1          809                      
8309978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
83110645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58248                      
8329978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
8339978SN/Asystem.ruby.network.routers4.throttle1.link_utilization     0.000224                      
83410645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47545                      
83510645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380360                      
83610526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
83710526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83810645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.link_utilization     0.038287                      
83910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        42371                      
84010645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1       843260                      
84110645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1       494161                      
84210645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       338968                      
84310645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1     60714720                      
84410645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      3953288                      
84510645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.link_utilization     0.082198                      
84610645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Request_Control::2        40332                      
84710645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1      1796167                      
84810645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1      1239377                      
84910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       322656                      
85010645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1    129324024                      
85110645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      9915016                      
85210645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.link_utilization     0.059676                      
85310645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Control::0      2661577                      
85410645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       203207                      
85510645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       123979                      
85610645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1763102                      
85710645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       574628                      
85810645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          370                      
85910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1112755                      
86010645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21292616                      
86110645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14630904                      
86210645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1       991832                      
86310645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14104816                      
86410645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41373216                      
86510645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        26640                      
86610645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8902040                      
86710645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.link_utilization     0.005284                      
86810645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Control::0       177916                      
86910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97855                      
87010645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15288                      
87110645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47545                      
87210645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1423328                      
87310645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7045560                      
87410645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       122304                      
87510645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380360                      
87610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000255                      
87710645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          809                      
87810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58248                      
88010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
88110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
88210229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
88310229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
88410645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::samples       6112062                       # delay histogram for vnet_0
88510645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::mean         0.754100                       # delay histogram for vnet_0
88610645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::stdev        2.339998                       # delay histogram for vnet_0
88710645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0           |     5536581     90.58%     90.58% |         390      0.01%     90.59% |      574653      9.40%     99.99% |         162      0.00%    100.00% |         217      0.00%    100.00% |          12      0.00%    100.00% |          47      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88810645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::total         6112062                       # delay histogram for vnet_0
88910229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
89010229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
89110645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples       4700521                       # delay histogram for vnet_1
89210645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::mean         0.045023                       # delay histogram for vnet_1
89310645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::stdev        0.596216                       # delay histogram for vnet_1
89410645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1           |     4673467     99.42%     99.42% |         451      0.01%     99.43% |         352      0.01%     99.44% |         567      0.01%     99.45% |       25509      0.54%    100.00% |         158      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |          10      0.00%    100.00% |           3      0.00%    100.00% # delay histogram for vnet_1
89510645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total         4700521                       # delay histogram for vnet_1
89610315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
89710315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89810645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples         82703                       # delay histogram for vnet_2
89910645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::mean         0.000121                       # delay histogram for vnet_2
90010645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::stdev        0.015550                       # delay histogram for vnet_2
90110645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2           |       82698     99.99%     99.99% |           0      0.00%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
90210645Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total           82703                       # delay histogram for vnet_2
90310628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::bucket_size          128                      
90410628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::max_bucket          1279                      
90510645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples         15017729                      
90610645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean            4.875602                      
90710645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean           3.591894                      
90810645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev           9.357091                      
90910645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist              |    15001612     99.89%     99.89% |       13925      0.09%     99.99% |         816      0.01%     99.99% |         883      0.01%    100.00% |         364      0.00%    100.00% |         107      0.00%    100.00% |           3      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           3      0.00%    100.00%
91010645Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total           15017729                      
91110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
91210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
91310645Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples     13626729                      
91410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               3                      
91510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean       3.000000                      
91610645Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13626729    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91710645Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total       13626729                      
91810628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::bucket_size          128                      
91910628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::max_bucket         1279                      
92010645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples      1391000                      
92110645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean      23.249665                      
92210645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean     20.961439                      
92310645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev     23.941766                      
92410645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist         |     1374883     98.84%     98.84% |       13925      1.00%     99.84% |         816      0.06%     99.90% |         883      0.06%     99.96% |         364      0.03%     99.99% |         107      0.01%    100.00% |           3      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           3      0.00%    100.00%
92510645Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total       1391000                      
92610526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size          256                      
92710526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket          2559                      
92810645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples          9551573                      
92910645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean            5.175450                      
93010645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean           3.300314                      
93110645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev          17.651144                      
93210645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist              |     9545752     99.94%     99.94% |        3768      0.04%     99.98% |        2002      0.02%    100.00% |          25      0.00%    100.00% |          25      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93310645Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total            9551573                      
93410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
93510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
93610645Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples      9200826                      
93710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               3                      
93810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean       3.000000                      
93910645Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9200826    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94010645Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total        9200826                      
94110526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size          256                      
94210526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket         2559                      
94310645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples       350747                      
94410645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean      62.242032                      
94510645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean     40.314149                      
94610645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev     71.440751                      
94710645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist         |      344926     98.34%     98.34% |        3768      1.07%     99.41% |        2002      0.57%     99.99% |          25      0.01%     99.99% |          25      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94810645Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total        350747                      
94910526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size          128                      
95010526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket         1279                      
95110645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples    127093109                      
95210645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean        3.119052                      
95310645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean       3.036517                      
95410645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev       2.234317                      
95510645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist          |   127086454     99.99%     99.99% |        5646      0.00%    100.00% |         489      0.00%    100.00% |         322      0.00%    100.00% |         142      0.00%    100.00% |          52      0.00%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
95610645Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total      127093109                      
95710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
95810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
95910645Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples    126277648                      
96010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            3                      
96110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
96210645Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   126277648    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
96310645Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total    126277648                      
96410526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
96510526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
96610645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples       815461                      
96710645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean    21.554760                      
96810645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean    19.772157                      
96910645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev    20.880175                      
97010645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist     |      808806     99.18%     99.18% |        5646      0.69%     99.88% |         489      0.06%     99.94% |         322      0.04%     99.98% |         142      0.02%     99.99% |          52      0.01%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
97110645Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total       815461                      
97210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size          128                      
97310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket         1279                      
97410645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples       493321                      
97510645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean      6.020581                      
97610645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean     3.953173                      
97710645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev    10.251314                      
97810645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist        |      493148     99.96%     99.96% |         127      0.03%     99.99% |          17      0.00%     99.99% |          15      0.00%    100.00% |           9      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97910645Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total       493321                      
98010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
98110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
98210645Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples       428061                      
98310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            3                      
98410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
98510645Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428061    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98610645Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total       428061                      
98710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
98810526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
98910645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples        65260                      
99010645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean    25.833527                      
99110645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean    24.149766                      
99210645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev    18.493474                      
99310645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist   |       65087     99.73%     99.73% |         127      0.19%     99.93% |          17      0.03%     99.96% |          15      0.02%     99.98% |           9      0.01%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99410645Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total        65260                      
99510645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
99610645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
99710645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::samples       339680                      
99810645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::mean     5.345204                      
99910645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::gmean     3.780937                      
100010645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::stdev     8.076413                      
100110645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist |      339429     99.93%     99.93% |         234      0.07%     99.99% |          11      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100210645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::total       339680                      
100310013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
100410013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
100510645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::samples       300571                      
100610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
100710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
100810645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300571    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100910645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::total       300571                      
101010645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
101110645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
101210645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::samples        39109                      
101310645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.369199                      
101410645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.378025                      
101510645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.121215                      
101610645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist |       38858     99.36%     99.36% |         234      0.60%     99.96% |          11      0.03%     99.98% |           3      0.01%     99.99% |           1      0.00%     99.99% |           2      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
101710645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::total        39109                      
101810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
101910013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
102010645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::samples       339680                      
102110013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::mean            3                      
102210013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
102310645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339680    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102410645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::total       339680                      
102510013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
102610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
102710645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::samples       339680                      
102810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
102910013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
103010645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339680    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
103110645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::total       339680                      
103210645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Fetch         177916      0.00%      0.00%
103310645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Data           97855      0.00%      0.00%
103410645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data       178363      0.00%      0.00%
103510645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack       143156      0.00%      0.00%
103610645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.DMA_READ          809      0.00%      0.00%
103710560Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
103810645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.CleanReplacement        15288      0.00%      0.00%
103910645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.Fetch       177916      0.00%      0.00%
104010645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_READ          447      0.00%      0.00%
104110645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_WRITE        45301      0.00%      0.00%
104210645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID.Memory_Data          447      0.00%      0.00%
104310645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID_W.Memory_Ack        45301      0.00%      0.00%
104410645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.Data         96058      0.00%      0.00%
104510645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_READ          362      0.00%      0.00%
104610645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_WRITE         1435      0.00%      0.00%
104710645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.CleanReplacement        15288      0.00%      0.00%
104810645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data       177916      0.00%      0.00%
104910645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack        96058      0.00%      0.00%
105010645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRD.Data          362      0.00%      0.00%
105110645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          362      0.00%      0.00%
105210645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWR.Data         1435      0.00%      0.00%
105310645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         1435      0.00%      0.00%
105410645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest   |         809    100.00%    100.00% |           0      0.00%    100.00%
105510645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest::total          809                      
105610560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
105710560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest::total        46736                      
105810645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data          |         809    100.00%    100.00% |           0      0.00%    100.00%
105910645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data::total            809                      
106010560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
106110560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack::total           46736                      
106210645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest |         809    100.00%    100.00% |           0      0.00%    100.00%
106310645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest::total          809                      
106410560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
106510560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
106610645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data  |         809    100.00%    100.00% |           0      0.00%    100.00%
106710645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data::total          809                      
106810560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
106910560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
107010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load      |     6268725     41.74%     41.74% |     8749004     58.26%    100.00%
107110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load::total     15017729                      
107210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch    |    68906101     54.22%     54.22% |    58187014     45.78%    100.00%
107310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch::total    127093115                      
107410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store     |     5364359     50.02%     50.02% |     5359895     49.98%    100.00%
107510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store::total     10724254                      
107610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv       |       15938     47.70%     47.70% |       17476     52.30%    100.00%
107710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv::total        33414                      
107810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement |      827888     31.76%     31.76% |     1778547     68.24%    100.00%
107910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement::total      2606435                      
108010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX  |       12260     51.09%     51.09% |       11738     48.91%    100.00%
108110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX::total        23998                      
108210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS  |       14169     56.03%     56.03% |       11118     43.97%    100.00%
108310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS::total        25287                      
108410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
108510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
108610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data      |         828     44.64%     44.64% |        1027     55.36%    100.00%
108710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data::total         1855                      
108810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive |      252860     19.71%     19.71% |     1029835     80.29%    100.00%
108910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive::total      1282695                      
109010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1 |       11118     43.96%     43.96% |       14173     56.04%    100.00%
109110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1::total        25291                      
109210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks |      578454     43.51%     43.51% |      751132     56.49%    100.00%
109310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks::total      1329586                      
109410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack       |       12149     54.85%     54.85% |       10001     45.15%    100.00%
109510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack::total        22150                      
109610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all   |       12977     54.06%     54.06% |       11028     45.94%    100.00%
109710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all::total        24005                      
109810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack    |      469035     27.80%     27.80% |     1218348     72.20%    100.00%
109910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack::total      1687383                      
110010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load   |      280457     20.44%     20.44% |     1091772     79.56%    100.00%
110110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load::total      1372229                      
110210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch |      323032     39.65%     39.65% |      491723     60.35%    100.00%
110310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch::total       814755                      
110410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store  |      225423     53.48%     53.48% |      196076     46.52%    100.00%
110510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store::total       421499                      
110610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv    |        4849     53.95%     53.95% |        4139     46.05%    100.00%
110710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv::total         8988                      
110810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load    |        8492     45.24%     45.24% |       10279     54.76%    100.00%
110910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load::total        18771                      
111010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch  |         112     15.86%     15.86% |         594     84.14%    100.00%
111110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch::total          706                      
111210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store   |        5744     50.09%     50.09% |        5723     49.91%    100.00%
111310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store::total        11467                      
111410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement |        9001     51.76%     51.76% |        8389     48.24%    100.00%
111510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement::total        17390                      
111610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load    |      552961     51.86%     51.86% |      513218     48.14%    100.00%
111710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load::total      1066179                      
111810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch  |    68582952     54.31%     54.31% |    57694696     45.69%    100.00%
111910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch::total    126277648                      
112010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store   |       12149     54.85%     54.85% |       10001     45.15%    100.00%
112110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store::total        22150                      
112210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv     |       10866     45.32%     45.32% |       13108     54.68%    100.00%
112310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv::total        23974                      
112410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement |      349852     38.80%     38.80% |      551810     61.20%    100.00%
112510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement::total       901662                      
112610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load    |     1151502     29.73%     29.73% |     2721068     70.27%    100.00%
112710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load::total      3872570                      
112810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store   |       80746     48.37%     48.37% |       86187     51.63%    100.00%
112910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store::total       166933                      
113010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv     |          47     57.32%     57.32% |          35     42.68%    100.00%
113110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv::total           82                      
113210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement |      170526     15.32%     15.32% |      942229     84.68%    100.00%
113310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1112755                      
113410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX |         332     72.81%     72.81% |         124     27.19%    100.00%
113510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          456                      
113610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS |         992     45.23%     45.23% |        1201     54.77%    100.00%
113710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2193                      
113810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load    |     4275313     49.21%     49.21% |     4412667     50.79%    100.00%
113910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load::total      8687980                      
114010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store   |     5040297     49.89%     49.89% |     5061908     50.11%    100.00%
114110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store::total     10102205                      
114210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv     |         176     47.57%     47.57% |         194     52.43%    100.00%
114310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv::total          370                      
114410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement |      298509     51.95%     51.95% |      276119     48.05%    100.00%
114510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement::total       574628                      
114610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX |       11928     50.67%     50.67% |       11614     49.33%    100.00%
114710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        23542                      
114810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS |       13177     57.06%     57.06% |        9917     42.94%    100.00%
114910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        23094                      
115010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
115110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
115210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive |      252860     19.71%     19.71% |     1029835     80.29%    100.00%
115310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1282695                      
115410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11118     43.96%     43.96% |       14173     56.04%    100.00%
115510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25291                      
115610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      348115     38.75%     38.75% |      550360     61.25%    100.00%
115710645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       898475                      
115810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data   |         828     44.64%     44.64% |        1027     55.36%    100.00%
115910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data::total         1855                      
116010645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      230339     53.43%     53.43% |      200772     46.57%    100.00%
116110645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431111                      
116210645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack    |       12149     54.85%     54.85% |       10001     45.15%    100.00%
116310645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack::total        22150                      
116410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all |       12977     54.06%     54.06% |       11028     45.94%    100.00%
116510645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all::total        24005                      
116610645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch |           5     83.33%     83.33% |           1     16.67%    100.00%
116710628Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.Ifetch::total            6                      
116810645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack |      469035     27.80%     27.80% |     1218348     72.20%    100.00%
116910645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1687383                      
117010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GET_INSTR       815461      0.00%      0.00%
117110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETS        1391156      0.00%      0.00%
117210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETX         432966      0.00%      0.00%
117310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_UPGRADE        22150      0.00%      0.00%
117410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_PUTX        1687383      0.00%      0.00%
117510645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement        95998      0.00%      0.00%
117610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement_clean        15348      0.00%      0.00%
117710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Data        177916      0.00%      0.00%
117810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Ack         113143      0.00%      0.00%
117910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data          23468      0.00%      0.00%
118010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data_clean         2193      0.00%      0.00%
118110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack               1505      0.00%      0.00%
118210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack_all           7534      0.00%      0.00%
118310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Unblock          25291      0.00%      0.00%
118410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Exclusive_Unblock      1737811      0.00%      0.00%
118510645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MEM_Inv           3594      0.00%      0.00%
118610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16427      0.00%      0.00%
118710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETS        34220      0.00%      0.00%
118810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETX       127269      0.00%      0.00%
118910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       799004      0.00%      0.00%
119010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETS        83018      0.00%      0.00%
119110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETX         1958      0.00%      0.00%
119210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        22150      0.00%      0.00%
119310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement          257      0.00%      0.00%
119410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7192      0.00%      0.00%
119510645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.MEM_Inv            3      0.00%      0.00%
119610628Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
119710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETS      1248475      0.00%      0.00%
119810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETX       279741      0.00%      0.00%
119910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement        95619      0.00%      0.00%
120010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         8056      0.00%      0.00%
120110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.MEM_Inv         1564      0.00%      0.00%
120210013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
120310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETS        25287      0.00%      0.00%
120410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETX        23998      0.00%      0.00%
120510645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_PUTX      1687383      0.00%      0.00%
120610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement          122      0.00%      0.00%
120710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          100      0.00%      0.00%
120810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.MEM_Inv          230      0.00%      0.00%
120910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.Mem_Ack       113143      0.00%      0.00%
121010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.MEM_Inv         1564      0.00%      0.00%
121110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.WB_Data          310      0.00%      0.00%
121210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.Ack_all           42      0.00%      0.00%
121310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          230      0.00%      0.00%
121410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.WB_Data           60      0.00%      0.00%
121510628Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MCT_I.Ack_all           40      0.00%      0.00%
121610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack           1245      0.00%      0.00%
121710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack_all         7192      0.00%      0.00%
121810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack            260      0.00%      0.00%
121910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack_all          260      0.00%      0.00%
122010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.MEM_Inv            3      0.00%      0.00%
122110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.ISS.Mem_Data        34220      0.00%      0.00%
122210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IS.Mem_Data        16427      0.00%      0.00%
122310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IM.Mem_Data       127269      0.00%      0.00%
122410645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          115      0.00%      0.00%
122510645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24108      0.00%      0.00%
122610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.L1_GETS           41      0.00%      0.00%
122710645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1713703      0.00%      0.00%
122810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        23085      0.00%      0.00%
122910645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2191      0.00%      0.00%
123010645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.Unblock           15      0.00%      0.00%
123110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IB.WB_Data           13      0.00%      0.00%
123210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            2      0.00%      0.00%
123310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_SB.Unblock        25276      0.00%      0.00%
12348968SN/A
12358968SN/A---------- End Simulation Statistics   ----------
1236