xref: /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.136865                       # Number of seconds simulated
sim_ticks                                5136864508000                       # Number of ticks simulated
final_tick                               5136864508000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 161248                       # Simulator instruction rate (inst/s)
host_op_rate                                   318747                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2030694494                       # Simulator tick rate (ticks/s)
host_mem_usage                                 783308                       # Number of bytes of host memory used
host_seconds                                  2529.61                       # Real time elapsed on the host
sim_insts                                   407895398                       # Number of instructions simulated
sim_ops                                     806304609                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2499136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1076928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10801024                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14380480                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1076928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1076928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9561920                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9561920                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        39049                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           47                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16827                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168766                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                224695                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149405                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149405                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       486510                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            586                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               209647                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2102649                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2799466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          209647                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             209647                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1861431                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1861431                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1861431                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       486510                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           586                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              209647                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2102649                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4660898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        224695                       # Total number of read requests seen
system.physmem.writeReqs                       149405                       # Total number of write requests seen
system.physmem.cpureqs                         378068                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     14380480                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9561920                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14380480                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9561920                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      102                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               3959                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14159                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13042                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 13152                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 16282                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13746                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13201                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13511                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 16248                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13928                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13310                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13277                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                15618                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                13156                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12636                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13394                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                15933                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9055                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  8495                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8476                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 11557                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8862                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8626                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8868                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 11671                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8971                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8652                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8710                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                11130                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 8376                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8093                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8654                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                11209                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           9                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5136864456000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  224695                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 149405                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    173100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     19795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7560                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3484                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3025                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2399                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1799                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1771                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1716                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1029                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      909                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      868                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      395                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      255                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6439                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       10                       # What write queue length does an incoming req see
system.physmem.totQLat                     4766626250                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                9279378750                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1122965000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3389787500                       # Total cycles spent in bank access
system.physmem.avgQLat                       21223.40                       # Average queueing delay per request
system.physmem.avgBankLat                    15093.02                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  41316.42                       # Average memory access latency
system.physmem.avgRdBW                           2.80                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.80                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.86                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        11.02                       # Average write queue length over time
system.physmem.readRowHits                     193644                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    105706                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.22                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  70.75                       # Row buffer hit rate for writes
system.physmem.avgGap                     13731260.24                       # Average gap between requests
system.iocache.replacements                     47574                       # number of replacements
system.iocache.tagsinuse                     0.116323                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47590                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4991909238000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.116323                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.007270                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.007270                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47629                       # number of overall misses
system.iocache.overall_misses::total            47629                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144901871                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144901871                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10053195615                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10053195615                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10198097486                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10198097486                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10198097486                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10198097486                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47629                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47629                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 159407.998900                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.700664                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 215179.700664                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.297109                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 214115.297109                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.297109                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 214115.297109                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        138033                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                12531                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.015322                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47629                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47629                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47629                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97611900                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     97611900                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7622408830                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7622408830                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7720020730                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7720020730                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7720020730                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7720020730                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107383.828383                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163150.873930                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.873930                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.559239                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 162086.559239                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162086.559239                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 162086.559239                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                86192778                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86192778                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1105969                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             81285940                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                79207876                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.443514                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        448117283                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27407295                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      425903825                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86192778                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79207876                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     163564309                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4697150                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     125610                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               63070837                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                35658                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         51192                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          380                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9007924                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                482953                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2789                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          257808166                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.261396                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.418051                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 94670555     36.72%     36.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1565511      0.61%     37.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71913522     27.89%     65.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   935622      0.36%     65.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1598852      0.62%     66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2418850      0.94%     67.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1070189      0.42%     67.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1376236      0.53%     68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 82258829     31.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            257808166                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192344                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.950429                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31124176                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              60511588                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 159357091                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3262426                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3552885                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              837683480                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   953                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3552885                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33860427                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37375460                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       11010468                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159557932                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              12450994                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834052267                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19515                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                5867687                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4751018                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             8643                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           995567635                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1810525606                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1810524958                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               648                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964273740                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 31293888                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             458980                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         466833                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  28792477                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17053482                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10121038                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1248085                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           996765                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  827936036                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1250306                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823005910                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            148163                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21984013                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33436004                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         197912                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     257808166                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.192319                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.383919                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            71353106     27.68%     27.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15525279      6.02%     33.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10289212      3.99%     37.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7463811      2.90%     40.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75897283     29.44%     70.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3839331      1.49%     71.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72507991     28.12%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              780183      0.30%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              151970      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       257808166                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  363662     34.07%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 553259     51.83%     85.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                150581     14.11%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            310965      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795485356     96.66%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17833485      2.17%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9376104      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823005910                       # Type of FU issued
system.cpu.iq.rate                           1.836586                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1067502                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001297                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905165811                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         851180208                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818537057                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 213                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                302                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           58                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              823762347                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     100                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1638684                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3078529                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        22784                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11411                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1710138                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1932419                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12218                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3552885                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                26109999                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2115264                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           829186342                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            321096                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17053482                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10121038                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             718511                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1615692                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 10262                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11411                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         648780                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       593291                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1242071                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             821133450                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17423083                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1872459                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26567058                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83190955                       # Number of branches executed
system.cpu.iew.exec_stores                    9143975                       # Number of stores executed
system.cpu.iew.exec_rate                     1.832407                       # Inst execution rate
system.cpu.iew.wb_sent                      820672114                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818537115                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639752264                       # num instructions producing a value
system.cpu.iew.wb_consumers                1045484939                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.826614                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611919                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22773726                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1052392                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1110510                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    254255281                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.171240                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.853929                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     82490050     32.44%     32.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11810591      4.65%     37.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3912535      1.54%     38.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74936309     29.47%     68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2436608      0.96%     69.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1481517      0.58%     69.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       940613      0.37%     70.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70914138     27.89%     97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5332920      2.10%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    254255281                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407895398                       # Number of instructions committed
system.cpu.commit.committedOps              806304609                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22385850                       # Number of memory references committed
system.cpu.commit.loads                      13974950                       # Number of loads committed
system.cpu.commit.membars                      473369                       # Number of memory barriers committed
system.cpu.commit.branches                   82185287                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735250581                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5332920                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1077922480                       # The number of ROB reads
system.cpu.rob.rob_writes                  1661728217                       # The number of ROB writes
system.cpu.timesIdled                         1219694                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190309117                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9825609154                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407895398                       # Number of Instructions Simulated
system.cpu.committedOps                     806304609                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407895398                       # Number of Instructions Simulated
system.cpu.cpi                               1.098608                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.098608                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.910243                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.910243                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1506572228                       # number of integer regfile reads
system.cpu.int_regfile_writes               976715078                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264599077                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402085                       # number of misc regfile writes
system.cpu.icache.replacements                1045531                       # number of replacements
system.cpu.icache.tagsinuse                510.125027                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7898981                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1046043                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.551297                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56071908000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.125027                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996338                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996338                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7898981                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7898981                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7898981                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7898981                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7898981                       # number of overall hits
system.cpu.icache.overall_hits::total         7898981                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1108941                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1108941                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1108941                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1108941                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1108941                       # number of overall misses
system.cpu.icache.overall_misses::total       1108941                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15254214993                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15254214993                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15254214993                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15254214993                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15254214993                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15254214993                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9007922                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9007922                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9007922                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9007922                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9007922                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9007922                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123107                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.123107                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.123107                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.123107                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.123107                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.123107                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13755.659673                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13755.659673                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13755.659673                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13755.659673                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13755.659673                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13755.659673                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        11697                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               280                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    41.775000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60573                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        60573                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        60573                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        60573                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        60573                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        60573                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1048368                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1048368                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1048368                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1048368                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1048368                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1048368                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12562155993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12562155993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12562155993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12562155993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12562155993                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12562155993                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116383                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116383                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116383                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.116383                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116383                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.116383                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.582445                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.582445                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.582445                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.582445                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.582445                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.582445                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         9623                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.015619                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          25274                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         9637                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.622600                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5103989981500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.015619                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375976                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375976                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25281                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25281                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25283                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25283                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25283                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25283                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        10506                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        10506                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        10506                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        10506                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        10506                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        10506                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    117420000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    117420000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    117420000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    117420000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    117420000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    117420000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        35787                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        35787                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        35789                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        35789                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        35789                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        35789                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.293570                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.293570                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.293554                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.293554                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.293554                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.293554                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11176.470588                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11176.470588                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11176.470588                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11176.470588                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11176.470588                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11176.470588                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1917                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1917                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        10506                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        10506                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        10506                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        10506                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        10506                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        10506                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     96408000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     96408000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     96408000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     96408000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     96408000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     96408000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.293570                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.293570                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.293554                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.293554                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.293554                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.293554                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9176.470588                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9176.470588                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9176.470588                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9176.470588                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9176.470588                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9176.470588                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       107366                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       12.959117                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         135123                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       107381                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.258351                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5099781673000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.959117                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.809945                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.809945                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       135139                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       135139                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       135139                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       135139                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       135139                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       135139                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       108408                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       108408                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       108408                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       108408                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       108408                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       108408                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1365628000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1365628000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1365628000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1365628000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1365628000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1365628000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       243547                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       243547                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       243547                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       243547                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       243547                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       243547                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.445121                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.445121                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.445121                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.445121                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.445121                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.445121                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12597.114604                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12597.114604                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12597.114604                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12597.114604                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12597.114604                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12597.114604                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        35267                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        35267                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       108408                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       108408                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       108408                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       108408                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       108408                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       108408                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1148812000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1148812000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1148812000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1148812000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1148812000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1148812000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.445121                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.445121                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.445121                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.445121                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.445121                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.445121                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10597.114604                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10597.114604                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10597.114604                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1660204                       # number of replacements
system.cpu.dcache.tagsinuse                511.993130                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19074634                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1660716                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.485789                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               27985000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.993130                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10985848                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10985848                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8083807                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8083807                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19069655                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19069655                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19069655                       # number of overall hits
system.cpu.dcache.overall_hits::total        19069655                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2236198                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2236198                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       317897                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       317897                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2554095                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2554095                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2554095                       # number of overall misses
system.cpu.dcache.overall_misses::total       2554095                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32136809500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32136809500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9657348993                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9657348993                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41794158493                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41794158493                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41794158493                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41794158493                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13222046                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13222046                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8401704                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8401704                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21623750                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21623750                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21623750                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21623750                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.169126                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.169126                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037837                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037837                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118115                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118115                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118115                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118115                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14371.182471                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14371.182471                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30378.861685                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30378.861685                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16363.588078                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16363.588078                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16363.588078                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16363.588078                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       398738                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42519                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.377878                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1561580                       # number of writebacks
system.cpu.dcache.writebacks::total           1561580                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       863817                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       863817                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25014                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25014                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       888831                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       888831                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       888831                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       888831                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1372381                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1372381                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292883                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       292883                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1665264                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1665264                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1665264                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1665264                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17480696000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17480696000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8813584993                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8813584993                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26294280993                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26294280993                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26294280993                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26294280993                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97294541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97294541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2465874000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2465874000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99760415500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99760415500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103795                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103795                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034860                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034860                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077011                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077011                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077011                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077011                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12737.494908                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12737.494908                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30092.511320                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30092.511320                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.857340                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.857340                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.857340                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.857340                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                113491                       # number of replacements
system.cpu.l2cache.tagsinuse             64842.078955                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3927958                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                177583                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.118998                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50032.816197                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    10.886318                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.133448                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3280.359245                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11517.883747                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.763440                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000166                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.050054                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.175749                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.989412                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       101572                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         8137                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1029165                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1334330                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2473204                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1598764                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1598764                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          341                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          341                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       156095                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       156095                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       101572                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         8137                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1029165                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1490425                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2629299                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       101572                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         8137                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1029165                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1490425                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2629299                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           47                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16828                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36875                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        53756                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         3686                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         3686                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132834                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132834                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           47                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16828                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169709                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        186590                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           47                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16828                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169709                       # number of overall misses
system.cpu.l2cache.overall_misses::total       186590                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6046500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       389500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1168943500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2535282000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3710661500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17110500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17110500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6867635000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6867635000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6046500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       389500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1168943500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9402917000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10578296500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6046500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       389500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1168943500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9402917000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10578296500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       101619                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         8143                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1045993                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1371205                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2526960                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1598764                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1598764                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4027                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4027                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288929                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288929                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       101619                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         8143                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1045993                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1660134                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2815889                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       101619                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         8143                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1045993                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1660134                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2815889                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000463                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000737                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016088                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026892                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021273                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.915322                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.915322                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.459746                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.459746                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000463                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000737                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016088                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102226                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.066263                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000463                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000737                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016088                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102226                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.066263                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128648.936170                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69464.196577                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68753.410169                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69027.857355                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4642.023874                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4642.023874                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51700.882304                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51700.882304                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128648.936170                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69464.196577                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55406.118709                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56692.730050                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128648.936170                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69464.196577                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55406.118709                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56692.730050                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102738                       # number of writebacks
system.cpu.l2cache.writebacks::total           102738                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            2                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           47                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16827                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36874                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        53754                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3686                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         3686                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132834                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132834                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           47                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16827                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169708                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       186588                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           47                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16827                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169708                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       186588                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5461043                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       314255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    959626979                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2076990471                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3042392748                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37820166                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37820166                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5229334603                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5229334603                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5461043                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       314255                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    959626979                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7306325074                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8271727351                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5461043                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       314255                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    959626979                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7306325074                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8271727351                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89185441500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89185441500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2304074500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2304074500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91489516000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91489516000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000463                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000737                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016087                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026892                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021272                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.915322                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.915322                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.459746                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.459746                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000463                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000737                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016087                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102225                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.066263                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000463                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000737                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016087                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102225                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.066263                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57028.999762                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56326.692819                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56598.443800                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10260.489962                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10260.489962                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39367.440588                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39367.440588                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57028.999762                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43052.331499                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44331.507659                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57028.999762                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43052.331499                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44331.507659                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------