stats.txt revision 9289:a31a1243a3ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.133289 # Number of seconds simulated 4sim_ticks 5133289198000 # Number of ticks simulated 5final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 170996 # Simulator instruction rate (inst/s) 8host_op_rate 338013 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2151657827 # Simulator tick rate (ticks/s) 10host_mem_usage 361992 # Number of bytes of host memory used 11host_seconds 2385.74 # Real time elapsed on the host 12sim_insts 407952579 # Number of instructions simulated 13sim_ops 806410876 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s) 49system.iocache.replacements 47577 # number of replacements 50system.iocache.tagsinuse 0.116486 # Cycle average of tags in use 51system.iocache.total_refs 0 # Total number of references to valid blocks. 52system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. 53system.iocache.avg_refs 0 # Average number of references to valid blocks. 54system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. 55system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor 56system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy 57system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy 58system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses 59system.iocache.ReadReq_misses::total 912 # number of ReadReq misses 60system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 61system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 62system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses 63system.iocache.demand_misses::total 47632 # number of demand (read+write) misses 64system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses 65system.iocache.overall_misses::total 47632 # number of overall misses 66system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles 67system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles 68system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles 69system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles 70system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles 71system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles 72system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles 73system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles 74system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) 75system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) 76system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 77system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 78system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses 79system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses 80system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses 81system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses 82system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 83system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 84system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 85system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 86system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 87system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 88system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 89system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 90system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency 91system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency 92system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency 93system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency 94system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency 95system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency 96system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency 97system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency 98system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked 99system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 100system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked 101system.iocache.blocked::no_targets 0 # number of cycles access was blocked 102system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked 103system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104system.iocache.fast_writes 0 # number of fast writes performed 105system.iocache.cache_copies 0 # number of cache copies performed 106system.iocache.writebacks::writebacks 46667 # number of writebacks 107system.iocache.writebacks::total 46667 # number of writebacks 108system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses 109system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses 110system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 111system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 112system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses 113system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses 114system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses 115system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses 116system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles 117system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles 118system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles 119system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles 120system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles 121system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles 122system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles 123system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles 124system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 125system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 126system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 127system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 128system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 129system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 130system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 131system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 132system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency 133system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency 134system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency 135system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency 136system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency 137system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency 138system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency 139system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency 140system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 141system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 142system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 143system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 144system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 145system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 146system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 147system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 148system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 149system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 150system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 151system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 152system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 153system.cpu.numCycles 448600431 # number of cpu cycles simulated 154system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 155system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 156system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups 157system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted 158system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect 159system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups 160system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits 161system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 162system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 163system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 164system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss 165system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed 166system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered 167system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken 168system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked 169system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing 170system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb 171system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked 172system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 173system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps 174system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR 175system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched 176system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed 177system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed 178system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total) 179system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total) 180system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total) 181system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 182system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total) 183system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total) 184system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total) 185system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total) 186system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total) 187system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total) 188system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total) 189system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total) 190system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total) 191system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 192system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 193system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 194system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total) 195system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle 196system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle 197system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle 198system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked 199system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running 200system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking 201system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing 202system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode 203system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode 204system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing 205system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle 206system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking 207system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst 208system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running 209system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking 210system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename 211system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full 212system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full 213system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full 214system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers 215system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed 216system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made 217system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups 218system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups 219system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed 220system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing 221system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed 222system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed 223system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer 224system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit. 225system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit. 226system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads. 227system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores. 228system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec) 229system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ 230system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued 231system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued 232system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling 233system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph 234system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed 235system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle 236system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle 237system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle 238system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 239system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle 240system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle 241system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle 242system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle 243system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle 244system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle 245system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle 246system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle 247system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle 248system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 249system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 250system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 251system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle 252system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 253system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available 254system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available 255system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available 256system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available 257system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available 258system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available 259system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available 260system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available 261system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available 262system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available 263system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available 264system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available 265system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available 266system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available 267system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available 268system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available 269system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available 270system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available 271system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available 272system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available 273system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available 274system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available 275system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available 276system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available 277system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available 278system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available 279system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available 280system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available 281system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available 282system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available 283system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available 284system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 285system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 286system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued 287system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued 288system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued 289system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued 290system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued 291system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued 292system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued 293system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued 294system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued 295system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued 296system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued 297system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued 298system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued 299system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued 300system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued 301system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued 302system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued 303system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued 304system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued 305system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued 306system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued 307system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued 308system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued 309system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued 310system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued 311system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued 312system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued 313system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued 314system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued 316system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued 317system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued 318system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 319system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 320system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued 321system.cpu.iq.rate 1.837676 # Inst issue rate 322system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested 323system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst) 324system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads 325system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes 326system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses 327system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads 328system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes 329system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses 330system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses 331system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses 332system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores 333system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 334system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed 335system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed 336system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations 337system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed 338system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 339system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 340system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled 341system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked 342system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 343system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing 344system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking 345system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking 346system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ 347system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch 348system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions 349system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions 350system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions 351system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall 352system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall 353system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations 354system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly 355system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly 356system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute 357system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions 358system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed 359system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute 360system.cpu.iew.exec_swp 0 # number of swp insts executed 361system.cpu.iew.exec_nop 0 # number of nop insts executed 362system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed 363system.cpu.iew.exec_branches 83283502 # Number of branches executed 364system.cpu.iew.exec_stores 9225749 # Number of stores executed 365system.cpu.iew.exec_rate 1.833188 # Inst execution rate 366system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit 367system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back 368system.cpu.iew.wb_producers 640500741 # num instructions producing a value 369system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value 370system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 371system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle 372system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back 373system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 374system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit 375system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards 376system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted 377system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle 378system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle 379system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle 380system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 381system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle 382system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle 383system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle 384system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle 385system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle 386system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle 387system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle 388system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle 389system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle 390system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 391system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 392system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 393system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle 394system.cpu.commit.committedInsts 407952579 # Number of instructions committed 395system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed 396system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 397system.cpu.commit.refs 22397454 # Number of memory references committed 398system.cpu.commit.loads 13980397 # Number of loads committed 399system.cpu.commit.membars 473477 # Number of memory barriers committed 400system.cpu.commit.branches 82193415 # Number of branches committed 401system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 402system.cpu.commit.int_insts 735346024 # Number of committed integer instructions. 403system.cpu.commit.function_calls 0 # Number of function calls committed. 404system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached 405system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 406system.cpu.rob.rob_reads 1080968615 # The number of ROB reads 407system.cpu.rob.rob_writes 1665910047 # The number of ROB writes 408system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself 409system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling 410system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 411system.cpu.committedInsts 407952579 # Number of Instructions Simulated 412system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated 413system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated 414system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction 415system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads 416system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle 417system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads 418system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads 419system.cpu.int_regfile_writes 977861305 # number of integer regfile writes 420system.cpu.fp_regfile_reads 65 # number of floating regfile reads 421system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads 422system.cpu.misc_regfile_writes 402500 # number of misc regfile writes 423system.cpu.icache.replacements 1068646 # number of replacements 424system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use 425system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks. 426system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks. 427system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks. 428system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. 429system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor 430system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy 431system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy 432system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits 433system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits 434system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits 435system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits 436system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits 437system.cpu.icache.overall_hits::total 8129454 # number of overall hits 438system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses 439system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses 440system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses 441system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses 442system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses 443system.cpu.icache.overall_misses::total 1139394 # number of overall misses 444system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles 445system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles 446system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles 447system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles 448system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles 449system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles 450system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses) 451system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses) 452system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses 453system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses 454system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses 455system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses 456system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses 457system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses 458system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses 459system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses 460system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses 461system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses 462system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency 463system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency 464system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency 465system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency 466system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency 467system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency 468system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked 469system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 470system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked 471system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 472system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked 473system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 474system.cpu.icache.fast_writes 0 # number of fast writes performed 475system.cpu.icache.cache_copies 0 # number of cache copies performed 476system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits 477system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits 478system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits 479system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits 480system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits 481system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits 482system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses 483system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses 484system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses 485system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses 486system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses 487system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses 488system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles 489system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles 490system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles 491system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles 492system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles 493system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles 494system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses 495system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses 496system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses 497system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # mshr miss rate for demand accesses 498system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for overall accesses 499system.cpu.icache.overall_mshr_miss_rate::total 0.115586 # mshr miss rate for overall accesses 500system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11707.158249 # average ReadReq mshr miss latency 501system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11707.158249 # average ReadReq mshr miss latency 502system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency 503system.cpu.icache.demand_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency 504system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency 505system.cpu.icache.overall_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency 506system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 507system.cpu.itb_walker_cache.replacements 9707 # number of replacements 508system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use 509system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks. 510system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks. 511system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks. 512system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit. 513system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor 514system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy 515system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy 516system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits 517system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits 518system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits 519system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits 520system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits 521system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits 522system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits 523system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits 524system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses 525system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses 526system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses 527system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses 528system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses 529system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses 530system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles 531system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles 532system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles 533system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles 534system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles 535system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles 536system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses) 537system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses) 538system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 539system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 540system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses 541system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses 542system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses 543system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses 544system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses 545system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses 546system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses 547system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses 548system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses 549system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses 550system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency 551system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency 552system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency 553system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency 554system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency 555system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency 556system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 563system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 564system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks 565system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks 566system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses 567system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses 568system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses 569system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses 570system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses 571system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses 572system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles 573system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles 574system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles 575system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles 576system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles 577system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles 578system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses 579system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses 580system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses 581system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses 582system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses 583system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses 584system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency 585system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency 586system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency 587system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency 588system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency 589system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency 590system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.dtb_walker_cache.replacements 107637 # number of replacements 592system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use 593system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks. 594system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks. 595system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks. 596system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. 597system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor 598system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy 599system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy 600system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits 601system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits 602system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits 603system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits 604system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits 605system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits 606system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses 607system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses 608system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses 609system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses 610system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses 611system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses 612system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles 613system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles 614system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles 615system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles 616system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles 617system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles 618system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses) 619system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses) 620system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses 621system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses 622system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses 623system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses 624system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses 625system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses 626system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses 627system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses 628system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses 629system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses 630system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency 631system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency 632system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency 633system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency 634system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency 635system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency 636system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 643system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 644system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks 645system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks 646system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses 647system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses 648system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses 649system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses 650system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses 651system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses 652system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles 653system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles 654system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles 655system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles 656system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles 657system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles 658system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses 659system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses 660system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses 661system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses 662system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses 663system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses 664system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency 665system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency 666system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency 667system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency 668system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency 669system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency 670system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 671system.cpu.dcache.replacements 1673658 # number of replacements 672system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use 673system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks. 674system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks. 675system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks. 676system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit. 677system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor 678system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 679system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy 680system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits 681system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits 682system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits 683system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits 684system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits 685system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits 686system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits 687system.cpu.dcache.overall_hits::total 19215231 # number of overall hits 688system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses 689system.cpu.dcache.ReadReq_misses::total 2269640 # number of ReadReq misses 690system.cpu.dcache.WriteReq_misses::cpu.data 319173 # number of WriteReq misses 691system.cpu.dcache.WriteReq_misses::total 319173 # number of WriteReq misses 692system.cpu.dcache.demand_misses::cpu.data 2588813 # number of demand (read+write) misses 693system.cpu.dcache.demand_misses::total 2588813 # number of demand (read+write) misses 694system.cpu.dcache.overall_misses::cpu.data 2588813 # number of overall misses 695system.cpu.dcache.overall_misses::total 2588813 # number of overall misses 696system.cpu.dcache.ReadReq_miss_latency::cpu.data 31726602500 # number of ReadReq miss cycles 697system.cpu.dcache.ReadReq_miss_latency::total 31726602500 # number of ReadReq miss cycles 698system.cpu.dcache.WriteReq_miss_latency::cpu.data 9823121491 # number of WriteReq miss cycles 699system.cpu.dcache.WriteReq_miss_latency::total 9823121491 # number of WriteReq miss cycles 700system.cpu.dcache.demand_miss_latency::cpu.data 41549723991 # number of demand (read+write) miss cycles 701system.cpu.dcache.demand_miss_latency::total 41549723991 # number of demand (read+write) miss cycles 702system.cpu.dcache.overall_miss_latency::cpu.data 41549723991 # number of overall miss cycles 703system.cpu.dcache.overall_miss_latency::total 41549723991 # number of overall miss cycles 704system.cpu.dcache.ReadReq_accesses::cpu.data 13396215 # number of ReadReq accesses(hits+misses) 705system.cpu.dcache.ReadReq_accesses::total 13396215 # number of ReadReq accesses(hits+misses) 706system.cpu.dcache.WriteReq_accesses::cpu.data 8407829 # number of WriteReq accesses(hits+misses) 707system.cpu.dcache.WriteReq_accesses::total 8407829 # number of WriteReq accesses(hits+misses) 708system.cpu.dcache.demand_accesses::cpu.data 21804044 # number of demand (read+write) accesses 709system.cpu.dcache.demand_accesses::total 21804044 # number of demand (read+write) accesses 710system.cpu.dcache.overall_accesses::cpu.data 21804044 # number of overall (read+write) accesses 711system.cpu.dcache.overall_accesses::total 21804044 # number of overall (read+write) accesses 712system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169424 # miss rate for ReadReq accesses 713system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses 714system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses 715system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses 716system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses 717system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses 718system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses 719system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses 720system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency 721system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency 722system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency 723system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency 724system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency 725system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency 727system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency 728system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked 729system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked 731system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked 733system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.dcache.fast_writes 0 # number of fast writes performed 735system.cpu.dcache.cache_copies 0 # number of cache copies performed 736system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks 737system.cpu.dcache.writebacks::total 1573837 # number of writebacks 738system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits 739system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits 740system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits 741system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits 742system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits 743system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits 744system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits 745system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits 746system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # number of ReadReq MSHR misses 747system.cpu.dcache.ReadReq_mshr_misses::total 1385457 # number of ReadReq MSHR misses 748system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293116 # number of WriteReq MSHR misses 749system.cpu.dcache.WriteReq_mshr_misses::total 293116 # number of WriteReq MSHR misses 750system.cpu.dcache.demand_mshr_misses::cpu.data 1678573 # number of demand (read+write) MSHR misses 751system.cpu.dcache.demand_mshr_misses::total 1678573 # number of demand (read+write) MSHR misses 752system.cpu.dcache.overall_mshr_misses::cpu.data 1678573 # number of overall MSHR misses 753system.cpu.dcache.overall_mshr_misses::total 1678573 # number of overall MSHR misses 754system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17084942000 # number of ReadReq MSHR miss cycles 755system.cpu.dcache.ReadReq_mshr_miss_latency::total 17084942000 # number of ReadReq MSHR miss cycles 756system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8988357491 # number of WriteReq MSHR miss cycles 757system.cpu.dcache.WriteReq_mshr_miss_latency::total 8988357491 # number of WriteReq MSHR miss cycles 758system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles 759system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles 760system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles 761system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles 762system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles 763system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles 764system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles 765system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles 766system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles 767system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles 768system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses 769system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses 770system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # mshr miss rate for WriteReq accesses 771system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034862 # mshr miss rate for WriteReq accesses 772system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for demand accesses 773system.cpu.dcache.demand_mshr_miss_rate::total 0.076984 # mshr miss rate for demand accesses 774system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for overall accesses 775system.cpu.dcache.overall_mshr_miss_rate::total 0.076984 # mshr miss rate for overall accesses 776system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.629202 # average ReadReq mshr miss latency 777system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.629202 # average ReadReq mshr miss latency 778system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30664.847675 # average WriteReq mshr miss latency 779system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30664.847675 # average WriteReq mshr miss latency 780system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency 781system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency 782system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency 783system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency 784system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 785system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 786system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 787system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 788system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 789system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 790system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 791system.cpu.l2cache.replacements 113860 # number of replacements 792system.cpu.l2cache.tagsinuse 64830.724160 # Cycle average of tags in use 793system.cpu.l2cache.total_refs 3973813 # Total number of references to valid blocks. 794system.cpu.l2cache.sampled_refs 177772 # Sample count of references to valid blocks. 795system.cpu.l2cache.avg_refs 22.353425 # Average number of references to valid blocks. 796system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 797system.cpu.l2cache.occ_blocks::writebacks 50128.354504 # Average occupied blocks per requestor 798system.cpu.l2cache.occ_blocks::cpu.dtb.walker 11.733619 # Average occupied blocks per requestor 799system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.162766 # Average occupied blocks per requestor 800system.cpu.l2cache.occ_blocks::cpu.inst 3228.532252 # Average occupied blocks per requestor 801system.cpu.l2cache.occ_blocks::cpu.data 11461.941019 # Average occupied blocks per requestor 802system.cpu.l2cache.occ_percent::writebacks 0.764898 # Average percentage of cache occupancy 803system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000179 # Average percentage of cache occupancy 804system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 805system.cpu.l2cache.occ_percent::cpu.inst 0.049263 # Average percentage of cache occupancy 806system.cpu.l2cache.occ_percent::cpu.data 0.174895 # Average percentage of cache occupancy 807system.cpu.l2cache.occ_percent::total 0.989238 # Average percentage of cache occupancy 808system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101628 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7965 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::cpu.inst 1052257 # number of ReadReq hits 811system.cpu.l2cache.ReadReq_hits::cpu.data 1347205 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::total 2509055 # number of ReadReq hits 813system.cpu.l2cache.Writeback_hits::writebacks 1608097 # number of Writeback hits 814system.cpu.l2cache.Writeback_hits::total 1608097 # number of Writeback hits 815system.cpu.l2cache.UpgradeReq_hits::cpu.data 328 # number of UpgradeReq hits 816system.cpu.l2cache.UpgradeReq_hits::total 328 # number of UpgradeReq hits 817system.cpu.l2cache.ReadExReq_hits::cpu.data 156120 # number of ReadExReq hits 818system.cpu.l2cache.ReadExReq_hits::total 156120 # number of ReadExReq hits 819system.cpu.l2cache.demand_hits::cpu.dtb.walker 101628 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.itb.walker 7965 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::cpu.inst 1052257 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::cpu.data 1503325 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::total 2665175 # number of demand (read+write) hits 824system.cpu.l2cache.overall_hits::cpu.dtb.walker 101628 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.itb.walker 7965 # number of overall hits 826system.cpu.l2cache.overall_hits::cpu.inst 1052257 # number of overall hits 827system.cpu.l2cache.overall_hits::cpu.data 1503325 # number of overall hits 828system.cpu.l2cache.overall_hits::total 2665175 # number of overall hits 829system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 39 # number of ReadReq misses 830system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 831system.cpu.l2cache.ReadReq_misses::cpu.inst 16857 # number of ReadReq misses 832system.cpu.l2cache.ReadReq_misses::cpu.data 37156 # number of ReadReq misses 833system.cpu.l2cache.ReadReq_misses::total 54059 # number of ReadReq misses 834system.cpu.l2cache.UpgradeReq_misses::cpu.data 3590 # number of UpgradeReq misses 835system.cpu.l2cache.UpgradeReq_misses::total 3590 # number of UpgradeReq misses 836system.cpu.l2cache.ReadExReq_misses::cpu.data 133151 # number of ReadExReq misses 837system.cpu.l2cache.ReadExReq_misses::total 133151 # number of ReadExReq misses 838system.cpu.l2cache.demand_misses::cpu.dtb.walker 39 # number of demand (read+write) misses 839system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::cpu.inst 16857 # number of demand (read+write) misses 841system.cpu.l2cache.demand_misses::cpu.data 170307 # number of demand (read+write) misses 842system.cpu.l2cache.demand_misses::total 187210 # number of demand (read+write) misses 843system.cpu.l2cache.overall_misses::cpu.dtb.walker 39 # number of overall misses 844system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 845system.cpu.l2cache.overall_misses::cpu.inst 16857 # number of overall misses 846system.cpu.l2cache.overall_misses::cpu.data 170307 # number of overall misses 847system.cpu.l2cache.overall_misses::total 187210 # number of overall misses 848system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2058500 # number of ReadReq miss cycles 849system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 371500 # number of ReadReq miss cycles 850system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 895435000 # number of ReadReq miss cycles 851system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1995543998 # number of ReadReq miss cycles 852system.cpu.l2cache.ReadReq_miss_latency::total 2893408998 # number of ReadReq miss cycles 853system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 37772999 # number of UpgradeReq miss cycles 854system.cpu.l2cache.UpgradeReq_miss_latency::total 37772999 # number of UpgradeReq miss cycles 855system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6939920000 # number of ReadExReq miss cycles 856system.cpu.l2cache.ReadExReq_miss_latency::total 6939920000 # number of ReadExReq miss cycles 857system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2058500 # number of demand (read+write) miss cycles 858system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 371500 # number of demand (read+write) miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 895435000 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 8935463998 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 9833328998 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2058500 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 371500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::cpu.inst 895435000 # number of overall miss cycles 865system.cpu.l2cache.overall_miss_latency::cpu.data 8935463998 # number of overall miss cycles 866system.cpu.l2cache.overall_miss_latency::total 9833328998 # number of overall miss cycles 867system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101667 # number of ReadReq accesses(hits+misses) 868system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7972 # number of ReadReq accesses(hits+misses) 869system.cpu.l2cache.ReadReq_accesses::cpu.inst 1069114 # number of ReadReq accesses(hits+misses) 870system.cpu.l2cache.ReadReq_accesses::cpu.data 1384361 # number of ReadReq accesses(hits+misses) 871system.cpu.l2cache.ReadReq_accesses::total 2563114 # number of ReadReq accesses(hits+misses) 872system.cpu.l2cache.Writeback_accesses::writebacks 1608097 # number of Writeback accesses(hits+misses) 873system.cpu.l2cache.Writeback_accesses::total 1608097 # number of Writeback accesses(hits+misses) 874system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3918 # number of UpgradeReq accesses(hits+misses) 875system.cpu.l2cache.UpgradeReq_accesses::total 3918 # number of UpgradeReq accesses(hits+misses) 876system.cpu.l2cache.ReadExReq_accesses::cpu.data 289271 # number of ReadExReq accesses(hits+misses) 877system.cpu.l2cache.ReadExReq_accesses::total 289271 # number of ReadExReq accesses(hits+misses) 878system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101667 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::cpu.itb.walker 7972 # number of demand (read+write) accesses 880system.cpu.l2cache.demand_accesses::cpu.inst 1069114 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::cpu.data 1673632 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::total 2852385 # number of demand (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101667 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.itb.walker 7972 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::cpu.inst 1069114 # number of overall (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.data 1673632 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::total 2852385 # number of overall (read+write) accesses 888system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000384 # miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000878 # miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015767 # miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_miss_rate::total 0.021091 # miss rate for ReadReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916284 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916284 # miss rate for UpgradeReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460298 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadExReq_miss_rate::total 0.460298 # miss rate for ReadExReq accesses 897system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000384 # miss rate for demand accesses 898system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000878 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015767 # miss rate for demand accesses 900system.cpu.l2cache.demand_miss_rate::cpu.data 0.101759 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::total 0.065633 # miss rate for demand accesses 902system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000384 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000878 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015767 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::cpu.data 0.101759 # miss rate for overall accesses 906system.cpu.l2cache.overall_miss_rate::total 0.065633 # miss rate for overall accesses 907system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52782.051282 # average ReadReq miss latency 908system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 53071.428571 # average ReadReq miss latency 909system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53119.475589 # average ReadReq miss latency 910system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53707.180482 # average ReadReq miss latency 911system.cpu.l2cache.ReadReq_avg_miss_latency::total 53523.169093 # average ReadReq miss latency 912system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 10521.726741 # average UpgradeReq miss latency 913system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 10521.726741 # average UpgradeReq miss latency 914system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52120.675023 # average ReadExReq miss latency 915system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52120.675023 # average ReadExReq miss latency 916system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency 917system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency 920system.cpu.l2cache.demand_avg_miss_latency::total 52525.661012 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency 922system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency 923system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency 924system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency 925system.cpu.l2cache.overall_avg_miss_latency::total 52525.661012 # average overall miss latency 926system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 927system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 928system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 929system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 930system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 931system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 932system.cpu.l2cache.fast_writes 0 # number of fast writes performed 933system.cpu.l2cache.cache_copies 0 # number of cache copies performed 934system.cpu.l2cache.writebacks::writebacks 102571 # number of writebacks 935system.cpu.l2cache.writebacks::total 102571 # number of writebacks 936system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 937system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 938system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 939system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 940system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 941system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 942system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 943system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 944system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 945system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 39 # number of ReadReq MSHR misses 946system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 947system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16855 # number of ReadReq MSHR misses 948system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37154 # number of ReadReq MSHR misses 949system.cpu.l2cache.ReadReq_mshr_misses::total 54055 # number of ReadReq MSHR misses 950system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3590 # number of UpgradeReq MSHR misses 951system.cpu.l2cache.UpgradeReq_mshr_misses::total 3590 # number of UpgradeReq MSHR misses 952system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133151 # number of ReadExReq MSHR misses 953system.cpu.l2cache.ReadExReq_mshr_misses::total 133151 # number of ReadExReq MSHR misses 954system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 39 # number of demand (read+write) MSHR misses 955system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 956system.cpu.l2cache.demand_mshr_misses::cpu.inst 16855 # number of demand (read+write) MSHR misses 957system.cpu.l2cache.demand_mshr_misses::cpu.data 170305 # number of demand (read+write) MSHR misses 958system.cpu.l2cache.demand_mshr_misses::total 187206 # number of demand (read+write) MSHR misses 959system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 39 # number of overall MSHR misses 960system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 961system.cpu.l2cache.overall_mshr_misses::cpu.inst 16855 # number of overall MSHR misses 962system.cpu.l2cache.overall_mshr_misses::cpu.data 170305 # number of overall MSHR misses 963system.cpu.l2cache.overall_mshr_misses::total 187206 # number of overall MSHR misses 964system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1582000 # number of ReadReq MSHR miss cycles 965system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287000 # number of ReadReq MSHR miss cycles 966system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 689639500 # number of ReadReq MSHR miss cycles 967system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1541128498 # number of ReadReq MSHR miss cycles 968system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2232636998 # number of ReadReq MSHR miss cycles 969system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 144031499 # number of UpgradeReq MSHR miss cycles 970system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 144031499 # number of UpgradeReq MSHR miss cycles 971system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5333340000 # number of ReadExReq MSHR miss cycles 972system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5333340000 # number of ReadExReq MSHR miss cycles 973system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1582000 # number of demand (read+write) MSHR miss cycles 974system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287000 # number of demand (read+write) MSHR miss cycles 975system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689639500 # number of demand (read+write) MSHR miss cycles 976system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6874468498 # number of demand (read+write) MSHR miss cycles 977system.cpu.l2cache.demand_mshr_miss_latency::total 7565976998 # number of demand (read+write) MSHR miss cycles 978system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1582000 # number of overall MSHR miss cycles 979system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287000 # number of overall MSHR miss cycles 980system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689639500 # number of overall MSHR miss cycles 981system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6874468498 # number of overall MSHR miss cycles 982system.cpu.l2cache.overall_mshr_miss_latency::total 7565976998 # number of overall MSHR miss cycles 983system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185727000 # number of ReadReq MSHR uncacheable cycles 984system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185727000 # number of ReadReq MSHR uncacheable cycles 985system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304773500 # number of WriteReq MSHR uncacheable cycles 986system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304773500 # number of WriteReq MSHR uncacheable cycles 987system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91490500500 # number of overall MSHR uncacheable cycles 988system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91490500500 # number of overall MSHR uncacheable cycles 989system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for ReadReq accesses 991system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for ReadReq accesses 992system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026838 # mshr miss rate for ReadReq accesses 993system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021090 # mshr miss rate for ReadReq accesses 994system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916284 # mshr miss rate for UpgradeReq accesses 995system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916284 # mshr miss rate for UpgradeReq accesses 996system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460298 # mshr miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460298 # mshr miss rate for ReadExReq accesses 998system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for demand accesses 999system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for demand accesses 1000system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for demand accesses 1001system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for demand accesses 1002system.cpu.l2cache.demand_mshr_miss_rate::total 0.065631 # mshr miss rate for demand accesses 1003system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for overall accesses 1004system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for overall accesses 1005system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for overall accesses 1006system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses 1007system.cpu.l2cache.overall_mshr_miss_rate::total 0.065631 # mshr miss rate for overall accesses 1008system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average ReadReq mshr miss latency 1009system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency 1010system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40916.018985 # average ReadReq mshr miss latency 1011system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41479.477257 # average ReadReq mshr miss latency 1012system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41303.061659 # average ReadReq mshr miss latency 1013system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40120.194708 # average UpgradeReq mshr miss latency 1014system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40120.194708 # average UpgradeReq mshr miss latency 1015system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40054.824973 # average ReadExReq mshr miss latency 1016system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40054.824973 # average ReadExReq mshr miss latency 1017system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency 1018system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency 1019system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency 1020system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency 1021system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency 1022system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency 1023system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency 1024system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency 1025system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency 1026system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency 1027system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1028system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1029system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1030system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1031system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1032system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1033system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1034system.cpu.kern.inst.arm 0 # number of arm instructions executed 1035system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1036 1037---------- End Simulation Statistics ---------- 1038