stats.txt revision 10645:cd95d4d51659
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.121937 # Number of seconds simulated 4sim_ticks 5121937205500 # Number of ticks simulated 5final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 133395 # Simulator instruction rate (inst/s) 8host_op_rate 263673 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1674179733 # Simulator tick rate (ticks/s) 10host_mem_usage 798472 # Number of bytes of host memory used 11host_seconds 3059.37 # Real time elapsed on the host 12sim_insts 408103625 # Number of instructions simulated 13sim_ops 806672783 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 185035 # Number of read requests accepted 52system.physmem.writeReqs 196277 # Number of write requests accepted 53system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue 57system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11869 # Per bank write bursts 64system.physmem.perBankRdBursts::1 11279 # Per bank write bursts 65system.physmem.perBankRdBursts::2 11900 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11555 # Per bank write bursts 67system.physmem.perBankRdBursts::4 12140 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11427 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11446 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11418 # Per bank write bursts 71system.physmem.perBankRdBursts::8 11156 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11288 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11167 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11604 # Per bank write bursts 75system.physmem.perBankRdBursts::12 11474 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12255 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11757 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11165 # Per bank write bursts 79system.physmem.perBankWrBursts::0 12900 # Per bank write bursts 80system.physmem.perBankWrBursts::1 13064 # Per bank write bursts 81system.physmem.perBankWrBursts::2 11983 # Per bank write bursts 82system.physmem.perBankWrBursts::3 10698 # Per bank write bursts 83system.physmem.perBankWrBursts::4 10899 # Per bank write bursts 84system.physmem.perBankWrBursts::5 11057 # Per bank write bursts 85system.physmem.perBankWrBursts::6 11263 # Per bank write bursts 86system.physmem.perBankWrBursts::7 11237 # Per bank write bursts 87system.physmem.perBankWrBursts::8 11985 # Per bank write bursts 88system.physmem.perBankWrBursts::9 12151 # Per bank write bursts 89system.physmem.perBankWrBursts::10 12710 # Per bank write bursts 90system.physmem.perBankWrBursts::11 12714 # Per bank write bursts 91system.physmem.perBankWrBursts::12 13328 # Per bank write bursts 92system.physmem.perBankWrBursts::13 13119 # Per bank write bursts 93system.physmem.perBankWrBursts::14 12767 # Per bank write bursts 94system.physmem.perBankWrBursts::15 11952 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 97system.physmem.totGap 5121937091000 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 185035 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 196277 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 227 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 187 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads 282system.physmem.totQLat 1977045500 # Total ticks spent queuing 283system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM 284system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers 285system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst 286system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 287system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst 288system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s 289system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s 290system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s 291system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s 292system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 293system.physmem.busUtil 0.04 # Data bus utilization in percentage 294system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 295system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 296system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 297system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing 298system.physmem.readRowHits 151994 # Number of row buffer hits during reads 299system.physmem.writeRowHits 151865 # Number of row buffer hits during writes 300system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads 301system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes 302system.physmem.avgGap 13432404.67 # Average gap between requests 303system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined 304system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ) 305system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ) 306system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ) 307system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ) 308system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) 309system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ) 310system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ) 311system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ) 312system.physmem_0.averagePower 668.764386 # Core power per rank (mW) 313system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states 314system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states 315system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states 317system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ) 319system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ) 320system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ) 321system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ) 322system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) 323system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ) 324system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ) 325system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ) 326system.physmem_1.averagePower 668.765080 # Core power per rank (mW) 327system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states 328system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states 329system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states 331system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.cpu.branchPred.lookups 86925803 # Number of BP lookups 333system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted 334system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect 335system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups 336system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits 337system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 338system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage 339system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target. 340system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks 342system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 343system.cpu.numCycles 449601109 # number of cpu cycles simulated 344system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 345system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 346system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss 347system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed 348system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered 349system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken 350system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked 351system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing 352system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb 353system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 354system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps 355system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions 356system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR 357system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched 358system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed 359system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed 360system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle 378system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle 379system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle 380system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked 381system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running 382system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking 383system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing 384system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode 385system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing 386system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle 387system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking 388system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst 389system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running 390system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking 391system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename 392system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full 393system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full 394system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full 395system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full 396system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed 397system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made 398system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups 399system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups 400system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed 401system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing 402system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed 403system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed 404system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer 405system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit. 406system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit. 407system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads. 408system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores. 409system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec) 410system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ 411system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued 412system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued 413system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling 414system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph 415system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed 416system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle 433system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued 468system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued 469system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued 470system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued 497system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued 498system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued 502system.cpu.iq.rate 1.833938 # Inst issue rate 503system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested 504system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst) 505system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads 506system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes 507system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses 508system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads 509system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes 510system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses 511system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses 512system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses 513system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores 514system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 515system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed 516system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed 517system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations 518system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed 519system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 520system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 521system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled 522system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked 523system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 524system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing 525system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking 526system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking 527system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ 528system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch 529system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions 530system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions 531system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions 532system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall 533system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall 534system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations 535system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly 536system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly 537system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute 538system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions 539system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed 540system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute 541system.cpu.iew.exec_swp 0 # number of swp insts executed 542system.cpu.iew.exec_nop 0 # number of nop insts executed 543system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed 544system.cpu.iew.exec_branches 83328554 # Number of branches executed 545system.cpu.iew.exec_stores 9168598 # Number of stores executed 546system.cpu.iew.exec_rate 1.830370 # Inst execution rate 547system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit 548system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back 549system.cpu.iew.wb_producers 641244168 # num instructions producing a value 550system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value 551system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 552system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle 553system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back 554system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 555system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit 556system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards 557system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted 558system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle 575system.cpu.commit.committedInsts 408103625 # Number of instructions committed 576system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed 577system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 578system.cpu.commit.refs 22427037 # Number of memory references committed 579system.cpu.commit.loads 14000251 # Number of loads committed 580system.cpu.commit.membars 475479 # Number of memory barriers committed 581system.cpu.commit.branches 82225235 # Number of branches committed 582system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 583system.cpu.commit.int_insts 735463006 # Number of committed integer instructions. 584system.cpu.commit.function_calls 1156113 # Number of function calls committed. 585system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction 586system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction 587system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction 588system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction 589system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 615system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction 616system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 619system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction 620system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached 621system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 622system.cpu.rob.rob_reads 1268751952 # The number of ROB reads 623system.cpu.rob.rob_writes 1665400460 # The number of ROB writes 624system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself 625system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling 626system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 627system.cpu.committedInsts 408103625 # Number of Instructions Simulated 628system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated 629system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction 630system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads 631system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle 632system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads 633system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads 634system.cpu.int_regfile_writes 656343554 # number of integer regfile writes 635system.cpu.fp_regfile_reads 191 # number of floating regfile reads 636system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads 637system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes 638system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads 639system.cpu.misc_regfile_writes 400219 # number of misc regfile writes 640system.cpu.dcache.tags.replacements 1658771 # number of replacements 641system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use 642system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks. 643system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks. 644system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks. 645system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 646system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor 647system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 648system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 649system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 650system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 651system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id 652system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 653system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 654system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses 655system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses 656system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits 657system.cpu.dcache.ReadReq_hits::total 11011311 # number of ReadReq hits 658system.cpu.dcache.WriteReq_hits::cpu.data 8082990 # number of WriteReq hits 659system.cpu.dcache.WriteReq_hits::total 8082990 # number of WriteReq hits 660system.cpu.dcache.SoftPFReq_hits::cpu.data 64916 # number of SoftPFReq hits 661system.cpu.dcache.SoftPFReq_hits::total 64916 # number of SoftPFReq hits 662system.cpu.dcache.demand_hits::cpu.data 19094301 # number of demand (read+write) hits 663system.cpu.dcache.demand_hits::total 19094301 # number of demand (read+write) hits 664system.cpu.dcache.overall_hits::cpu.data 19159217 # number of overall hits 665system.cpu.dcache.overall_hits::total 19159217 # number of overall hits 666system.cpu.dcache.ReadReq_misses::cpu.data 1795762 # number of ReadReq misses 667system.cpu.dcache.ReadReq_misses::total 1795762 # number of ReadReq misses 668system.cpu.dcache.WriteReq_misses::cpu.data 334107 # number of WriteReq misses 669system.cpu.dcache.WriteReq_misses::total 334107 # number of WriteReq misses 670system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses 671system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses 672system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses 673system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses 674system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses 675system.cpu.dcache.overall_misses::total 2536228 # number of overall misses 676system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles 677system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles 678system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles 679system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles 680system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles 681system.cpu.dcache.demand_miss_latency::total 39308801261 # number of demand (read+write) miss cycles 682system.cpu.dcache.overall_miss_latency::cpu.data 39308801261 # number of overall miss cycles 683system.cpu.dcache.overall_miss_latency::total 39308801261 # number of overall miss cycles 684system.cpu.dcache.ReadReq_accesses::cpu.data 12807073 # number of ReadReq accesses(hits+misses) 685system.cpu.dcache.ReadReq_accesses::total 12807073 # number of ReadReq accesses(hits+misses) 686system.cpu.dcache.WriteReq_accesses::cpu.data 8417097 # number of WriteReq accesses(hits+misses) 687system.cpu.dcache.WriteReq_accesses::total 8417097 # number of WriteReq accesses(hits+misses) 688system.cpu.dcache.SoftPFReq_accesses::cpu.data 471275 # number of SoftPFReq accesses(hits+misses) 689system.cpu.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) 690system.cpu.dcache.demand_accesses::cpu.data 21224170 # number of demand (read+write) accesses 691system.cpu.dcache.demand_accesses::total 21224170 # number of demand (read+write) accesses 692system.cpu.dcache.overall_accesses::cpu.data 21695445 # number of overall (read+write) accesses 693system.cpu.dcache.overall_accesses::total 21695445 # number of overall (read+write) accesses 694system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140216 # miss rate for ReadReq accesses 695system.cpu.dcache.ReadReq_miss_rate::total 0.140216 # miss rate for ReadReq accesses 696system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039694 # miss rate for WriteReq accesses 697system.cpu.dcache.WriteReq_miss_rate::total 0.039694 # miss rate for WriteReq accesses 698system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862255 # miss rate for SoftPFReq accesses 699system.cpu.dcache.SoftPFReq_miss_rate::total 0.862255 # miss rate for SoftPFReq accesses 700system.cpu.dcache.demand_miss_rate::cpu.data 0.100351 # miss rate for demand accesses 701system.cpu.dcache.demand_miss_rate::total 0.100351 # miss rate for demand accesses 702system.cpu.dcache.overall_miss_rate::cpu.data 0.116901 # miss rate for overall accesses 703system.cpu.dcache.overall_miss_rate::total 0.116901 # miss rate for overall accesses 704system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484 # average ReadReq miss latency 705system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484 # average ReadReq miss latency 706system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582 # average WriteReq miss latency 707system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582 # average WriteReq miss latency 708system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358 # average overall miss latency 709system.cpu.dcache.demand_avg_miss_latency::total 18455.971358 # average overall miss latency 710system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518 # average overall miss latency 711system.cpu.dcache.overall_avg_miss_latency::total 15498.922518 # average overall miss latency 712system.cpu.dcache.blocked_cycles::no_mshrs 371080 # number of cycles access was blocked 713system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 714system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked 715system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 716system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked 717system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 718system.cpu.dcache.fast_writes 0 # number of fast writes performed 719system.cpu.dcache.cache_copies 0 # number of cache copies performed 720system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks 721system.cpu.dcache.writebacks::total 1560107 # number of writebacks 722system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits 723system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits 724system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits 725system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits 726system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits 727system.cpu.dcache.demand_mshr_hits::total 871197 # number of demand (read+write) MSHR hits 728system.cpu.dcache.overall_mshr_hits::cpu.data 871197 # number of overall MSHR hits 729system.cpu.dcache.overall_mshr_hits::total 871197 # number of overall MSHR hits 730system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968802 # number of ReadReq MSHR misses 731system.cpu.dcache.ReadReq_mshr_misses::total 968802 # number of ReadReq MSHR misses 732system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289870 # number of WriteReq MSHR misses 733system.cpu.dcache.WriteReq_mshr_misses::total 289870 # number of WriteReq MSHR misses 734system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402896 # number of SoftPFReq MSHR misses 735system.cpu.dcache.SoftPFReq_mshr_misses::total 402896 # number of SoftPFReq MSHR misses 736system.cpu.dcache.demand_mshr_misses::cpu.data 1258672 # number of demand (read+write) MSHR misses 737system.cpu.dcache.demand_mshr_misses::total 1258672 # number of demand (read+write) MSHR misses 738system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses 739system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses 740system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles 741system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles 742system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles 743system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles 744system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles 745system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles 746system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles 747system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles 748system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles 749system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles 750system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles 751system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles 752system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles 753system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles 754system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles 755system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles 756system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses 757system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses 758system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses 759system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses 760system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses 761system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses 762system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses 763system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses 764system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses 765system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency 767system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency 769system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency 770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency 771system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency 772system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency 773system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency 774system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency 775system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency 776system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 777system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 778system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 779system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 780system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 781system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 782system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 783system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements 784system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use 785system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks. 786system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks. 787system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks. 788system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit. 789system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor 790system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy 791system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy 792system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 793system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 794system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 795system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 796system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 797system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses 798system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses 799system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits 800system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits 801system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits 802system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits 803system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits 804system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits 805system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses 806system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses 807system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses 808system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses 809system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses 810system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses 811system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770692 # number of ReadReq miss cycles 812system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770692 # number of ReadReq miss cycles 813system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770692 # number of demand (read+write) miss cycles 814system.cpu.dtb_walker_cache.demand_miss_latency::total 935770692 # number of demand (read+write) miss cycles 815system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770692 # number of overall miss cycles 816system.cpu.dtb_walker_cache.overall_miss_latency::total 935770692 # number of overall miss cycles 817system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses) 818system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses) 819system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses 820system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses 821system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses 822system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses 823system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses 824system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses 825system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses 826system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses 827system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses 828system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses 829system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177435 # average ReadReq miss latency 830system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177435 # average ReadReq miss latency 831system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177435 # average overall miss latency 832system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177435 # average overall miss latency 833system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177435 # average overall miss latency 834system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177435 # average overall miss latency 835system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 842system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 843system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks 844system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks 845system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses 846system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses 847system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses 848system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses 849system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses 850system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses 851system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624452 # number of ReadReq MSHR miss cycles 852system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624452 # number of ReadReq MSHR miss cycles 853system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624452 # number of demand (read+write) MSHR miss cycles 854system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624452 # number of demand (read+write) MSHR miss cycles 855system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624452 # number of overall MSHR miss cycles 856system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624452 # number of overall MSHR miss cycles 857system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses 858system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses 859system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses 860system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses 861system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses 862system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses 863system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average ReadReq mshr miss latency 864system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448965 # average ReadReq mshr miss latency 865system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average overall mshr miss latency 866system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448965 # average overall mshr miss latency 867system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average overall mshr miss latency 868system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448965 # average overall mshr miss latency 869system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 870system.cpu.icache.tags.replacements 1000352 # number of replacements 871system.cpu.icache.tags.tagsinuse 509.220531 # Cycle average of tags in use 872system.cpu.icache.tags.total_refs 8118136 # Total number of references to valid blocks. 873system.cpu.icache.tags.sampled_refs 1000864 # Sample count of references to valid blocks. 874system.cpu.icache.tags.avg_refs 8.111128 # Average number of references to valid blocks. 875system.cpu.icache.tags.warmup_cycle 147684343000 # Cycle when the warmup percentage was hit. 876system.cpu.icache.tags.occ_blocks::cpu.inst 509.220531 # Average occupied blocks per requestor 877system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy 878system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 880system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id 883system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 884system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses 885system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses 886system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits 887system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits 888system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits 889system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits 890system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits 891system.cpu.icache.overall_hits::total 8118136 # number of overall hits 892system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses 893system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses 894system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses 895system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses 896system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses 897system.cpu.icache.overall_misses::total 1063017 # number of overall misses 898system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles 899system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles 900system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles 901system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles 902system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles 903system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles 904system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses) 905system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses 907system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses 908system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses 909system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses 910system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115783 # miss rate for ReadReq accesses 911system.cpu.icache.ReadReq_miss_rate::total 0.115783 # miss rate for ReadReq accesses 912system.cpu.icache.demand_miss_rate::cpu.inst 0.115783 # miss rate for demand accesses 913system.cpu.icache.demand_miss_rate::total 0.115783 # miss rate for demand accesses 914system.cpu.icache.overall_miss_rate::cpu.inst 0.115783 # miss rate for overall accesses 915system.cpu.icache.overall_miss_rate::total 0.115783 # miss rate for overall accesses 916system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374 # average ReadReq miss latency 917system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374 # average ReadReq miss latency 918system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency 919system.cpu.icache.demand_avg_miss_latency::total 13889.291374 # average overall miss latency 920system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::total 13889.291374 # average overall miss latency 922system.cpu.icache.blocked_cycles::no_mshrs 7778 # number of cycles access was blocked 923system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked 924system.cpu.icache.blocked::no_mshrs 283 # number of cycles access was blocked 925system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 926system.cpu.icache.avg_blocked_cycles::no_mshrs 27.484099 # average number of cycles each access was blocked 927system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked 928system.cpu.icache.fast_writes 0 # number of fast writes performed 929system.cpu.icache.cache_copies 0 # number of cache copies performed 930system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62082 # number of ReadReq MSHR hits 931system.cpu.icache.ReadReq_mshr_hits::total 62082 # number of ReadReq MSHR hits 932system.cpu.icache.demand_mshr_hits::cpu.inst 62082 # number of demand (read+write) MSHR hits 933system.cpu.icache.demand_mshr_hits::total 62082 # number of demand (read+write) MSHR hits 934system.cpu.icache.overall_mshr_hits::cpu.inst 62082 # number of overall MSHR hits 935system.cpu.icache.overall_mshr_hits::total 62082 # number of overall MSHR hits 936system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1000935 # number of ReadReq MSHR misses 937system.cpu.icache.ReadReq_mshr_misses::total 1000935 # number of ReadReq MSHR misses 938system.cpu.icache.demand_mshr_misses::cpu.inst 1000935 # number of demand (read+write) MSHR misses 939system.cpu.icache.demand_mshr_misses::total 1000935 # number of demand (read+write) MSHR misses 940system.cpu.icache.overall_mshr_misses::cpu.inst 1000935 # number of overall MSHR misses 941system.cpu.icache.overall_mshr_misses::total 1000935 # number of overall MSHR misses 942system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12121618509 # number of ReadReq MSHR miss cycles 943system.cpu.icache.ReadReq_mshr_miss_latency::total 12121618509 # number of ReadReq MSHR miss cycles 944system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12121618509 # number of demand (read+write) MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::total 12121618509 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12121618509 # number of overall MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::total 12121618509 # number of overall MSHR miss cycles 948system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for ReadReq accesses 949system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109021 # mshr miss rate for ReadReq accesses 950system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for demand accesses 951system.cpu.icache.demand_mshr_miss_rate::total 0.109021 # mshr miss rate for demand accesses 952system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for overall accesses 953system.cpu.icache.overall_mshr_miss_rate::total 0.109021 # mshr miss rate for overall accesses 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency 960system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 961system.cpu.itb_walker_cache.tags.replacements 14419 # number of replacements 962system.cpu.itb_walker_cache.tags.tagsinuse 6.299272 # Cycle average of tags in use 963system.cpu.itb_walker_cache.tags.total_refs 25752 # Total number of references to valid blocks. 964system.cpu.itb_walker_cache.tags.sampled_refs 14435 # Sample count of references to valid blocks. 965system.cpu.itb_walker_cache.tags.avg_refs 1.783997 # Average number of references to valid blocks. 966system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000 # Cycle when the warmup percentage was hit. 967system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.299272 # Average occupied blocks per requestor 968system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.393704 # Average percentage of cache occupancy 969system.cpu.itb_walker_cache.tags.occ_percent::total 0.393704 # Average percentage of cache occupancy 970system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 971system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 972system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 973system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 974system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 975system.cpu.itb_walker_cache.tags.tag_accesses 97449 # Number of tag accesses 976system.cpu.itb_walker_cache.tags.data_accesses 97449 # Number of data accesses 977system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25750 # number of ReadReq hits 978system.cpu.itb_walker_cache.ReadReq_hits::total 25750 # number of ReadReq hits 979system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 980system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 981system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits 982system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits 983system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits 984system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits 985system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses 986system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses 987system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses 988system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses 989system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses 990system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses 991system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 177860993 # number of ReadReq miss cycles 992system.cpu.itb_walker_cache.ReadReq_miss_latency::total 177860993 # number of ReadReq miss cycles 993system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 177860993 # number of demand (read+write) miss cycles 994system.cpu.itb_walker_cache.demand_miss_latency::total 177860993 # number of demand (read+write) miss cycles 995system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 177860993 # number of overall miss cycles 996system.cpu.itb_walker_cache.overall_miss_latency::total 177860993 # number of overall miss cycles 997system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41065 # number of ReadReq accesses(hits+misses) 998system.cpu.itb_walker_cache.ReadReq_accesses::total 41065 # number of ReadReq accesses(hits+misses) 999system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1000system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 1001system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41067 # number of demand (read+write) accesses 1002system.cpu.itb_walker_cache.demand_accesses::total 41067 # number of demand (read+write) accesses 1003system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41067 # number of overall (read+write) accesses 1004system.cpu.itb_walker_cache.overall_accesses::total 41067 # number of overall (read+write) accesses 1005system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372945 # miss rate for ReadReq accesses 1006system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372945 # miss rate for ReadReq accesses 1007system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372927 # miss rate for demand accesses 1008system.cpu.itb_walker_cache.demand_miss_rate::total 0.372927 # miss rate for demand accesses 1009system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372927 # miss rate for overall accesses 1010system.cpu.itb_walker_cache.overall_miss_rate::total 0.372927 # miss rate for overall accesses 1011system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515704 # average ReadReq miss latency 1012system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515704 # average ReadReq miss latency 1013system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515704 # average overall miss latency 1014system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515704 # average overall miss latency 1015system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515704 # average overall miss latency 1016system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515704 # average overall miss latency 1017system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1018system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1019system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1020system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1021system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1022system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1023system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1024system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1025system.cpu.itb_walker_cache.writebacks::writebacks 3318 # number of writebacks 1026system.cpu.itb_walker_cache.writebacks::total 3318 # number of writebacks 1027system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15315 # number of ReadReq MSHR misses 1028system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15315 # number of ReadReq MSHR misses 1029system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15315 # number of demand (read+write) MSHR misses 1030system.cpu.itb_walker_cache.demand_mshr_misses::total 15315 # number of demand (read+write) MSHR misses 1031system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15315 # number of overall MSHR misses 1032system.cpu.itb_walker_cache.overall_mshr_misses::total 15315 # number of overall MSHR misses 1033system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147213025 # number of ReadReq MSHR miss cycles 1034system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147213025 # number of ReadReq MSHR miss cycles 1035system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147213025 # number of demand (read+write) MSHR miss cycles 1036system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147213025 # number of demand (read+write) MSHR miss cycles 1037system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147213025 # number of overall MSHR miss cycles 1038system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147213025 # number of overall MSHR miss cycles 1039system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372945 # mshr miss rate for ReadReq accesses 1040system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372945 # mshr miss rate for ReadReq accesses 1041system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for demand accesses 1042system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372927 # mshr miss rate for demand accesses 1043system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for overall accesses 1044system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses 1045system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average ReadReq mshr miss latency 1046system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342475 # average ReadReq mshr miss latency 1047system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average overall mshr miss latency 1048system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342475 # average overall mshr miss latency 1049system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average overall mshr miss latency 1050system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342475 # average overall mshr miss latency 1051system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1052system.cpu.l2cache.tags.replacements 112445 # number of replacements 1053system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use 1054system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks. 1055system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks. 1056system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks. 1057system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1058system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor 1059system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor 1060system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor 1061system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor 1062system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor 1063system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy 1064system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy 1065system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy 1066system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy 1067system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy 1068system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy 1069system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id 1070system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1071system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id 1072system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id 1073system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id 1074system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id 1075system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id 1076system.cpu.l2cache.tags.tag_accesses 35103909 # Number of tag accesses 1077system.cpu.l2cache.tags.data_accesses 35103909 # Number of data accesses 1078system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69111 # number of ReadReq hits 1079system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12768 # number of ReadReq hits 1080system.cpu.l2cache.ReadReq_hits::cpu.inst 984459 # number of ReadReq hits 1081system.cpu.l2cache.ReadReq_hits::cpu.data 1335184 # number of ReadReq hits 1082system.cpu.l2cache.ReadReq_hits::total 2401522 # number of ReadReq hits 1083system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits 1084system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits 1085system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits 1086system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits 1087system.cpu.l2cache.ReadExReq_hits::cpu.data 154410 # number of ReadExReq hits 1088system.cpu.l2cache.ReadExReq_hits::total 154410 # number of ReadExReq hits 1089system.cpu.l2cache.demand_hits::cpu.dtb.walker 69111 # number of demand (read+write) hits 1090system.cpu.l2cache.demand_hits::cpu.itb.walker 12768 # number of demand (read+write) hits 1091system.cpu.l2cache.demand_hits::cpu.inst 984459 # number of demand (read+write) hits 1092system.cpu.l2cache.demand_hits::cpu.data 1489594 # number of demand (read+write) hits 1093system.cpu.l2cache.demand_hits::total 2555932 # number of demand (read+write) hits 1094system.cpu.l2cache.overall_hits::cpu.dtb.walker 69111 # number of overall hits 1095system.cpu.l2cache.overall_hits::cpu.itb.walker 12768 # number of overall hits 1096system.cpu.l2cache.overall_hits::cpu.inst 984459 # number of overall hits 1097system.cpu.l2cache.overall_hits::cpu.data 1489594 # number of overall hits 1098system.cpu.l2cache.overall_hits::total 2555932 # number of overall hits 1099system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses 1100system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1101system.cpu.l2cache.ReadReq_misses::cpu.inst 16359 # number of ReadReq misses 1102system.cpu.l2cache.ReadReq_misses::cpu.data 35824 # number of ReadReq misses 1103system.cpu.l2cache.ReadReq_misses::total 52251 # number of ReadReq misses 1104system.cpu.l2cache.UpgradeReq_misses::cpu.data 1504 # number of UpgradeReq misses 1105system.cpu.l2cache.UpgradeReq_misses::total 1504 # number of UpgradeReq misses 1106system.cpu.l2cache.ReadExReq_misses::cpu.data 133327 # number of ReadExReq misses 1107system.cpu.l2cache.ReadExReq_misses::total 133327 # number of ReadExReq misses 1108system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses 1109system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1110system.cpu.l2cache.demand_misses::cpu.inst 16359 # number of demand (read+write) misses 1111system.cpu.l2cache.demand_misses::cpu.data 169151 # number of demand (read+write) misses 1112system.cpu.l2cache.demand_misses::total 185578 # number of demand (read+write) misses 1113system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses 1114system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1115system.cpu.l2cache.overall_misses::cpu.inst 16359 # number of overall misses 1116system.cpu.l2cache.overall_misses::cpu.data 169151 # number of overall misses 1117system.cpu.l2cache.overall_misses::total 185578 # number of overall misses 1118system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5303750 # number of ReadReq miss cycles 1119system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467500 # number of ReadReq miss cycles 1120system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1250815250 # number of ReadReq miss cycles 1121system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2830285496 # number of ReadReq miss cycles 1122system.cpu.l2cache.ReadReq_miss_latency::total 4086871996 # number of ReadReq miss cycles 1123system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17716796 # number of UpgradeReq miss cycles 1124system.cpu.l2cache.UpgradeReq_miss_latency::total 17716796 # number of UpgradeReq miss cycles 1125system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290586712 # number of ReadExReq miss cycles 1126system.cpu.l2cache.ReadExReq_miss_latency::total 9290586712 # number of ReadExReq miss cycles 1127system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5303750 # number of demand (read+write) miss cycles 1128system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467500 # number of demand (read+write) miss cycles 1129system.cpu.l2cache.demand_miss_latency::cpu.inst 1250815250 # number of demand (read+write) miss cycles 1130system.cpu.l2cache.demand_miss_latency::cpu.data 12120872208 # number of demand (read+write) miss cycles 1131system.cpu.l2cache.demand_miss_latency::total 13377458708 # number of demand (read+write) miss cycles 1132system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5303750 # number of overall miss cycles 1133system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467500 # number of overall miss cycles 1134system.cpu.l2cache.overall_miss_latency::cpu.inst 1250815250 # number of overall miss cycles 1135system.cpu.l2cache.overall_miss_latency::cpu.data 12120872208 # number of overall miss cycles 1136system.cpu.l2cache.overall_miss_latency::total 13377458708 # number of overall miss cycles 1137system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69173 # number of ReadReq accesses(hits+misses) 1138system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12774 # number of ReadReq accesses(hits+misses) 1139system.cpu.l2cache.ReadReq_accesses::cpu.inst 1000818 # number of ReadReq accesses(hits+misses) 1140system.cpu.l2cache.ReadReq_accesses::cpu.data 1371008 # number of ReadReq accesses(hits+misses) 1141system.cpu.l2cache.ReadReq_accesses::total 2453773 # number of ReadReq accesses(hits+misses) 1142system.cpu.l2cache.Writeback_accesses::writebacks 1585447 # number of Writeback accesses(hits+misses) 1143system.cpu.l2cache.Writeback_accesses::total 1585447 # number of Writeback accesses(hits+misses) 1144system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1813 # number of UpgradeReq accesses(hits+misses) 1145system.cpu.l2cache.UpgradeReq_accesses::total 1813 # number of UpgradeReq accesses(hits+misses) 1146system.cpu.l2cache.ReadExReq_accesses::cpu.data 287737 # number of ReadExReq accesses(hits+misses) 1147system.cpu.l2cache.ReadExReq_accesses::total 287737 # number of ReadExReq accesses(hits+misses) 1148system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69173 # number of demand (read+write) accesses 1149system.cpu.l2cache.demand_accesses::cpu.itb.walker 12774 # number of demand (read+write) accesses 1150system.cpu.l2cache.demand_accesses::cpu.inst 1000818 # number of demand (read+write) accesses 1151system.cpu.l2cache.demand_accesses::cpu.data 1658745 # number of demand (read+write) accesses 1152system.cpu.l2cache.demand_accesses::total 2741510 # number of demand (read+write) accesses 1153system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69173 # number of overall (read+write) accesses 1154system.cpu.l2cache.overall_accesses::cpu.itb.walker 12774 # number of overall (read+write) accesses 1155system.cpu.l2cache.overall_accesses::cpu.inst 1000818 # number of overall (read+write) accesses 1156system.cpu.l2cache.overall_accesses::cpu.data 1658745 # number of overall (read+write) accesses 1157system.cpu.l2cache.overall_accesses::total 2741510 # number of overall (read+write) accesses 1158system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses 1159system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000470 # miss rate for ReadReq accesses 1160system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016346 # miss rate for ReadReq accesses 1161system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026130 # miss rate for ReadReq accesses 1162system.cpu.l2cache.ReadReq_miss_rate::total 0.021294 # miss rate for ReadReq accesses 1163system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.829564 # miss rate for UpgradeReq accesses 1164system.cpu.l2cache.UpgradeReq_miss_rate::total 0.829564 # miss rate for UpgradeReq accesses 1165system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463364 # miss rate for ReadExReq accesses 1166system.cpu.l2cache.ReadExReq_miss_rate::total 0.463364 # miss rate for ReadExReq accesses 1167system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses 1168system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000470 # miss rate for demand accesses 1169system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016346 # miss rate for demand accesses 1170system.cpu.l2cache.demand_miss_rate::cpu.data 0.101975 # miss rate for demand accesses 1171system.cpu.l2cache.demand_miss_rate::total 0.067692 # miss rate for demand accesses 1172system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses 1173system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000470 # miss rate for overall accesses 1174system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016346 # miss rate for overall accesses 1175system.cpu.l2cache.overall_miss_rate::cpu.data 0.101975 # miss rate for overall accesses 1176system.cpu.l2cache.overall_miss_rate::total 0.067692 # miss rate for overall accesses 1177system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85544.354839 # average ReadReq miss latency 1178system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77916.666667 # average ReadReq miss latency 1179system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76460.373495 # average ReadReq miss latency 1180system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79005.289638 # average ReadReq miss latency 1181system.cpu.l2cache.ReadReq_avg_miss_latency::total 78216.148897 # average ReadReq miss latency 1182system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11779.784574 # average UpgradeReq miss latency 1183system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11779.784574 # average UpgradeReq miss latency 1184system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69682.710269 # average ReadExReq miss latency 1185system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69682.710269 # average ReadExReq miss latency 1186system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency 1187system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency 1188system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency 1189system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency 1190system.cpu.l2cache.demand_avg_miss_latency::total 72085.369537 # average overall miss latency 1191system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency 1192system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency 1193system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency 1194system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency 1195system.cpu.l2cache.overall_avg_miss_latency::total 72085.369537 # average overall miss latency 1196system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1197system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1198system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1199system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1200system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1201system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1202system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1203system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1204system.cpu.l2cache.writebacks::writebacks 102890 # number of writebacks 1205system.cpu.l2cache.writebacks::total 102890 # number of writebacks 1206system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 1207system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits 1208system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 1209system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1210system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits 1211system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1212system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1213system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits 1214system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1215system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 62 # number of ReadReq MSHR misses 1216system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1217system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16356 # number of ReadReq MSHR misses 1218system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35821 # number of ReadReq MSHR misses 1219system.cpu.l2cache.ReadReq_mshr_misses::total 52245 # number of ReadReq MSHR misses 1220system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1504 # number of UpgradeReq MSHR misses 1221system.cpu.l2cache.UpgradeReq_mshr_misses::total 1504 # number of UpgradeReq MSHR misses 1222system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133327 # number of ReadExReq MSHR misses 1223system.cpu.l2cache.ReadExReq_mshr_misses::total 133327 # number of ReadExReq MSHR misses 1224system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses 1225system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1226system.cpu.l2cache.demand_mshr_misses::cpu.inst 16356 # number of demand (read+write) MSHR misses 1227system.cpu.l2cache.demand_mshr_misses::cpu.data 169148 # number of demand (read+write) MSHR misses 1228system.cpu.l2cache.demand_mshr_misses::total 185572 # number of demand (read+write) MSHR misses 1229system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses 1230system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1231system.cpu.l2cache.overall_mshr_misses::cpu.inst 16356 # number of overall MSHR misses 1232system.cpu.l2cache.overall_mshr_misses::cpu.data 169148 # number of overall MSHR misses 1233system.cpu.l2cache.overall_mshr_misses::total 185572 # number of overall MSHR misses 1234system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4538750 # number of ReadReq MSHR miss cycles 1235system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles 1236system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1045537500 # number of ReadReq MSHR miss cycles 1237system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2387984748 # number of ReadReq MSHR miss cycles 1238system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3438452498 # number of ReadReq MSHR miss cycles 1239system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15960982 # number of UpgradeReq MSHR miss cycles 1240system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15960982 # number of UpgradeReq MSHR miss cycles 1241system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7616458286 # number of ReadExReq MSHR miss cycles 1242system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7616458286 # number of ReadExReq MSHR miss cycles 1243system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4538750 # number of demand (read+write) MSHR miss cycles 1244system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles 1245system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1045537500 # number of demand (read+write) MSHR miss cycles 1246system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10004443034 # number of demand (read+write) MSHR miss cycles 1247system.cpu.l2cache.demand_mshr_miss_latency::total 11054910784 # number of demand (read+write) MSHR miss cycles 1248system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4538750 # number of overall MSHR miss cycles 1249system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles 1250system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1045537500 # number of overall MSHR miss cycles 1251system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10004443034 # number of overall MSHR miss cycles 1252system.cpu.l2cache.overall_mshr_miss_latency::total 11054910784 # number of overall MSHR miss cycles 1253system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89282348000 # number of ReadReq MSHR uncacheable cycles 1254system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89282348000 # number of ReadReq MSHR uncacheable cycles 1255system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2403570000 # number of WriteReq MSHR uncacheable cycles 1256system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2403570000 # number of WriteReq MSHR uncacheable cycles 1257system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91685918000 # number of overall MSHR uncacheable cycles 1258system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91685918000 # number of overall MSHR uncacheable cycles 1259system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1260system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for ReadReq accesses 1261system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for ReadReq accesses 1262system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026127 # mshr miss rate for ReadReq accesses 1263system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021292 # mshr miss rate for ReadReq accesses 1264system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829564 # mshr miss rate for UpgradeReq accesses 1265system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829564 # mshr miss rate for UpgradeReq accesses 1266system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463364 # mshr miss rate for ReadExReq accesses 1267system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463364 # mshr miss rate for ReadExReq accesses 1268system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses 1269system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for demand accesses 1270system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for demand accesses 1271system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for demand accesses 1272system.cpu.l2cache.demand_mshr_miss_rate::total 0.067690 # mshr miss rate for demand accesses 1273system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses 1274system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for overall accesses 1275system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for overall accesses 1276system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for overall accesses 1277system.cpu.l2cache.overall_mshr_miss_rate::total 0.067690 # mshr miss rate for overall accesses 1278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average ReadReq mshr miss latency 1279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency 1280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435 # average ReadReq mshr miss latency 1281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777 # average ReadReq mshr miss latency 1282system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302 # average ReadReq mshr miss latency 1283system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053 # average UpgradeReq mshr miss latency 1284system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053 # average UpgradeReq mshr miss latency 1285system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637 # average ReadExReq mshr miss latency 1286system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637 # average ReadExReq mshr miss latency 1287system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency 1288system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1289system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency 1290system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency 1291system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency 1292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency 1293system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1294system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency 1295system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency 1296system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency 1297system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1298system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1299system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1300system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1301system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1302system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1303system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1304system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution 1305system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution 1306system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution 1307system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution 1308system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution 1309system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1310system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution 1311system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution 1312system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution 1313system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution 1314system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution 1315system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes) 1316system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes) 1317system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes) 1318system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes) 1319system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes) 1320system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu.toL2Bus.pkt_size::total 278739955 # Cumulative packet size per connected master and slave (bytes) 1325system.cpu.toL2Bus.snoops 59032 # Total snoops (count) 1326system.cpu.toL2Bus.snoop_fanout::samples 4387424 # Request fanout histogram 1327system.cpu.toL2Bus.snoop_fanout::mean 3.010858 # Request fanout histogram 1328system.cpu.toL2Bus.snoop_fanout::stdev 0.103635 # Request fanout histogram 1329system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1330system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1331system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1332system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1333system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram 1334system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram 1335system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1336system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1337system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1338system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram 1339system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks) 1340system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1341system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) 1342system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1343system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks) 1344system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1345system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks) 1346system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1347system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks) 1348system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1349system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks) 1350system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1351system.iobus.trans_dist::ReadReq 225722 # Transaction distribution 1352system.iobus.trans_dist::ReadResp 225722 # Transaction distribution 1353system.iobus.trans_dist::WriteReq 57753 # Transaction distribution 1354system.iobus.trans_dist::WriteResp 11033 # Transaction distribution 1355system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1356system.iobus.trans_dist::MessageReq 1643 # Transaction distribution 1357system.iobus.trans_dist::MessageResp 1643 # Transaction distribution 1358system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1359system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1360system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 1361system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1362system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1363system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1364system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1365system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1366system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 1367system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1368system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1369system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1370system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1371system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1372system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1373system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1374system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1375system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1376system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes) 1377system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) 1379system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) 1381system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1383system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1384system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 1385system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1386system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1387system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1388system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1389system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1390system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 1391system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1392system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1393system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1394system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1395system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1396system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1397system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1398system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1399system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1400system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) 1403system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) 1405system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) 1407system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1408system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1409system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1410system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1411system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1412system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 1413system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1414system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1415system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1416system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1417system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1418system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1419system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1420system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1421system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1422system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1423system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1424system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 1425system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1426system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1427system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1428system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1429system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1430system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1431system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1432system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) 1433system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1434system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1435system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1436system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1437system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1438system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1439system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1440system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1441system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1442system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks) 1443system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1444system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1445system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1446system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks) 1447system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1448system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks) 1449system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1450system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) 1451system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1452system.iocache.tags.replacements 47584 # number of replacements 1453system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use 1454system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1455system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. 1456system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1457system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit. 1458system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor 1459system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy 1460system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy 1461system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1462system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1463system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1464system.iocache.tags.tag_accesses 428751 # Number of tag accesses 1465system.iocache.tags.data_accesses 428751 # Number of data accesses 1466system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses 1467system.iocache.ReadReq_misses::total 919 # number of ReadReq misses 1468system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1469system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses 1470system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses 1471system.iocache.demand_misses::total 919 # number of demand (read+write) misses 1472system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses 1473system.iocache.overall_misses::total 919 # number of overall misses 1474system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles 1475system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles 1476system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles 1477system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles 1478system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles 1479system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles 1480system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles 1481system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles 1482system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) 1483system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) 1484system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1485system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 1486system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses 1487system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses 1488system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses 1489system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses 1490system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1491system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1492system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1493system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1494system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1495system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1496system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1497system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1498system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency 1499system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency 1500system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency 1501system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency 1502system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency 1503system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency 1504system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency 1505system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency 1506system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked 1507system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1508system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked 1509system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1510system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked 1511system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1512system.iocache.fast_writes 0 # number of fast writes performed 1513system.iocache.cache_copies 0 # number of cache copies performed 1514system.iocache.writebacks::writebacks 46667 # number of writebacks 1515system.iocache.writebacks::total 46667 # number of writebacks 1516system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses 1517system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses 1518system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1519system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses 1520system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses 1521system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses 1522system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses 1523system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses 1524system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles 1525system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles 1526system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles 1527system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles 1528system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles 1529system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles 1530system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles 1531system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles 1532system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1533system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1534system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1535system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1536system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1537system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1538system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1539system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1540system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency 1541system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency 1542system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency 1543system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency 1544system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency 1545system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency 1546system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency 1547system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency 1548system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1549system.membus.trans_dist::ReadReq 662612 # Transaction distribution 1550system.membus.trans_dist::ReadResp 662585 # Transaction distribution 1551system.membus.trans_dist::WriteReq 13919 # Transaction distribution 1552system.membus.trans_dist::WriteResp 13919 # Transaction distribution 1553system.membus.trans_dist::Writeback 149557 # Transaction distribution 1554system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1555system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1556system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution 1557system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution 1558system.membus.trans_dist::ReadExReq 133043 # Transaction distribution 1559system.membus.trans_dist::ReadExResp 133041 # Transaction distribution 1560system.membus.trans_dist::MessageReq 1643 # Transaction distribution 1561system.membus.trans_dist::MessageResp 1643 # Transaction distribution 1562system.membus.trans_dist::BadAddressError 27 # Transaction distribution 1563system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) 1564system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes) 1566system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes) 1569system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes) 1570system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes) 1571system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes) 1572system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes) 1573system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) 1575system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes) 1576system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes) 1577system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes) 1578system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) 1581system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes) 1582system.membus.snoops 1603 # Total snoops (count) 1583system.membus.snoop_fanout::samples 384714 # Request fanout histogram 1584system.membus.snoop_fanout::mean 1 # Request fanout histogram 1585system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1586system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1587system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1588system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram 1589system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1590system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1591system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1592system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1593system.membus.snoop_fanout::total 384714 # Request fanout histogram 1594system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks) 1595system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1596system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks) 1597system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1598system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) 1599system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1600system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks) 1601system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1602system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks) 1603system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1604system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) 1605system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1606system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks) 1607system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1608system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks) 1609system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1610system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1611system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1612system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1613system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1614system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1615system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1616system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1617system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1618system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1619system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1620system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1621system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1622system.cpu.kern.inst.arm 0 # number of arm instructions executed 1623system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1624 1625---------- End Simulation Statistics ---------- 1626