stats.txt revision 10433:821cbe4a183b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.129877 # Number of seconds simulated 4sim_ticks 5129876981500 # Number of ticks simulated 5final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 181923 # Simulator instruction rate (inst/s) 8host_op_rate 359604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2288414721 # Simulator tick rate (ticks/s) 10host_mem_usage 752624 # Number of bytes of host memory used 11host_seconds 2241.67 # Real time elapsed on the host 12sim_insts 407812863 # Number of instructions simulated 13sim_ops 806114915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory 36system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 186153 # Number of read requests accepted 55system.physmem.writeReqs 149802 # Number of write requests accepted 56system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11465 # Per bank write bursts 67system.physmem.perBankRdBursts::1 11004 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11873 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11540 # Per bank write bursts 70system.physmem.perBankRdBursts::4 11961 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11322 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11640 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11420 # Per bank write bursts 74system.physmem.perBankRdBursts::8 11351 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11861 # Per bank write bursts 76system.physmem.perBankRdBursts::10 11826 # Per bank write bursts 77system.physmem.perBankRdBursts::11 12031 # Per bank write bursts 78system.physmem.perBankRdBursts::12 11538 # Per bank write bursts 79system.physmem.perBankRdBursts::13 12375 # Per bank write bursts 80system.physmem.perBankRdBursts::14 11569 # Per bank write bursts 81system.physmem.perBankRdBursts::15 11089 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10234 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9627 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9640 # Per bank write bursts 85system.physmem.perBankWrBursts::3 9149 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9237 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9047 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8744 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8727 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9070 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9221 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9815 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9405 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9499 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9604 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9640 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9124 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 100system.physmem.totGap 5129876930000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 186153 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 149802 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads 265system.physmem.totQLat 2030519500 # Total ticks spent queuing 266system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing 281system.physmem.readRowHits 152396 # Number of row buffer hits during reads 282system.physmem.writeRowHits 110551 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes 285system.physmem.avgGap 15269535.89 # Average gap between requests 286system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states 288system.physmem.memoryStateTime::REF 171297620000 # Time in different power states 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 290system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 292system.physmem.actEnergy::0 267480360 # Energy for activate commands per rank (pJ) 293system.physmem.actEnergy::1 282131640 # Energy for activate commands per rank (pJ) 294system.physmem.preEnergy::0 145946625 # Energy for precharge commands per rank (pJ) 295system.physmem.preEnergy::1 153940875 # Energy for precharge commands per rank (pJ) 296system.physmem.readEnergy::0 719347200 # Energy for read commands per rank (pJ) 297system.physmem.readEnergy::1 730392000 # Energy for read commands per rank (pJ) 298system.physmem.writeEnergy::0 482144400 # Energy for write commands per rank (pJ) 299system.physmem.writeEnergy::1 488449440 # Energy for write commands per rank (pJ) 300system.physmem.refreshEnergy::0 335058144720 # Energy for refresh commands per rank (pJ) 301system.physmem.refreshEnergy::1 335058144720 # Energy for refresh commands per rank (pJ) 302system.physmem.actBackEnergy::0 129492550125 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 129753331110 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2964331954500 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2964103199250 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3430497567930 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3430569589035 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.729942 # Core power per rank (mW) 309system.physmem.averagePower::1 668.743982 # Core power per rank (mW) 310system.membus.trans_dist::ReadReq 662528 # Transaction distribution 311system.membus.trans_dist::ReadResp 662520 # Transaction distribution 312system.membus.trans_dist::WriteReq 13776 # Transaction distribution 313system.membus.trans_dist::WriteResp 13776 # Transaction distribution 314system.membus.trans_dist::Writeback 103082 # Transaction distribution 315system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 316system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 317system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution 318system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution 319system.membus.trans_dist::ReadExReq 133413 # Transaction distribution 320system.membus.trans_dist::ReadExResp 133410 # Transaction distribution 321system.membus.trans_dist::MessageReq 1645 # Transaction distribution 322system.membus.trans_dist::MessageResp 1645 # Transaction distribution 323system.membus.trans_dist::BadAddressError 8 # Transaction distribution 324system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes) 334system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) 338system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes) 339system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes) 340system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 341system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 342system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes) 343system.membus.snoops 943 # Total snoops (count) 344system.membus.snoop_fanout::samples 338647 # Request fanout histogram 345system.membus.snoop_fanout::mean 1 # Request fanout histogram 346system.membus.snoop_fanout::stdev 0 # Request fanout histogram 347system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 348system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 349system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram 350system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 351system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 352system.membus.snoop_fanout::min_value 1 # Request fanout histogram 353system.membus.snoop_fanout::max_value 1 # Request fanout histogram 354system.membus.snoop_fanout::total 338647 # Request fanout histogram 355system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks) 356system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 357system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks) 358system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 359system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) 360system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 361system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks) 362system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 363system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 364system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 365system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) 366system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 367system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks) 368system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 369system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks) 370system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 371system.iocache.tags.replacements 47584 # number of replacements 372system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use 373system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 374system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. 375system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 376system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit. 377system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor 378system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy 379system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy 380system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 381system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 382system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 383system.iocache.tags.tag_accesses 428751 # Number of tag accesses 384system.iocache.tags.data_accesses 428751 # Number of data accesses 385system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 386system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 387system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses 388system.iocache.ReadReq_misses::total 919 # number of ReadReq misses 389system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses 390system.iocache.demand_misses::total 919 # number of demand (read+write) misses 391system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses 392system.iocache.overall_misses::total 919 # number of overall misses 393system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles 394system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles 395system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles 396system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles 397system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles 398system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles 399system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) 400system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) 401system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 402system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 403system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses 404system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses 405system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses 406system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses 407system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 409system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 410system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 411system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 412system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 413system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency 414system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency 415system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency 416system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency 417system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency 418system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency 419system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 420system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 422system.iocache.blocked::no_targets 0 # number of cycles access was blocked 423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.iocache.fast_writes 46720 # number of fast writes performed 426system.iocache.cache_copies 0 # number of cache copies performed 427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses 428system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses 429system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 430system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses 431system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses 432system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses 433system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses 434system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses 435system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles 436system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles 437system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles 438system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles 439system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles 440system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles 441system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles 442system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles 443system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 444system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 445system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 446system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 447system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 448system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 449system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 450system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 451system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency 452system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency 453system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency 454system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency 455system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency 456system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency 457system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency 458system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency 459system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 461system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 462system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 463system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 464system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 465system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 466system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 467system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 468system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 469system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 470system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 471system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 472system.iobus.trans_dist::ReadReq 225575 # Transaction distribution 473system.iobus.trans_dist::ReadResp 225575 # Transaction distribution 474system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 475system.iobus.trans_dist::WriteResp 57606 # Transaction distribution 476system.iobus.trans_dist::MessageReq 1645 # Transaction distribution 477system.iobus.trans_dist::MessageResp 1645 # Transaction distribution 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 492system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 495system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) 498system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) 499system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) 500system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) 501system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 510system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 511system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 513system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 514system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 516system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 519system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) 522system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) 523system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) 524system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) 525system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes) 526system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks) 527system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 528system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 529system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 530system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 531system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 532system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 533system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 534system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 535system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 537system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 539system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 540system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 541system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 543system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 544system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 545system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 546system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 547system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 548system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 549system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 550system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 551system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 552system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) 553system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 554system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 555system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 556system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 557system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 558system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 559system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 561system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 562system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks) 563system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 564system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 565system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 566system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) 567system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 568system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks) 569system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 570system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) 571system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 572system.cpu_clk_domain.clock 500 # Clock period in ticks 573system.cpu.branchPred.lookups 86898883 # Number of BP lookups 574system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted 575system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect 576system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups 577system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits 578system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 579system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage 580system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target. 581system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions. 582system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 583system.cpu.numCycles 449490093 # number of cpu cycles simulated 584system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 585system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 586system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss 587system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed 588system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered 589system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken 590system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked 591system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing 592system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb 593system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 594system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps 595system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions 596system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR 597system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched 598system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed 599system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed 600system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total) 606system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total) 607system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total) 608system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total) 609system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total) 610system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total) 611system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total) 612system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total) 613system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 614system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 615system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 616system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total) 617system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle 618system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle 619system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle 620system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked 621system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running 622system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking 623system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing 624system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode 625system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing 626system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle 627system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking 628system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst 629system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running 630system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking 631system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename 632system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full 633system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full 634system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full 635system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full 636system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed 637system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made 638system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups 639system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups 640system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed 641system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing 642system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed 643system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed 644system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer 645system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit. 646system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit. 647system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads. 648system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores. 649system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec) 650system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ 651system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued 652system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued 653system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling 654system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph 655system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed 656system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle 666system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle 667system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle 668system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle 669system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 670system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 671system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 672system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle 673system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 674system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available 675system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available 676system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available 677system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available 678system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available 679system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available 680system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available 681system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available 682system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available 693system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available 694system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available 696system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available 697system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available 698system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available 699system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available 700system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available 701system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available 702system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available 703system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available 704system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available 705system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 706system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 707system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued 708system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued 709system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued 710system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued 711system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 712system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 713system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued 714system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 715system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 716system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued 727system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued 728system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 730system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 731system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 732system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 733system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 734system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 735system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 736system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued 737system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued 738system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued 739system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 740system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 741system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued 742system.cpu.iq.rate 1.833363 # Inst issue rate 743system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested 744system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst) 745system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads 746system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes 747system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses 748system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads 749system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes 750system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses 751system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses 752system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 753system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores 754system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 755system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed 756system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed 757system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations 758system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed 759system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 760system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 761system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled 762system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked 763system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 764system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing 765system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking 766system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking 767system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ 768system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch 769system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions 770system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions 771system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions 772system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall 773system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall 774system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations 775system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly 776system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly 777system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute 778system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions 779system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed 780system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute 781system.cpu.iew.exec_swp 0 # number of swp insts executed 782system.cpu.iew.exec_nop 0 # number of nop insts executed 783system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed 784system.cpu.iew.exec_branches 83289157 # Number of branches executed 785system.cpu.iew.exec_stores 9174614 # Number of stores executed 786system.cpu.iew.exec_rate 1.829760 # Inst execution rate 787system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit 788system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back 789system.cpu.iew.wb_producers 640910074 # num instructions producing a value 790system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value 791system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 792system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle 793system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back 794system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 795system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit 796system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards 797system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted 798system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle 803system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle 806system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle 807system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle 808system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle 809system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle 810system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle 811system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 812system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 813system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 814system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle 815system.cpu.commit.committedInsts 407812863 # Number of instructions committed 816system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed 817system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 818system.cpu.commit.refs 22429266 # Number of memory references committed 819system.cpu.commit.loads 14000019 # Number of loads committed 820system.cpu.commit.membars 474889 # Number of memory barriers committed 821system.cpu.commit.branches 82168190 # Number of branches committed 822system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 823system.cpu.commit.int_insts 734958550 # Number of committed integer instructions. 824system.cpu.commit.function_calls 1155635 # Number of function calls committed. 825system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction 826system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction 827system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction 828system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction 829system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 830system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 831system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 832system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 833system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 834system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 843system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 844system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 846system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 847system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 848system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 849system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 850system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 851system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 852system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 853system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 854system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 855system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction 856system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction 857system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 858system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 859system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction 860system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached 861system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 862system.cpu.rob.rob_reads 1268217156 # The number of ROB reads 863system.cpu.rob.rob_writes 1664635865 # The number of ROB writes 864system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself 865system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling 866system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 867system.cpu.committedInsts 407812863 # Number of Instructions Simulated 868system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated 869system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction 870system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads 871system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle 872system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads 873system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads 874system.cpu.int_regfile_writes 655932610 # number of integer regfile writes 875system.cpu.fp_regfile_reads 56 # number of floating regfile reads 876system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads 877system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes 878system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads 879system.cpu.misc_regfile_writes 402863 # number of misc regfile writes 880system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 891system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes) 895system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes) 896system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes) 897system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes) 898system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes) 899system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes) 901system.cpu.toL2Bus.snoops 61506 # Total snoops (count) 902system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram 915system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks) 916system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 917system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks) 918system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 919system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks) 920system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 923system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks) 924system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 925system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks) 926system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 927system.cpu.icache.tags.replacements 1003070 # number of replacements 928system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use 929system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks. 930system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks. 931system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks. 932system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit. 933system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor 934system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy 935system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy 936system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 937system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 938system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id 939system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 940system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 941system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses 942system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses 943system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits 944system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits 945system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits 946system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits 947system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits 948system.cpu.icache.overall_hits::total 8117984 # number of overall hits 949system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses 950system.cpu.icache.ReadReq_misses::total 1066696 # number of ReadReq misses 951system.cpu.icache.demand_misses::cpu.inst 1066696 # number of demand (read+write) misses 952system.cpu.icache.demand_misses::total 1066696 # number of demand (read+write) misses 953system.cpu.icache.overall_misses::cpu.inst 1066696 # number of overall misses 954system.cpu.icache.overall_misses::total 1066696 # number of overall misses 955system.cpu.icache.ReadReq_miss_latency::cpu.inst 14789893561 # number of ReadReq miss cycles 956system.cpu.icache.ReadReq_miss_latency::total 14789893561 # number of ReadReq miss cycles 957system.cpu.icache.demand_miss_latency::cpu.inst 14789893561 # number of demand (read+write) miss cycles 958system.cpu.icache.demand_miss_latency::total 14789893561 # number of demand (read+write) miss cycles 959system.cpu.icache.overall_miss_latency::cpu.inst 14789893561 # number of overall miss cycles 960system.cpu.icache.overall_miss_latency::total 14789893561 # number of overall miss cycles 961system.cpu.icache.ReadReq_accesses::cpu.inst 9184680 # number of ReadReq accesses(hits+misses) 962system.cpu.icache.ReadReq_accesses::total 9184680 # number of ReadReq accesses(hits+misses) 963system.cpu.icache.demand_accesses::cpu.inst 9184680 # number of demand (read+write) accesses 964system.cpu.icache.demand_accesses::total 9184680 # number of demand (read+write) accesses 965system.cpu.icache.overall_accesses::cpu.inst 9184680 # number of overall (read+write) accesses 966system.cpu.icache.overall_accesses::total 9184680 # number of overall (read+write) accesses 967system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses 968system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses 969system.cpu.icache.demand_miss_rate::cpu.inst 0.116139 # miss rate for demand accesses 970system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses 971system.cpu.icache.overall_miss_rate::cpu.inst 0.116139 # miss rate for overall accesses 972system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses 973system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency 974system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency 975system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency 976system.cpu.icache.demand_avg_miss_latency::total 13865.143922 # average overall miss latency 977system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency 978system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency 979system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked 980system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 981system.cpu.icache.blocked::no_mshrs 266 # number of cycles access was blocked 982system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 983system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked 984system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 985system.cpu.icache.fast_writes 0 # number of fast writes performed 986system.cpu.icache.cache_copies 0 # number of cache copies performed 987system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits 988system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits 989system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits 990system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits 991system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits 992system.cpu.icache.overall_mshr_hits::total 63068 # number of overall MSHR hits 993system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1003628 # number of ReadReq MSHR misses 994system.cpu.icache.ReadReq_mshr_misses::total 1003628 # number of ReadReq MSHR misses 995system.cpu.icache.demand_mshr_misses::cpu.inst 1003628 # number of demand (read+write) MSHR misses 996system.cpu.icache.demand_mshr_misses::total 1003628 # number of demand (read+write) MSHR misses 997system.cpu.icache.overall_mshr_misses::cpu.inst 1003628 # number of overall MSHR misses 998system.cpu.icache.overall_mshr_misses::total 1003628 # number of overall MSHR misses 999system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143729999 # number of ReadReq MSHR miss cycles 1000system.cpu.icache.ReadReq_mshr_miss_latency::total 12143729999 # number of ReadReq MSHR miss cycles 1001system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143729999 # number of demand (read+write) MSHR miss cycles 1002system.cpu.icache.demand_mshr_miss_latency::total 12143729999 # number of demand (read+write) MSHR miss cycles 1003system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles 1004system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles 1005system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses 1006system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses 1007system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses 1008system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses 1009system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses 1010system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses 1011system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency 1012system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency 1013system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency 1014system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency 1015system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency 1016system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency 1017system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1018system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements 1019system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use 1020system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks. 1021system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks. 1022system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks. 1023system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit. 1024system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor 1025system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy 1026system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy 1027system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 1028system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1029system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 1030system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 1031system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 1032system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses 1033system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses 1034system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits 1035system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits 1036system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1037system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 1038system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits 1039system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits 1040system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits 1041system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits 1042system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses 1043system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses 1044system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses 1045system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses 1046system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses 1047system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses 1048system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles 1049system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles 1050system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles 1051system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles 1052system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles 1053system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles 1054system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses) 1055system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses) 1056system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1057system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 1058system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses 1059system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses 1060system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses 1061system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses 1062system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses 1063system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses 1064system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses 1065system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses 1066system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses 1067system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses 1068system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency 1069system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency 1070system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency 1071system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency 1072system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency 1073system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency 1074system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1075system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1076system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1077system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1078system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1079system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1080system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1081system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1082system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks 1083system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks 1084system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses 1085system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses 1086system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses 1087system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses 1088system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses 1089system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses 1090system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles 1091system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles 1092system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles 1093system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles 1094system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles 1095system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles 1096system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses 1097system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses 1098system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses 1099system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses 1100system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses 1101system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses 1102system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency 1103system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency 1104system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency 1105system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency 1106system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency 1107system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency 1108system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1109system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements 1110system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use 1111system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks. 1112system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks. 1113system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks. 1114system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit. 1115system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor 1116system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy 1117system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy 1118system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 1119system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1120system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1121system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 1122system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1123system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses 1124system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses 1125system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits 1126system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits 1127system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits 1128system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits 1129system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits 1130system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits 1131system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses 1132system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses 1133system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses 1134system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses 1135system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses 1136system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses 1137system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles 1138system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles 1139system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles 1140system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles 1141system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles 1142system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles 1143system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses) 1144system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses) 1145system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses 1146system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses 1147system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses 1148system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses 1149system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses 1150system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses 1151system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses 1152system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses 1153system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses 1154system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses 1155system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency 1156system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency 1157system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency 1158system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency 1159system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency 1160system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency 1161system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1162system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1163system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1164system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1165system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1166system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1167system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1168system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 1169system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks 1170system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks 1171system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses 1172system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses 1173system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses 1174system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses 1175system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses 1176system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses 1177system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles 1178system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles 1179system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles 1180system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles 1181system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles 1182system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles 1183system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses 1184system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses 1185system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses 1186system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses 1187system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses 1188system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses 1189system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency 1190system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency 1191system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency 1192system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency 1193system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency 1194system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency 1195system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1196system.cpu.dcache.tags.replacements 1661725 # number of replacements 1197system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use 1198system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks. 1199system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks. 1200system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks. 1201system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 1202system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor 1203system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 1204system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy 1205system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1206system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 1207system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 1208system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 1209system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1210system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses 1211system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses 1212system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits 1213system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits 1214system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits 1215system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits 1216system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits 1217system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits 1218system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits 1219system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits 1220system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits 1221system.cpu.dcache.overall_hits::total 19136904 # number of overall hits 1222system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses 1223system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses 1224system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses 1225system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses 1226system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses 1227system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses 1228system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses 1229system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses 1230system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses 1231system.cpu.dcache.overall_misses::total 2541858 # number of overall misses 1232system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles 1233system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles 1234system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles 1235system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles 1236system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles 1237system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles 1238system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles 1239system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles 1240system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses) 1241system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses) 1242system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses) 1243system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses) 1244system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses) 1245system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses) 1246system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses 1247system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses 1248system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses 1249system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses 1250system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses 1251system.cpu.dcache.ReadReq_miss_rate::total 0.140856 # miss rate for ReadReq accesses 1252system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039678 # miss rate for WriteReq accesses 1253system.cpu.dcache.WriteReq_miss_rate::total 0.039678 # miss rate for WriteReq accesses 1254system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.861736 # miss rate for SoftPFReq accesses 1255system.cpu.dcache.SoftPFReq_miss_rate::total 0.861736 # miss rate for SoftPFReq accesses 1256system.cpu.dcache.demand_miss_rate::cpu.data 0.100686 # miss rate for demand accesses 1257system.cpu.dcache.demand_miss_rate::total 0.100686 # miss rate for demand accesses 1258system.cpu.dcache.overall_miss_rate::cpu.data 0.117251 # miss rate for overall accesses 1259system.cpu.dcache.overall_miss_rate::total 0.117251 # miss rate for overall accesses 1260system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067 # average ReadReq miss latency 1261system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067 # average ReadReq miss latency 1262system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633 # average WriteReq miss latency 1263system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633 # average WriteReq miss latency 1264system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500 # average overall miss latency 1265system.cpu.dcache.demand_avg_miss_latency::total 18469.794500 # average overall miss latency 1266system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118 # average overall miss latency 1267system.cpu.dcache.overall_avg_miss_latency::total 15515.167118 # average overall miss latency 1268system.cpu.dcache.blocked_cycles::no_mshrs 377678 # number of cycles access was blocked 1269system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1270system.cpu.dcache.blocked::no_mshrs 40377 # number of cycles access was blocked 1271system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1272system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked 1273system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1274system.cpu.dcache.fast_writes 0 # number of fast writes performed 1275system.cpu.dcache.cache_copies 0 # number of cache copies performed 1276system.cpu.dcache.writebacks::writebacks 1562629 # number of writebacks 1277system.cpu.dcache.writebacks::total 1562629 # number of writebacks 1278system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829779 # number of ReadReq MSHR hits 1279system.cpu.dcache.ReadReq_mshr_hits::total 829779 # number of ReadReq MSHR hits 1280system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44137 # number of WriteReq MSHR hits 1281system.cpu.dcache.WriteReq_mshr_hits::total 44137 # number of WriteReq MSHR hits 1282system.cpu.dcache.demand_mshr_hits::cpu.data 873916 # number of demand (read+write) MSHR hits 1283system.cpu.dcache.demand_mshr_hits::total 873916 # number of demand (read+write) MSHR hits 1284system.cpu.dcache.overall_mshr_hits::cpu.data 873916 # number of overall MSHR hits 1285system.cpu.dcache.overall_mshr_hits::total 873916 # number of overall MSHR hits 1286system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971383 # number of ReadReq MSHR misses 1287system.cpu.dcache.ReadReq_mshr_misses::total 971383 # number of ReadReq MSHR misses 1288system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289936 # number of WriteReq MSHR misses 1289system.cpu.dcache.WriteReq_mshr_misses::total 289936 # number of WriteReq MSHR misses 1290system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403164 # number of SoftPFReq MSHR misses 1291system.cpu.dcache.SoftPFReq_mshr_misses::total 403164 # number of SoftPFReq MSHR misses 1292system.cpu.dcache.demand_mshr_misses::cpu.data 1261319 # number of demand (read+write) MSHR misses 1293system.cpu.dcache.demand_mshr_misses::total 1261319 # number of demand (read+write) MSHR misses 1294system.cpu.dcache.overall_mshr_misses::cpu.data 1664483 # number of overall MSHR misses 1295system.cpu.dcache.overall_mshr_misses::total 1664483 # number of overall MSHR misses 1296system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264764518 # number of ReadReq MSHR miss cycles 1297system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264764518 # number of ReadReq MSHR miss cycles 1298system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11214941849 # number of WriteReq MSHR miss cycles 1299system.cpu.dcache.WriteReq_mshr_miss_latency::total 11214941849 # number of WriteReq MSHR miss cycles 1300system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5603688502 # number of SoftPFReq MSHR miss cycles 1301system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5603688502 # number of SoftPFReq MSHR miss cycles 1302system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23479706367 # number of demand (read+write) MSHR miss cycles 1303system.cpu.dcache.demand_mshr_miss_latency::total 23479706367 # number of demand (read+write) MSHR miss cycles 1304system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29083394869 # number of overall MSHR miss cycles 1305system.cpu.dcache.overall_mshr_miss_latency::total 29083394869 # number of overall MSHR miss cycles 1306system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364659500 # number of ReadReq MSHR uncacheable cycles 1307system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364659500 # number of ReadReq MSHR uncacheable cycles 1308system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538935000 # number of WriteReq MSHR uncacheable cycles 1309system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538935000 # number of WriteReq MSHR uncacheable cycles 1310system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903594500 # number of overall MSHR uncacheable cycles 1311system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903594500 # number of overall MSHR uncacheable cycles 1312system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075965 # mshr miss rate for ReadReq accesses 1313system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075965 # mshr miss rate for ReadReq accesses 1314system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034435 # mshr miss rate for WriteReq accesses 1315system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034435 # mshr miss rate for WriteReq accesses 1316system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854405 # mshr miss rate for SoftPFReq accesses 1317system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854405 # mshr miss rate for SoftPFReq accesses 1318system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059477 # mshr miss rate for demand accesses 1319system.cpu.dcache.demand_mshr_miss_rate::total 0.059477 # mshr miss rate for demand accesses 1320system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076779 # mshr miss rate for overall accesses 1321system.cpu.dcache.overall_mshr_miss_rate::total 0.076779 # mshr miss rate for overall accesses 1322system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198 # average ReadReq mshr miss latency 1323system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198 # average ReadReq mshr miss latency 1324system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714 # average WriteReq mshr miss latency 1325system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714 # average WriteReq mshr miss latency 1326system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency 1327system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency 1328system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency 1329system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency 1330system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency 1331system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency 1332system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1333system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1334system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1335system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1336system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1337system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1338system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1339system.cpu.l2cache.tags.replacements 112646 # number of replacements 1340system.cpu.l2cache.tags.tagsinuse 64814.554294 # Cycle average of tags in use 1341system.cpu.l2cache.tags.total_refs 3852282 # Total number of references to valid blocks. 1342system.cpu.l2cache.tags.sampled_refs 176740 # Sample count of references to valid blocks. 1343system.cpu.l2cache.tags.avg_refs 21.796322 # Average number of references to valid blocks. 1344system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1345system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor 1346system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor 1347system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor 1348system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor 1349system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor 1350system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy 1351system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy 1352system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1353system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049973 # Average percentage of cache occupancy 1354system.cpu.l2cache.tags.occ_percent::cpu.data 0.170446 # Average percentage of cache occupancy 1355system.cpu.l2cache.tags.occ_percent::total 0.988992 # Average percentage of cache occupancy 1356system.cpu.l2cache.tags.occ_task_id_blocks::1024 64094 # Occupied blocks per task id 1357system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 1358system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id 1359system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3429 # Occupied blocks per task id 1360system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5695 # Occupied blocks per task id 1361system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54337 # Occupied blocks per task id 1362system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977997 # Percentage of cache occupancy per task id 1363system.cpu.l2cache.tags.tag_accesses 35174951 # Number of tag accesses 1364system.cpu.l2cache.tags.data_accesses 35174951 # Number of data accesses 1365system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69400 # number of ReadReq hits 1366system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13641 # number of ReadReq hits 1367system.cpu.l2cache.ReadReq_hits::cpu.inst 987138 # number of ReadReq hits 1368system.cpu.l2cache.ReadReq_hits::cpu.data 1338009 # number of ReadReq hits 1369system.cpu.l2cache.ReadReq_hits::total 2408188 # number of ReadReq hits 1370system.cpu.l2cache.Writeback_hits::writebacks 1587489 # number of Writeback hits 1371system.cpu.l2cache.Writeback_hits::total 1587489 # number of Writeback hits 1372system.cpu.l2cache.UpgradeReq_hits::cpu.data 311 # number of UpgradeReq hits 1373system.cpu.l2cache.UpgradeReq_hits::total 311 # number of UpgradeReq hits 1374system.cpu.l2cache.ReadExReq_hits::cpu.data 154123 # number of ReadExReq hits 1375system.cpu.l2cache.ReadExReq_hits::total 154123 # number of ReadExReq hits 1376system.cpu.l2cache.demand_hits::cpu.dtb.walker 69400 # number of demand (read+write) hits 1377system.cpu.l2cache.demand_hits::cpu.itb.walker 13641 # number of demand (read+write) hits 1378system.cpu.l2cache.demand_hits::cpu.inst 987138 # number of demand (read+write) hits 1379system.cpu.l2cache.demand_hits::cpu.data 1492132 # number of demand (read+write) hits 1380system.cpu.l2cache.demand_hits::total 2562311 # number of demand (read+write) hits 1381system.cpu.l2cache.overall_hits::cpu.dtb.walker 69400 # number of overall hits 1382system.cpu.l2cache.overall_hits::cpu.itb.walker 13641 # number of overall hits 1383system.cpu.l2cache.overall_hits::cpu.inst 987138 # number of overall hits 1384system.cpu.l2cache.overall_hits::cpu.data 1492132 # number of overall hits 1385system.cpu.l2cache.overall_hits::total 2562311 # number of overall hits 1386system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 64 # number of ReadReq misses 1387system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1388system.cpu.l2cache.ReadReq_misses::cpu.inst 16384 # number of ReadReq misses 1389system.cpu.l2cache.ReadReq_misses::cpu.data 35861 # number of ReadReq misses 1390system.cpu.l2cache.ReadReq_misses::total 52315 # number of ReadReq misses 1391system.cpu.l2cache.UpgradeReq_misses::cpu.data 1456 # number of UpgradeReq misses 1392system.cpu.l2cache.UpgradeReq_misses::total 1456 # number of UpgradeReq misses 1393system.cpu.l2cache.ReadExReq_misses::cpu.data 133693 # number of ReadExReq misses 1394system.cpu.l2cache.ReadExReq_misses::total 133693 # number of ReadExReq misses 1395system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses 1396system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1397system.cpu.l2cache.demand_misses::cpu.inst 16384 # number of demand (read+write) misses 1398system.cpu.l2cache.demand_misses::cpu.data 169554 # number of demand (read+write) misses 1399system.cpu.l2cache.demand_misses::total 186008 # number of demand (read+write) misses 1400system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses 1401system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1402system.cpu.l2cache.overall_misses::cpu.inst 16384 # number of overall misses 1403system.cpu.l2cache.overall_misses::cpu.data 169554 # number of overall misses 1404system.cpu.l2cache.overall_misses::total 186008 # number of overall misses 1405system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5398250 # number of ReadReq miss cycles 1406system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467000 # number of ReadReq miss cycles 1407system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1244423000 # number of ReadReq miss cycles 1408system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2844994996 # number of ReadReq miss cycles 1409system.cpu.l2cache.ReadReq_miss_latency::total 4095283246 # number of ReadReq miss cycles 1410system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17419754 # number of UpgradeReq miss cycles 1411system.cpu.l2cache.UpgradeReq_miss_latency::total 17419754 # number of UpgradeReq miss cycles 1412system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9341540216 # number of ReadExReq miss cycles 1413system.cpu.l2cache.ReadExReq_miss_latency::total 9341540216 # number of ReadExReq miss cycles 1414system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5398250 # number of demand (read+write) miss cycles 1415system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467000 # number of demand (read+write) miss cycles 1416system.cpu.l2cache.demand_miss_latency::cpu.inst 1244423000 # number of demand (read+write) miss cycles 1417system.cpu.l2cache.demand_miss_latency::cpu.data 12186535212 # number of demand (read+write) miss cycles 1418system.cpu.l2cache.demand_miss_latency::total 13436823462 # number of demand (read+write) miss cycles 1419system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5398250 # number of overall miss cycles 1420system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467000 # number of overall miss cycles 1421system.cpu.l2cache.overall_miss_latency::cpu.inst 1244423000 # number of overall miss cycles 1422system.cpu.l2cache.overall_miss_latency::cpu.data 12186535212 # number of overall miss cycles 1423system.cpu.l2cache.overall_miss_latency::total 13436823462 # number of overall miss cycles 1424system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69464 # number of ReadReq accesses(hits+misses) 1425system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13647 # number of ReadReq accesses(hits+misses) 1426system.cpu.l2cache.ReadReq_accesses::cpu.inst 1003522 # number of ReadReq accesses(hits+misses) 1427system.cpu.l2cache.ReadReq_accesses::cpu.data 1373870 # number of ReadReq accesses(hits+misses) 1428system.cpu.l2cache.ReadReq_accesses::total 2460503 # number of ReadReq accesses(hits+misses) 1429system.cpu.l2cache.Writeback_accesses::writebacks 1587489 # number of Writeback accesses(hits+misses) 1430system.cpu.l2cache.Writeback_accesses::total 1587489 # number of Writeback accesses(hits+misses) 1431system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1767 # number of UpgradeReq accesses(hits+misses) 1432system.cpu.l2cache.UpgradeReq_accesses::total 1767 # number of UpgradeReq accesses(hits+misses) 1433system.cpu.l2cache.ReadExReq_accesses::cpu.data 287816 # number of ReadExReq accesses(hits+misses) 1434system.cpu.l2cache.ReadExReq_accesses::total 287816 # number of ReadExReq accesses(hits+misses) 1435system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69464 # number of demand (read+write) accesses 1436system.cpu.l2cache.demand_accesses::cpu.itb.walker 13647 # number of demand (read+write) accesses 1437system.cpu.l2cache.demand_accesses::cpu.inst 1003522 # number of demand (read+write) accesses 1438system.cpu.l2cache.demand_accesses::cpu.data 1661686 # number of demand (read+write) accesses 1439system.cpu.l2cache.demand_accesses::total 2748319 # number of demand (read+write) accesses 1440system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69464 # number of overall (read+write) accesses 1441system.cpu.l2cache.overall_accesses::cpu.itb.walker 13647 # number of overall (read+write) accesses 1442system.cpu.l2cache.overall_accesses::cpu.inst 1003522 # number of overall (read+write) accesses 1443system.cpu.l2cache.overall_accesses::cpu.data 1661686 # number of overall (read+write) accesses 1444system.cpu.l2cache.overall_accesses::total 2748319 # number of overall (read+write) accesses 1445system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 1446system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000440 # miss rate for ReadReq accesses 1447system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016326 # miss rate for ReadReq accesses 1448system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026102 # miss rate for ReadReq accesses 1449system.cpu.l2cache.ReadReq_miss_rate::total 0.021262 # miss rate for ReadReq accesses 1450system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823995 # miss rate for UpgradeReq accesses 1451system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823995 # miss rate for UpgradeReq accesses 1452system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464509 # miss rate for ReadExReq accesses 1453system.cpu.l2cache.ReadExReq_miss_rate::total 0.464509 # miss rate for ReadExReq accesses 1454system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 1455system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000440 # miss rate for demand accesses 1456system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016326 # miss rate for demand accesses 1457system.cpu.l2cache.demand_miss_rate::cpu.data 0.102037 # miss rate for demand accesses 1458system.cpu.l2cache.demand_miss_rate::total 0.067681 # miss rate for demand accesses 1459system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 1460system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000440 # miss rate for overall accesses 1461system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016326 # miss rate for overall accesses 1462system.cpu.l2cache.overall_miss_rate::cpu.data 0.102037 # miss rate for overall accesses 1463system.cpu.l2cache.overall_miss_rate::total 0.067681 # miss rate for overall accesses 1464system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84347.656250 # average ReadReq miss latency 1465system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77833.333333 # average ReadReq miss latency 1466system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75953.552246 # average ReadReq miss latency 1467system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79333.955997 # average ReadReq miss latency 1468system.cpu.l2cache.ReadReq_avg_miss_latency::total 78281.243353 # average ReadReq miss latency 1469system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11964.116758 # average UpgradeReq miss latency 1470system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11964.116758 # average UpgradeReq miss latency 1471system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69873.069016 # average ReadExReq miss latency 1472system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69873.069016 # average ReadExReq miss latency 1473system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency 1474system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency 1475system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency 1476system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency 1477system.cpu.l2cache.demand_avg_miss_latency::total 72237.879349 # average overall miss latency 1478system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency 1479system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency 1480system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency 1481system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency 1482system.cpu.l2cache.overall_avg_miss_latency::total 72237.879349 # average overall miss latency 1483system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1484system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1485system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1486system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1487system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1488system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1489system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1490system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1491system.cpu.l2cache.writebacks::writebacks 103082 # number of writebacks 1492system.cpu.l2cache.writebacks::total 103082 # number of writebacks 1493system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 1494system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1495system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 1496system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 1497system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1498system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 1499system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 1500system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1501system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 1502system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 64 # number of ReadReq MSHR misses 1503system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1504system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16378 # number of ReadReq MSHR misses 1505system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35860 # number of ReadReq MSHR misses 1506system.cpu.l2cache.ReadReq_mshr_misses::total 52308 # number of ReadReq MSHR misses 1507system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1456 # number of UpgradeReq MSHR misses 1508system.cpu.l2cache.UpgradeReq_mshr_misses::total 1456 # number of UpgradeReq MSHR misses 1509system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133693 # number of ReadExReq MSHR misses 1510system.cpu.l2cache.ReadExReq_mshr_misses::total 133693 # number of ReadExReq MSHR misses 1511system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses 1512system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1513system.cpu.l2cache.demand_mshr_misses::cpu.inst 16378 # number of demand (read+write) MSHR misses 1514system.cpu.l2cache.demand_mshr_misses::cpu.data 169553 # number of demand (read+write) MSHR misses 1515system.cpu.l2cache.demand_mshr_misses::total 186001 # number of demand (read+write) MSHR misses 1516system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses 1517system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1518system.cpu.l2cache.overall_mshr_misses::cpu.inst 16378 # number of overall MSHR misses 1519system.cpu.l2cache.overall_mshr_misses::cpu.data 169553 # number of overall MSHR misses 1520system.cpu.l2cache.overall_mshr_misses::total 186001 # number of overall MSHR misses 1521system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4610750 # number of ReadReq MSHR miss cycles 1522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles 1523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1038765000 # number of ReadReq MSHR miss cycles 1524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2399725996 # number of ReadReq MSHR miss cycles 1525system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3443493246 # number of ReadReq MSHR miss cycles 1526system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14596954 # number of UpgradeReq MSHR miss cycles 1527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14596954 # number of UpgradeReq MSHR miss cycles 1528system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7662739284 # number of ReadExReq MSHR miss cycles 1529system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7662739284 # number of ReadExReq MSHR miss cycles 1530system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4610750 # number of demand (read+write) MSHR miss cycles 1531system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles 1532system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1038765000 # number of demand (read+write) MSHR miss cycles 1533system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10062465280 # number of demand (read+write) MSHR miss cycles 1534system.cpu.l2cache.demand_mshr_miss_latency::total 11106232530 # number of demand (read+write) MSHR miss cycles 1535system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles 1536system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles 1537system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles 1538system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles 1539system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles 1540system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles 1541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles 1542system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles 1543system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles 1544system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles 1545system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles 1546system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses 1547system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses 1548system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses 1549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses 1550system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses 1551system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses 1552system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses 1553system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses 1554system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses 1555system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses 1556system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses 1557system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses 1558system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses 1559system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses 1560system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses 1561system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses 1562system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses 1563system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses 1564system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses 1565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency 1566system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency 1567system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency 1568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency 1569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency 1570system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency 1571system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency 1572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency 1573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency 1574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency 1575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency 1577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency 1578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency 1579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency 1580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1581system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency 1582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency 1583system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency 1584system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1585system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1587system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1589system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu.kern.inst.arm 0 # number of arm instructions executed 1592system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1593 1594---------- End Simulation Statistics ---------- 1595