18504SN/A 28504SN/A---------- Begin Simulation Statistics ---------- 311441Sandreas.hansson@arm.comsim_seconds 5.230834 # Number of seconds simulated 411441Sandreas.hansson@arm.comsim_ticks 5230834315000 # Number of ticks simulated 511441Sandreas.hansson@arm.comfinal_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68504SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 207627 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 410431 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 2662189440 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 751184 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 1964.86 # Real time elapsed on the host 1211441Sandreas.hansson@arm.comsim_insts 407959263 # Number of instructions simulated 1311441Sandreas.hansson@arm.comsim_ops 806441023 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 1711441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 1811441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory 1911441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory 2010535Sandreas.hansson@arm.comsystem.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 2111441Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11615232 # Number of bytes read from this memory 2211441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory 2311441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory 2411441Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory 2511441Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9293760 # Number of bytes written to this memory 2611441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory 2711441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 2811441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory 2911441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory 3010535Sandreas.hansson@arm.comsystem.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 3111441Sandreas.hansson@arm.comsystem.physmem.num_reads::total 181488 # Number of read requests responded to by this memory 3211441Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory 3311441Sandreas.hansson@arm.comsystem.physmem.num_writes::total 145215 # Number of write requests responded to by this memory 3411441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s) 3511441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s) 3611441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s) 3711441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s) 3811441Sandreas.hansson@arm.comsystem.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s) 3911441Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s) 4011441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s) 4111441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s) 4211441Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s) 4311441Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s) 4411441Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s) 4511441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s) 4611441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s) 4711441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s) 4811441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s) 4911441Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s) 5011441Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s) 5111441Sandreas.hansson@arm.comsystem.physmem.readReqs 181488 # Number of read requests accepted 5211441Sandreas.hansson@arm.comsystem.physmem.writeReqs 145215 # Number of write requests accepted 5311441Sandreas.hansson@arm.comsystem.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue 5411441Sandreas.hansson@arm.comsystem.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue 5511441Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM 5611441Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue 5711441Sandreas.hansson@arm.comsystem.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM 5811441Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side 5911441Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side 6011441Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue 6110892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6211336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6311441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 11156 # Per bank write bursts 6411441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 11363 # Per bank write bursts 6511441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 11879 # Per bank write bursts 6611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 11399 # Per bank write bursts 6711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 11231 # Per bank write bursts 6811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 10765 # Per bank write bursts 6911441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 10426 # Per bank write bursts 7011441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10967 # Per bank write bursts 7111441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 10953 # Per bank write bursts 7211441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 10767 # Per bank write bursts 7311441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 11374 # Per bank write bursts 7411441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 11178 # Per bank write bursts 7511441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 12058 # Per bank write bursts 7611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 12613 # Per bank write bursts 7711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 11821 # Per bank write bursts 7811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 11247 # Per bank write bursts 7911441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 9305 # Per bank write bursts 8011441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 9167 # Per bank write bursts 8111441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 9550 # Per bank write bursts 8211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 8690 # Per bank write bursts 8311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 9047 # Per bank write bursts 8411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 8729 # Per bank write bursts 8511441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 8333 # Per bank write bursts 8611441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 8814 # Per bank write bursts 8711441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 9019 # Per bank write bursts 8811441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 9026 # Per bank write bursts 8911441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 9076 # Per bank write bursts 9011441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 9210 # Per bank write bursts 9111441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 9034 # Per bank write bursts 9211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 9699 # Per bank write bursts 9311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 9456 # Per bank write bursts 9411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 9034 # Per bank write bursts 959978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9611441Sandreas.hansson@arm.comsystem.physmem.numWrRetry 10 # Number of times write queue was full causing retry 9711441Sandreas.hansson@arm.comsystem.physmem.totGap 5230834265500 # Total gap between requests 989978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10411441Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 181488 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1069978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1079978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11111441Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 145215 # Write request sizes (log2) 11211441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see 11311441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see 11411441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see 11511441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see 11611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see 11711336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see 11811441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see 11911441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see 12011245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 12111441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see 12211336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see 12311441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see 12411441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 12511441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 12611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see 12711441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 12811441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 12911441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 13011336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13111219Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13410148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1359924Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1369797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see 16011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see 16111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see 16211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see 16311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see 16411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see 16511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see 16611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see 16711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see 16811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see 16911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see 17011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see 17111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see 17211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see 17311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see 17411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see 17511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see 17611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see 17711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see 17811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see 17911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see 18011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see 18111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see 18211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see 18311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see 18411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see 18511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see 18611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see 18711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see 18811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see 18911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see 19011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see 19111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see 19211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see 19311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see 19411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see 19511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 19611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see 19711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see 19811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see 19911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see 20011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see 20111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see 20211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see 20311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 20411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 20511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see 20611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see 20711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see 20811441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation 20911441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation 21011441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation 21111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation 21211441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation 21311441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation 21411441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation 21511441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation 21611441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation 21711441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation 21811441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation 21911441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation 22011441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation 22111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation 22211441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes 22311441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes 22411441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes 22511441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes 22610148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 22711441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes 22811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads 22911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads 23011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads 23111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads 23211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads 23311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads 23411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads 23511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads 23611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads 23711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads 23811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads 23911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads 24011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads 24111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads 24211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads 24311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads 24411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads 24511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads 24611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads 24711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads 24811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads 24911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads 25011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads 25111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads 25211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads 25311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads 25411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads 25511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads 25611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads 25711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads 25811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads 25911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads 26011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads 26111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads 26211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads 26311441Sandreas.hansson@arm.comsystem.physmem.totQLat 2046328821 # Total ticks spent queuing 26411441Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM 26511441Sandreas.hansson@arm.comsystem.physmem.totBusLat 905985000 # Total ticks spent in databus transfers 26611441Sandreas.hansson@arm.comsystem.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst 2679978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26811441Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst 26911441Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s 27011441Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s 27111441Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s 27211441Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s 2739978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27410726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 2759978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 27610892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 27711441Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 27811441Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing 27911441Sandreas.hansson@arm.comsystem.physmem.readRowHits 147319 # Number of row buffer hits during reads 28011441Sandreas.hansson@arm.comsystem.physmem.writeRowHits 107244 # Number of row buffer hits during writes 28111441Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads 28211336Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes 28311441Sandreas.hansson@arm.comsystem.physmem.avgGap 16010977.14 # Average gap between requests 28411441Sandreas.hansson@arm.comsystem.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined 28511441Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ) 28611441Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ) 28711441Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ) 28811441Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ) 28911441Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ) 29011441Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ) 29111441Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ) 29211441Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ) 29311441Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.813765 # Core power per rank (mW) 29411441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states 29511441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states 29610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 29711441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states 29810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 29911441Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ) 30011441Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ) 30111441Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ) 30211441Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ) 30311441Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ) 30411441Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ) 30511441Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ) 30611441Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ) 30711441Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.831291 # Core power per rank (mW) 30811441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states 30911441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states 31010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31111441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states 31210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 31311441Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 94759510 # Number of BP lookups 31411441Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted 31511441Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect 31611441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups 31711441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 0 # Number of BTB hits 3189481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 31911441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 32011441Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target. 32111441Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions. 32211441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups. 32311441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits. 32411441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses. 32511441Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches. 32610535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 32710036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 32811441Sandreas.hansson@arm.comsystem.cpu.numCycles 480891878 # number of cpu cycles simulated 3298504SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3308504SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 33111441Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss 33211441Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed 33311441Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered 33411441Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken 33511441Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked 33611441Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing 33711441Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb 33811441Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 33911441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps 34011441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions 34111441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR 34211441Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched 34311441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed 34411441Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed 34511441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total) 34611441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total) 34711441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total) 3488504SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 34911441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total) 35011441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total) 35111441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total) 35211441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total) 35311441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total) 35411441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total) 35511441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total) 35611441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total) 35711441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total) 3588504SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3598504SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3608504SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 36111441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total) 36211441Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle 36311441Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle 36411441Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle 36511441Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked 36611441Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 157784659 # Number of cycles decode is running 36711441Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking 36811441Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing 36911441Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode 37011441Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing 37111441Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle 37211441Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking 37311441Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst 37411441Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 161343580 # Number of cycles rename is running 37511441Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking 37611441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename 37711441Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full 37811441Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full 37911441Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full 38011441Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full 38111441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed 38211441Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made 38311441Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups 38411441Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups 38511441Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed 38611441Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing 38711441Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 601367 # count of serializing insts renamed 38811441Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed 38911441Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer 39011441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit. 39111441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit. 39211441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads. 39311441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores. 39411441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec) 39511441Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ 39611441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued 39711441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued 39811441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling 39911441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph 40011441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed 40111441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle 40211441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle 40311441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle 4048504SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 40511441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle 40611441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle 40711441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle 40811441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle 40911441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle 41011441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle 41111441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle 41211441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle 41311441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle 4148504SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4158504SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4168504SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 41711441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle 4188504SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 41911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available 42011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available 42111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available 42211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available 42311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available 42411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available 42511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available 42611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available 42711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available 42811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available 42911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available 43011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available 43111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available 43211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available 43311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available 43411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available 43511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available 43611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available 43711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available 43811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available 43911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available 44011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available 44111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available 44211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available 44311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available 44411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available 44511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available 44611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available 44711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available 44811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available 44911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available 4508504SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4518504SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 45211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued 45311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued 45411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued 45511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued 45611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued 45711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued 45811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued 45911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued 46011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued 46111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued 46211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued 46311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued 46411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued 46511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued 46611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued 46711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued 46811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued 46911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued 47011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued 47111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued 47211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued 47311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued 47411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued 47511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued 47611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued 47711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued 47811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued 47911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued 48011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued 48111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued 48211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued 48311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued 4848504SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4858504SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 48611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 846301447 # Type of FU issued 48711441Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.759858 # Inst issue rate 48811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested 48911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst) 49011441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads 49111441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes 49211441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses 49311441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads 49411441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes 49511441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses 49611441Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses 49711441Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses 49811441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores 4998504SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 50011441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed 50111441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed 50211441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations 50311441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed 5048504SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5058504SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 50611441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled 50711441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked 5088504SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 50911441Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing 51011441Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking 51111441Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking 51211441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ 51311441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch 51411441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions 51511441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions 51611441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions 51711441Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall 51811441Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall 51911441Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations 52011441Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly 52111441Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly 52211441Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute 52311441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions 52411441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed 52511441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute 5268504SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5278504SN/Asystem.cpu.iew.exec_nop 0 # number of nop insts executed 52811441Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 30041341 # number of memory reference insts executed 52911441Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 84810471 # Number of branches executed 53011441Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 9925440 # Number of stores executed 53111441Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.747546 # Inst execution rate 53211441Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit 53311441Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 836180959 # cumulative count of insts written-back 53411441Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 651539387 # num instructions producing a value 53511441Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value 53611441Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.738813 # insts written-back per cycle 53711441Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back 53811441Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit 53911441Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards 54011441Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted 54111441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle 54211441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle 54311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle 5448504SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 54511441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle 54611441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle 54711441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle 54811441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle 54911441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle 55011441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle 55111441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle 55211441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle 55311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle 5548504SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5558504SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5568504SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 55711441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle 55811441Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 407959263 # Number of instructions committed 55911441Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed 5608504SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 56111441Sandreas.hansson@arm.comsystem.cpu.commit.refs 22368017 # Number of memory references committed 56211441Sandreas.hansson@arm.comsystem.cpu.commit.loads 13951296 # Number of loads committed 56311441Sandreas.hansson@arm.comsystem.cpu.commit.membars 447981 # Number of memory barriers committed 56411441Sandreas.hansson@arm.comsystem.cpu.commit.branches 82209281 # Number of branches committed 56510645Snilay@cs.wisc.edusystem.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 56611441Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 735219945 # Number of committed integer instructions. 56711441Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 1155854 # Number of function calls committed. 56811441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction 56911441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction 57011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction 57111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction 57211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction 57311441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction 57411441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction 57511441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction 57611441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction 57711441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction 57811441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction 57911441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction 58011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction 58111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction 58211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction 58311441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction 58411441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction 58511441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction 58611441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction 58711441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction 58811441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction 58911441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction 59011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction 59111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction 59211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction 59311441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction 59411441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction 59511441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction 59611441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction 59711441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction 59811441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction 59911441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction 60010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 60110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 60211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 806441023 # Class of committed instruction 60311441Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached 60411441Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1325977641 # The number of ROB reads 60511441Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1738470998 # The number of ROB writes 60611441Sandreas.hansson@arm.comsystem.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself 60711441Sandreas.hansson@arm.comsystem.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling 60811441Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 60911441Sandreas.hansson@arm.comsystem.cpu.committedInsts 407959263 # Number of Instructions Simulated 61011441Sandreas.hansson@arm.comsystem.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated 61111441Sandreas.hansson@arm.comsystem.cpu.cpi 1.178774 # CPI: Cycles Per Instruction 61211441Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads 61311441Sandreas.hansson@arm.comsystem.cpu.ipc 0.848339 # IPC: Instructions Per Cycle 61411441Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads 61511441Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1112363546 # number of integer regfile reads 61611441Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 669949193 # number of integer regfile writes 61711441Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 124 # number of floating regfile reads 61811441Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 420347609 # number of cc regfile reads 61911441Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 325273387 # number of cc regfile writes 62011441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 273375214 # number of misc regfile reads 62111441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 400822 # number of misc regfile writes 62211441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1703381 # number of replacements 62311441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use 62411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks. 62511441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks. 62611441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks. 62711441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit. 62811441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor 62911441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 63011441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 63110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63211441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id 63311441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 63411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 63511441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 63610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63711441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses 63811441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses 63911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits 64011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits 64111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits 64211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits 64311441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits 64411441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits 64511441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits 64611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits 64711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits 64811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 21312315 # number of overall hits 64911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses 65011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses 65111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses 65211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses 65311441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses 65411441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses 65511441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses 65611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses 65711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses 65811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2620606 # number of overall misses 65911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles 66011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles 66111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # number of WriteReq miss cycles 66211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 20451778744 # number of WriteReq miss cycles 66311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 52129012244 # number of demand (read+write) miss cycles 66411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 52129012244 # number of demand (read+write) miss cycles 66511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 52129012244 # number of overall miss cycles 66611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 52129012244 # number of overall miss cycles 66711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 15046860 # number of ReadReq accesses(hits+misses) 66811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 15046860 # number of ReadReq accesses(hits+misses) 66911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 8407012 # number of WriteReq accesses(hits+misses) 67011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 8407012 # number of WriteReq accesses(hits+misses) 67111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 479049 # number of SoftPFReq accesses(hits+misses) 67211441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 479049 # number of SoftPFReq accesses(hits+misses) 67311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses 67411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses 67511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses 67611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses 67711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses 67811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses 67911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses 68011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses 68111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses 68211441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses 68311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses 68411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses 68511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses 68611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses 68711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency 68811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency 68911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency 69011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency 69111441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency 69211441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency 69311441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency 69411441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency 69511441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked 69611441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked 69711441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked 69811441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 69911441Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked 70011441Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked 70111441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks 70211441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1592887 # number of writebacks 70311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits 70411441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits 70511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits 70611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits 70711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits 70811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits 70911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 910407 # number of overall MSHR hits 71011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 910407 # number of overall MSHR hits 71111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1015040 # number of ReadReq MSHR misses 71211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1015040 # number of ReadReq MSHR misses 71311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 287119 # number of WriteReq MSHR misses 71411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 287119 # number of WriteReq MSHR misses 71511441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 404591 # number of SoftPFReq MSHR misses 71611441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses 71711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1302159 # number of demand (read+write) MSHR misses 71811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1302159 # number of demand (read+write) MSHR misses 71911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1706750 # number of overall MSHR misses 72011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1706750 # number of overall MSHR misses 72111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable 72211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable 72311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable 72411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable 72511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses 72611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses 72711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles 72811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles 72911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles 73011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles 73111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles 73211441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles 73311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles 73411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles 73511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles 73611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles 73711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles 73811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles 73911456Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles 74011456Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles 74111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses 74211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses 74311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses 74411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses 74511441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses 74611441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses 74711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses 74811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses 74911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses 75011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses 75111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency 75211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency 75311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency 75411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency 75511441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency 75611441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency 75711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency 75811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency 75911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency 76011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency 76111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency 76211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency 76311456Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency 76411456Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency 76511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements 76611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use 76711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks. 76811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks. 76911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks. 77011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit. 77111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor 77211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy 77311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy 77411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 77511336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 77611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 77711336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 77811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 77911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses 78011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses 78111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits 78211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits 78311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits 78411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits 78511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits 78611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits 78711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses 78811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses 78911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses 79011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses 79111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses 79211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses 79311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles 79411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles 79511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles 79611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles 79711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles 79811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles 79911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses) 80011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses) 80111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses 80211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses 80311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses 80411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses 80511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses 80611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses 80711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses 80811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses 80911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses 81011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses 81111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency 81211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency 81311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency 81411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency 81511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency 81611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency 81710535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 81810535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81910535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 82010535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 82110535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 82210535Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 82311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks 82411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks 82511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses 82611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses 82711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses 82811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses 82911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses 83011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses 83111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles 83211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles 83311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles 83411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles 83511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles 83611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles 83711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses 83811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses 83911441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses 84011441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses 84111441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses 84211441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses 84311441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency 84411441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency 84511441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 84611441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency 84711441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 84811441Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency 84911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1273398 # number of replacements 85011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use 85111441Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks. 85211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks. 85311441Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks. 85411441Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit. 85511441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor 85611441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy 85711441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy 85811103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 86011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 86111441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id 86211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 86311103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 86411441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses 86511441Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 14031709 # Number of data accesses 86611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits 86711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits 86811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits 86911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits 87011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits 87111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 11313989 # number of overall hits 87211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses 87311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses 87411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses 87511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses 87611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses 87711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1443748 # number of overall misses 87811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles 87911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles 88011441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles 88111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles 88211441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles 88311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles 88411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses) 88511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses) 88611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses 88711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses 88811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses 88911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses 89011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses 89111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses 89211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses 89311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses 89411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses 89511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses 89611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency 89711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency 89811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency 89911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency 90011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency 90111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency 90211441Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked 90311441Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked 90411441Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked 90511441Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 90611441Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked 90711441Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked 90811441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1273398 # number of writebacks 90911441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1273398 # number of writebacks 91011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits 91111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits 91211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits 91311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits 91411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits 91511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits 91611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses 91711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses 91811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses 91911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses 92011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses 92111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses 92211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles 92311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles 92411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles 92511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles 92611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles 92711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles 92811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses 92911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses 93011441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses 93111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses 93211441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses 93311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses 93411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency 93511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency 93611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 93711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency 93811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 93911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency 94011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements 94111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use 94211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks. 94311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks. 94411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks. 94511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit. 94611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor 94711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy 94811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy 94911441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 95011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 95111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 95211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 95311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 95411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 95511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses 95611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses 95711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits 95811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits 9599449SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 9609449SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 96111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits 96211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits 96311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits 96411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits 96511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses 96611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses 96711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses 96811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses 96911441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses 97011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses 97111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles 97211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles 97311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles 97411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles 97511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles 97611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles 97711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses) 97811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses) 9799449SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 9809449SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 98111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses 98211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses 98311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses 98411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses 98511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses 98611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses 98711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses 98811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses 98911441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses 99011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses 99111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency 99211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency 99311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency 99411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency 99511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency 99611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency 9978504SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 9988504SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9998504SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 10008504SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 10018983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10028983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 100311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks 100411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks 100511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses 100611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses 100711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses 100811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses 100911441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses 101011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses 101111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles 101211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles 101311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles 101411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles 101511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles 101611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles 101711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses 101811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses 101911441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses 102011441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses 102111441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses 102211441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses 102311441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency 102411441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency 102511441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 102611441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency 102711441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 102811441Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency 102911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 108236 # number of replacements 103011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use 103111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks. 103211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks. 103311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks. 10349838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 103511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor 103611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor 103711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor 103811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor 103911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor 104011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.746636 # Average percentage of cache occupancy 104111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000889 # Average percentage of cache occupancy 104211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy 104311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy 104411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy 104511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.988097 # Average percentage of cache occupancy 104611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 64158 # Occupied blocks per task id 104711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 104811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id 104911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id 105011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id 105111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id 105211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.978973 # Percentage of cache occupancy per task id 105311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 49981831 # Number of tag accesses 105411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 49981831 # Number of data accesses 105511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1631474 # number of WritebackDirty hits 105611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits 105711441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1270391 # number of WritebackClean hits 105811441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits 105911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits 106011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits 106111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits 106211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits 106311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1257840 # number of ReadCleanReq hits 106411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits 106511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 140642 # number of ReadSharedReq hits 106611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13110 # number of ReadSharedReq hits 106711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits 106811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1533991 # number of ReadSharedReq hits 106911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits 107011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 13110 # number of demand (read+write) hits 107111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits 107211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1537435 # number of demand (read+write) hits 107311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2949027 # number of demand (read+write) hits 107411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 140642 # number of overall hits 107511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 13110 # number of overall hits 107611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits 107711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits 107811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2949027 # number of overall hits 107911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses 108011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses 108111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 127805 # number of ReadExReq misses 108211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 127805 # number of ReadExReq misses 108311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15982 # number of ReadCleanReq misses 108411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses 108511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 124 # number of ReadSharedReq misses 108611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 7 # number of ReadSharedReq misses 108711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 38662 # number of ReadSharedReq misses 108811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 38793 # number of ReadSharedReq misses 108911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses 109011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 109111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15982 # number of demand (read+write) misses 109211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 166467 # number of demand (read+write) misses 109311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 182580 # number of demand (read+write) misses 109411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses 109511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 109611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses 109711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses 109811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 182580 # number of overall misses 109911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60579000 # number of UpgradeReq miss cycles 110011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles 110111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16318726500 # number of ReadExReq miss cycles 110211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 16318726500 # number of ReadExReq miss cycles 110311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2135667000 # number of ReadCleanReq miss cycles 110411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles 110511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 17077500 # number of ReadSharedReq miss cycles 110611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 945500 # number of ReadSharedReq miss cycles 110711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5106603500 # number of ReadSharedReq miss cycles 110811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 5124626500 # number of ReadSharedReq miss cycles 110911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17077500 # number of demand (read+write) miss cycles 111011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 945500 # number of demand (read+write) miss cycles 111111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles 111211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 21425330000 # number of demand (read+write) miss cycles 111311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 23579020000 # number of demand (read+write) miss cycles 111411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17077500 # number of overall miss cycles 111511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 945500 # number of overall miss cycles 111611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles 111711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles 111811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 23579020000 # number of overall miss cycles 111911441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1631474 # number of WritebackDirty accesses(hits+misses) 112011441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses) 112111441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1270391 # number of WritebackClean accesses(hits+misses) 112211441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses) 112311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1838 # number of UpgradeReq accesses(hits+misses) 112411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 1838 # number of UpgradeReq accesses(hits+misses) 112511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 285001 # number of ReadExReq accesses(hits+misses) 112611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 285001 # number of ReadExReq accesses(hits+misses) 112711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1273822 # number of ReadCleanReq accesses(hits+misses) 112811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses) 112911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 140766 # number of ReadSharedReq accesses(hits+misses) 113011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13117 # number of ReadSharedReq accesses(hits+misses) 113111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses) 113211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1572784 # number of ReadSharedReq accesses(hits+misses) 113311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 140766 # number of demand (read+write) accesses 113411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 13117 # number of demand (read+write) accesses 113511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses 113611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1703902 # number of demand (read+write) accesses 113711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 3131607 # number of demand (read+write) accesses 113811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 140766 # number of overall (read+write) accesses 113911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 13117 # number of overall (read+write) accesses 114011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses 114111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses 114211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses 114311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815016 # miss rate for UpgradeReq accesses 114411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.815016 # miss rate for UpgradeReq accesses 114511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.448437 # miss rate for ReadExReq accesses 114611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.448437 # miss rate for ReadExReq accesses 114711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.012546 # miss rate for ReadCleanReq accesses 114811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses 114911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000881 # miss rate for ReadSharedReq accesses 115011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000534 # miss rate for ReadSharedReq accesses 115111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses 115211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses 115311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000881 # miss rate for demand accesses 115411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000534 # miss rate for demand accesses 115511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.012546 # miss rate for demand accesses 115611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.097698 # miss rate for demand accesses 115711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.058302 # miss rate for demand accesses 115811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses 115911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000534 # miss rate for overall accesses 116011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses 116111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses 116211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses 116311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency 116411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency 116511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency 116611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency 116711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency 116811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency 116911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency 117011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency 117111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency 117211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency 117311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency 117411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency 117511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency 117611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency 117711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency 117811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency 117911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency 118011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency 118111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency 118211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency 11839285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11849285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11859285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11869285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11879285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11889285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 118911441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks 119011441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98548 # number of writebacks 119111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 119211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 119311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits 119411245Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits 119511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 119611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 119711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 119811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits 119911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 120011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 120111441Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 120211441Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 120311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses 120411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses 120511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses 120611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses 120711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses 120811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses 120911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses 121011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses 121111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses 121211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses 121311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses 121411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 121511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses 121611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses 121711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses 121811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses 121911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 122011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses 122111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses 122211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses 122311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable 122411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable 122511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable 122611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable 122711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses 122811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses 122911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles 123011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles 123111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles 123211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles 123311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles 123411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles 123511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles 123611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles 123711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles 123811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles 123911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles 124011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles 124111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles 124211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles 124311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles 124411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles 124511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles 124611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles 124711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles 124811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles 124911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles 125011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles 125111456Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles 125211456Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles 125310892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 125410892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 125511441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses 125611441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses 125711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses 125811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses 125911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses 126011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses 126111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses 126211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses 126311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses 126411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses 126511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses 126611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses 126711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses 126811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses 126911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses 127011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses 127111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses 127211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses 127311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses 127411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses 127511441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency 127611441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency 127711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency 127811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency 127911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency 128011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency 128111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency 128211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency 128311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency 128411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency 128511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency 128611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency 128711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency 128811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency 128911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 129011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency 129111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency 129211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency 129311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency 129411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 129511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency 129611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency 129711456Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency 129811456Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency 129911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter. 130011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data. 130111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 130211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. 130311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 130411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 130511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution 130611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution 130711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution 130811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution 130911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution 131011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution 131111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution 131211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution 131311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution 131411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution 131511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution 131611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution 131711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution 131811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution 131911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution 132010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution 132111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes) 132211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes) 132311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes) 132411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes) 132511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes) 132611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes) 132711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes) 132811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes) 132911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes) 133011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes) 133111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 217979 # Total snoops (count) 133211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram 133311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram 133411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram 133510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 133611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram 133711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram 133811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram 133911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 134011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 134110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 134211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 134311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 134411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram 134511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks) 134610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 134711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks) 134810535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 134911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks) 135010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 135111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks) 135210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 135311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks) 135410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 135511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks) 135610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 135711441Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 212035 # Transaction distribution 135811441Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 212035 # Transaction distribution 135911336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 57756 # Transaction distribution 136011336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 57756 # Transaction distribution 136111441Sandreas.hansson@arm.comsystem.iobus.trans_dist::MessageReq 1666 # Transaction distribution 136211441Sandreas.hansson@arm.comsystem.iobus.trans_dist::MessageResp 1666 # Transaction distribution 136310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 136410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 136511336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 136610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 136711138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 136810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 136910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 137011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes) 137110787Snilay@cs.wisc.edusystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 137210549Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 137310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 137410639Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 137510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 137610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 137710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 137810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 137911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) 138011336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes) 138111441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes) 138211441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes) 138311441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes) 138411441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes) 138511441Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes) 138610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 138710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 138811336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 138910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 139011138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 139110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 139210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 139311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes) 139410787Snilay@cs.wisc.edusystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 139510549Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 139610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 139710639Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 139810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 139910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 140010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 140110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 140211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) 140311336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes) 140411441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes) 140511441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes) 140611441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes) 140711441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes) 140811441Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes) 140911441Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks) 141010535Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 141111441Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks) 141210535Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 141311441Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 141410535Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 141511441Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks) 141610535Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 141711441Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks) 141810535Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 141911441Sandreas.hansson@arm.comsystem.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks) 142010535Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 142111441Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks) 142210535Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 142311441Sandreas.hansson@arm.comsystem.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks) 142410535Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 142511441Sandreas.hansson@arm.comsystem.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks) 142610535Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 142711441Sandreas.hansson@arm.comsystem.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks) 142810535Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 142911245Sandreas.sandberg@arm.comsystem.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks) 143010535Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 143111245Sandreas.sandberg@arm.comsystem.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 143211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 143311441Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks) 143410535Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 143511441Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 143610535Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 143711245Sandreas.sandberg@arm.comsystem.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 143810535Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 143911441Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 144010535Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 144111441Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 144210535Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 144311441Sandreas.hansson@arm.comsystem.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks) 144410535Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 144511441Sandreas.hansson@arm.comsystem.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks) 144610535Sandreas.hansson@arm.comsystem.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 144711336Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks) 144810535Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 144911441Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks) 145010535Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 145111441Sandreas.hansson@arm.comsystem.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks) 145210535Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 145311441Sandreas.hansson@arm.comsystem.iocache.tags.replacements 47572 # number of replacements 145411441Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use 145510535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 145611441Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. 145710535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 145811441Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit. 145911441Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor 146011441Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy 146111441Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy 146210535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 146310535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 146410535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 146511441Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 428643 # Number of tag accesses 146611441Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 428643 # Number of data accesses 146711441Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses 146811441Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 907 # number of ReadReq misses 146910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 147010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 147111456Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses 147211456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47627 # number of demand (read+write) misses 147311456Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses 147411456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47627 # number of overall misses 147511441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles 147611441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles 147711441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles 147811441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles 147911456Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles 148011456Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles 148111456Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles 148211456Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles 148311441Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) 148411441Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) 148510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 148610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 148711456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses 148811456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses 148911456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses 149011456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses 149110535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 149210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 149310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 149410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 149510535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 149610535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 149710535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 149810535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 149911441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency 150011441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency 150111441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency 150211441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency 150311456Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency 150411456Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency 150511456Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency 150611456Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency 150711441Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked 150810535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 150911441Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 20 # number of cycles access was blocked 151010535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 151111441Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked 151210535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 151310811Snilay@cs.wisc.edusystem.iocache.writebacks::writebacks 46667 # number of writebacks 151410811Snilay@cs.wisc.edusystem.iocache.writebacks::total 46667 # number of writebacks 151511441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses 151611441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses 151710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 151810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses 151911456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses 152011456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses 152111456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses 152211456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses 152311441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles 152411441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles 152511441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles 152611441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles 152711456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles 152811456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles 152911456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles 153011456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles 153110535Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 153210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 153310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 153410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 153510535Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 153610535Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 153710535Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 153810535Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 153911441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency 154011441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency 154111441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency 154211441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency 154311456Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency 154411456Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency 154511456Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency 154611456Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency 154711336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 573476 # Transaction distribution 154811441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 628544 # Transaction distribution 154911441Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 13974 # Transaction distribution 155011441Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 13974 # Transaction distribution 155111441Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 145215 # Transaction distribution 155211441Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 10528 # Transaction distribution 155311441Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 2175 # Transaction distribution 155411441Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 20 # Transaction distribution 155511441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 127539 # Transaction distribution 155611441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 127538 # Transaction distribution 155711441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution 155811441Sandreas.hansson@arm.comsystem.membus.trans_dist::MessageReq 1666 # Transaction distribution 155911441Sandreas.hansson@arm.comsystem.membus.trans_dist::MessageResp 1666 # Transaction distribution 156011441Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 611 # Transaction distribution 156110892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 156211441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes) 156311441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes) 156411336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes) 156511441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes) 156611441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes) 156711441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes) 156811441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes) 156911441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes) 157011441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes) 157111441Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes) 157211441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes) 157311441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes) 157411336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes) 157511441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes) 157611441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes) 157711441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes) 157810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 157910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) 158011441Sandreas.hansson@arm.comsystem.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes) 158111441Sandreas.hansson@arm.comsystem.membus.snoops 1549 # Total snoops (count) 158211441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 976982 # Request fanout histogram 158311441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1.001705 # Request fanout histogram 158411441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram 158510535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 158610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 158711441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram 158811441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram 158910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 159010535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 159110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 2 # Request fanout histogram 159211441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 976982 # Request fanout histogram 159311441Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks) 159410535Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 159511441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks) 159610535Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 159711441Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks) 159810535Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 159911441Sandreas.hansson@arm.comsystem.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks) 160010535Sandreas.hansson@arm.comsystem.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 160111441Sandreas.hansson@arm.comsystem.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks) 160210535Sandreas.hansson@arm.comsystem.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 160311441Sandreas.hansson@arm.comsystem.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks) 160410535Sandreas.hansson@arm.comsystem.membus.respLayer0.utilization 0.0 # Layer utilization (%) 160511441Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks) 160610726Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 160711441Sandreas.hansson@arm.comsystem.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks) 160810535Sandreas.hansson@arm.comsystem.membus.respLayer4.utilization 0.0 # Layer utilization (%) 160910535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 161010535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 161111336Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 161210535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 161310535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 161410535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 161510535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 161610535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 161710535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 161810535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 161910535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 162010535Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 16218504SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 16228504SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 16238504SN/A 16248504SN/A---------- End Simulation Statistics ---------- 1625