stats.txt revision 11374:c1525cc9ec7f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.460623 # Number of seconds simulated 4sim_ticks 47460623015500 # Number of ticks simulated 5final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 557401 # Simulator instruction rate (inst/s) 8host_op_rate 655644 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30226773681 # Simulator tick rate (ticks/s) 10host_mem_usage 730476 # Number of bytes of host memory used 11host_seconds 1570.15 # Real time elapsed on the host 12sim_insts 875204273 # Number of instructions simulated 13sim_ops 1029460892 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 12415040 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 115712 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 117120 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2511992 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 9752208 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13330752 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 455552 # Number of bytes read from this memory 27system.physmem.bytes_read::total 53916868 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3183732 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2511992 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 5695724 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 73320768 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 73341352 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1280 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1221 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 90153 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 185555 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 193985 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1808 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1830 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 39338 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 152391 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 208293 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 7118 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 882972 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1145637 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1148211 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1647 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 67082 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 250201 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 261586 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 2438 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2468 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 52928 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 205480 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 280880 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9599 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1136034 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 67082 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 52928 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 120009 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1544876 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1545310 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1544876 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1647 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 67082 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 250635 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 261586 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 2438 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2468 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 52928 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 205480 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 280880 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9599 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2681343 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 882972 # Number of read requests accepted 84system.physmem.writeReqs 1148211 # Number of write requests accepted 85system.physmem.readBursts 882972 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1148211 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 56486656 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue 89system.physmem.bytesWritten 73339968 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 53916868 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 73341352 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 53897 # Per bank write bursts 96system.physmem.perBankRdBursts::1 57581 # Per bank write bursts 97system.physmem.perBankRdBursts::2 50596 # Per bank write bursts 98system.physmem.perBankRdBursts::3 56941 # Per bank write bursts 99system.physmem.perBankRdBursts::4 52224 # Per bank write bursts 100system.physmem.perBankRdBursts::5 57867 # Per bank write bursts 101system.physmem.perBankRdBursts::6 48622 # Per bank write bursts 102system.physmem.perBankRdBursts::7 53589 # Per bank write bursts 103system.physmem.perBankRdBursts::8 50057 # Per bank write bursts 104system.physmem.perBankRdBursts::9 95322 # Per bank write bursts 105system.physmem.perBankRdBursts::10 46946 # Per bank write bursts 106system.physmem.perBankRdBursts::11 52908 # Per bank write bursts 107system.physmem.perBankRdBursts::12 47194 # Per bank write bursts 108system.physmem.perBankRdBursts::13 52526 # Per bank write bursts 109system.physmem.perBankRdBursts::14 52237 # Per bank write bursts 110system.physmem.perBankRdBursts::15 54097 # Per bank write bursts 111system.physmem.perBankWrBursts::0 68696 # Per bank write bursts 112system.physmem.perBankWrBursts::1 73430 # Per bank write bursts 113system.physmem.perBankWrBursts::2 69832 # Per bank write bursts 114system.physmem.perBankWrBursts::3 74009 # Per bank write bursts 115system.physmem.perBankWrBursts::4 72053 # Per bank write bursts 116system.physmem.perBankWrBursts::5 74820 # Per bank write bursts 117system.physmem.perBankWrBursts::6 69700 # Per bank write bursts 118system.physmem.perBankWrBursts::7 72497 # Per bank write bursts 119system.physmem.perBankWrBursts::8 69824 # Per bank write bursts 120system.physmem.perBankWrBursts::9 74930 # Per bank write bursts 121system.physmem.perBankWrBursts::10 66965 # Per bank write bursts 122system.physmem.perBankWrBursts::11 71787 # Per bank write bursts 123system.physmem.perBankWrBursts::12 69900 # Per bank write bursts 124system.physmem.perBankWrBursts::13 73092 # Per bank write bursts 125system.physmem.perBankWrBursts::14 71437 # Per bank write bursts 126system.physmem.perBankWrBursts::15 72965 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 49 # Number of times write queue was full causing retry 129system.physmem.totGap 47460619650000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 839747 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1145637 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 632223 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 71339 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 35282 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 31150 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 27029 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 24072 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 21057 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 18521 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 14779 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2467 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1357 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 874 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 674 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 507 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 376 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 293 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 33201 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 39474 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 49559 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 52179 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 57658 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 60584 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 63950 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 67460 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 69091 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 68874 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 71191 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 73992 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 71007 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 71950 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 78189 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 71162 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 66652 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 64454 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 3233 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1565 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1104 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 916 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 789 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 640 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 509 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 414 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 499 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 407 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 378 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 363 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 334 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 316 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 377 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 282 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 182 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 166 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 141 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 939668 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 138.161751 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 95.082106 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 185.728908 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 647019 68.86% 68.86% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 180648 19.22% 88.08% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 40379 4.30% 92.38% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 17830 1.90% 94.28% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 14299 1.52% 95.80% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 8441 0.90% 96.70% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 5223 0.56% 97.25% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4905 0.52% 97.77% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 20924 2.23% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 939668 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 60779 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 14.521496 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 130.920998 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 60776 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 60779 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60779 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 18.854160 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.212866 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.632019 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 48749 80.21% 80.21% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 9610 15.81% 96.02% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 589 0.97% 96.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 189 0.31% 97.30% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 137 0.23% 97.52% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 124 0.20% 97.73% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 218 0.36% 98.09% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 91 0.15% 98.24% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 270 0.44% 98.68% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 61 0.10% 98.78% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 30 0.05% 98.83% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 50 0.08% 98.91% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 255 0.42% 99.33% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 52 0.09% 99.42% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 24 0.04% 99.46% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 99 0.16% 99.62% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 170 0.28% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 3 0.00% 99.92% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 22 0.04% 99.96% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 60779 # Writes before turning the bus around for reads 300system.physmem.totQLat 27990688881 # Total ticks spent queuing 301system.physmem.totMemAccLat 44539513881 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 4413020000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 31713.76 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 50463.76 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.02 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 316system.physmem.readRowHits 659544 # Number of row buffer hits during reads 317system.physmem.writeRowHits 429323 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 74.73 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 37.46 # Row buffer hit rate for writes 320system.physmem.avgGap 23365998.85 # Average gap between requests 321system.physmem.pageHitRate 53.68 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 3575759040 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 1951059000 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 3364272600 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 3726194400 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 1199863250505 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 27423860344500 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 31736237846445 # Total energy per rank (pJ) 330system.physmem_0.averagePower 668.685699 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 45621402632571 # Time in different power states 332system.physmem_0.memoryStateTime::REF 1584814400000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 254405603429 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 3528047880 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 1925026125 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 3519999600 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 3699373680 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 1198418138910 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 27425127986250 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 31736115538845 # Total energy per rank (pJ) 344system.physmem_1.averagePower 668.683122 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 45623502554973 # Time in different power states 346system.physmem_1.memoryStateTime::REF 1584814400000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 252305273527 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 357system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 358system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 363system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 376system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 377system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 378system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 379system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 380system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 381system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 382system.cpu_clk_domain.clock 500 # Clock period in ticks 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu0.dtb.walker.walks 102194 # Table walker walks requested 413system.cpu0.dtb.walker.walksLong 102194 # Table walker walks initiated with long descriptors 414system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9208 # Level at which table walker walks with long descriptors terminate 415system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76624 # Level at which table walker walks with long descriptors terminate 416system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 417system.cpu0.dtb.walker.walkWaitTime::samples 102185 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::mean 0.254440 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::stdev 81.335431 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::0-2047 102184 100.00% 100.00% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::total 102185 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkCompletionTime::samples 85841 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::0-65535 85046 99.07% 99.07% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::65536-131071 170 0.20% 99.27% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::131072-196607 522 0.61% 99.88% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::196608-262143 25 0.03% 99.91% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.94% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::393216-458751 28 0.03% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::total 85841 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walksPending::samples 4536625496 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::mean 0.282786 # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::stdev 0.450353 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::0 3253731032 71.72% 71.72% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::1 1282894464 28.28% 100.00% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::total 4536625496 # Table walker pending requests distribution 444system.cpu0.dtb.walker.walkPageSizes::4K 76625 89.27% 89.27% # Table walker page sizes translated 445system.cpu0.dtb.walker.walkPageSizes::2M 9208 10.73% 100.00% # Table walker page sizes translated 446system.cpu0.dtb.walker.walkPageSizes::total 85833 # Table walker page sizes translated 447system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 102194 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 102194 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85833 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85833 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin::total 188027 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.inst_hits 0 # ITB inst hits 455system.cpu0.dtb.inst_misses 0 # ITB inst misses 456system.cpu0.dtb.read_hits 85563003 # DTB read hits 457system.cpu0.dtb.read_misses 75756 # DTB read misses 458system.cpu0.dtb.write_hits 77475573 # DTB write hits 459system.cpu0.dtb.write_misses 26438 # DTB write misses 460system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 461system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 462system.cpu0.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 463system.cpu0.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 464system.cpu0.dtb.flush_entries 34001 # Number of entries that have been flushed from TLB 465system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 466system.cpu0.dtb.prefetch_faults 4044 # Number of TLB faults due to prefetch 467system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 468system.cpu0.dtb.perms_faults 8915 # Number of TLB faults due to permissions restrictions 469system.cpu0.dtb.read_accesses 85638759 # DTB read accesses 470system.cpu0.dtb.write_accesses 77502011 # DTB write accesses 471system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 472system.cpu0.dtb.hits 163038576 # DTB hits 473system.cpu0.dtb.misses 102194 # DTB misses 474system.cpu0.dtb.accesses 163140770 # DTB accesses 475system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 484system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 485system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 486system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 487system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 488system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 493system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 494system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 495system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 501system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 502system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 504system.cpu0.itb.walker.walks 56381 # Table walker walks requested 505system.cpu0.itb.walker.walksLong 56381 # Table walker walks initiated with long descriptors 506system.cpu0.itb.walker.walksLongTerminationLevel::Level2 642 # Level at which table walker walks with long descriptors terminate 507system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50009 # Level at which table walker walks with long descriptors terminate 508system.cpu0.itb.walker.walkWaitTime::samples 56381 # Table walker wait (enqueue to first request) latency 509system.cpu0.itb.walker.walkWaitTime::0 56381 100.00% 100.00% # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkWaitTime::total 56381 # Table walker wait (enqueue to first request) latency 511system.cpu0.itb.walker.walkCompletionTime::samples 50651 # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::mean 25304.495469 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990 # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::0-65535 49913 98.54% 98.54% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::65536-131071 55 0.11% 98.65% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::131072-196607 593 1.17% 99.82% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.84% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.06% 99.90% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.92% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::393216-458751 34 0.07% 99.99% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::total 50651 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 526system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 527system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 528system.cpu0.itb.walker.walkPageSizes::4K 50009 98.73% 98.73% # Table walker page sizes translated 529system.cpu0.itb.walker.walkPageSizes::2M 642 1.27% 100.00% # Table walker page sizes translated 530system.cpu0.itb.walker.walkPageSizes::total 50651 # Table walker page sizes translated 531system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56381 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56381 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50651 # Table walker requests started/completed, data/inst 536system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50651 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin::total 107032 # Table walker requests started/completed, data/inst 538system.cpu0.itb.inst_hits 455204971 # ITB inst hits 539system.cpu0.itb.inst_misses 56381 # ITB inst misses 540system.cpu0.itb.read_hits 0 # DTB read hits 541system.cpu0.itb.read_misses 0 # DTB read misses 542system.cpu0.itb.write_hits 0 # DTB write hits 543system.cpu0.itb.write_misses 0 # DTB write misses 544system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 545system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 546system.cpu0.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 547system.cpu0.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 548system.cpu0.itb.flush_entries 24108 # Number of entries that have been flushed from TLB 549system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 550system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 551system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 552system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 553system.cpu0.itb.read_accesses 0 # DTB read accesses 554system.cpu0.itb.write_accesses 0 # DTB write accesses 555system.cpu0.itb.inst_accesses 455261352 # ITB inst accesses 556system.cpu0.itb.hits 455204971 # DTB hits 557system.cpu0.itb.misses 56381 # DTB misses 558system.cpu0.itb.accesses 455261352 # DTB accesses 559system.cpu0.numCycles 94921246031 # number of cpu cycles simulated 560system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 561system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 562system.cpu0.kern.inst.arm 0 # number of arm instructions executed 563system.cpu0.kern.inst.quiesce 13214 # number of quiesce instructions executed 564system.cpu0.committedInsts 454926589 # Number of instructions committed 565system.cpu0.committedOps 534313943 # Number of ops (including micro ops) committed 566system.cpu0.num_int_alu_accesses 491049300 # Number of integer alu accesses 567system.cpu0.num_fp_alu_accesses 395385 # Number of float alu accesses 568system.cpu0.num_func_calls 27308099 # number of times a function call or return occured 569system.cpu0.num_conditional_control_insts 68959046 # number of instructions that are conditional controls 570system.cpu0.num_int_insts 491049300 # number of integer instructions 571system.cpu0.num_fp_insts 395385 # number of float instructions 572system.cpu0.num_int_register_reads 709557386 # number of times the integer registers were read 573system.cpu0.num_int_register_writes 389375063 # number of times the integer registers were written 574system.cpu0.num_fp_register_reads 654866 # number of times the floating registers were read 575system.cpu0.num_fp_register_writes 293356 # number of times the floating registers were written 576system.cpu0.num_cc_register_reads 117980325 # number of times the CC registers were read 577system.cpu0.num_cc_register_writes 117652107 # number of times the CC registers were written 578system.cpu0.num_mem_refs 163029477 # number of memory refs 579system.cpu0.num_load_insts 85557806 # Number of load instructions 580system.cpu0.num_store_insts 77471671 # Number of store instructions 581system.cpu0.num_idle_cycles 93727706914.782028 # Number of idle cycles 582system.cpu0.num_busy_cycles 1193539116.217975 # Number of busy cycles 583system.cpu0.not_idle_fraction 0.012574 # Percentage of non-idle cycles 584system.cpu0.idle_fraction 0.987426 # Percentage of idle cycles 585system.cpu0.Branches 101606994 # Number of branches fetched 586system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 587system.cpu0.op_class::IntAlu 370328410 69.27% 69.27% # Class of executed instruction 588system.cpu0.op_class::IntMult 1177627 0.22% 69.49% # Class of executed instruction 589system.cpu0.op_class::IntDiv 60510 0.01% 69.50% # Class of executed instruction 590system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 591system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 592system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 593system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 594system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 595system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 596system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 597system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 598system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 599system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 600system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 601system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 602system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 603system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 604system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 605system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 606system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 607system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.50% # Class of executed instruction 608system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 609system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.50% # Class of executed instruction 610system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.50% # Class of executed instruction 611system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 612system.cpu0.op_class::SimdFloatMisc 39424 0.01% 69.51% # Class of executed instruction 613system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 614system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 615system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 616system.cpu0.op_class::MemRead 85557806 16.00% 85.51% # Class of executed instruction 617system.cpu0.op_class::MemWrite 77471671 14.49% 100.00% # Class of executed instruction 618system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 619system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 620system.cpu0.op_class::total 534635449 # Class of executed instruction 621system.cpu0.dcache.tags.replacements 5459134 # number of replacements 622system.cpu0.dcache.tags.tagsinuse 479.881862 # Cycle average of tags in use 623system.cpu0.dcache.tags.total_refs 157334556 # Total number of references to valid blocks. 624system.cpu0.dcache.tags.sampled_refs 5459646 # Sample count of references to valid blocks. 625system.cpu0.dcache.tags.avg_refs 28.817721 # Average number of references to valid blocks. 626system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 627system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.881862 # Average occupied blocks per requestor 628system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy 629system.cpu0.dcache.tags.occ_percent::total 0.937269 # Average percentage of cache occupancy 630system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 632system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id 633system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 634system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 635system.cpu0.dcache.tags.tag_accesses 331496751 # Number of tag accesses 636system.cpu0.dcache.tags.data_accesses 331496751 # Number of data accesses 637system.cpu0.dcache.ReadReq_hits::cpu0.data 79723477 # number of ReadReq hits 638system.cpu0.dcache.ReadReq_hits::total 79723477 # number of ReadReq hits 639system.cpu0.dcache.WriteReq_hits::cpu0.data 73152105 # number of WriteReq hits 640system.cpu0.dcache.WriteReq_hits::total 73152105 # number of WriteReq hits 641system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits 642system.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits 643system.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits 644system.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits 645system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits 646system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits 647system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits 648system.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits 649system.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits 650system.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits 651system.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits 652system.cpu0.dcache.overall_hits::total 153075138 # number of overall hits 653system.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses 654system.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses 655system.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses 656system.cpu0.dcache.WriteReq_misses::total 1350734 # number of WriteReq misses 657system.cpu0.dcache.SoftPFReq_misses::cpu0.data 619590 # number of SoftPFReq misses 658system.cpu0.dcache.SoftPFReq_misses::total 619590 # number of SoftPFReq misses 659system.cpu0.dcache.WriteLineReq_misses::cpu0.data 750130 # number of WriteLineReq misses 660system.cpu0.dcache.WriteLineReq_misses::total 750130 # number of WriteLineReq misses 661system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632 # number of LoadLockedReq misses 662system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses 663system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses 664system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses 665system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses 666system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses 667system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses 668system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses 669system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles 670system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles 671system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles 675system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles 682system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles 684system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles 685system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) 686system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses 698system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses 699system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses 700system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses 701system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses 702system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses 703system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses 705system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses 714system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses 715system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses 716system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses 717system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency 718system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency 719system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency 721system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency 723system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency 725system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency 730system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency 733system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 739system.cpu0.dcache.fast_writes 0 # number of fast writes performed 740system.cpu0.dcache.cache_copies 0 # number of cache copies performed 741system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks 742system.cpu0.dcache.writebacks::total 5459134 # number of writebacks 743system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits 744system.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21402 # number of WriteReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::total 21402 # number of WriteReq MSHR hits 747system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43300 # number of LoadLockedReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits 749system.cpu0.dcache.demand_mshr_hits::cpu0.data 45637 # number of demand (read+write) MSHR hits 750system.cpu0.dcache.demand_mshr_hits::total 45637 # number of demand (read+write) MSHR hits 751system.cpu0.dcache.overall_mshr_hits::cpu0.data 45637 # number of overall MSHR hits 752system.cpu0.dcache.overall_mshr_hits::total 45637 # number of overall MSHR hits 753system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2959708 # number of ReadReq MSHR misses 754system.cpu0.dcache.ReadReq_mshr_misses::total 2959708 # number of ReadReq MSHR misses 755system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1329332 # number of WriteReq MSHR misses 756system.cpu0.dcache.WriteReq_mshr_misses::total 1329332 # number of WriteReq MSHR misses 757system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses 758system.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses 759system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses 760system.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses 761system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses 765system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses 766system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses 768system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses 769system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 770system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 774system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles 776system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles 777system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33090463000 # number of WriteReq MSHR miss cycles 778system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33090463000 # number of WriteReq MSHR miss cycles 779system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14878889500 # number of SoftPFReq MSHR miss cycles 780system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14878889500 # number of SoftPFReq MSHR miss cycles 781system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles 782system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles 783system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles 784system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles 785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles 786system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles 787system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles 788system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles 789system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles 790system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles 791system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles 792system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles 793system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles 794system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles 795system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles 796system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles 797system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles 798system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses 800system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses 805system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses 806system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses 807system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses 812system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses 813system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses 814system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses 815system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency 817system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency 819system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency 820system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency 821system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency 822system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency 823system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 828system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 829system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency 830system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency 831system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency 833system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency 835system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency 836system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency 837system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency 838system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency 839system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 840system.cpu0.icache.tags.replacements 5000286 # number of replacements 841system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use 842system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. 843system.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. 844system.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. 845system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. 846system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor 847system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy 848system.cpu0.icache.tags.occ_percent::total 0.999714 # Average percentage of cache occupancy 849system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 850system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 851system.cpu0.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 852system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id 853system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 854system.cpu0.icache.tags.tag_accesses 915410741 # Number of tag accesses 855system.cpu0.icache.tags.data_accesses 915410741 # Number of data accesses 856system.cpu0.icache.ReadReq_hits::cpu0.inst 450204172 # number of ReadReq hits 857system.cpu0.icache.ReadReq_hits::total 450204172 # number of ReadReq hits 858system.cpu0.icache.demand_hits::cpu0.inst 450204172 # number of demand (read+write) hits 859system.cpu0.icache.demand_hits::total 450204172 # number of demand (read+write) hits 860system.cpu0.icache.overall_hits::cpu0.inst 450204172 # number of overall hits 861system.cpu0.icache.overall_hits::total 450204172 # number of overall hits 862system.cpu0.icache.ReadReq_misses::cpu0.inst 5000799 # number of ReadReq misses 863system.cpu0.icache.ReadReq_misses::total 5000799 # number of ReadReq misses 864system.cpu0.icache.demand_misses::cpu0.inst 5000799 # number of demand (read+write) misses 865system.cpu0.icache.demand_misses::total 5000799 # number of demand (read+write) misses 866system.cpu0.icache.overall_misses::cpu0.inst 5000799 # number of overall misses 867system.cpu0.icache.overall_misses::total 5000799 # number of overall misses 868system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55488072500 # number of ReadReq miss cycles 869system.cpu0.icache.ReadReq_miss_latency::total 55488072500 # number of ReadReq miss cycles 870system.cpu0.icache.demand_miss_latency::cpu0.inst 55488072500 # number of demand (read+write) miss cycles 871system.cpu0.icache.demand_miss_latency::total 55488072500 # number of demand (read+write) miss cycles 872system.cpu0.icache.overall_miss_latency::cpu0.inst 55488072500 # number of overall miss cycles 873system.cpu0.icache.overall_miss_latency::total 55488072500 # number of overall miss cycles 874system.cpu0.icache.ReadReq_accesses::cpu0.inst 455204971 # number of ReadReq accesses(hits+misses) 875system.cpu0.icache.ReadReq_accesses::total 455204971 # number of ReadReq accesses(hits+misses) 876system.cpu0.icache.demand_accesses::cpu0.inst 455204971 # number of demand (read+write) accesses 877system.cpu0.icache.demand_accesses::total 455204971 # number of demand (read+write) accesses 878system.cpu0.icache.overall_accesses::cpu0.inst 455204971 # number of overall (read+write) accesses 879system.cpu0.icache.overall_accesses::total 455204971 # number of overall (read+write) accesses 880system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010986 # miss rate for ReadReq accesses 881system.cpu0.icache.ReadReq_miss_rate::total 0.010986 # miss rate for ReadReq accesses 882system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010986 # miss rate for demand accesses 883system.cpu0.icache.demand_miss_rate::total 0.010986 # miss rate for demand accesses 884system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010986 # miss rate for overall accesses 885system.cpu0.icache.overall_miss_rate::total 0.010986 # miss rate for overall accesses 886system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11095.841385 # average ReadReq miss latency 887system.cpu0.icache.ReadReq_avg_miss_latency::total 11095.841385 # average ReadReq miss latency 888system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 889system.cpu0.icache.demand_avg_miss_latency::total 11095.841385 # average overall miss latency 890system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 891system.cpu0.icache.overall_avg_miss_latency::total 11095.841385 # average overall miss latency 892system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 894system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 895system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 896system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 897system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 898system.cpu0.icache.fast_writes 0 # number of fast writes performed 899system.cpu0.icache.cache_copies 0 # number of cache copies performed 900system.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks 901system.cpu0.icache.writebacks::total 5000286 # number of writebacks 902system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses 903system.cpu0.icache.ReadReq_mshr_misses::total 5000799 # number of ReadReq MSHR misses 904system.cpu0.icache.demand_mshr_misses::cpu0.inst 5000799 # number of demand (read+write) MSHR misses 905system.cpu0.icache.demand_mshr_misses::total 5000799 # number of demand (read+write) MSHR misses 906system.cpu0.icache.overall_mshr_misses::cpu0.inst 5000799 # number of overall MSHR misses 907system.cpu0.icache.overall_mshr_misses::total 5000799 # number of overall MSHR misses 908system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 909system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 910system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 911system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 912system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 52987673000 # number of ReadReq MSHR miss cycles 913system.cpu0.icache.ReadReq_mshr_miss_latency::total 52987673000 # number of ReadReq MSHR miss cycles 914system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 52987673000 # number of demand (read+write) MSHR miss cycles 915system.cpu0.icache.demand_mshr_miss_latency::total 52987673000 # number of demand (read+write) MSHR miss cycles 916system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 52987673000 # number of overall MSHR miss cycles 917system.cpu0.icache.overall_mshr_miss_latency::total 52987673000 # number of overall MSHR miss cycles 918system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 919system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 920system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 921system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 922system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for ReadReq accesses 923system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010986 # mshr miss rate for ReadReq accesses 924system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for demand accesses 925system.cpu0.icache.demand_mshr_miss_rate::total 0.010986 # mshr miss rate for demand accesses 926system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for overall accesses 927system.cpu0.icache.overall_mshr_miss_rate::total 0.010986 # mshr miss rate for overall accesses 928system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average ReadReq mshr miss latency 929system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10595.841385 # average ReadReq mshr miss latency 930system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 931system.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 932system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 933system.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 934system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 935system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 936system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 937system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 938system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued 940system.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified 941system.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue 942system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 943system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 944system.cpu0.l2cache.prefetcher.pfSpanPage 974782 # number of prefetches not generated due to page crossing 945system.cpu0.l2cache.tags.replacements 2298690 # number of replacements 946system.cpu0.l2cache.tags.tagsinuse 16186.717586 # Cycle average of tags in use 947system.cpu0.l2cache.tags.total_refs 14759696 # Total number of references to valid blocks. 948system.cpu0.l2cache.tags.sampled_refs 2314768 # Sample count of references to valid blocks. 949system.cpu0.l2cache.tags.avg_refs 6.376318 # Average number of references to valid blocks. 950system.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit. 951system.cpu0.l2cache.tags.occ_blocks::writebacks 15157.672211 # Average occupied blocks per requestor 952system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.142846 # Average occupied blocks per requestor 953system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.415973 # Average occupied blocks per requestor 954system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.486557 # Average occupied blocks per requestor 955system.cpu0.l2cache.tags.occ_percent::writebacks 0.925151 # Average percentage of cache occupancy 956system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003244 # Average percentage of cache occupancy 957system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004664 # Average percentage of cache occupancy 958system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054900 # Average percentage of cache occupancy 959system.cpu0.l2cache.tags.occ_percent::total 0.987959 # Average percentage of cache occupancy 960system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1325 # Occupied blocks per task id 961system.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 962system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14699 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 683 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 429 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1043 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4210 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6256 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id 975system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080872 # Percentage of cache occupancy per task id 976system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897156 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.tag_accesses 354680611 # Number of tag accesses 979system.cpu0.l2cache.tags.data_accesses 354680611 # Number of data accesses 980system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 235924 # number of ReadReq hits 981system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143301 # number of ReadReq hits 982system.cpu0.l2cache.ReadReq_hits::total 379225 # number of ReadReq hits 983system.cpu0.l2cache.WritebackDirty_hits::writebacks 3602563 # number of WritebackDirty hits 984system.cpu0.l2cache.WritebackDirty_hits::total 3602563 # number of WritebackDirty hits 985system.cpu0.l2cache.WritebackClean_hits::writebacks 6855894 # number of WritebackClean hits 986system.cpu0.l2cache.WritebackClean_hits::total 6855894 # number of WritebackClean hits 987system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 389 # number of UpgradeReq hits 988system.cpu0.l2cache.UpgradeReq_hits::total 389 # number of UpgradeReq hits 989system.cpu0.l2cache.ReadExReq_hits::cpu0.data 855344 # number of ReadExReq hits 990system.cpu0.l2cache.ReadExReq_hits::total 855344 # number of ReadExReq hits 991system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4541852 # number of ReadCleanReq hits 992system.cpu0.l2cache.ReadCleanReq_hits::total 4541852 # number of ReadCleanReq hits 993system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2786021 # number of ReadSharedReq hits 994system.cpu0.l2cache.ReadSharedReq_hits::total 2786021 # number of ReadSharedReq hits 995system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 182713 # number of InvalidateReq hits 996system.cpu0.l2cache.InvalidateReq_hits::total 182713 # number of InvalidateReq hits 997system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 235924 # number of demand (read+write) hits 998system.cpu0.l2cache.demand_hits::cpu0.itb.walker 143301 # number of demand (read+write) hits 999system.cpu0.l2cache.demand_hits::cpu0.inst 4541852 # number of demand (read+write) hits 1000system.cpu0.l2cache.demand_hits::cpu0.data 3641365 # number of demand (read+write) hits 1001system.cpu0.l2cache.demand_hits::total 8562442 # number of demand (read+write) hits 1002system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 235924 # number of overall hits 1003system.cpu0.l2cache.overall_hits::cpu0.itb.walker 143301 # number of overall hits 1004system.cpu0.l2cache.overall_hits::cpu0.inst 4541852 # number of overall hits 1005system.cpu0.l2cache.overall_hits::cpu0.data 3641365 # number of overall hits 1006system.cpu0.l2cache.overall_hits::total 8562442 # number of overall hits 1007system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9735 # number of ReadReq misses 1008system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7677 # number of ReadReq misses 1009system.cpu0.l2cache.ReadReq_misses::total 17412 # number of ReadReq misses 1010system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 241880 # number of UpgradeReq misses 1011system.cpu0.l2cache.UpgradeReq_misses::total 241880 # number of UpgradeReq misses 1012system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190989 # number of SCUpgradeReq misses 1013system.cpu0.l2cache.SCUpgradeReq_misses::total 190989 # number of SCUpgradeReq misses 1014system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 17 # number of SCUpgradeFailReq misses 1015system.cpu0.l2cache.SCUpgradeFailReq_misses::total 17 # number of SCUpgradeFailReq misses 1016system.cpu0.l2cache.ReadExReq_misses::cpu0.data 251163 # number of ReadExReq misses 1017system.cpu0.l2cache.ReadExReq_misses::total 251163 # number of ReadExReq misses 1018system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 458947 # number of ReadCleanReq misses 1019system.cpu0.l2cache.ReadCleanReq_misses::total 458947 # number of ReadCleanReq misses 1020system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 908465 # number of ReadSharedReq misses 1021system.cpu0.l2cache.ReadSharedReq_misses::total 908465 # number of ReadSharedReq misses 1022system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 565429 # number of InvalidateReq misses 1023system.cpu0.l2cache.InvalidateReq_misses::total 565429 # number of InvalidateReq misses 1024system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9735 # number of demand (read+write) misses 1025system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7677 # number of demand (read+write) misses 1026system.cpu0.l2cache.demand_misses::cpu0.inst 458947 # number of demand (read+write) misses 1027system.cpu0.l2cache.demand_misses::cpu0.data 1159628 # number of demand (read+write) misses 1028system.cpu0.l2cache.demand_misses::total 1635987 # number of demand (read+write) misses 1029system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9735 # number of overall misses 1030system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7677 # number of overall misses 1031system.cpu0.l2cache.overall_misses::cpu0.inst 458947 # number of overall misses 1032system.cpu0.l2cache.overall_misses::cpu0.data 1159628 # number of overall misses 1033system.cpu0.l2cache.overall_misses::total 1635987 # number of overall misses 1034system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 390278500 # number of ReadReq miss cycles 1035system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 327424000 # number of ReadReq miss cycles 1036system.cpu0.l2cache.ReadReq_miss_latency::total 717702500 # number of ReadReq miss cycles 1037system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3214093500 # number of UpgradeReq miss cycles 1038system.cpu0.l2cache.UpgradeReq_miss_latency::total 3214093500 # number of UpgradeReq miss cycles 1039system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1890945000 # number of SCUpgradeReq miss cycles 1040system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1890945000 # number of SCUpgradeReq miss cycles 1041system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5616997 # number of SCUpgradeFailReq miss cycles 1042system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5616997 # number of SCUpgradeFailReq miss cycles 1043system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16356012499 # number of ReadExReq miss cycles 1044system.cpu0.l2cache.ReadExReq_miss_latency::total 16356012499 # number of ReadExReq miss cycles 1045system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18207706500 # number of ReadCleanReq miss cycles 1046system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18207706500 # number of ReadCleanReq miss cycles 1047system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36093910000 # number of ReadSharedReq miss cycles 1048system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36093910000 # number of ReadSharedReq miss cycles 1049system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 390401000 # number of InvalidateReq miss cycles 1050system.cpu0.l2cache.InvalidateReq_miss_latency::total 390401000 # number of InvalidateReq miss cycles 1051system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 390278500 # number of demand (read+write) miss cycles 1052system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 327424000 # number of demand (read+write) miss cycles 1053system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18207706500 # number of demand (read+write) miss cycles 1054system.cpu0.l2cache.demand_miss_latency::cpu0.data 52449922499 # number of demand (read+write) miss cycles 1055system.cpu0.l2cache.demand_miss_latency::total 71375331499 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 390278500 # number of overall miss cycles 1057system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 327424000 # number of overall miss cycles 1058system.cpu0.l2cache.overall_miss_latency::cpu0.inst 18207706500 # number of overall miss cycles 1059system.cpu0.l2cache.overall_miss_latency::cpu0.data 52449922499 # number of overall miss cycles 1060system.cpu0.l2cache.overall_miss_latency::total 71375331499 # number of overall miss cycles 1061system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 245659 # number of ReadReq accesses(hits+misses) 1062system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150978 # number of ReadReq accesses(hits+misses) 1063system.cpu0.l2cache.ReadReq_accesses::total 396637 # number of ReadReq accesses(hits+misses) 1064system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3602563 # number of WritebackDirty accesses(hits+misses) 1065system.cpu0.l2cache.WritebackDirty_accesses::total 3602563 # number of WritebackDirty accesses(hits+misses) 1066system.cpu0.l2cache.WritebackClean_accesses::writebacks 6855894 # number of WritebackClean accesses(hits+misses) 1067system.cpu0.l2cache.WritebackClean_accesses::total 6855894 # number of WritebackClean accesses(hits+misses) 1068system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242269 # number of UpgradeReq accesses(hits+misses) 1069system.cpu0.l2cache.UpgradeReq_accesses::total 242269 # number of UpgradeReq accesses(hits+misses) 1070system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190989 # number of SCUpgradeReq accesses(hits+misses) 1071system.cpu0.l2cache.SCUpgradeReq_accesses::total 190989 # number of SCUpgradeReq accesses(hits+misses) 1072system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 17 # number of SCUpgradeFailReq accesses(hits+misses) 1073system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 17 # number of SCUpgradeFailReq accesses(hits+misses) 1074system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1106507 # number of ReadExReq accesses(hits+misses) 1075system.cpu0.l2cache.ReadExReq_accesses::total 1106507 # number of ReadExReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5000799 # number of ReadCleanReq accesses(hits+misses) 1077system.cpu0.l2cache.ReadCleanReq_accesses::total 5000799 # number of ReadCleanReq accesses(hits+misses) 1078system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3694486 # number of ReadSharedReq accesses(hits+misses) 1079system.cpu0.l2cache.ReadSharedReq_accesses::total 3694486 # number of ReadSharedReq accesses(hits+misses) 1080system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 748142 # number of InvalidateReq accesses(hits+misses) 1081system.cpu0.l2cache.InvalidateReq_accesses::total 748142 # number of InvalidateReq accesses(hits+misses) 1082system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 245659 # number of demand (read+write) accesses 1083system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150978 # number of demand (read+write) accesses 1084system.cpu0.l2cache.demand_accesses::cpu0.inst 5000799 # number of demand (read+write) accesses 1085system.cpu0.l2cache.demand_accesses::cpu0.data 4800993 # number of demand (read+write) accesses 1086system.cpu0.l2cache.demand_accesses::total 10198429 # number of demand (read+write) accesses 1087system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 245659 # number of overall (read+write) accesses 1088system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150978 # number of overall (read+write) accesses 1089system.cpu0.l2cache.overall_accesses::cpu0.inst 5000799 # number of overall (read+write) accesses 1090system.cpu0.l2cache.overall_accesses::cpu0.data 4800993 # number of overall (read+write) accesses 1091system.cpu0.l2cache.overall_accesses::total 10198429 # number of overall (read+write) accesses 1092system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for ReadReq accesses 1093system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050848 # miss rate for ReadReq accesses 1094system.cpu0.l2cache.ReadReq_miss_rate::total 0.043899 # miss rate for ReadReq accesses 1095system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998394 # miss rate for UpgradeReq accesses 1096system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998394 # miss rate for UpgradeReq accesses 1097system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1098system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1099system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1100system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1101system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.226987 # miss rate for ReadExReq accesses 1102system.cpu0.l2cache.ReadExReq_miss_rate::total 0.226987 # miss rate for ReadExReq accesses 1103system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091775 # miss rate for ReadCleanReq accesses 1104system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091775 # miss rate for ReadCleanReq accesses 1105system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.245898 # miss rate for ReadSharedReq accesses 1106system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.245898 # miss rate for ReadSharedReq accesses 1107system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755778 # miss rate for InvalidateReq accesses 1108system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755778 # miss rate for InvalidateReq accesses 1109system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for demand accesses 1110system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050848 # miss rate for demand accesses 1111system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091775 # miss rate for demand accesses 1112system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241539 # miss rate for demand accesses 1113system.cpu0.l2cache.demand_miss_rate::total 0.160416 # miss rate for demand accesses 1114system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for overall accesses 1115system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050848 # miss rate for overall accesses 1116system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091775 # miss rate for overall accesses 1117system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241539 # miss rate for overall accesses 1118system.cpu0.l2cache.overall_miss_rate::total 0.160416 # miss rate for overall accesses 1119system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average ReadReq miss latency 1120system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42649.993487 # average ReadReq miss latency 1121system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41218.843326 # average ReadReq miss latency 1122system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13287.967174 # average UpgradeReq miss latency 1123system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13287.967174 # average UpgradeReq miss latency 1124system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9900.805806 # average SCUpgradeReq miss latency 1125system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9900.805806 # average SCUpgradeReq miss latency 1126system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 330411.588235 # average SCUpgradeFailReq miss latency 1127system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 330411.588235 # average SCUpgradeFailReq miss latency 1128system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65121.106608 # average ReadExReq miss latency 1129system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65121.106608 # average ReadExReq miss latency 1130system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39672.786836 # average ReadCleanReq miss latency 1131system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39672.786836 # average ReadCleanReq miss latency 1132system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39730.655556 # average ReadSharedReq miss latency 1133system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39730.655556 # average ReadSharedReq miss latency 1134system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 690.450967 # average InvalidateReq miss latency 1135system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 690.450967 # average InvalidateReq miss latency 1136system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average overall miss latency 1137system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42649.993487 # average overall miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39672.786836 # average overall miss latency 1139system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 1140system.cpu0.l2cache.demand_avg_miss_latency::total 43628.299919 # average overall miss latency 1141system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average overall miss latency 1142system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42649.993487 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39672.786836 # average overall miss latency 1144system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 1145system.cpu0.l2cache.overall_avg_miss_latency::total 43628.299919 # average overall miss latency 1146system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1147system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1148system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1149system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1150system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1151system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1152system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1153system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1154system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks 1155system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks 1156system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits 1157system.cpu0.l2cache.ReadExReq_mshr_hits::total 5831 # number of ReadExReq MSHR hits 1158system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 658 # number of ReadSharedReq MSHR hits 1159system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 658 # number of ReadSharedReq MSHR hits 1160system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6489 # number of demand (read+write) MSHR hits 1161system.cpu0.l2cache.demand_mshr_hits::total 6489 # number of demand (read+write) MSHR hits 1162system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6489 # number of overall MSHR hits 1163system.cpu0.l2cache.overall_mshr_hits::total 6489 # number of overall MSHR hits 1164system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9735 # number of ReadReq MSHR misses 1165system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7677 # number of ReadReq MSHR misses 1166system.cpu0.l2cache.ReadReq_mshr_misses::total 17412 # number of ReadReq MSHR misses 1167system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 676944 # number of HardPFReq MSHR misses 1168system.cpu0.l2cache.HardPFReq_mshr_misses::total 676944 # number of HardPFReq MSHR misses 1169system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 241880 # number of UpgradeReq MSHR misses 1170system.cpu0.l2cache.UpgradeReq_mshr_misses::total 241880 # number of UpgradeReq MSHR misses 1171system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190989 # number of SCUpgradeReq MSHR misses 1172system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190989 # number of SCUpgradeReq MSHR misses 1173system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 17 # number of SCUpgradeFailReq MSHR misses 1174system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 17 # number of SCUpgradeFailReq MSHR misses 1175system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 245332 # number of ReadExReq MSHR misses 1176system.cpu0.l2cache.ReadExReq_mshr_misses::total 245332 # number of ReadExReq MSHR misses 1177system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 458947 # number of ReadCleanReq MSHR misses 1178system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 458947 # number of ReadCleanReq MSHR misses 1179system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 907807 # number of ReadSharedReq MSHR misses 1180system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 907807 # number of ReadSharedReq MSHR misses 1181system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 565429 # number of InvalidateReq MSHR misses 1182system.cpu0.l2cache.InvalidateReq_mshr_misses::total 565429 # number of InvalidateReq MSHR misses 1183system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9735 # number of demand (read+write) MSHR misses 1184system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7677 # number of demand (read+write) MSHR misses 1185system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 458947 # number of demand (read+write) MSHR misses 1186system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1153139 # number of demand (read+write) MSHR misses 1187system.cpu0.l2cache.demand_mshr_misses::total 1629498 # number of demand (read+write) MSHR misses 1188system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9735 # number of overall MSHR misses 1189system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7677 # number of overall MSHR misses 1190system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 458947 # number of overall MSHR misses 1191system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1153139 # number of overall MSHR misses 1192system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 676944 # number of overall MSHR misses 1193system.cpu0.l2cache.overall_mshr_misses::total 2306442 # number of overall MSHR misses 1194system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1195system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 1196system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72575 # number of ReadReq MSHR uncacheable 1197system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 1198system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 1199system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1200system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 1201system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 101499 # number of overall MSHR uncacheable misses 1202system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of ReadReq MSHR miss cycles 1203system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 281362000 # number of ReadReq MSHR miss cycles 1204system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 613230500 # number of ReadReq MSHR miss cycles 1205system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of HardPFReq MSHR miss cycles 1206system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37650647602 # number of HardPFReq MSHR miss cycles 1207system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7335732000 # number of UpgradeReq MSHR miss cycles 1208system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7335732000 # number of UpgradeReq MSHR miss cycles 1209system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3705379500 # number of SCUpgradeReq MSHR miss cycles 1210system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3705379500 # number of SCUpgradeReq MSHR miss cycles 1211system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5238997 # number of SCUpgradeFailReq MSHR miss cycles 1212system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5238997 # number of SCUpgradeFailReq MSHR miss cycles 1213system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14201538999 # number of ReadExReq MSHR miss cycles 1214system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14201538999 # number of ReadExReq MSHR miss cycles 1215system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15454024500 # number of ReadCleanReq MSHR miss cycles 1216system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15454024500 # number of ReadCleanReq MSHR miss cycles 1217system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30580591000 # number of ReadSharedReq MSHR miss cycles 1218system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30580591000 # number of ReadSharedReq MSHR miss cycles 1219system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39622342000 # number of InvalidateReq MSHR miss cycles 1220system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39622342000 # number of InvalidateReq MSHR miss cycles 1221system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of demand (read+write) MSHR miss cycles 1222system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 281362000 # number of demand (read+write) MSHR miss cycles 1223system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15454024500 # number of demand (read+write) MSHR miss cycles 1224system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44782129999 # number of demand (read+write) MSHR miss cycles 1225system.cpu0.l2cache.demand_mshr_miss_latency::total 60849384999 # number of demand (read+write) MSHR miss cycles 1226system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of overall MSHR miss cycles 1227system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 281362000 # number of overall MSHR miss cycles 1228system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15454024500 # number of overall MSHR miss cycles 1229system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44782129999 # number of overall MSHR miss cycles 1230system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of overall MSHR miss cycles 1231system.cpu0.l2cache.overall_mshr_miss_latency::total 98500032601 # number of overall MSHR miss cycles 1232system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 1233system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5203415000 # number of ReadReq MSHR uncacheable cycles 1234system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10834186500 # number of ReadReq MSHR uncacheable cycles 1235system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles 1236system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles 1237system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 1238system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles 1239system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles 1240system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for ReadReq accesses 1241system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for ReadReq accesses 1242system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043899 # mshr miss rate for ReadReq accesses 1243system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1244system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1245system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses 1246system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses 1247system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1248system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1249system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1250system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1251system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221718 # mshr miss rate for ReadExReq accesses 1252system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221718 # mshr miss rate for ReadExReq accesses 1253system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for ReadCleanReq accesses 1254system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091775 # mshr miss rate for ReadCleanReq accesses 1255system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245719 # mshr miss rate for ReadSharedReq accesses 1256system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245719 # mshr miss rate for ReadSharedReq accesses 1257system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755778 # mshr miss rate for InvalidateReq accesses 1258system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755778 # mshr miss rate for InvalidateReq accesses 1259system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for demand accesses 1260system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for demand accesses 1261system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for demand accesses 1262system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for demand accesses 1263system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159779 # mshr miss rate for demand accesses 1264system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for overall accesses 1265system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for overall accesses 1266system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for overall accesses 1267system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for overall accesses 1268system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1269system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226157 # mshr miss rate for overall accesses 1270system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average ReadReq mshr miss latency 1271system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average ReadReq mshr miss latency 1272system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326 # average ReadReq mshr miss latency 1273system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average HardPFReq mshr miss latency 1274system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748 # average HardPFReq mshr miss latency 1275system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817 # average UpgradeReq mshr miss latency 1276system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817 # average UpgradeReq mshr miss latency 1277system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006 # average SCUpgradeReq mshr miss latency 1278system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006 # average SCUpgradeReq mshr miss latency 1279system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118 # average SCUpgradeFailReq mshr miss latency 1280system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118 # average SCUpgradeFailReq mshr miss latency 1281system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480 # average ReadExReq mshr miss latency 1282system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480 # average ReadExReq mshr miss latency 1283system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average ReadCleanReq mshr miss latency 1284system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836 # average ReadCleanReq mshr miss latency 1285system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156 # average ReadSharedReq mshr miss latency 1286system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156 # average ReadSharedReq mshr miss latency 1287system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676 # average InvalidateReq mshr miss latency 1288system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676 # average InvalidateReq mshr miss latency 1289system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency 1290system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 1291system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 1292system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 1293system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589 # average overall mshr miss latency 1294system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency 1295system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 1296system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 1297system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 1298system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency 1299system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency 1300system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 1301system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency 1302system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency 1303system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency 1304system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency 1305system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 1306system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency 1307system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency 1308system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1309system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. 1310system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1311system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1312system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. 1313system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1314system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1315system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution 1316system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution 1317system.cpu0.toL2Bus.trans_dist::WriteReq 28925 # Transaction distribution 1318system.cpu0.toL2Bus.trans_dist::WriteResp 28924 # Transaction distribution 1319system.cpu0.toL2Bus.trans_dist::WritebackDirty 5081322 # Transaction distribution 1320system.cpu0.toL2Bus.trans_dist::WritebackClean 6856856 # Transaction distribution 1321system.cpu0.toL2Bus.trans_dist::CleanEvict 2248329 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::HardPFReq 834929 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::UpgradeReq 427184 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348871 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::UpgradeResp 496915 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::ReadExReq 1135852 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::ReadExResp 1114697 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5000799 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4556956 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::InvalidateReq 799366 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::InvalidateResp 748142 # Transaction distribution 1335system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15088134 # Packet count per connected master and slave (bytes) 1336system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17701155 # Packet count per connected master and slave (bytes) 1337system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 319339 # Packet count per connected master and slave (bytes) 1338system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542421 # Packet count per connected master and slave (bytes) 1339system.cpu0.toL2Bus.pkt_count::total 33651049 # Packet count per connected master and slave (bytes) 1340system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 640241940 # Cumulative packet size per connected master and slave (bytes) 1341system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663021135 # Cumulative packet size per connected master and slave (bytes) 1342system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1207824 # Cumulative packet size per connected master and slave (bytes) 1343system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1965272 # Cumulative packet size per connected master and slave (bytes) 1344system.cpu0.toL2Bus.pkt_size::total 1306436171 # Cumulative packet size per connected master and slave (bytes) 1345system.cpu0.toL2Bus.snoops 6076867 # Total snoops (count) 1346system.cpu0.toL2Bus.snoop_fanout::samples 17397758 # Request fanout histogram 1347system.cpu0.toL2Bus.snoop_fanout::mean 0.114750 # Request fanout histogram 1348system.cpu0.toL2Bus.snoop_fanout::stdev 0.318774 # Request fanout histogram 1349system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1350system.cpu0.toL2Bus.snoop_fanout::0 15401663 88.53% 88.53% # Request fanout histogram 1351system.cpu0.toL2Bus.snoop_fanout::1 1995797 11.47% 100.00% # Request fanout histogram 1352system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram 1353system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1354system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1355system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1356system.cpu0.toL2Bus.snoop_fanout::total 17397758 # Request fanout histogram 1357system.cpu0.toL2Bus.reqLayer0.occupancy 21478508994 # Layer occupancy (ticks) 1358system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1359system.cpu0.toL2Bus.snoopLayer0.occupancy 177190009 # Layer occupancy (ticks) 1360system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1361system.cpu0.toL2Bus.respLayer0.occupancy 7544323500 # Layer occupancy (ticks) 1362system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1363system.cpu0.toL2Bus.respLayer1.occupancy 7836374127 # Layer occupancy (ticks) 1364system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1365system.cpu0.toL2Bus.respLayer2.occupancy 168361000 # Layer occupancy (ticks) 1366system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1367system.cpu0.toL2Bus.respLayer3.occupancy 296762000 # Layer occupancy (ticks) 1368system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1369system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1370system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1371system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1372system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1373system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1374system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1375system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1376system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1377system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1378system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1379system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1380system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1381system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1382system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1383system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1384system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1385system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1386system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1387system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1388system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1389system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1390system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1391system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1392system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1393system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1394system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1395system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1396system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1397system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1398system.cpu1.dtb.walker.walks 108457 # Table walker walks requested 1399system.cpu1.dtb.walker.walksLong 108457 # Table walker walks initiated with long descriptors 1400system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9827 # Level at which table walker walks with long descriptors terminate 1401system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84631 # Level at which table walker walks with long descriptors terminate 1402system.cpu1.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 1403system.cpu1.dtb.walker.walkWaitTime::samples 108435 # Table walker wait (enqueue to first request) latency 1404system.cpu1.dtb.walker.walkWaitTime::mean 0.073777 # Table walker wait (enqueue to first request) latency 1405system.cpu1.dtb.walker.walkWaitTime::stdev 24.294348 # Table walker wait (enqueue to first request) latency 1406system.cpu1.dtb.walker.walkWaitTime::0-511 108434 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1407system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1408system.cpu1.dtb.walker.walkWaitTime::total 108435 # Table walker wait (enqueue to first request) latency 1409system.cpu1.dtb.walker.walkCompletionTime::samples 94480 # Table walker service (enqueue to completion) latency 1410system.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930 # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554 # Table walker service (enqueue to completion) latency 1412system.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287 # Table walker service (enqueue to completion) latency 1413system.cpu1.dtb.walker.walkCompletionTime::0-65535 93351 98.81% 98.81% # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::65536-131071 176 0.19% 98.99% # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walkCompletionTime::131072-196607 798 0.84% 99.84% # Table walker service (enqueue to completion) latency 1416system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.04% 99.88% # Table walker service (enqueue to completion) latency 1417system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.93% # Table walker service (enqueue to completion) latency 1418system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.03% 99.95% # Table walker service (enqueue to completion) latency 1419system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.03% 99.98% # Table walker service (enqueue to completion) latency 1420system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 1421system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 1422system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1423system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1424system.cpu1.dtb.walker.walkCompletionTime::total 94480 # Table walker service (enqueue to completion) latency 1425system.cpu1.dtb.walker.walksPending::samples 3353012192 # Table walker pending requests distribution 1426system.cpu1.dtb.walker.walksPending::mean 1.550742 # Table walker pending requests distribution 1427system.cpu1.dtb.walker.walksPending::0 -1846644332 -55.07% -55.07% # Table walker pending requests distribution 1428system.cpu1.dtb.walker.walksPending::1 5199656524 155.07% 100.00% # Table walker pending requests distribution 1429system.cpu1.dtb.walker.walksPending::total 3353012192 # Table walker pending requests distribution 1430system.cpu1.dtb.walker.walkPageSizes::4K 84631 89.60% 89.60% # Table walker page sizes translated 1431system.cpu1.dtb.walker.walkPageSizes::2M 9827 10.40% 100.00% # Table walker page sizes translated 1432system.cpu1.dtb.walker.walkPageSizes::total 94458 # Table walker page sizes translated 1433system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108457 # Table walker requests started/completed, data/inst 1434system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1435system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108457 # Table walker requests started/completed, data/inst 1436system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 94458 # Table walker requests started/completed, data/inst 1437system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1438system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 94458 # Table walker requests started/completed, data/inst 1439system.cpu1.dtb.walker.walkRequestOrigin::total 202915 # Table walker requests started/completed, data/inst 1440system.cpu1.dtb.inst_hits 0 # ITB inst hits 1441system.cpu1.dtb.inst_misses 0 # ITB inst misses 1442system.cpu1.dtb.read_hits 79507348 # DTB read hits 1443system.cpu1.dtb.read_misses 80723 # DTB read misses 1444system.cpu1.dtb.write_hits 72319570 # DTB write hits 1445system.cpu1.dtb.write_misses 27734 # DTB write misses 1446system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1447system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1448system.cpu1.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 1449system.cpu1.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 1450system.cpu1.dtb.flush_entries 39844 # Number of entries that have been flushed from TLB 1451system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1452system.cpu1.dtb.prefetch_faults 4607 # Number of TLB faults due to prefetch 1453system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1454system.cpu1.dtb.perms_faults 10580 # Number of TLB faults due to permissions restrictions 1455system.cpu1.dtb.read_accesses 79588071 # DTB read accesses 1456system.cpu1.dtb.write_accesses 72347304 # DTB write accesses 1457system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1458system.cpu1.dtb.hits 151826918 # DTB hits 1459system.cpu1.dtb.misses 108457 # DTB misses 1460system.cpu1.dtb.accesses 151935375 # DTB accesses 1461system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1462system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1463system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1464system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1465system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1466system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1467system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1468system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1469system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1470system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1471system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1472system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1473system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1474system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1475system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1476system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1477system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1478system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1479system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1480system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1481system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1482system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1483system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1484system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1485system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1486system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1487system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1488system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1489system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1490system.cpu1.itb.walker.walks 59789 # Table walker walks requested 1491system.cpu1.itb.walker.walksLong 59789 # Table walker walks initiated with long descriptors 1492system.cpu1.itb.walker.walksLongTerminationLevel::Level2 555 # Level at which table walker walks with long descriptors terminate 1493system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54230 # Level at which table walker walks with long descriptors terminate 1494system.cpu1.itb.walker.walkWaitTime::samples 59789 # Table walker wait (enqueue to first request) latency 1495system.cpu1.itb.walker.walkWaitTime::0 59789 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1496system.cpu1.itb.walker.walkWaitTime::total 59789 # Table walker wait (enqueue to first request) latency 1497system.cpu1.itb.walker.walkCompletionTime::samples 54785 # Table walker service (enqueue to completion) latency 1498system.cpu1.itb.walker.walkCompletionTime::mean 26806.178699 # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376 # Table walker service (enqueue to completion) latency 1500system.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406 # Table walker service (enqueue to completion) latency 1501system.cpu1.itb.walker.walkCompletionTime::0-65535 53612 97.86% 97.86% # Table walker service (enqueue to completion) latency 1502system.cpu1.itb.walker.walkCompletionTime::65536-131071 36 0.07% 97.92% # Table walker service (enqueue to completion) latency 1503system.cpu1.itb.walker.walkCompletionTime::131072-196607 992 1.81% 99.74% # Table walker service (enqueue to completion) latency 1504system.cpu1.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.79% # Table walker service (enqueue to completion) latency 1505system.cpu1.itb.walker.walkCompletionTime::262144-327679 57 0.10% 99.89% # Table walker service (enqueue to completion) latency 1506system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.91% # Table walker service (enqueue to completion) latency 1507system.cpu1.itb.walker.walkCompletionTime::393216-458751 37 0.07% 99.98% # Table walker service (enqueue to completion) latency 1508system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.98% # Table walker service (enqueue to completion) latency 1509system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1510system.cpu1.itb.walker.walkCompletionTime::589824-655359 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1511system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1512system.cpu1.itb.walker.walkCompletionTime::total 54785 # Table walker service (enqueue to completion) latency 1513system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution 1514system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution 1515system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution 1516system.cpu1.itb.walker.walkPageSizes::4K 54230 98.99% 98.99% # Table walker page sizes translated 1517system.cpu1.itb.walker.walkPageSizes::2M 555 1.01% 100.00% # Table walker page sizes translated 1518system.cpu1.itb.walker.walkPageSizes::total 54785 # Table walker page sizes translated 1519system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1520system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59789 # Table walker requests started/completed, data/inst 1521system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59789 # Table walker requests started/completed, data/inst 1522system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1523system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54785 # Table walker requests started/completed, data/inst 1524system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54785 # Table walker requests started/completed, data/inst 1525system.cpu1.itb.walker.walkRequestOrigin::total 114574 # Table walker requests started/completed, data/inst 1526system.cpu1.itb.inst_hits 420546617 # ITB inst hits 1527system.cpu1.itb.inst_misses 59789 # ITB inst misses 1528system.cpu1.itb.read_hits 0 # DTB read hits 1529system.cpu1.itb.read_misses 0 # DTB read misses 1530system.cpu1.itb.write_hits 0 # DTB write hits 1531system.cpu1.itb.write_misses 0 # DTB write misses 1532system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1533system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1534system.cpu1.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 1535system.cpu1.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 1536system.cpu1.itb.flush_entries 27682 # Number of entries that have been flushed from TLB 1537system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1538system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1539system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1540system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1541system.cpu1.itb.read_accesses 0 # DTB read accesses 1542system.cpu1.itb.write_accesses 0 # DTB write accesses 1543system.cpu1.itb.inst_accesses 420606406 # ITB inst accesses 1544system.cpu1.itb.hits 420546617 # DTB hits 1545system.cpu1.itb.misses 59789 # DTB misses 1546system.cpu1.itb.accesses 420606406 # DTB accesses 1547system.cpu1.numCycles 94920662633 # number of cpu cycles simulated 1548system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1549system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1550system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1551system.cpu1.kern.inst.quiesce 5531 # number of quiesce instructions executed 1552system.cpu1.committedInsts 420277684 # Number of instructions committed 1553system.cpu1.committedOps 495146949 # Number of ops (including micro ops) committed 1554system.cpu1.num_int_alu_accesses 454880180 # Number of integer alu accesses 1555system.cpu1.num_fp_alu_accesses 506575 # Number of float alu accesses 1556system.cpu1.num_func_calls 25039229 # number of times a function call or return occured 1557system.cpu1.num_conditional_control_insts 63957319 # number of instructions that are conditional controls 1558system.cpu1.num_int_insts 454880180 # number of integer instructions 1559system.cpu1.num_fp_insts 506575 # number of float instructions 1560system.cpu1.num_int_register_reads 664278142 # number of times the integer registers were read 1561system.cpu1.num_int_register_writes 361063382 # number of times the integer registers were written 1562system.cpu1.num_fp_register_reads 809640 # number of times the floating registers were read 1563system.cpu1.num_fp_register_writes 450820 # number of times the floating registers were written 1564system.cpu1.num_cc_register_reads 110083158 # number of times the CC registers were read 1565system.cpu1.num_cc_register_writes 109779727 # number of times the CC registers were written 1566system.cpu1.num_mem_refs 151817768 # number of memory refs 1567system.cpu1.num_load_insts 79504880 # Number of load instructions 1568system.cpu1.num_store_insts 72312888 # Number of store instructions 1569system.cpu1.num_idle_cycles 93883487625.302155 # Number of idle cycles 1570system.cpu1.num_busy_cycles 1037175007.697842 # Number of busy cycles 1571system.cpu1.not_idle_fraction 0.010927 # Percentage of non-idle cycles 1572system.cpu1.idle_fraction 0.989073 # Percentage of idle cycles 1573system.cpu1.Branches 93646526 # Number of branches fetched 1574system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1575system.cpu1.op_class::IntAlu 342430715 69.12% 69.12% # Class of executed instruction 1576system.cpu1.op_class::IntMult 1035788 0.21% 69.33% # Class of executed instruction 1577system.cpu1.op_class::IntDiv 58966 0.01% 69.34% # Class of executed instruction 1578system.cpu1.op_class::FloatAdd 0 0.00% 69.34% # Class of executed instruction 1579system.cpu1.op_class::FloatCmp 0 0.00% 69.34% # Class of executed instruction 1580system.cpu1.op_class::FloatCvt 0 0.00% 69.34% # Class of executed instruction 1581system.cpu1.op_class::FloatMult 0 0.00% 69.34% # Class of executed instruction 1582system.cpu1.op_class::FloatDiv 0 0.00% 69.34% # Class of executed instruction 1583system.cpu1.op_class::FloatSqrt 0 0.00% 69.34% # Class of executed instruction 1584system.cpu1.op_class::SimdAdd 0 0.00% 69.34% # Class of executed instruction 1585system.cpu1.op_class::SimdAddAcc 0 0.00% 69.34% # Class of executed instruction 1586system.cpu1.op_class::SimdAlu 0 0.00% 69.34% # Class of executed instruction 1587system.cpu1.op_class::SimdCmp 0 0.00% 69.34% # Class of executed instruction 1588system.cpu1.op_class::SimdCvt 0 0.00% 69.34% # Class of executed instruction 1589system.cpu1.op_class::SimdMisc 0 0.00% 69.34% # Class of executed instruction 1590system.cpu1.op_class::SimdMult 0 0.00% 69.34% # Class of executed instruction 1591system.cpu1.op_class::SimdMultAcc 0 0.00% 69.34% # Class of executed instruction 1592system.cpu1.op_class::SimdShift 0 0.00% 69.34% # Class of executed instruction 1593system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.34% # Class of executed instruction 1594system.cpu1.op_class::SimdSqrt 0 0.00% 69.34% # Class of executed instruction 1595system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.34% # Class of executed instruction 1596system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.34% # Class of executed instruction 1597system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.34% # Class of executed instruction 1598system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.34% # Class of executed instruction 1599system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.34% # Class of executed instruction 1600system.cpu1.op_class::SimdFloatMisc 72713 0.01% 69.36% # Class of executed instruction 1601system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction 1602system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction 1603system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction 1604system.cpu1.op_class::MemRead 79504880 16.05% 85.40% # Class of executed instruction 1605system.cpu1.op_class::MemWrite 72312888 14.60% 100.00% # Class of executed instruction 1606system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1607system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1608system.cpu1.op_class::total 495415992 # Class of executed instruction 1609system.cpu1.dcache.tags.replacements 5111729 # number of replacements 1610system.cpu1.dcache.tags.tagsinuse 453.815972 # Cycle average of tags in use 1611system.cpu1.dcache.tags.total_refs 146515734 # Total number of references to valid blocks. 1612system.cpu1.dcache.tags.sampled_refs 5112105 # Sample count of references to valid blocks. 1613system.cpu1.dcache.tags.avg_refs 28.660549 # Average number of references to valid blocks. 1614system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. 1615system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.815972 # Average occupied blocks per requestor 1616system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886359 # Average percentage of cache occupancy 1617system.cpu1.dcache.tags.occ_percent::total 0.886359 # Average percentage of cache occupancy 1618system.cpu1.dcache.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id 1619system.cpu1.dcache.tags.age_task_id_blocks_1024::2 373 # Occupied blocks per task id 1620system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 1621system.cpu1.dcache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 1622system.cpu1.dcache.tags.tag_accesses 308802786 # Number of tag accesses 1623system.cpu1.dcache.tags.data_accesses 308802786 # Number of data accesses 1624system.cpu1.dcache.ReadReq_hits::cpu1.data 74029008 # number of ReadReq hits 1625system.cpu1.dcache.ReadReq_hits::total 74029008 # number of ReadReq hits 1626system.cpu1.dcache.WriteReq_hits::cpu1.data 68561672 # number of WriteReq hits 1627system.cpu1.dcache.WriteReq_hits::total 68561672 # number of WriteReq hits 1628system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits 1629system.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits 1630system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits 1631system.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits 1632system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits 1633system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits 1634system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits 1635system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits 1636system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits 1637system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits 1638system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits 1639system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits 1640system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses 1641system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses 1642system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses 1643system.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses 1644system.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses 1645system.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses 1646system.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses 1647system.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses 1648system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses 1649system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses 1650system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses 1651system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses 1652system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses 1653system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses 1654system.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses 1655system.cpu1.dcache.overall_misses::total 4814576 # number of overall misses 1656system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles 1657system.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles 1658system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles 1659system.cpu1.dcache.WriteReq_miss_latency::total 30099423000 # number of WriteReq miss cycles 1660system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18095848000 # number of WriteLineReq miss cycles 1661system.cpu1.dcache.WriteLineReq_miss_latency::total 18095848000 # number of WriteLineReq miss cycles 1662system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2729020500 # number of LoadLockedReq miss cycles 1663system.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles 1664system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles 1665system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles 1666system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles 1667system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles 1668system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles 1669system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles 1670system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles 1671system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles 1672system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) 1673system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) 1674system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) 1675system.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) 1676system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) 1677system.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) 1678system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) 1679system.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) 1680system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) 1681system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) 1682system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) 1683system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) 1684system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses 1685system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses 1686system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses 1687system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses 1688system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses 1689system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses 1690system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses 1691system.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses 1692system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses 1693system.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses 1694system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses 1695system.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses 1696system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses 1697system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses 1698system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses 1699system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses 1700system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses 1701system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses 1702system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses 1703system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses 1704system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency 1705system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency 1706system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency 1707system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency 1708system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency 1709system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency 1710system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency 1711system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency 1712system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency 1713system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency 1714system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1715system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1716system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency 1717system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency 1718system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency 1719system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency 1720system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1721system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1722system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1723system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1724system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1725system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1726system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1727system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1728system.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks 1729system.cpu1.dcache.writebacks::total 5111729 # number of writebacks 1730system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits 1731system.cpu1.dcache.ReadReq_mshr_hits::total 16692 # number of ReadReq MSHR hits 1732system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 1734system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44979 # number of LoadLockedReq MSHR hits 1735system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44979 # number of LoadLockedReq MSHR hits 1736system.cpu1.dcache.demand_mshr_hits::cpu1.data 17094 # number of demand (read+write) MSHR hits 1737system.cpu1.dcache.demand_mshr_hits::total 17094 # number of demand (read+write) MSHR hits 1738system.cpu1.dcache.overall_mshr_hits::cpu1.data 17094 # number of overall MSHR hits 1739system.cpu1.dcache.overall_mshr_hits::total 17094 # number of overall MSHR hits 1740system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858353 # number of ReadReq MSHR misses 1741system.cpu1.dcache.ReadReq_mshr_misses::total 2858353 # number of ReadReq MSHR misses 1742system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1312828 # number of WriteReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::total 1312828 # number of WriteReq MSHR misses 1744system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses 1745system.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses 1746system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses 1747system.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses 1748system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 1749system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 1750system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses 1751system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses 1752system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses 1753system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses 1754system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses 1755system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses 1756system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 1757system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable 1758system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 1759system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 1760system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 1761system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses 1762system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles 1763system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles 1764system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28757951500 # number of WriteReq MSHR miss cycles 1765system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28757951500 # number of WriteReq MSHR miss cycles 1766system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14279978500 # number of SoftPFReq MSHR miss cycles 1767system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14279978500 # number of SoftPFReq MSHR miss cycles 1768system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles 1769system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles 1770system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles 1771system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles 1772system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles 1773system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles 1774system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles 1775system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles 1776system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles 1777system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles 1778system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles 1779system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles 1780system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles 1781system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles 1782system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles 1783system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles 1784system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles 1785system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles 1786system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses 1787system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses 1788system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses 1789system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses 1790system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses 1791system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses 1792system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses 1793system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses 1794system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses 1795system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses 1796system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses 1797system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses 1798system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses 1799system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses 1800system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses 1801system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses 1802system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency 1803system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency 1804system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency 1805system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency 1806system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency 1807system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency 1808system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency 1809system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency 1810system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency 1811system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency 1812system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency 1813system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency 1814system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1815system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1816system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency 1817system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency 1818system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency 1819system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency 1820system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency 1821system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency 1822system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency 1823system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency 1824system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency 1826system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1827system.cpu1.icache.tags.replacements 4920276 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_percent::total 0.968867 # Average percentage of cache occupancy 1836system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1837system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id 1839system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1840system.cpu1.icache.tags.tag_accesses 846014027 # Number of tag accesses 1841system.cpu1.icache.tags.data_accesses 846014027 # Number of data accesses 1842system.cpu1.icache.ReadReq_hits::cpu1.inst 415625824 # number of ReadReq hits 1843system.cpu1.icache.ReadReq_hits::total 415625824 # number of ReadReq hits 1844system.cpu1.icache.demand_hits::cpu1.inst 415625824 # number of demand (read+write) hits 1845system.cpu1.icache.demand_hits::total 415625824 # number of demand (read+write) hits 1846system.cpu1.icache.overall_hits::cpu1.inst 415625824 # number of overall hits 1847system.cpu1.icache.overall_hits::total 415625824 # number of overall hits 1848system.cpu1.icache.ReadReq_misses::cpu1.inst 4920793 # number of ReadReq misses 1849system.cpu1.icache.ReadReq_misses::total 4920793 # number of ReadReq misses 1850system.cpu1.icache.demand_misses::cpu1.inst 4920793 # number of demand (read+write) misses 1851system.cpu1.icache.demand_misses::total 4920793 # number of demand (read+write) misses 1852system.cpu1.icache.overall_misses::cpu1.inst 4920793 # number of overall misses 1853system.cpu1.icache.overall_misses::total 4920793 # number of overall misses 1854system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53750624000 # number of ReadReq miss cycles 1855system.cpu1.icache.ReadReq_miss_latency::total 53750624000 # number of ReadReq miss cycles 1856system.cpu1.icache.demand_miss_latency::cpu1.inst 53750624000 # number of demand (read+write) miss cycles 1857system.cpu1.icache.demand_miss_latency::total 53750624000 # number of demand (read+write) miss cycles 1858system.cpu1.icache.overall_miss_latency::cpu1.inst 53750624000 # number of overall miss cycles 1859system.cpu1.icache.overall_miss_latency::total 53750624000 # number of overall miss cycles 1860system.cpu1.icache.ReadReq_accesses::cpu1.inst 420546617 # number of ReadReq accesses(hits+misses) 1861system.cpu1.icache.ReadReq_accesses::total 420546617 # number of ReadReq accesses(hits+misses) 1862system.cpu1.icache.demand_accesses::cpu1.inst 420546617 # number of demand (read+write) accesses 1863system.cpu1.icache.demand_accesses::total 420546617 # number of demand (read+write) accesses 1864system.cpu1.icache.overall_accesses::cpu1.inst 420546617 # number of overall (read+write) accesses 1865system.cpu1.icache.overall_accesses::total 420546617 # number of overall (read+write) accesses 1866system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011701 # miss rate for ReadReq accesses 1867system.cpu1.icache.ReadReq_miss_rate::total 0.011701 # miss rate for ReadReq accesses 1868system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011701 # miss rate for demand accesses 1869system.cpu1.icache.demand_miss_rate::total 0.011701 # miss rate for demand accesses 1870system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011701 # miss rate for overall accesses 1871system.cpu1.icache.overall_miss_rate::total 0.011701 # miss rate for overall accesses 1872system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10923.162994 # average ReadReq miss latency 1873system.cpu1.icache.ReadReq_avg_miss_latency::total 10923.162994 # average ReadReq miss latency 1874system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 1875system.cpu1.icache.demand_avg_miss_latency::total 10923.162994 # average overall miss latency 1876system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 1877system.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency 1878system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1879system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1882system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1884system.cpu1.icache.fast_writes 0 # number of fast writes performed 1885system.cpu1.icache.cache_copies 0 # number of cache copies performed 1886system.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks 1887system.cpu1.icache.writebacks::total 4920276 # number of writebacks 1888system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # number of ReadReq MSHR misses 1889system.cpu1.icache.ReadReq_mshr_misses::total 4920793 # number of ReadReq MSHR misses 1890system.cpu1.icache.demand_mshr_misses::cpu1.inst 4920793 # number of demand (read+write) MSHR misses 1891system.cpu1.icache.demand_mshr_misses::total 4920793 # number of demand (read+write) MSHR misses 1892system.cpu1.icache.overall_mshr_misses::cpu1.inst 4920793 # number of overall MSHR misses 1893system.cpu1.icache.overall_mshr_misses::total 4920793 # number of overall MSHR misses 1894system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1895system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1896system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1897system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1898system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51290227500 # number of ReadReq MSHR miss cycles 1899system.cpu1.icache.ReadReq_mshr_miss_latency::total 51290227500 # number of ReadReq MSHR miss cycles 1900system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51290227500 # number of demand (read+write) MSHR miss cycles 1901system.cpu1.icache.demand_mshr_miss_latency::total 51290227500 # number of demand (read+write) MSHR miss cycles 1902system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51290227500 # number of overall MSHR miss cycles 1903system.cpu1.icache.overall_mshr_miss_latency::total 51290227500 # number of overall MSHR miss cycles 1904system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14763500 # number of ReadReq MSHR uncacheable cycles 1905system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14763500 # number of ReadReq MSHR uncacheable cycles 1906system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14763500 # number of overall MSHR uncacheable cycles 1907system.cpu1.icache.overall_mshr_uncacheable_latency::total 14763500 # number of overall MSHR uncacheable cycles 1908system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for ReadReq accesses 1909system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011701 # mshr miss rate for ReadReq accesses 1910system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for demand accesses 1911system.cpu1.icache.demand_mshr_miss_rate::total 0.011701 # mshr miss rate for demand accesses 1912system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for overall accesses 1913system.cpu1.icache.overall_mshr_miss_rate::total 0.011701 # mshr miss rate for overall accesses 1914system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average ReadReq mshr miss latency 1915system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10423.162994 # average ReadReq mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1917system.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1919system.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency 1923system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency 1924system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1925system.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued 1926system.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified 1927system.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue 1928system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1929system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1930system.cpu1.l2cache.prefetcher.pfSpanPage 877146 # number of prefetches not generated due to page crossing 1931system.cpu1.l2cache.tags.replacements 1947890 # number of replacements 1932system.cpu1.l2cache.tags.tagsinuse 13258.686630 # Cycle average of tags in use 1933system.cpu1.l2cache.tags.total_refs 14658232 # Total number of references to valid blocks. 1934system.cpu1.l2cache.tags.sampled_refs 1963173 # Sample count of references to valid blocks. 1935system.cpu1.l2cache.tags.avg_refs 7.466602 # Average number of references to valid blocks. 1936system.cpu1.l2cache.tags.warmup_cycle 10431898029000 # Cycle when the warmup percentage was hit. 1937system.cpu1.l2cache.tags.occ_blocks::writebacks 12337.010876 # Average occupied blocks per requestor 1938system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.483445 # Average occupied blocks per requestor 1939system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.799198 # Average occupied blocks per requestor 1940system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 783.393111 # Average occupied blocks per requestor 1941system.cpu1.l2cache.tags.occ_percent::writebacks 0.752991 # Average percentage of cache occupancy 1942system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003936 # Average percentage of cache occupancy 1943system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004504 # Average percentage of cache occupancy 1944system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.047815 # Average percentage of cache occupancy 1945system.cpu1.l2cache.tags.occ_percent::total 0.809246 # Average percentage of cache occupancy 1946system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1528 # Occupied blocks per task id 1947system.cpu1.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 1948system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13687 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 43 # Occupied blocks per task id 1950system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 698 # Occupied blocks per task id 1951system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 787 # Occupied blocks per task id 1952system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id 1953system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 29 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 680 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6525 # Occupied blocks per task id 1956system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6482 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.093262 # Percentage of cache occupancy per task id 1958system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 1959system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.835388 # Percentage of cache occupancy per task id 1960system.cpu1.l2cache.tags.tag_accesses 340572805 # Number of tag accesses 1961system.cpu1.l2cache.tags.data_accesses 340572805 # Number of data accesses 1962system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 256581 # number of ReadReq hits 1963system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155471 # number of ReadReq hits 1964system.cpu1.l2cache.ReadReq_hits::total 412052 # number of ReadReq hits 1965system.cpu1.l2cache.WritebackDirty_hits::writebacks 3259472 # number of WritebackDirty hits 1966system.cpu1.l2cache.WritebackDirty_hits::total 3259472 # number of WritebackDirty hits 1967system.cpu1.l2cache.WritebackClean_hits::writebacks 6771640 # number of WritebackClean hits 1968system.cpu1.l2cache.WritebackClean_hits::total 6771640 # number of WritebackClean hits 1969system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 476 # number of UpgradeReq hits 1970system.cpu1.l2cache.UpgradeReq_hits::total 476 # number of UpgradeReq hits 1971system.cpu1.l2cache.ReadExReq_hits::cpu1.data 874528 # number of ReadExReq hits 1972system.cpu1.l2cache.ReadExReq_hits::total 874528 # number of ReadExReq hits 1973system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4470558 # number of ReadCleanReq hits 1974system.cpu1.l2cache.ReadCleanReq_hits::total 4470558 # number of ReadCleanReq hits 1975system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2746836 # number of ReadSharedReq hits 1976system.cpu1.l2cache.ReadSharedReq_hits::total 2746836 # number of ReadSharedReq hits 1977system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 216255 # number of InvalidateReq hits 1978system.cpu1.l2cache.InvalidateReq_hits::total 216255 # number of InvalidateReq hits 1979system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 256581 # number of demand (read+write) hits 1980system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155471 # number of demand (read+write) hits 1981system.cpu1.l2cache.demand_hits::cpu1.inst 4470558 # number of demand (read+write) hits 1982system.cpu1.l2cache.demand_hits::cpu1.data 3621364 # number of demand (read+write) hits 1983system.cpu1.l2cache.demand_hits::total 8503974 # number of demand (read+write) hits 1984system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 256581 # number of overall hits 1985system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155471 # number of overall hits 1986system.cpu1.l2cache.overall_hits::cpu1.inst 4470558 # number of overall hits 1987system.cpu1.l2cache.overall_hits::cpu1.data 3621364 # number of overall hits 1988system.cpu1.l2cache.overall_hits::total 8503974 # number of overall hits 1989system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9634 # number of ReadReq misses 1990system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8009 # number of ReadReq misses 1991system.cpu1.l2cache.ReadReq_misses::total 17643 # number of ReadReq misses 1992system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 195149 # number of UpgradeReq misses 1993system.cpu1.l2cache.UpgradeReq_misses::total 195149 # number of UpgradeReq misses 1994system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193373 # number of SCUpgradeReq misses 1995system.cpu1.l2cache.SCUpgradeReq_misses::total 193373 # number of SCUpgradeReq misses 1996system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 14 # number of SCUpgradeFailReq misses 1997system.cpu1.l2cache.SCUpgradeFailReq_misses::total 14 # number of SCUpgradeFailReq misses 1998system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244689 # number of ReadExReq misses 1999system.cpu1.l2cache.ReadExReq_misses::total 244689 # number of ReadExReq misses 2000system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 450235 # number of ReadCleanReq misses 2001system.cpu1.l2cache.ReadCleanReq_misses::total 450235 # number of ReadCleanReq misses 2002system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 858358 # number of ReadSharedReq misses 2003system.cpu1.l2cache.ReadSharedReq_misses::total 858358 # number of ReadSharedReq misses 2004system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265386 # number of InvalidateReq misses 2005system.cpu1.l2cache.InvalidateReq_misses::total 265386 # number of InvalidateReq misses 2006system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9634 # number of demand (read+write) misses 2007system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8009 # number of demand (read+write) misses 2008system.cpu1.l2cache.demand_misses::cpu1.inst 450235 # number of demand (read+write) misses 2009system.cpu1.l2cache.demand_misses::cpu1.data 1103047 # number of demand (read+write) misses 2010system.cpu1.l2cache.demand_misses::total 1570925 # number of demand (read+write) misses 2011system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9634 # number of overall misses 2012system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8009 # number of overall misses 2013system.cpu1.l2cache.overall_misses::cpu1.inst 450235 # number of overall misses 2014system.cpu1.l2cache.overall_misses::cpu1.data 1103047 # number of overall misses 2015system.cpu1.l2cache.overall_misses::total 1570925 # number of overall misses 2016system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 459999000 # number of ReadReq miss cycles 2017system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 417305500 # number of ReadReq miss cycles 2018system.cpu1.l2cache.ReadReq_miss_latency::total 877304500 # number of ReadReq miss cycles 2019system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3163875000 # number of UpgradeReq miss cycles 2020system.cpu1.l2cache.UpgradeReq_miss_latency::total 3163875000 # number of UpgradeReq miss cycles 2021system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2039332500 # number of SCUpgradeReq miss cycles 2022system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2039332500 # number of SCUpgradeReq miss cycles 2023system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6154498 # number of SCUpgradeFailReq miss cycles 2024system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6154498 # number of SCUpgradeFailReq miss cycles 2025system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13641270998 # number of ReadExReq miss cycles 2026system.cpu1.l2cache.ReadExReq_miss_latency::total 13641270998 # number of ReadExReq miss cycles 2027system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17048494000 # number of ReadCleanReq miss cycles 2028system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17048494000 # number of ReadCleanReq miss cycles 2029system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33667115000 # number of ReadSharedReq miss cycles 2030system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33667115000 # number of ReadSharedReq miss cycles 2031system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 534332000 # number of InvalidateReq miss cycles 2032system.cpu1.l2cache.InvalidateReq_miss_latency::total 534332000 # number of InvalidateReq miss cycles 2033system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 459999000 # number of demand (read+write) miss cycles 2034system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 417305500 # number of demand (read+write) miss cycles 2035system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17048494000 # number of demand (read+write) miss cycles 2036system.cpu1.l2cache.demand_miss_latency::cpu1.data 47308385998 # number of demand (read+write) miss cycles 2037system.cpu1.l2cache.demand_miss_latency::total 65234184498 # number of demand (read+write) miss cycles 2038system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 459999000 # number of overall miss cycles 2039system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 417305500 # number of overall miss cycles 2040system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17048494000 # number of overall miss cycles 2041system.cpu1.l2cache.overall_miss_latency::cpu1.data 47308385998 # number of overall miss cycles 2042system.cpu1.l2cache.overall_miss_latency::total 65234184498 # number of overall miss cycles 2043system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 266215 # number of ReadReq accesses(hits+misses) 2044system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163480 # number of ReadReq accesses(hits+misses) 2045system.cpu1.l2cache.ReadReq_accesses::total 429695 # number of ReadReq accesses(hits+misses) 2046system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3259472 # number of WritebackDirty accesses(hits+misses) 2047system.cpu1.l2cache.WritebackDirty_accesses::total 3259472 # number of WritebackDirty accesses(hits+misses) 2048system.cpu1.l2cache.WritebackClean_accesses::writebacks 6771640 # number of WritebackClean accesses(hits+misses) 2049system.cpu1.l2cache.WritebackClean_accesses::total 6771640 # number of WritebackClean accesses(hits+misses) 2050system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 195625 # number of UpgradeReq accesses(hits+misses) 2051system.cpu1.l2cache.UpgradeReq_accesses::total 195625 # number of UpgradeReq accesses(hits+misses) 2052system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193373 # number of SCUpgradeReq accesses(hits+misses) 2053system.cpu1.l2cache.SCUpgradeReq_accesses::total 193373 # number of SCUpgradeReq accesses(hits+misses) 2054system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 14 # number of SCUpgradeFailReq accesses(hits+misses) 2055system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 14 # number of SCUpgradeFailReq accesses(hits+misses) 2056system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119217 # number of ReadExReq accesses(hits+misses) 2057system.cpu1.l2cache.ReadExReq_accesses::total 1119217 # number of ReadExReq accesses(hits+misses) 2058system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4920793 # number of ReadCleanReq accesses(hits+misses) 2059system.cpu1.l2cache.ReadCleanReq_accesses::total 4920793 # number of ReadCleanReq accesses(hits+misses) 2060system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3605194 # number of ReadSharedReq accesses(hits+misses) 2061system.cpu1.l2cache.ReadSharedReq_accesses::total 3605194 # number of ReadSharedReq accesses(hits+misses) 2062system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 481641 # number of InvalidateReq accesses(hits+misses) 2063system.cpu1.l2cache.InvalidateReq_accesses::total 481641 # number of InvalidateReq accesses(hits+misses) 2064system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 266215 # number of demand (read+write) accesses 2065system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163480 # number of demand (read+write) accesses 2066system.cpu1.l2cache.demand_accesses::cpu1.inst 4920793 # number of demand (read+write) accesses 2067system.cpu1.l2cache.demand_accesses::cpu1.data 4724411 # number of demand (read+write) accesses 2068system.cpu1.l2cache.demand_accesses::total 10074899 # number of demand (read+write) accesses 2069system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 266215 # number of overall (read+write) accesses 2070system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163480 # number of overall (read+write) accesses 2071system.cpu1.l2cache.overall_accesses::cpu1.inst 4920793 # number of overall (read+write) accesses 2072system.cpu1.l2cache.overall_accesses::cpu1.data 4724411 # number of overall (read+write) accesses 2073system.cpu1.l2cache.overall_accesses::total 10074899 # number of overall (read+write) accesses 2074system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for ReadReq accesses 2075system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048991 # miss rate for ReadReq accesses 2076system.cpu1.l2cache.ReadReq_miss_rate::total 0.041059 # miss rate for ReadReq accesses 2077system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997567 # miss rate for UpgradeReq accesses 2078system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997567 # miss rate for UpgradeReq accesses 2079system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2080system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2081system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2082system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2083system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.218625 # miss rate for ReadExReq accesses 2084system.cpu1.l2cache.ReadExReq_miss_rate::total 0.218625 # miss rate for ReadExReq accesses 2085system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091496 # miss rate for ReadCleanReq accesses 2086system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091496 # miss rate for ReadCleanReq accesses 2087system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.238089 # miss rate for ReadSharedReq accesses 2088system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.238089 # miss rate for ReadSharedReq accesses 2089system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.551004 # miss rate for InvalidateReq accesses 2090system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.551004 # miss rate for InvalidateReq accesses 2091system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for demand accesses 2092system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048991 # miss rate for demand accesses 2093system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091496 # miss rate for demand accesses 2094system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.233478 # miss rate for demand accesses 2095system.cpu1.l2cache.demand_miss_rate::total 0.155925 # miss rate for demand accesses 2096system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for overall accesses 2097system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048991 # miss rate for overall accesses 2098system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091496 # miss rate for overall accesses 2099system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.233478 # miss rate for overall accesses 2100system.cpu1.l2cache.overall_miss_rate::total 0.155925 # miss rate for overall accesses 2101system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average ReadReq miss latency 2102system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 52104.569859 # average ReadReq miss latency 2103system.cpu1.l2cache.ReadReq_avg_miss_latency::total 49725.358499 # average ReadReq miss latency 2104system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16212.611902 # average UpgradeReq miss latency 2105system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16212.611902 # average UpgradeReq miss latency 2106system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10546.107781 # average SCUpgradeReq miss latency 2107system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10546.107781 # average SCUpgradeReq miss latency 2108system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 439607 # average SCUpgradeFailReq miss latency 2109system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 439607 # average SCUpgradeFailReq miss latency 2110system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55749.424772 # average ReadExReq miss latency 2111system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55749.424772 # average ReadExReq miss latency 2112system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37865.767877 # average ReadCleanReq miss latency 2113system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37865.767877 # average ReadCleanReq miss latency 2114system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39222.696124 # average ReadSharedReq miss latency 2115system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39222.696124 # average ReadSharedReq miss latency 2116system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2013.414423 # average InvalidateReq miss latency 2117system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2013.414423 # average InvalidateReq miss latency 2118system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average overall miss latency 2119system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 52104.569859 # average overall miss latency 2120system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37865.767877 # average overall miss latency 2121system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 2122system.cpu1.l2cache.demand_avg_miss_latency::total 41525.970048 # average overall miss latency 2123system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average overall miss latency 2124system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 52104.569859 # average overall miss latency 2125system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37865.767877 # average overall miss latency 2126system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 2127system.cpu1.l2cache.overall_avg_miss_latency::total 41525.970048 # average overall miss latency 2128system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2129system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2130system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2131system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2132system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2133system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2134system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2135system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2136system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks 2137system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks 2138system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits 2139system.cpu1.l2cache.ReadExReq_mshr_hits::total 6962 # number of ReadExReq MSHR hits 2140system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 454 # number of ReadSharedReq MSHR hits 2141system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 454 # number of ReadSharedReq MSHR hits 2142system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 2143system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 2144system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7416 # number of demand (read+write) MSHR hits 2145system.cpu1.l2cache.demand_mshr_hits::total 7416 # number of demand (read+write) MSHR hits 2146system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7416 # number of overall MSHR hits 2147system.cpu1.l2cache.overall_mshr_hits::total 7416 # number of overall MSHR hits 2148system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9634 # number of ReadReq MSHR misses 2149system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8009 # number of ReadReq MSHR misses 2150system.cpu1.l2cache.ReadReq_mshr_misses::total 17643 # number of ReadReq MSHR misses 2151system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688811 # number of HardPFReq MSHR misses 2152system.cpu1.l2cache.HardPFReq_mshr_misses::total 688811 # number of HardPFReq MSHR misses 2153system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 195149 # number of UpgradeReq MSHR misses 2154system.cpu1.l2cache.UpgradeReq_mshr_misses::total 195149 # number of UpgradeReq MSHR misses 2155system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193373 # number of SCUpgradeReq MSHR misses 2156system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193373 # number of SCUpgradeReq MSHR misses 2157system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 14 # number of SCUpgradeFailReq MSHR misses 2158system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 14 # number of SCUpgradeFailReq MSHR misses 2159system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237727 # number of ReadExReq MSHR misses 2160system.cpu1.l2cache.ReadExReq_mshr_misses::total 237727 # number of ReadExReq MSHR misses 2161system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 450235 # number of ReadCleanReq MSHR misses 2162system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 450235 # number of ReadCleanReq MSHR misses 2163system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 857904 # number of ReadSharedReq MSHR misses 2164system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 857904 # number of ReadSharedReq MSHR misses 2165system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 265385 # number of InvalidateReq MSHR misses 2166system.cpu1.l2cache.InvalidateReq_mshr_misses::total 265385 # number of InvalidateReq MSHR misses 2167system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9634 # number of demand (read+write) MSHR misses 2168system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8009 # number of demand (read+write) MSHR misses 2169system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 450235 # number of demand (read+write) MSHR misses 2170system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1095631 # number of demand (read+write) MSHR misses 2171system.cpu1.l2cache.demand_mshr_misses::total 1563509 # number of demand (read+write) MSHR misses 2172system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9634 # number of overall MSHR misses 2173system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8009 # number of overall MSHR misses 2174system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 450235 # number of overall MSHR misses 2175system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1095631 # number of overall MSHR misses 2176system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688811 # number of overall MSHR misses 2177system.cpu1.l2cache.overall_mshr_misses::total 2252320 # number of overall MSHR misses 2178system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2179system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 2180system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8821 # number of ReadReq MSHR uncacheable 2181system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 2182system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 2183system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2184system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 2185system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17914 # number of overall MSHR uncacheable misses 2186system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of ReadReq MSHR miss cycles 2187system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369251500 # number of ReadReq MSHR miss cycles 2188system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 771446500 # number of ReadReq MSHR miss cycles 2189system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of HardPFReq MSHR miss cycles 2190system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40532964082 # number of HardPFReq MSHR miss cycles 2191system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6306578500 # number of UpgradeReq MSHR miss cycles 2192system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6306578500 # number of UpgradeReq MSHR miss cycles 2193system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3905504500 # number of SCUpgradeReq MSHR miss cycles 2194system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3905504500 # number of SCUpgradeReq MSHR miss cycles 2195system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5728498 # number of SCUpgradeFailReq MSHR miss cycles 2196system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5728498 # number of SCUpgradeFailReq MSHR miss cycles 2197system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11332534498 # number of ReadExReq MSHR miss cycles 2198system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11332534498 # number of ReadExReq MSHR miss cycles 2199system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14347084000 # number of ReadCleanReq MSHR miss cycles 2200system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14347084000 # number of ReadCleanReq MSHR miss cycles 2201system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28473868000 # number of ReadSharedReq MSHR miss cycles 2202system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28473868000 # number of ReadSharedReq MSHR miss cycles 2203system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13840214500 # number of InvalidateReq MSHR miss cycles 2204system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13840214500 # number of InvalidateReq MSHR miss cycles 2205system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of demand (read+write) MSHR miss cycles 2206system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369251500 # number of demand (read+write) MSHR miss cycles 2207system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14347084000 # number of demand (read+write) MSHR miss cycles 2208system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39806402498 # number of demand (read+write) MSHR miss cycles 2209system.cpu1.l2cache.demand_mshr_miss_latency::total 54924932998 # number of demand (read+write) MSHR miss cycles 2210system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of overall MSHR miss cycles 2211system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369251500 # number of overall MSHR miss cycles 2212system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14347084000 # number of overall MSHR miss cycles 2213system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39806402498 # number of overall MSHR miss cycles 2214system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of overall MSHR miss cycles 2215system.cpu1.l2cache.overall_mshr_miss_latency::total 95457897080 # number of overall MSHR miss cycles 2216system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles 2217system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1390451500 # number of ReadReq MSHR uncacheable cycles 2218system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1404390000 # number of ReadReq MSHR uncacheable cycles 2219system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles 2220system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles 2221system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles 2222system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles 2223system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles 2224system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses 2225system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses 2226system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses 2227system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2228system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2229system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses 2230system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses 2231system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2232system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2233system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2234system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2235system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212405 # mshr miss rate for ReadExReq accesses 2236system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212405 # mshr miss rate for ReadExReq accesses 2237system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for ReadCleanReq accesses 2238system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091496 # mshr miss rate for ReadCleanReq accesses 2239system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.237963 # mshr miss rate for ReadSharedReq accesses 2240system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237963 # mshr miss rate for ReadSharedReq accesses 2241system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.551002 # mshr miss rate for InvalidateReq accesses 2242system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.551002 # mshr miss rate for InvalidateReq accesses 2243system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for demand accesses 2244system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for demand accesses 2245system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for demand accesses 2246system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for demand accesses 2247system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155189 # mshr miss rate for demand accesses 2248system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for overall accesses 2249system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for overall accesses 2250system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for overall accesses 2251system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for overall accesses 2252system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2253system.cpu1.l2cache.overall_mshr_miss_rate::total 0.223558 # mshr miss rate for overall accesses 2254system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average ReadReq mshr miss latency 2255system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average ReadReq mshr miss latency 2256system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 43725.358499 # average ReadReq mshr miss latency 2257system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average HardPFReq mshr miss latency 2258system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58844.826929 # average HardPFReq mshr miss latency 2259system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32316.734905 # average UpgradeReq mshr miss latency 2260system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905 # average UpgradeReq mshr miss latency 2261system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531 # average SCUpgradeReq mshr miss latency 2262system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531 # average SCUpgradeReq mshr miss latency 2263system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571 # average SCUpgradeFailReq mshr miss latency 2264system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571 # average SCUpgradeFailReq mshr miss latency 2265system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889 # average ReadExReq mshr miss latency 2266system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889 # average ReadExReq mshr miss latency 2267system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average ReadCleanReq mshr miss latency 2268system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877 # average ReadCleanReq mshr miss latency 2269system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911 # average ReadSharedReq mshr miss latency 2270system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911 # average ReadSharedReq mshr miss latency 2271system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317 # average InvalidateReq mshr miss latency 2272system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317 # average InvalidateReq mshr miss latency 2273system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency 2274system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 2275system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 2276system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 2277system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040 # average overall mshr miss latency 2278system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency 2279system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 2280system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 2281system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 2282system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency 2283system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency 2284system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency 2285system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency 2286system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency 2287system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency 2288system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency 2289system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency 2290system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency 2291system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency 2292system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2293system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. 2294system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2295system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2296system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. 2297system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2298system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2299system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution 2300system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution 2301system.cpu1.toL2Bus.trans_dist::WriteReq 9093 # Transaction distribution 2302system.cpu1.toL2Bus.trans_dist::WriteResp 9093 # Transaction distribution 2303system.cpu1.toL2Bus.trans_dist::WritebackDirty 4367100 # Transaction distribution 2304system.cpu1.toL2Bus.trans_dist::WritebackClean 6772532 # Transaction distribution 2305system.cpu1.toL2Bus.trans_dist::CleanEvict 2206652 # Transaction distribution 2306system.cpu1.toL2Bus.trans_dist::HardPFReq 838220 # Transaction distribution 2307system.cpu1.toL2Bus.trans_dist::UpgradeReq 373270 # Transaction distribution 2308system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 349428 # Transaction distribution 2309system.cpu1.toL2Bus.trans_dist::UpgradeResp 455882 # Transaction distribution 2310system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 2311system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 2312system.cpu1.toL2Bus.trans_dist::ReadExReq 1149239 # Transaction distribution 2313system.cpu1.toL2Bus.trans_dist::ReadExResp 1127446 # Transaction distribution 2314system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4920793 # Transaction distribution 2315system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4454860 # Transaction distribution 2316system.cpu1.toL2Bus.trans_dist::InvalidateReq 528061 # Transaction distribution 2317system.cpu1.toL2Bus.trans_dist::InvalidateResp 481641 # Transaction distribution 2318system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14762082 # Packet count per connected master and slave (bytes) 2319system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16505656 # Packet count per connected master and slave (bytes) 2320system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 342155 # Packet count per connected master and slave (bytes) 2321system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 581136 # Packet count per connected master and slave (bytes) 2322system.cpu1.toL2Bus.pkt_count::total 32191029 # Packet count per connected master and slave (bytes) 2323system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 629828856 # Cumulative packet size per connected master and slave (bytes) 2324system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 636046096 # Cumulative packet size per connected master and slave (bytes) 2325system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1307840 # Cumulative packet size per connected master and slave (bytes) 2326system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2129720 # Cumulative packet size per connected master and slave (bytes) 2327system.cpu1.toL2Bus.pkt_size::total 1269312512 # Cumulative packet size per connected master and slave (bytes) 2328system.cpu1.toL2Bus.snoops 5644464 # Total snoops (count) 2329system.cpu1.toL2Bus.snoop_fanout::samples 16439738 # Request fanout histogram 2330system.cpu1.toL2Bus.snoop_fanout::mean 0.118176 # Request fanout histogram 2331system.cpu1.toL2Bus.snoop_fanout::stdev 0.322847 # Request fanout histogram 2332system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2333system.cpu1.toL2Bus.snoop_fanout::0 14497112 88.18% 88.18% # Request fanout histogram 2334system.cpu1.toL2Bus.snoop_fanout::1 1942467 11.82% 100.00% # Request fanout histogram 2335system.cpu1.toL2Bus.snoop_fanout::2 159 0.00% 100.00% # Request fanout histogram 2336system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2337system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2338system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2339system.cpu1.toL2Bus.snoop_fanout::total 16439738 # Request fanout histogram 2340system.cpu1.toL2Bus.reqLayer0.occupancy 20566237996 # Layer occupancy (ticks) 2341system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2342system.cpu1.toL2Bus.snoopLayer0.occupancy 185505924 # Layer occupancy (ticks) 2343system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2344system.cpu1.toL2Bus.respLayer0.occupancy 7381299500 # Layer occupancy (ticks) 2345system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2346system.cpu1.toL2Bus.respLayer1.occupancy 7535601373 # Layer occupancy (ticks) 2347system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2348system.cpu1.toL2Bus.respLayer2.occupancy 178675000 # Layer occupancy (ticks) 2349system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2350system.cpu1.toL2Bus.respLayer3.occupancy 314921000 # Layer occupancy (ticks) 2351system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2352system.iobus.trans_dist::ReadReq 40334 # Transaction distribution 2353system.iobus.trans_dist::ReadResp 40334 # Transaction distribution 2354system.iobus.trans_dist::WriteReq 136621 # Transaction distribution 2355system.iobus.trans_dist::WriteResp 136621 # Transaction distribution 2356system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) 2357system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2358system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2359system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2360system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2361system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2362system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2363system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2364system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2365system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2366system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2367system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2368system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2369system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) 2370system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) 2371system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) 2372system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2373system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2374system.iobus.pkt_count::total 353910 # Packet count per connected master and slave (bytes) 2375system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) 2376system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2377system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2378system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2379system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2380system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2381system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2382system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2383system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2384system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2385system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2386system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2387system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2388system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) 2389system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) 2390system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) 2391system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2392system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2393system.iobus.pkt_size::total 7496681 # Cumulative packet size per connected master and slave (bytes) 2394system.iobus.reqLayer0.occupancy 36912500 # Layer occupancy (ticks) 2395system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2396system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 2397system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2398system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) 2399system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2400system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2401system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2402system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 2403system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2404system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2405system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2406system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2407system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2408system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2409system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2410system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2411system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2412system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 2413system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2414system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2415system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2416system.iobus.reqLayer23.occupancy 26561500 # Layer occupancy (ticks) 2417system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2418system.iobus.reqLayer24.occupancy 37416000 # Layer occupancy (ticks) 2419system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2420system.iobus.reqLayer25.occupancy 567387857 # Layer occupancy (ticks) 2421system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2422system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) 2423system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2424system.iobus.respLayer3.occupancy 147910000 # Layer occupancy (ticks) 2425system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2426system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2427system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2428system.iocache.tags.replacements 115602 # number of replacements 2429system.iocache.tags.tagsinuse 11.206206 # Cycle average of tags in use 2430system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2431system.iocache.tags.sampled_refs 115618 # Sample count of references to valid blocks. 2432system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2433system.iocache.tags.warmup_cycle 9192082489000 # Cycle when the warmup percentage was hit. 2434system.iocache.tags.occ_blocks::realview.ethernet 7.403530 # Average occupied blocks per requestor 2435system.iocache.tags.occ_blocks::realview.ide 3.802676 # Average occupied blocks per requestor 2436system.iocache.tags.occ_percent::realview.ethernet 0.462721 # Average percentage of cache occupancy 2437system.iocache.tags.occ_percent::realview.ide 0.237667 # Average percentage of cache occupancy 2438system.iocache.tags.occ_percent::total 0.700388 # Average percentage of cache occupancy 2439system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2440system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2441system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2442system.iocache.tags.tag_accesses 1040820 # Number of tag accesses 2443system.iocache.tags.data_accesses 1040820 # Number of data accesses 2444system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2445system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses 2446system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses 2447system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2448system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2449system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2450system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2451system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2452system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses 2453system.iocache.demand_misses::total 8919 # number of demand (read+write) misses 2454system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2455system.iocache.overall_misses::realview.ide 8879 # number of overall misses 2456system.iocache.overall_misses::total 8919 # number of overall misses 2457system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2458system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles 2459system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles 2460system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2461system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2462system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles 2463system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles 2464system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2465system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles 2466system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles 2467system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2468system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles 2469system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles 2470system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2471system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) 2472system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) 2473system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2474system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2475system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2476system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2477system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2478system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses 2479system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses 2480system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2481system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses 2482system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses 2483system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2484system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2485system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2486system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2487system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2488system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2489system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2490system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2491system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2492system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2493system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2494system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2495system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2496system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2497system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency 2498system.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency 2499system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2500system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2501system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency 2502system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency 2503system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2504system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 2505system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency 2506system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2507system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 2508system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency 2509system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked 2510system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2511system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked 2512system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2513system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked 2514system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2515system.iocache.fast_writes 0 # number of fast writes performed 2516system.iocache.cache_copies 0 # number of cache copies performed 2517system.iocache.writebacks::writebacks 106693 # number of writebacks 2518system.iocache.writebacks::total 106693 # number of writebacks 2519system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2520system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses 2521system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses 2522system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2523system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2524system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2525system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2526system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2527system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses 2528system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses 2529system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2530system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses 2531system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses 2532system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2533system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles 2534system.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles 2535system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2536system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2537system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles 2538system.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles 2539system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2540system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles 2541system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles 2542system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2543system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles 2544system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles 2545system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2546system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2547system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2548system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2549system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2550system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2551system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2552system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2553system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2554system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2555system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2556system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2557system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2558system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2559system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787 # average ReadReq mshr miss latency 2560system.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237 # average ReadReq mshr miss latency 2561system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2562system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2563system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency 2564system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency 2565system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2566system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 2567system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency 2568system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2569system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 2570system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency 2571system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2572system.l2c.tags.replacements 1288575 # number of replacements 2573system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use 2574system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. 2575system.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. 2576system.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. 2577system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. 2578system.l2c.tags.occ_blocks::writebacks 24026.415823 # Average occupied blocks per requestor 2579system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.847205 # Average occupied blocks per requestor 2580system.l2c.tags.occ_blocks::cpu0.itb.walker 272.174490 # Average occupied blocks per requestor 2581system.l2c.tags.occ_blocks::cpu0.inst 3917.360352 # Average occupied blocks per requestor 2582system.l2c.tags.occ_blocks::cpu0.data 7074.037074 # Average occupied blocks per requestor 2583system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11678.333096 # Average occupied blocks per requestor 2584system.l2c.tags.occ_blocks::cpu1.dtb.walker 109.068959 # Average occupied blocks per requestor 2585system.l2c.tags.occ_blocks::cpu1.itb.walker 171.850259 # Average occupied blocks per requestor 2586system.l2c.tags.occ_blocks::cpu1.inst 3448.642027 # Average occupied blocks per requestor 2587system.l2c.tags.occ_blocks::cpu1.data 6022.848319 # Average occupied blocks per requestor 2588system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6430.905066 # Average occupied blocks per requestor 2589system.l2c.tags.occ_percent::writebacks 0.366614 # Average percentage of cache occupancy 2590system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002790 # Average percentage of cache occupancy 2591system.l2c.tags.occ_percent::cpu0.itb.walker 0.004153 # Average percentage of cache occupancy 2592system.l2c.tags.occ_percent::cpu0.inst 0.059774 # Average percentage of cache occupancy 2593system.l2c.tags.occ_percent::cpu0.data 0.107941 # Average percentage of cache occupancy 2594system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.178197 # Average percentage of cache occupancy 2595system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy 2596system.l2c.tags.occ_percent::cpu1.itb.walker 0.002622 # Average percentage of cache occupancy 2597system.l2c.tags.occ_percent::cpu1.inst 0.052622 # Average percentage of cache occupancy 2598system.l2c.tags.occ_percent::cpu1.data 0.091901 # Average percentage of cache occupancy 2599system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.098128 # Average percentage of cache occupancy 2600system.l2c.tags.occ_percent::total 0.966408 # Average percentage of cache occupancy 2601system.l2c.tags.occ_task_id_blocks::1022 9960 # Occupied blocks per task id 2602system.l2c.tags.occ_task_id_blocks::1023 230 # Occupied blocks per task id 2603system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id 2604system.l2c.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id 2605system.l2c.tags.age_task_id_blocks_1022::3 303 # Occupied blocks per task id 2606system.l2c.tags.age_task_id_blocks_1022::4 9611 # Occupied blocks per task id 2607system.l2c.tags.age_task_id_blocks_1023::4 230 # Occupied blocks per task id 2608system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 2609system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id 2610system.l2c.tags.age_task_id_blocks_1024::2 1722 # Occupied blocks per task id 2611system.l2c.tags.age_task_id_blocks_1024::3 5705 # Occupied blocks per task id 2612system.l2c.tags.age_task_id_blocks_1024::4 40867 # Occupied blocks per task id 2613system.l2c.tags.occ_task_id_percent::1022 0.151978 # Percentage of cache occupancy per task id 2614system.l2c.tags.occ_task_id_percent::1023 0.003510 # Percentage of cache occupancy per task id 2615system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 2616system.l2c.tags.tag_accesses 68640564 # Number of tag accesses 2617system.l2c.tags.data_accesses 68640564 # Number of data accesses 2618system.l2c.WritebackDirty_hits::writebacks 2576614 # number of WritebackDirty hits 2619system.l2c.WritebackDirty_hits::total 2576614 # number of WritebackDirty hits 2620system.l2c.UpgradeReq_hits::cpu0.data 159474 # number of UpgradeReq hits 2621system.l2c.UpgradeReq_hits::cpu1.data 125945 # number of UpgradeReq hits 2622system.l2c.UpgradeReq_hits::total 285419 # number of UpgradeReq hits 2623system.l2c.SCUpgradeReq_hits::cpu0.data 36876 # number of SCUpgradeReq hits 2624system.l2c.SCUpgradeReq_hits::cpu1.data 37537 # number of SCUpgradeReq hits 2625system.l2c.SCUpgradeReq_hits::total 74413 # number of SCUpgradeReq hits 2626system.l2c.ReadExReq_hits::cpu0.data 50046 # number of ReadExReq hits 2627system.l2c.ReadExReq_hits::cpu1.data 51540 # number of ReadExReq hits 2628system.l2c.ReadExReq_hits::total 101586 # number of ReadExReq hits 2629system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5134 # number of ReadSharedReq hits 2630system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3916 # number of ReadSharedReq hits 2631system.l2c.ReadSharedReq_hits::cpu0.inst 411784 # number of ReadSharedReq hits 2632system.l2c.ReadSharedReq_hits::cpu0.data 545243 # number of ReadSharedReq hits 2633system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276625 # number of ReadSharedReq hits 2634system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5262 # number of ReadSharedReq hits 2635system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4295 # number of ReadSharedReq hits 2636system.l2c.ReadSharedReq_hits::cpu1.inst 410923 # number of ReadSharedReq hits 2637system.l2c.ReadSharedReq_hits::cpu1.data 516914 # number of ReadSharedReq hits 2638system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 270635 # number of ReadSharedReq hits 2639system.l2c.ReadSharedReq_hits::total 2450731 # number of ReadSharedReq hits 2640system.l2c.InvalidateReq_hits::cpu0.data 123087 # number of InvalidateReq hits 2641system.l2c.InvalidateReq_hits::cpu1.data 119603 # number of InvalidateReq hits 2642system.l2c.InvalidateReq_hits::total 242690 # number of InvalidateReq hits 2643system.l2c.demand_hits::cpu0.dtb.walker 5134 # number of demand (read+write) hits 2644system.l2c.demand_hits::cpu0.itb.walker 3916 # number of demand (read+write) hits 2645system.l2c.demand_hits::cpu0.inst 411784 # number of demand (read+write) hits 2646system.l2c.demand_hits::cpu0.data 595289 # number of demand (read+write) hits 2647system.l2c.demand_hits::cpu0.l2cache.prefetcher 276625 # number of demand (read+write) hits 2648system.l2c.demand_hits::cpu1.dtb.walker 5262 # number of demand (read+write) hits 2649system.l2c.demand_hits::cpu1.itb.walker 4295 # number of demand (read+write) hits 2650system.l2c.demand_hits::cpu1.inst 410923 # number of demand (read+write) hits 2651system.l2c.demand_hits::cpu1.data 568454 # number of demand (read+write) hits 2652system.l2c.demand_hits::cpu1.l2cache.prefetcher 270635 # number of demand (read+write) hits 2653system.l2c.demand_hits::total 2552317 # number of demand (read+write) hits 2654system.l2c.overall_hits::cpu0.dtb.walker 5134 # number of overall hits 2655system.l2c.overall_hits::cpu0.itb.walker 3916 # number of overall hits 2656system.l2c.overall_hits::cpu0.inst 411784 # number of overall hits 2657system.l2c.overall_hits::cpu0.data 595289 # number of overall hits 2658system.l2c.overall_hits::cpu0.l2cache.prefetcher 276625 # number of overall hits 2659system.l2c.overall_hits::cpu1.dtb.walker 5262 # number of overall hits 2660system.l2c.overall_hits::cpu1.itb.walker 4295 # number of overall hits 2661system.l2c.overall_hits::cpu1.inst 410923 # number of overall hits 2662system.l2c.overall_hits::cpu1.data 568454 # number of overall hits 2663system.l2c.overall_hits::cpu1.l2cache.prefetcher 270635 # number of overall hits 2664system.l2c.overall_hits::total 2552317 # number of overall hits 2665system.l2c.UpgradeReq_misses::cpu0.data 60660 # number of UpgradeReq misses 2666system.l2c.UpgradeReq_misses::cpu1.data 57967 # number of UpgradeReq misses 2667system.l2c.UpgradeReq_misses::total 118627 # number of UpgradeReq misses 2668system.l2c.SCUpgradeReq_misses::cpu0.data 11966 # number of SCUpgradeReq misses 2669system.l2c.SCUpgradeReq_misses::cpu1.data 14089 # number of SCUpgradeReq misses 2670system.l2c.SCUpgradeReq_misses::total 26055 # number of SCUpgradeReq misses 2671system.l2c.ReadExReq_misses::cpu0.data 73366 # number of ReadExReq misses 2672system.l2c.ReadExReq_misses::cpu1.data 52915 # number of ReadExReq misses 2673system.l2c.ReadExReq_misses::total 126281 # number of ReadExReq misses 2674system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1280 # number of ReadSharedReq misses 2675system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1221 # number of ReadSharedReq misses 2676system.l2c.ReadSharedReq_misses::cpu0.inst 47163 # number of ReadSharedReq misses 2677system.l2c.ReadSharedReq_misses::cpu0.data 114217 # number of ReadSharedReq misses 2678system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 194151 # number of ReadSharedReq misses 2679system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1808 # number of ReadSharedReq misses 2680system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1830 # number of ReadSharedReq misses 2681system.l2c.ReadSharedReq_misses::cpu1.inst 39312 # number of ReadSharedReq misses 2682system.l2c.ReadSharedReq_misses::cpu1.data 102014 # number of ReadSharedReq misses 2683system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208359 # number of ReadSharedReq misses 2684system.l2c.ReadSharedReq_misses::total 711355 # number of ReadSharedReq misses 2685system.l2c.InvalidateReq_misses::cpu0.data 431001 # number of InvalidateReq misses 2686system.l2c.InvalidateReq_misses::cpu1.data 129981 # number of InvalidateReq misses 2687system.l2c.InvalidateReq_misses::total 560982 # number of InvalidateReq misses 2688system.l2c.demand_misses::cpu0.dtb.walker 1280 # number of demand (read+write) misses 2689system.l2c.demand_misses::cpu0.itb.walker 1221 # number of demand (read+write) misses 2690system.l2c.demand_misses::cpu0.inst 47163 # number of demand (read+write) misses 2691system.l2c.demand_misses::cpu0.data 187583 # number of demand (read+write) misses 2692system.l2c.demand_misses::cpu0.l2cache.prefetcher 194151 # number of demand (read+write) misses 2693system.l2c.demand_misses::cpu1.dtb.walker 1808 # number of demand (read+write) misses 2694system.l2c.demand_misses::cpu1.itb.walker 1830 # number of demand (read+write) misses 2695system.l2c.demand_misses::cpu1.inst 39312 # number of demand (read+write) misses 2696system.l2c.demand_misses::cpu1.data 154929 # number of demand (read+write) misses 2697system.l2c.demand_misses::cpu1.l2cache.prefetcher 208359 # number of demand (read+write) misses 2698system.l2c.demand_misses::total 837636 # number of demand (read+write) misses 2699system.l2c.overall_misses::cpu0.dtb.walker 1280 # number of overall misses 2700system.l2c.overall_misses::cpu0.itb.walker 1221 # number of overall misses 2701system.l2c.overall_misses::cpu0.inst 47163 # number of overall misses 2702system.l2c.overall_misses::cpu0.data 187583 # number of overall misses 2703system.l2c.overall_misses::cpu0.l2cache.prefetcher 194151 # number of overall misses 2704system.l2c.overall_misses::cpu1.dtb.walker 1808 # number of overall misses 2705system.l2c.overall_misses::cpu1.itb.walker 1830 # number of overall misses 2706system.l2c.overall_misses::cpu1.inst 39312 # number of overall misses 2707system.l2c.overall_misses::cpu1.data 154929 # number of overall misses 2708system.l2c.overall_misses::cpu1.l2cache.prefetcher 208359 # number of overall misses 2709system.l2c.overall_misses::total 837636 # number of overall misses 2710system.l2c.UpgradeReq_miss_latency::cpu0.data 923139500 # number of UpgradeReq miss cycles 2711system.l2c.UpgradeReq_miss_latency::cpu1.data 911457500 # number of UpgradeReq miss cycles 2712system.l2c.UpgradeReq_miss_latency::total 1834597000 # number of UpgradeReq miss cycles 2713system.l2c.SCUpgradeReq_miss_latency::cpu0.data 172867000 # number of SCUpgradeReq miss cycles 2714system.l2c.SCUpgradeReq_miss_latency::cpu1.data 183172000 # number of SCUpgradeReq miss cycles 2715system.l2c.SCUpgradeReq_miss_latency::total 356039000 # number of SCUpgradeReq miss cycles 2716system.l2c.ReadExReq_miss_latency::cpu0.data 10023511500 # number of ReadExReq miss cycles 2717system.l2c.ReadExReq_miss_latency::cpu1.data 7102572500 # number of ReadExReq miss cycles 2718system.l2c.ReadExReq_miss_latency::total 17126084000 # number of ReadExReq miss cycles 2719system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 179763500 # number of ReadSharedReq miss cycles 2720system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 168992000 # number of ReadSharedReq miss cycles 2721system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6377154500 # number of ReadSharedReq miss cycles 2722system.l2c.ReadSharedReq_miss_latency::cpu0.data 15730524500 # number of ReadSharedReq miss cycles 2723system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of ReadSharedReq miss cycles 2724system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 254502500 # number of ReadSharedReq miss cycles 2725system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 255185000 # number of ReadSharedReq miss cycles 2726system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5294694000 # number of ReadSharedReq miss cycles 2727system.l2c.ReadSharedReq_miss_latency::cpu1.data 14274314499 # number of ReadSharedReq miss cycles 2728system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of ReadSharedReq miss cycles 2729system.l2c.ReadSharedReq_miss_latency::total 110856686244 # number of ReadSharedReq miss cycles 2730system.l2c.InvalidateReq_miss_latency::cpu0.data 147802000 # number of InvalidateReq miss cycles 2731system.l2c.InvalidateReq_miss_latency::cpu1.data 150755500 # number of InvalidateReq miss cycles 2732system.l2c.InvalidateReq_miss_latency::total 298557500 # number of InvalidateReq miss cycles 2733system.l2c.demand_miss_latency::cpu0.dtb.walker 179763500 # number of demand (read+write) miss cycles 2734system.l2c.demand_miss_latency::cpu0.itb.walker 168992000 # number of demand (read+write) miss cycles 2735system.l2c.demand_miss_latency::cpu0.inst 6377154500 # number of demand (read+write) miss cycles 2736system.l2c.demand_miss_latency::cpu0.data 25754036000 # number of demand (read+write) miss cycles 2737system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of demand (read+write) miss cycles 2738system.l2c.demand_miss_latency::cpu1.dtb.walker 254502500 # number of demand (read+write) miss cycles 2739system.l2c.demand_miss_latency::cpu1.itb.walker 255185000 # number of demand (read+write) miss cycles 2740system.l2c.demand_miss_latency::cpu1.inst 5294694000 # number of demand (read+write) miss cycles 2741system.l2c.demand_miss_latency::cpu1.data 21376886999 # number of demand (read+write) miss cycles 2742system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of demand (read+write) miss cycles 2743system.l2c.demand_miss_latency::total 127982770244 # number of demand (read+write) miss cycles 2744system.l2c.overall_miss_latency::cpu0.dtb.walker 179763500 # number of overall miss cycles 2745system.l2c.overall_miss_latency::cpu0.itb.walker 168992000 # number of overall miss cycles 2746system.l2c.overall_miss_latency::cpu0.inst 6377154500 # number of overall miss cycles 2747system.l2c.overall_miss_latency::cpu0.data 25754036000 # number of overall miss cycles 2748system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of overall miss cycles 2749system.l2c.overall_miss_latency::cpu1.dtb.walker 254502500 # number of overall miss cycles 2750system.l2c.overall_miss_latency::cpu1.itb.walker 255185000 # number of overall miss cycles 2751system.l2c.overall_miss_latency::cpu1.inst 5294694000 # number of overall miss cycles 2752system.l2c.overall_miss_latency::cpu1.data 21376886999 # number of overall miss cycles 2753system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of overall miss cycles 2754system.l2c.overall_miss_latency::total 127982770244 # number of overall miss cycles 2755system.l2c.WritebackDirty_accesses::writebacks 2576614 # number of WritebackDirty accesses(hits+misses) 2756system.l2c.WritebackDirty_accesses::total 2576614 # number of WritebackDirty accesses(hits+misses) 2757system.l2c.UpgradeReq_accesses::cpu0.data 220134 # number of UpgradeReq accesses(hits+misses) 2758system.l2c.UpgradeReq_accesses::cpu1.data 183912 # number of UpgradeReq accesses(hits+misses) 2759system.l2c.UpgradeReq_accesses::total 404046 # number of UpgradeReq accesses(hits+misses) 2760system.l2c.SCUpgradeReq_accesses::cpu0.data 48842 # number of SCUpgradeReq accesses(hits+misses) 2761system.l2c.SCUpgradeReq_accesses::cpu1.data 51626 # number of SCUpgradeReq accesses(hits+misses) 2762system.l2c.SCUpgradeReq_accesses::total 100468 # number of SCUpgradeReq accesses(hits+misses) 2763system.l2c.ReadExReq_accesses::cpu0.data 123412 # number of ReadExReq accesses(hits+misses) 2764system.l2c.ReadExReq_accesses::cpu1.data 104455 # number of ReadExReq accesses(hits+misses) 2765system.l2c.ReadExReq_accesses::total 227867 # number of ReadExReq accesses(hits+misses) 2766system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6414 # number of ReadSharedReq accesses(hits+misses) 2767system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5137 # number of ReadSharedReq accesses(hits+misses) 2768system.l2c.ReadSharedReq_accesses::cpu0.inst 458947 # number of ReadSharedReq accesses(hits+misses) 2769system.l2c.ReadSharedReq_accesses::cpu0.data 659460 # number of ReadSharedReq accesses(hits+misses) 2770system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 470776 # number of ReadSharedReq accesses(hits+misses) 2771system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7070 # number of ReadSharedReq accesses(hits+misses) 2772system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6125 # number of ReadSharedReq accesses(hits+misses) 2773system.l2c.ReadSharedReq_accesses::cpu1.inst 450235 # number of ReadSharedReq accesses(hits+misses) 2774system.l2c.ReadSharedReq_accesses::cpu1.data 618928 # number of ReadSharedReq accesses(hits+misses) 2775system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 478994 # number of ReadSharedReq accesses(hits+misses) 2776system.l2c.ReadSharedReq_accesses::total 3162086 # number of ReadSharedReq accesses(hits+misses) 2777system.l2c.InvalidateReq_accesses::cpu0.data 554088 # number of InvalidateReq accesses(hits+misses) 2778system.l2c.InvalidateReq_accesses::cpu1.data 249584 # number of InvalidateReq accesses(hits+misses) 2779system.l2c.InvalidateReq_accesses::total 803672 # number of InvalidateReq accesses(hits+misses) 2780system.l2c.demand_accesses::cpu0.dtb.walker 6414 # number of demand (read+write) accesses 2781system.l2c.demand_accesses::cpu0.itb.walker 5137 # number of demand (read+write) accesses 2782system.l2c.demand_accesses::cpu0.inst 458947 # number of demand (read+write) accesses 2783system.l2c.demand_accesses::cpu0.data 782872 # number of demand (read+write) accesses 2784system.l2c.demand_accesses::cpu0.l2cache.prefetcher 470776 # number of demand (read+write) accesses 2785system.l2c.demand_accesses::cpu1.dtb.walker 7070 # number of demand (read+write) accesses 2786system.l2c.demand_accesses::cpu1.itb.walker 6125 # number of demand (read+write) accesses 2787system.l2c.demand_accesses::cpu1.inst 450235 # number of demand (read+write) accesses 2788system.l2c.demand_accesses::cpu1.data 723383 # number of demand (read+write) accesses 2789system.l2c.demand_accesses::cpu1.l2cache.prefetcher 478994 # number of demand (read+write) accesses 2790system.l2c.demand_accesses::total 3389953 # number of demand (read+write) accesses 2791system.l2c.overall_accesses::cpu0.dtb.walker 6414 # number of overall (read+write) accesses 2792system.l2c.overall_accesses::cpu0.itb.walker 5137 # number of overall (read+write) accesses 2793system.l2c.overall_accesses::cpu0.inst 458947 # number of overall (read+write) accesses 2794system.l2c.overall_accesses::cpu0.data 782872 # number of overall (read+write) accesses 2795system.l2c.overall_accesses::cpu0.l2cache.prefetcher 470776 # number of overall (read+write) accesses 2796system.l2c.overall_accesses::cpu1.dtb.walker 7070 # number of overall (read+write) accesses 2797system.l2c.overall_accesses::cpu1.itb.walker 6125 # number of overall (read+write) accesses 2798system.l2c.overall_accesses::cpu1.inst 450235 # number of overall (read+write) accesses 2799system.l2c.overall_accesses::cpu1.data 723383 # number of overall (read+write) accesses 2800system.l2c.overall_accesses::cpu1.l2cache.prefetcher 478994 # number of overall (read+write) accesses 2801system.l2c.overall_accesses::total 3389953 # number of overall (read+write) accesses 2802system.l2c.UpgradeReq_miss_rate::cpu0.data 0.275559 # miss rate for UpgradeReq accesses 2803system.l2c.UpgradeReq_miss_rate::cpu1.data 0.315189 # miss rate for UpgradeReq accesses 2804system.l2c.UpgradeReq_miss_rate::total 0.293598 # miss rate for UpgradeReq accesses 2805system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.244994 # miss rate for SCUpgradeReq accesses 2806system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.272905 # miss rate for SCUpgradeReq accesses 2807system.l2c.SCUpgradeReq_miss_rate::total 0.259336 # miss rate for SCUpgradeReq accesses 2808system.l2c.ReadExReq_miss_rate::cpu0.data 0.594480 # miss rate for ReadExReq accesses 2809system.l2c.ReadExReq_miss_rate::cpu1.data 0.506582 # miss rate for ReadExReq accesses 2810system.l2c.ReadExReq_miss_rate::total 0.554187 # miss rate for ReadExReq accesses 2811system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for ReadSharedReq accesses 2812system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.237687 # miss rate for ReadSharedReq accesses 2813system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102763 # miss rate for ReadSharedReq accesses 2814system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.173198 # miss rate for ReadSharedReq accesses 2815system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for ReadSharedReq accesses 2816system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for ReadSharedReq accesses 2817system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.298776 # miss rate for ReadSharedReq accesses 2818system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087314 # miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164824 # miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_miss_rate::total 0.224964 # miss rate for ReadSharedReq accesses 2822system.l2c.InvalidateReq_miss_rate::cpu0.data 0.777857 # miss rate for InvalidateReq accesses 2823system.l2c.InvalidateReq_miss_rate::cpu1.data 0.520791 # miss rate for InvalidateReq accesses 2824system.l2c.InvalidateReq_miss_rate::total 0.698024 # miss rate for InvalidateReq accesses 2825system.l2c.demand_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for demand accesses 2826system.l2c.demand_miss_rate::cpu0.itb.walker 0.237687 # miss rate for demand accesses 2827system.l2c.demand_miss_rate::cpu0.inst 0.102763 # miss rate for demand accesses 2828system.l2c.demand_miss_rate::cpu0.data 0.239609 # miss rate for demand accesses 2829system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for demand accesses 2830system.l2c.demand_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for demand accesses 2831system.l2c.demand_miss_rate::cpu1.itb.walker 0.298776 # miss rate for demand accesses 2832system.l2c.demand_miss_rate::cpu1.inst 0.087314 # miss rate for demand accesses 2833system.l2c.demand_miss_rate::cpu1.data 0.214173 # miss rate for demand accesses 2834system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for demand accesses 2835system.l2c.demand_miss_rate::total 0.247094 # miss rate for demand accesses 2836system.l2c.overall_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for overall accesses 2837system.l2c.overall_miss_rate::cpu0.itb.walker 0.237687 # miss rate for overall accesses 2838system.l2c.overall_miss_rate::cpu0.inst 0.102763 # miss rate for overall accesses 2839system.l2c.overall_miss_rate::cpu0.data 0.239609 # miss rate for overall accesses 2840system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for overall accesses 2841system.l2c.overall_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for overall accesses 2842system.l2c.overall_miss_rate::cpu1.itb.walker 0.298776 # miss rate for overall accesses 2843system.l2c.overall_miss_rate::cpu1.inst 0.087314 # miss rate for overall accesses 2844system.l2c.overall_miss_rate::cpu1.data 0.214173 # miss rate for overall accesses 2845system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for overall accesses 2846system.l2c.overall_miss_rate::total 0.247094 # miss rate for overall accesses 2847system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15218.257501 # average UpgradeReq miss latency 2848system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15723.730743 # average UpgradeReq miss latency 2849system.l2c.UpgradeReq_avg_miss_latency::total 15465.256645 # average UpgradeReq miss latency 2850system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14446.515126 # average SCUpgradeReq miss latency 2851system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13001.064660 # average SCUpgradeReq miss latency 2852system.l2c.SCUpgradeReq_avg_miss_latency::total 13664.901171 # average SCUpgradeReq miss latency 2853system.l2c.ReadExReq_avg_miss_latency::cpu0.data 136623.388218 # average ReadExReq miss latency 2854system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134226.070112 # average ReadExReq miss latency 2855system.l2c.ReadExReq_avg_miss_latency::total 135618.850025 # average ReadExReq miss latency 2856system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average ReadSharedReq miss latency 2857system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138404.586405 # average ReadSharedReq miss latency 2858system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135215.200475 # average ReadSharedReq miss latency 2859system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137724.896469 # average ReadSharedReq miss latency 2860system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average ReadSharedReq miss latency 2861system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average ReadSharedReq miss latency 2862system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139445.355191 # average ReadSharedReq miss latency 2863system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134683.913309 # average ReadSharedReq miss latency 2864system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139925.054394 # average ReadSharedReq miss latency 2865system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average ReadSharedReq miss latency 2866system.l2c.ReadSharedReq_avg_miss_latency::total 155838.767203 # average ReadSharedReq miss latency 2867system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 342.927279 # average InvalidateReq miss latency 2868system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1159.827206 # average InvalidateReq miss latency 2869system.l2c.InvalidateReq_avg_miss_latency::total 532.205133 # average InvalidateReq miss latency 2870system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average overall miss latency 2871system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138404.586405 # average overall miss latency 2872system.l2c.demand_avg_miss_latency::cpu0.inst 135215.200475 # average overall miss latency 2873system.l2c.demand_avg_miss_latency::cpu0.data 137294.083153 # average overall miss latency 2874system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average overall miss latency 2875system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average overall miss latency 2876system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139445.355191 # average overall miss latency 2877system.l2c.demand_avg_miss_latency::cpu1.inst 134683.913309 # average overall miss latency 2878system.l2c.demand_avg_miss_latency::cpu1.data 137978.603096 # average overall miss latency 2879system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 2880system.l2c.demand_avg_miss_latency::total 152790.436710 # average overall miss latency 2881system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average overall miss latency 2882system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138404.586405 # average overall miss latency 2883system.l2c.overall_avg_miss_latency::cpu0.inst 135215.200475 # average overall miss latency 2884system.l2c.overall_avg_miss_latency::cpu0.data 137294.083153 # average overall miss latency 2885system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average overall miss latency 2886system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average overall miss latency 2887system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139445.355191 # average overall miss latency 2888system.l2c.overall_avg_miss_latency::cpu1.inst 134683.913309 # average overall miss latency 2889system.l2c.overall_avg_miss_latency::cpu1.data 137978.603096 # average overall miss latency 2890system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 2891system.l2c.overall_avg_miss_latency::total 152790.436710 # average overall miss latency 2892system.l2c.blocked_cycles::no_mshrs 1300 # number of cycles access was blocked 2893system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2894system.l2c.blocked::no_mshrs 25 # number of cycles access was blocked 2895system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2896system.l2c.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked 2897system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2898system.l2c.fast_writes 0 # number of fast writes performed 2899system.l2c.cache_copies 0 # number of cache copies performed 2900system.l2c.writebacks::writebacks 1038944 # number of writebacks 2901system.l2c.writebacks::total 1038944 # number of writebacks 2902system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 98 # number of ReadSharedReq MSHR hits 2903system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 2904system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 68 # number of ReadSharedReq MSHR hits 2905system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2906system.l2c.ReadSharedReq_mshr_hits::total 208 # number of ReadSharedReq MSHR hits 2907system.l2c.demand_mshr_hits::cpu0.inst 98 # number of demand (read+write) MSHR hits 2908system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 2909system.l2c.demand_mshr_hits::cpu1.inst 68 # number of demand (read+write) MSHR hits 2910system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 2911system.l2c.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits 2912system.l2c.overall_mshr_hits::cpu0.inst 98 # number of overall MSHR hits 2913system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 2914system.l2c.overall_mshr_hits::cpu1.inst 68 # number of overall MSHR hits 2915system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 2916system.l2c.overall_mshr_hits::total 208 # number of overall MSHR hits 2917system.l2c.CleanEvict_mshr_misses::writebacks 42465 # number of CleanEvict MSHR misses 2918system.l2c.CleanEvict_mshr_misses::total 42465 # number of CleanEvict MSHR misses 2919system.l2c.UpgradeReq_mshr_misses::cpu0.data 60660 # number of UpgradeReq MSHR misses 2920system.l2c.UpgradeReq_mshr_misses::cpu1.data 57967 # number of UpgradeReq MSHR misses 2921system.l2c.UpgradeReq_mshr_misses::total 118627 # number of UpgradeReq MSHR misses 2922system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11966 # number of SCUpgradeReq MSHR misses 2923system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 14089 # number of SCUpgradeReq MSHR misses 2924system.l2c.SCUpgradeReq_mshr_misses::total 26055 # number of SCUpgradeReq MSHR misses 2925system.l2c.ReadExReq_mshr_misses::cpu0.data 73366 # number of ReadExReq MSHR misses 2926system.l2c.ReadExReq_mshr_misses::cpu1.data 52915 # number of ReadExReq MSHR misses 2927system.l2c.ReadExReq_mshr_misses::total 126281 # number of ReadExReq MSHR misses 2928system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1280 # number of ReadSharedReq MSHR misses 2929system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1221 # number of ReadSharedReq MSHR misses 2930system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 47065 # 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number of ReadExReq MSHR miss cycles 2985system.l2c.ReadExReq_mshr_miss_latency::total 15862682228 # number of ReadExReq MSHR miss cycles 2986system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 166958510 # number of ReadSharedReq MSHR miss cycles 2987system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 156778008 # number of ReadSharedReq MSHR miss cycles 2988system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5894891941 # number of ReadSharedReq MSHR miss cycles 2989system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14584550481 # number of ReadSharedReq MSHR miss cycles 2990system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30771342562 # number of ReadSharedReq MSHR miss cycles 2991system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 236409526 # number of ReadSharedReq MSHR miss cycles 2992system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 236875020 # number of ReadSharedReq MSHR miss cycles 2993system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4895215723 # 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number of overall MSHR miss cycles 3012system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 156778008 # number of overall MSHR miss cycles 3013system.l2c.overall_mshr_miss_latency::cpu0.inst 5894891941 # number of overall MSHR miss cycles 3014system.l2c.overall_mshr_miss_latency::cpu0.data 23874081941 # number of overall MSHR miss cycles 3015system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30771342562 # number of overall MSHR miss cycles 3016system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 236409526 # number of overall MSHR miss cycles 3017system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236875020 # number of overall MSHR miss cycles 3018system.l2c.overall_mshr_miss_latency::cpu1.inst 4895215723 # number of overall MSHR miss cycles 3019system.l2c.overall_mshr_miss_latency::cpu1.data 19824782063 # number of overall MSHR miss cycles 3020system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of overall MSHR miss cycles 3021system.l2c.overall_mshr_miss_latency::total 119579260538 # number of overall MSHR miss cycles 3022system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 3023system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4673220523 # number of ReadReq MSHR uncacheable cycles 3024system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles 3025system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1233601518 # number of ReadReq MSHR uncacheable cycles 3026system.l2c.ReadReq_mshr_uncacheable_latency::total 10773300041 # number of ReadReq MSHR uncacheable cycles 3027system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles 3028system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles 3029system.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles 3030system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 3031system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles 3032system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles 3033system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles 3034system.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles 3035system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3036system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3037system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses 3038system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315189 # mshr miss rate for UpgradeReq accesses 3039system.l2c.UpgradeReq_mshr_miss_rate::total 0.293598 # mshr miss rate for UpgradeReq accesses 3040system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244994 # mshr miss rate for SCUpgradeReq accesses 3041system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.272905 # mshr miss rate for SCUpgradeReq accesses 3042system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259336 # mshr miss rate for SCUpgradeReq accesses 3043system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.594480 # mshr miss rate for ReadExReq accesses 3044system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506582 # mshr miss rate for ReadExReq accesses 3045system.l2c.ReadExReq_mshr_miss_rate::total 0.554187 # mshr miss rate for ReadExReq accesses 3046system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for ReadSharedReq accesses 3047system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for ReadSharedReq accesses 3048system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for ReadSharedReq accesses 3049system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173160 # mshr miss rate for ReadSharedReq accesses 3050system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for ReadSharedReq accesses 3051system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for ReadSharedReq accesses 3052system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for ReadSharedReq accesses 3053system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for ReadSharedReq accesses 3054system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164796 # mshr miss rate for ReadSharedReq accesses 3055system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for ReadSharedReq accesses 3056system.l2c.ReadSharedReq_mshr_miss_rate::total 0.224898 # mshr miss rate for ReadSharedReq accesses 3057system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.777857 # mshr miss rate for InvalidateReq accesses 3058system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.520791 # mshr miss rate for InvalidateReq accesses 3059system.l2c.InvalidateReq_mshr_miss_rate::total 0.698024 # mshr miss rate for InvalidateReq accesses 3060system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for demand accesses 3061system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for demand accesses 3062system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for demand accesses 3063system.l2c.demand_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for demand accesses 3064system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for demand accesses 3065system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for demand accesses 3066system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for demand accesses 3067system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for demand accesses 3068system.l2c.demand_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for demand accesses 3069system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for demand accesses 3070system.l2c.demand_mshr_miss_rate::total 0.247032 # mshr miss rate for demand accesses 3071system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for overall accesses 3072system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for overall accesses 3073system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for overall accesses 3074system.l2c.overall_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for overall accesses 3075system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for overall accesses 3076system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for overall accesses 3077system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for overall accesses 3078system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for overall accesses 3079system.l2c.overall_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for overall accesses 3080system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for overall accesses 3081system.l2c.overall_mshr_miss_rate::total 0.247032 # mshr miss rate for overall accesses 3082system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70695.590175 # average UpgradeReq mshr miss latency 3083system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70766.608588 # average UpgradeReq mshr miss latency 3084system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70730.293272 # average UpgradeReq mshr miss latency 3085system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73743.774026 # average SCUpgradeReq mshr miss latency 3086system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73774.575910 # average SCUpgradeReq mshr miss latency 3087system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73760.429860 # average SCUpgradeReq mshr miss latency 3088system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 126619.025979 # average ReadExReq mshr miss latency 3089system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124220.934858 # average ReadExReq mshr miss latency 3090system.l2c.ReadExReq_avg_mshr_miss_latency::total 125614.163873 # average ReadExReq mshr miss latency 3091system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average ReadSharedReq mshr miss latency 3092system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average ReadSharedReq mshr miss latency 3093system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average ReadSharedReq mshr miss latency 3094system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127719.546737 # average ReadSharedReq mshr miss latency 3095system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average ReadSharedReq mshr miss latency 3096system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average ReadSharedReq mshr miss latency 3097system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average ReadSharedReq mshr miss latency 3098system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average ReadSharedReq mshr miss latency 3099system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129921.775101 # average ReadSharedReq mshr miss latency 3100system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average ReadSharedReq mshr miss latency 3101system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 145844.077680 # average ReadSharedReq mshr miss latency 3102system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68994.942002 # average InvalidateReq mshr miss latency 3103system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69165.770374 # average InvalidateReq mshr miss latency 3104system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69034.523384 # average InvalidateReq mshr miss latency 3105system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency 3106system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency 3107system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency 3108system.l2c.demand_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency 3109system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency 3110system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency 3111system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency 3112system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency 3113system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 3114system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 3115system.l2c.demand_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 3116system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency 3117system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency 3118system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency 3119system.l2c.overall_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency 3120system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency 3121system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency 3122system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency 3123system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency 3124system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 3125system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 3126system.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 3127system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 3128system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency 3129system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency 3130system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency 3131system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency 3132system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency 3133system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency 3134system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency 3135system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 3136system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency 3137system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency 3138system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency 3139system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency 3140system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3141system.membus.trans_dist::ReadReq 81394 # Transaction distribution 3142system.membus.trans_dist::ReadResp 801457 # Transaction distribution 3143system.membus.trans_dist::WriteReq 38017 # Transaction distribution 3144system.membus.trans_dist::WriteResp 38017 # Transaction distribution 3145system.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution 3146system.membus.trans_dist::CleanEvict 202586 # Transaction distribution 3147system.membus.trans_dist::UpgradeReq 388021 # Transaction distribution 3148system.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution 3149system.membus.trans_dist::UpgradeResp 24 # Transaction distribution 3150system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 3151system.membus.trans_dist::ReadExReq 139521 # Transaction distribution 3152system.membus.trans_dist::ReadExResp 122200 # Transaction distribution 3153system.membus.trans_dist::ReadSharedReq 720063 # Transaction distribution 3154system.membus.trans_dist::InvalidateReq 663960 # Transaction distribution 3155system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) 3156system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3157system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24516 # Packet count per connected master and slave (bytes) 3158system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4262617 # Packet count per connected master and slave (bytes) 3159system.membus.pkt_count_system.l2c.mem_side::total 4409841 # Packet count per connected master and slave (bytes) 3160system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238367 # Packet count per connected master and slave (bytes) 3161system.membus.pkt_count_system.iocache.mem_side::total 238367 # Packet count per connected master and slave (bytes) 3162system.membus.pkt_count::total 4648208 # Packet count per connected master and slave (bytes) 3163system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) 3164system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3165system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49032 # Cumulative packet size per connected master and slave (bytes) 3166system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 119974316 # Cumulative packet size per connected master and slave (bytes) 3167system.membus.pkt_size_system.l2c.mem_side::total 120179275 # Cumulative packet size per connected master and slave (bytes) 3168system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283904 # Cumulative packet size per connected master and slave (bytes) 3169system.membus.pkt_size_system.iocache.mem_side::total 7283904 # Cumulative packet size per connected master and slave (bytes) 3170system.membus.pkt_size::total 127463179 # Cumulative packet size per connected master and slave (bytes) 3171system.membus.snoops 565217 # Total snoops (count) 3172system.membus.snoop_fanout::samples 3689099 # Request fanout histogram 3173system.membus.snoop_fanout::mean 1 # Request fanout histogram 3174system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3175system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3176system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3177system.membus.snoop_fanout::1 3689099 100.00% 100.00% # Request fanout histogram 3178system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3179system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3180system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3181system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3182system.membus.snoop_fanout::total 3689099 # Request fanout histogram 3183system.membus.reqLayer0.occupancy 101296000 # Layer occupancy (ticks) 3184system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3185system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3186system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3187system.membus.reqLayer2.occupancy 20132498 # Layer occupancy (ticks) 3188system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3189system.membus.reqLayer5.occupancy 7983633356 # Layer occupancy (ticks) 3190system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3191system.membus.respLayer2.occupancy 4606610325 # Layer occupancy (ticks) 3192system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3193system.membus.respLayer3.occupancy 45425919 # Layer occupancy (ticks) 3194system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3195system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3196system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3197system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3198system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3199system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3200system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3201system.realview.ethernet.txBytes 966 # Bytes Transmitted 3202system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3203system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3204system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3205system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3206system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3207system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3208system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3209system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3210system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3211system.realview.ethernet.totPackets 3 # Total Packets 3212system.realview.ethernet.totBytes 966 # Total Bytes 3213system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3214system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3215system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3216system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3217system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3218system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3219system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3220system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3221system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3222system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3223system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3224system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3225system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3226system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3227system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3228system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3229system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3230system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3231system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3232system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3233system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3234system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3235system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3236system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3237system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3238system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3239system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3240system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3241system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3242system.realview.ethernet.droppedPackets 0 # number of packets dropped 3243system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3244system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3245system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3246system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3247system.toL2Bus.snoop_filter.tot_requests 10607741 # Total number of requests made to the snoop filter. 3248system.toL2Bus.snoop_filter.hit_single_requests 5778542 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3249system.toL2Bus.snoop_filter.hit_multi_requests 1706398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3250system.toL2Bus.snoop_filter.tot_snoops 126357 # Total number of snoops made to the snoop filter. 3251system.toL2Bus.snoop_filter.hit_single_snoops 115095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3252system.toL2Bus.snoop_filter.hit_multi_snoops 11262 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3253system.toL2Bus.trans_dist::ReadReq 81396 # Transaction distribution 3254system.toL2Bus.trans_dist::ReadResp 3972795 # Transaction distribution 3255system.toL2Bus.trans_dist::WriteReq 38017 # Transaction distribution 3256system.toL2Bus.trans_dist::WriteResp 38017 # Transaction distribution 3257system.toL2Bus.trans_dist::WritebackDirty 3722299 # Transaction distribution 3258system.toL2Bus.trans_dist::CleanEvict 2264546 # Transaction distribution 3259system.toL2Bus.trans_dist::UpgradeReq 665609 # Transaction distribution 3260system.toL2Bus.trans_dist::SCUpgradeReq 384259 # Transaction distribution 3261system.toL2Bus.trans_dist::UpgradeResp 1049868 # Transaction distribution 3262system.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution 3263system.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 3264system.toL2Bus.trans_dist::ReadExReq 281631 # Transaction distribution 3265system.toL2Bus.trans_dist::ReadExResp 281631 # Transaction distribution 3266system.toL2Bus.trans_dist::ReadSharedReq 3898638 # Transaction distribution 3267system.toL2Bus.trans_dist::InvalidateReq 910400 # Transaction distribution 3268system.toL2Bus.trans_dist::InvalidateResp 803672 # Transaction distribution 3269system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8440853 # Packet count per connected master and slave (bytes) 3270system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7105433 # Packet count per connected master and slave (bytes) 3271system.toL2Bus.pkt_count::total 15546286 # Packet count per connected master and slave (bytes) 3272system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 205041299 # Cumulative packet size per connected master and slave (bytes) 3273system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177324920 # Cumulative packet size per connected master and slave (bytes) 3274system.toL2Bus.pkt_size::total 382366219 # Cumulative packet size per connected master and slave (bytes) 3275system.toL2Bus.snoops 2848440 # Total snoops (count) 3276system.toL2Bus.snoop_fanout::samples 7664337 # Request fanout histogram 3277system.toL2Bus.snoop_fanout::mean 0.347835 # Request fanout histogram 3278system.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram 3279system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3280system.toL2Bus.snoop_fanout::0 5009678 65.36% 65.36% # Request fanout histogram 3281system.toL2Bus.snoop_fanout::1 2643397 34.49% 99.85% # Request fanout histogram 3282system.toL2Bus.snoop_fanout::2 11262 0.15% 100.00% # Request fanout histogram 3283system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3284system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3285system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3286system.toL2Bus.snoop_fanout::total 7664337 # Request fanout histogram 3287system.toL2Bus.reqLayer0.occupancy 8363064932 # Layer occupancy (ticks) 3288system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3289system.toL2Bus.snoopLayer0.occupancy 2585436 # Layer occupancy (ticks) 3290system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3291system.toL2Bus.respLayer0.occupancy 3816515270 # Layer occupancy (ticks) 3292system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3293system.toL2Bus.respLayer1.occupancy 3482933794 # Layer occupancy (ticks) 3294system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3295 3296---------- End Simulation Statistics ---------- 3297