stats.txt revision 11138:a611a23c8cc2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.474700 # Number of seconds simulated 4sim_ticks 47474700369500 # Number of ticks simulated 5final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 631720 # Simulator instruction rate (inst/s) 8host_op_rate 743100 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34016391858 # Simulator tick rate (ticks/s) 10host_mem_usage 766400 # Number of bytes of host memory used 11host_seconds 1395.64 # Real time elapsed on the host 12sim_insts 881655060 # Number of instructions simulated 13sim_ops 1037101350 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 127360 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 143744 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3459124 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 40376840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 12078528 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 91584 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 86464 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2488056 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 17058000 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14991744 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 410816 # Number of bytes read from this memory 27system.physmem.bytes_read::total 91312260 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3459124 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2488056 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 5947180 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 77042688 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 77063272 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1990 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2246 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 94456 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 630901 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 188727 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1431 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1351 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 38964 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 266544 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 234246 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6419 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1467275 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1203792 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1206366 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2683 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 3028 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 72862 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 850492 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 254420 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1929 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1821 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 52408 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 359307 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 315784 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8653 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1923388 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 72862 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 52408 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 125271 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1622816 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1623249 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1622816 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2683 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 3028 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 72862 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 850925 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 254420 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1929 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1821 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 52408 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 359307 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 315784 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8653 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3546637 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1467275 # Number of read requests accepted 84system.physmem.writeReqs 1206366 # Number of write requests accepted 85system.physmem.readBursts 1467275 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1206366 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 93873920 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 31680 # Total number of bytes read from write queue 89system.physmem.bytesWritten 77062336 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 91312260 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 77063272 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 495 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 220616 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 87562 # Per bank write bursts 96system.physmem.perBankRdBursts::1 88840 # Per bank write bursts 97system.physmem.perBankRdBursts::2 82797 # Per bank write bursts 98system.physmem.perBankRdBursts::3 92927 # Per bank write bursts 99system.physmem.perBankRdBursts::4 90148 # Per bank write bursts 100system.physmem.perBankRdBursts::5 93986 # Per bank write bursts 101system.physmem.perBankRdBursts::6 87799 # Per bank write bursts 102system.physmem.perBankRdBursts::7 94269 # Per bank write bursts 103system.physmem.perBankRdBursts::8 90753 # Per bank write bursts 104system.physmem.perBankRdBursts::9 132105 # Per bank write bursts 105system.physmem.perBankRdBursts::10 81290 # Per bank write bursts 106system.physmem.perBankRdBursts::11 92144 # Per bank write bursts 107system.physmem.perBankRdBursts::12 81361 # Per bank write bursts 108system.physmem.perBankRdBursts::13 87555 # Per bank write bursts 109system.physmem.perBankRdBursts::14 92182 # Per bank write bursts 110system.physmem.perBankRdBursts::15 91062 # Per bank write bursts 111system.physmem.perBankWrBursts::0 71771 # Per bank write bursts 112system.physmem.perBankWrBursts::1 74672 # Per bank write bursts 113system.physmem.perBankWrBursts::2 72652 # Per bank write bursts 114system.physmem.perBankWrBursts::3 78055 # Per bank write bursts 115system.physmem.perBankWrBursts::4 74620 # Per bank write bursts 116system.physmem.perBankWrBursts::5 78875 # Per bank write bursts 117system.physmem.perBankWrBursts::6 73591 # Per bank write bursts 118system.physmem.perBankWrBursts::7 76891 # Per bank write bursts 119system.physmem.perBankWrBursts::8 77107 # Per bank write bursts 120system.physmem.perBankWrBursts::9 78277 # Per bank write bursts 121system.physmem.perBankWrBursts::10 71128 # Per bank write bursts 122system.physmem.perBankWrBursts::11 78119 # Per bank write bursts 123system.physmem.perBankWrBursts::12 70456 # Per bank write bursts 124system.physmem.perBankWrBursts::13 74533 # Per bank write bursts 125system.physmem.perBankWrBursts::14 76600 # Per bank write bursts 126system.physmem.perBankWrBursts::15 76752 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 39 # Number of times write queue was full causing retry 129system.physmem.totGap 47474697259000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1424050 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1203792 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 1195881 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 91231 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 37643 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 32050 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 26760 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 23675 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 20974 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 18326 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 14619 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2367 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 941 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 584 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 447 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 348 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 253 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 224 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 18047 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 20216 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 49731 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 58137 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 63836 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 67727 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 72112 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 73557 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 75338 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 76158 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 77610 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 81366 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 78544 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 78356 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 81800 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 76571 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 72953 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 70532 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1899 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1287 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 892 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 734 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 591 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 574 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 376 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 359 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 330 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 302 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 246 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 118 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 940579 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 181.734800 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 113.091903 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 237.596263 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 569137 60.51% 60.51% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 185879 19.76% 80.27% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 61156 6.50% 86.77% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 31438 3.34% 90.12% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 21576 2.29% 92.41% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 13250 1.41% 93.82% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 9973 1.06% 94.88% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 9805 1.04% 95.92% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 38365 4.08% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 940579 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 68336 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.464104 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 309.922160 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 68334 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 68336 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 68336 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 17.620273 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 17.104093 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 6.841865 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 64690 94.66% 94.66% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 1540 2.25% 96.92% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 239 0.35% 97.27% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 282 0.41% 97.68% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 82 0.12% 97.80% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 291 0.43% 98.23% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 162 0.24% 98.46% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 86 0.13% 98.59% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 81 0.12% 98.71% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 117 0.17% 98.88% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 30 0.04% 98.92% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 46 0.07% 98.99% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 391 0.57% 99.56% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 42 0.06% 99.62% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 42 0.06% 99.69% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 142 0.21% 99.89% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 21 0.03% 99.92% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::100-103 7 0.01% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 68336 # Writes before turning the bus around for reads 298system.physmem.totQLat 37142962355 # Total ticks spent queuing 299system.physmem.totMemAccLat 64645087355 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 7333900000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 25322.79 # Average queueing delay per DRAM burst 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 303system.physmem.avgMemAccLat 44072.79 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 1.98 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 309system.physmem.busUtil 0.03 # Data bus utilization in percentage 310system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 314system.physmem.readRowHits 1168360 # Number of row buffer hits during reads 315system.physmem.writeRowHits 561939 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 46.67 # Row buffer hit rate for writes 318system.physmem.avgGap 17756571.38 # Average gap between requests 319system.physmem.pageHitRate 64.78 # Row buffer hit rate, read and write combined 320system.physmem_0.actEnergy 3585949920 # Energy for activate commands per rank (pJ) 321system.physmem_0.preEnergy 1956619500 # Energy for precharge commands per rank (pJ) 322system.physmem_0.readEnergy 5602958400 # Energy for read commands per rank (pJ) 323system.physmem_0.writeEnergy 3895302960 # Energy for write commands per rank (pJ) 324system.physmem_0.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) 325system.physmem_0.actBackEnergy 1230768339570 # Energy for active background per rank (pJ) 326system.physmem_0.preBackEnergy 27405197149500 # Energy for precharge background per rank (pJ) 327system.physmem_0.totalEnergy 31751822762730 # Total energy per rank (pJ) 328system.physmem_0.averagePower 668.815694 # Core power per rank (mW) 329system.physmem_0.memoryStateTime::IDLE 45589938065590 # Time in different power states 330system.physmem_0.memoryStateTime::REF 1585284480000 # Time in different power states 331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 332system.physmem_0.memoryStateTime::ACT 299474968160 # Time in different power states 333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.physmem_1.actEnergy 3524827320 # Energy for activate commands per rank (pJ) 335system.physmem_1.preEnergy 1923268875 # Energy for precharge commands per rank (pJ) 336system.physmem_1.readEnergy 5837886600 # Energy for read commands per rank (pJ) 337system.physmem_1.writeEnergy 3907258560 # Energy for write commands per rank (pJ) 338system.physmem_1.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) 339system.physmem_1.actBackEnergy 1224297828675 # Energy for active background per rank (pJ) 340system.physmem_1.preBackEnergy 27410873036250 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 31751180549160 # Total energy per rank (pJ) 342system.physmem_1.averagePower 668.802167 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 45599398366763 # Time in different power states 344system.physmem_1.memoryStateTime::REF 1585284480000 # Time in different power states 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 346system.physmem_1.memoryStateTime::ACT 290016828237 # Time in different power states 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 348system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 356system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 361system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 374system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 375system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 376system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 377system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 378system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 379system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 380system.cpu_clk_domain.clock 500 # Clock period in ticks 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 390system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 391system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 392system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 393system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 394system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 399system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 400system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 402system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 405system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 406system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 407system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 408system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 409system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 410system.cpu0.dtb.walker.walks 101051 # Table walker walks requested 411system.cpu0.dtb.walker.walksLong 101051 # Table walker walks initiated with long descriptors 412system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8300 # Level at which table walker walks with long descriptors terminate 413system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 78014 # Level at which table walker walks with long descriptors terminate 414system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 415system.cpu0.dtb.walker.walkWaitTime::samples 101044 # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::0 101044 100.00% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::total 101044 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkCompletionTime::samples 86321 # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013 # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020 # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::0-65535 84871 98.32% 98.32% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::65536-131071 161 0.19% 98.51% # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1103 1.28% 99.78% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.83% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::262144-327679 57 0.07% 99.90% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.93% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.02% 99.99% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::total 86321 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walksPending::samples 1368339312 # Table walker pending requests distribution 435system.cpu0.dtb.walker.walksPending::mean -0.519630 # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::0 2079369704 151.96% 151.96% # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::1 -711030392 -51.96% 100.00% # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::total 1368339312 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walkPageSizes::4K 78015 90.38% 90.38% # Table walker page sizes translated 440system.cpu0.dtb.walker.walkPageSizes::2M 8300 9.62% 100.00% # Table walker page sizes translated 441system.cpu0.dtb.walker.walkPageSizes::total 86315 # Table walker page sizes translated 442system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101051 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101051 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 86315 # Table walker requests started/completed, data/inst 446system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 86315 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin::total 187366 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.inst_hits 0 # ITB inst hits 450system.cpu0.dtb.inst_misses 0 # ITB inst misses 451system.cpu0.dtb.read_hits 83039604 # DTB read hits 452system.cpu0.dtb.read_misses 74585 # DTB read misses 453system.cpu0.dtb.write_hits 76137695 # DTB write hits 454system.cpu0.dtb.write_misses 26466 # DTB write misses 455system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 456system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu0.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 459system.cpu0.dtb.flush_entries 37690 # Number of entries that have been flushed from TLB 460system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu0.dtb.prefetch_faults 4076 # Number of TLB faults due to prefetch 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 10173 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 83114189 # DTB read accesses 465system.cpu0.dtb.write_accesses 76164161 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 159177299 # DTB hits 468system.cpu0.dtb.misses 101051 # DTB misses 469system.cpu0.dtb.accesses 159278350 # DTB accesses 470system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 479system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 480system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 481system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 482system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 483system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 484system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 485system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 486system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 489system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 494system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 495system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 496system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 497system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 498system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 499system.cpu0.itb.walker.walks 61250 # Table walker walks requested 500system.cpu0.itb.walker.walksLong 61250 # Table walker walks initiated with long descriptors 501system.cpu0.itb.walker.walksLongTerminationLevel::Level2 499 # Level at which table walker walks with long descriptors terminate 502system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55525 # Level at which table walker walks with long descriptors terminate 503system.cpu0.itb.walker.walkWaitTime::samples 61250 # Table walker wait (enqueue to first request) latency 504system.cpu0.itb.walker.walkWaitTime::0 61250 100.00% 100.00% # Table walker wait (enqueue to first request) latency 505system.cpu0.itb.walker.walkWaitTime::total 61250 # Table walker wait (enqueue to first request) latency 506system.cpu0.itb.walker.walkCompletionTime::samples 56024 # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065 # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992 # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128 # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::0-65535 54387 97.08% 97.08% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.07% 97.15% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::131072-196607 1384 2.47% 99.62% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::196608-262143 41 0.07% 99.69% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::262144-327679 72 0.13% 99.82% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::327680-393215 22 0.04% 99.86% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::393216-458751 55 0.10% 99.96% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::total 56024 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walksPending::samples 1978837204 # Table walker pending requests distribution 524system.cpu0.itb.walker.walksPending::0 1978837204 100.00% 100.00% # Table walker pending requests distribution 525system.cpu0.itb.walker.walksPending::total 1978837204 # Table walker pending requests distribution 526system.cpu0.itb.walker.walkPageSizes::4K 55525 99.11% 99.11% # Table walker page sizes translated 527system.cpu0.itb.walker.walkPageSizes::2M 499 0.89% 100.00% # Table walker page sizes translated 528system.cpu0.itb.walker.walkPageSizes::total 56024 # Table walker page sizes translated 529system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61250 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61250 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56024 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56024 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin::total 117274 # Table walker requests started/completed, data/inst 536system.cpu0.itb.inst_hits 441205116 # ITB inst hits 537system.cpu0.itb.inst_misses 61250 # ITB inst misses 538system.cpu0.itb.read_hits 0 # DTB read hits 539system.cpu0.itb.read_misses 0 # DTB read misses 540system.cpu0.itb.write_hits 0 # DTB write hits 541system.cpu0.itb.write_misses 0 # DTB write misses 542system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 543system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 544system.cpu0.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 545system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 546system.cpu0.itb.flush_entries 26202 # Number of entries that have been flushed from TLB 547system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 548system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 549system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 550system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 551system.cpu0.itb.read_accesses 0 # DTB read accesses 552system.cpu0.itb.write_accesses 0 # DTB write accesses 553system.cpu0.itb.inst_accesses 441266366 # ITB inst accesses 554system.cpu0.itb.hits 441205116 # DTB hits 555system.cpu0.itb.misses 61250 # DTB misses 556system.cpu0.itb.accesses 441266366 # DTB accesses 557system.cpu0.numCycles 94949400739 # number of cpu cycles simulated 558system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 559system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 560system.cpu0.committedInsts 440958495 # Number of instructions committed 561system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed 562system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses 563system.cpu0.num_fp_alu_accesses 531836 # Number of float alu accesses 564system.cpu0.num_func_calls 26928397 # number of times a function call or return occured 565system.cpu0.num_conditional_control_insts 66358328 # number of instructions that are conditional controls 566system.cpu0.num_int_insts 478066113 # number of integer instructions 567system.cpu0.num_fp_insts 531836 # number of float instructions 568system.cpu0.num_int_register_reads 691558601 # number of times the integer registers were read 569system.cpu0.num_int_register_writes 378884875 # number of times the integer registers were written 570system.cpu0.num_fp_register_reads 853461 # number of times the floating registers were read 571system.cpu0.num_fp_register_writes 460304 # number of times the floating registers were written 572system.cpu0.num_cc_register_reads 113354931 # number of times the CC registers were read 573system.cpu0.num_cc_register_writes 113143261 # number of times the CC registers were written 574system.cpu0.num_mem_refs 159167445 # number of memory refs 575system.cpu0.num_load_insts 83034076 # Number of load instructions 576system.cpu0.num_store_insts 76133369 # Number of store instructions 577system.cpu0.num_idle_cycles 93735186324.296036 # Number of idle cycles 578system.cpu0.num_busy_cycles 1214214414.703974 # Number of busy cycles 579system.cpu0.not_idle_fraction 0.012788 # Percentage of non-idle cycles 580system.cpu0.idle_fraction 0.987212 # Percentage of idle cycles 581system.cpu0.Branches 98314010 # Number of branches fetched 582system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 583system.cpu0.op_class::IntAlu 359396375 69.13% 69.13% # Class of executed instruction 584system.cpu0.op_class::IntMult 1169846 0.23% 69.36% # Class of executed instruction 585system.cpu0.op_class::IntDiv 59621 0.01% 69.37% # Class of executed instruction 586system.cpu0.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction 587system.cpu0.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction 588system.cpu0.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction 589system.cpu0.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction 590system.cpu0.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction 591system.cpu0.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction 592system.cpu0.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction 593system.cpu0.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction 594system.cpu0.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction 595system.cpu0.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction 596system.cpu0.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction 597system.cpu0.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction 598system.cpu0.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction 599system.cpu0.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction 600system.cpu0.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction 601system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction 602system.cpu0.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction 603system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction 604system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction 605system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction 606system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.37% # Class of executed instruction 607system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction 608system.cpu0.op_class::SimdFloatMisc 75402 0.01% 69.38% # Class of executed instruction 609system.cpu0.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction 610system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction 611system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction 612system.cpu0.op_class::MemRead 83034076 15.97% 85.36% # Class of executed instruction 613system.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Class of executed instruction 614system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 615system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 616system.cpu0.op_class::total 519868732 # Class of executed instruction 617system.cpu0.kern.inst.arm 0 # number of arm instructions executed 618system.cpu0.kern.inst.quiesce 7168 # number of quiesce instructions executed 619system.cpu0.dcache.tags.replacements 5565465 # number of replacements 620system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use 621system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks. 622system.cpu0.dcache.tags.sampled_refs 5565977 # Sample count of references to valid blocks. 623system.cpu0.dcache.tags.avg_refs 27.554484 # Average number of references to valid blocks. 624system.cpu0.dcache.tags.warmup_cycle 6293402000 # Cycle when the warmup percentage was hit. 625system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.695844 # Average occupied blocks per requestor 626system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983781 # Average percentage of cache occupancy 627system.cpu0.dcache.tags.occ_percent::total 0.983781 # Average percentage of cache occupancy 628system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 629system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 630system.cpu0.dcache.tags.age_task_id_blocks_1024::1 429 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 632system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu0.dcache.tags.tag_accesses 323920102 # Number of tag accesses 634system.cpu0.dcache.tags.data_accesses 323920102 # Number of data accesses 635system.cpu0.dcache.ReadReq_hits::cpu0.data 77284320 # number of ReadReq hits 636system.cpu0.dcache.ReadReq_hits::total 77284320 # number of ReadReq hits 637system.cpu0.dcache.WriteReq_hits::cpu0.data 71935312 # number of WriteReq hits 638system.cpu0.dcache.WriteReq_hits::total 71935312 # number of WriteReq hits 639system.cpu0.dcache.SoftPFReq_hits::cpu0.data 189585 # number of SoftPFReq hits 640system.cpu0.dcache.SoftPFReq_hits::total 189585 # number of SoftPFReq hits 641system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125588 # number of WriteLineReq hits 642system.cpu0.dcache.WriteLineReq_hits::total 125588 # number of WriteLineReq hits 643system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1730584 # number of LoadLockedReq hits 644system.cpu0.dcache.LoadLockedReq_hits::total 1730584 # number of LoadLockedReq hits 645system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1699772 # number of StoreCondReq hits 646system.cpu0.dcache.StoreCondReq_hits::total 1699772 # number of StoreCondReq hits 647system.cpu0.dcache.demand_hits::cpu0.data 149219632 # number of demand (read+write) hits 648system.cpu0.dcache.demand_hits::total 149219632 # number of demand (read+write) hits 649system.cpu0.dcache.overall_hits::cpu0.data 149409217 # number of overall hits 650system.cpu0.dcache.overall_hits::total 149409217 # number of overall hits 651system.cpu0.dcache.ReadReq_misses::cpu0.data 3014242 # number of ReadReq misses 652system.cpu0.dcache.ReadReq_misses::total 3014242 # number of ReadReq misses 653system.cpu0.dcache.WriteReq_misses::cpu0.data 1370827 # number of WriteReq misses 654system.cpu0.dcache.WriteReq_misses::total 1370827 # number of WriteReq misses 655system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635540 # number of SoftPFReq misses 656system.cpu0.dcache.SoftPFReq_misses::total 635540 # number of SoftPFReq misses 657system.cpu0.dcache.WriteLineReq_misses::cpu0.data 782263 # number of WriteLineReq misses 658system.cpu0.dcache.WriteLineReq_misses::total 782263 # number of WriteLineReq misses 659system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168057 # number of LoadLockedReq misses 660system.cpu0.dcache.LoadLockedReq_misses::total 168057 # number of LoadLockedReq misses 661system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197269 # number of StoreCondReq misses 662system.cpu0.dcache.StoreCondReq_misses::total 197269 # number of StoreCondReq misses 663system.cpu0.dcache.demand_misses::cpu0.data 4385069 # number of demand (read+write) misses 664system.cpu0.dcache.demand_misses::total 4385069 # number of demand (read+write) misses 665system.cpu0.dcache.overall_misses::cpu0.data 5020609 # number of overall misses 666system.cpu0.dcache.overall_misses::total 5020609 # number of overall misses 667system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52298763500 # number of ReadReq miss cycles 668system.cpu0.dcache.ReadReq_miss_latency::total 52298763500 # number of ReadReq miss cycles 669system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33070874000 # number of WriteReq miss cycles 670system.cpu0.dcache.WriteReq_miss_latency::total 33070874000 # number of WriteReq miss cycles 671system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65701301500 # number of WriteLineReq miss cycles 672system.cpu0.dcache.WriteLineReq_miss_latency::total 65701301500 # number of WriteLineReq miss cycles 673system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2847254500 # number of LoadLockedReq miss cycles 674system.cpu0.dcache.LoadLockedReq_miss_latency::total 2847254500 # number of LoadLockedReq miss cycles 675system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4866222000 # number of StoreCondReq miss cycles 676system.cpu0.dcache.StoreCondReq_miss_latency::total 4866222000 # number of StoreCondReq miss cycles 677system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3481500 # number of StoreCondFailReq miss cycles 678system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3481500 # number of StoreCondFailReq miss cycles 679system.cpu0.dcache.demand_miss_latency::cpu0.data 85369637500 # number of demand (read+write) miss cycles 680system.cpu0.dcache.demand_miss_latency::total 85369637500 # number of demand (read+write) miss cycles 681system.cpu0.dcache.overall_miss_latency::cpu0.data 85369637500 # number of overall miss cycles 682system.cpu0.dcache.overall_miss_latency::total 85369637500 # number of overall miss cycles 683system.cpu0.dcache.ReadReq_accesses::cpu0.data 80298562 # number of ReadReq accesses(hits+misses) 684system.cpu0.dcache.ReadReq_accesses::total 80298562 # number of ReadReq accesses(hits+misses) 685system.cpu0.dcache.WriteReq_accesses::cpu0.data 73306139 # number of WriteReq accesses(hits+misses) 686system.cpu0.dcache.WriteReq_accesses::total 73306139 # number of WriteReq accesses(hits+misses) 687system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825125 # number of SoftPFReq accesses(hits+misses) 688system.cpu0.dcache.SoftPFReq_accesses::total 825125 # number of SoftPFReq accesses(hits+misses) 689system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 907851 # number of WriteLineReq accesses(hits+misses) 690system.cpu0.dcache.WriteLineReq_accesses::total 907851 # number of WriteLineReq accesses(hits+misses) 691system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898641 # number of LoadLockedReq accesses(hits+misses) 692system.cpu0.dcache.LoadLockedReq_accesses::total 1898641 # number of LoadLockedReq accesses(hits+misses) 693system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897041 # number of StoreCondReq accesses(hits+misses) 694system.cpu0.dcache.StoreCondReq_accesses::total 1897041 # number of StoreCondReq accesses(hits+misses) 695system.cpu0.dcache.demand_accesses::cpu0.data 153604701 # number of demand (read+write) accesses 696system.cpu0.dcache.demand_accesses::total 153604701 # number of demand (read+write) accesses 697system.cpu0.dcache.overall_accesses::cpu0.data 154429826 # number of overall (read+write) accesses 698system.cpu0.dcache.overall_accesses::total 154429826 # number of overall (read+write) accesses 699system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037538 # miss rate for ReadReq accesses 700system.cpu0.dcache.ReadReq_miss_rate::total 0.037538 # miss rate for ReadReq accesses 701system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018700 # miss rate for WriteReq accesses 702system.cpu0.dcache.WriteReq_miss_rate::total 0.018700 # miss rate for WriteReq accesses 703system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770235 # miss rate for SoftPFReq accesses 704system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770235 # miss rate for SoftPFReq accesses 705system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.861665 # miss rate for WriteLineReq accesses 706system.cpu0.dcache.WriteLineReq_miss_rate::total 0.861665 # miss rate for WriteLineReq accesses 707system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088514 # miss rate for LoadLockedReq accesses 708system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088514 # miss rate for LoadLockedReq accesses 709system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103988 # miss rate for StoreCondReq accesses 710system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103988 # miss rate for StoreCondReq accesses 711system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028548 # miss rate for demand accesses 712system.cpu0.dcache.demand_miss_rate::total 0.028548 # miss rate for demand accesses 713system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032511 # miss rate for overall accesses 714system.cpu0.dcache.overall_miss_rate::total 0.032511 # miss rate for overall accesses 715system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311 # average ReadReq miss latency 716system.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311 # average ReadReq miss latency 717system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184 # average WriteReq miss latency 718system.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184 # average WriteReq miss latency 719system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731 # average WriteLineReq miss latency 720system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731 # average WriteLineReq miss latency 721system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208 # average LoadLockedReq miss latency 722system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208 # average LoadLockedReq miss latency 723system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869 # average StoreCondReq miss latency 724system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869 # average StoreCondReq miss latency 725system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 726system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 727system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091 # average overall miss latency 728system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091 # average overall miss latency 729system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068 # average overall miss latency 731system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 732system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu0.dcache.fast_writes 0 # number of fast writes performed 738system.cpu0.dcache.cache_copies 0 # number of cache copies performed 739system.cpu0.dcache.writebacks::writebacks 3771246 # number of writebacks 740system.cpu0.dcache.writebacks::total 3771246 # number of writebacks 741system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 38597 # number of ReadReq MSHR hits 742system.cpu0.dcache.ReadReq_mshr_hits::total 38597 # number of ReadReq MSHR hits 743system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21414 # number of WriteReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::total 21414 # number of WriteReq MSHR hits 745system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46766 # number of LoadLockedReq MSHR hits 746system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46766 # number of LoadLockedReq MSHR hits 747system.cpu0.dcache.demand_mshr_hits::cpu0.data 60011 # number of demand (read+write) MSHR hits 748system.cpu0.dcache.demand_mshr_hits::total 60011 # number of demand (read+write) MSHR hits 749system.cpu0.dcache.overall_mshr_hits::cpu0.data 60011 # number of overall MSHR hits 750system.cpu0.dcache.overall_mshr_hits::total 60011 # number of overall MSHR hits 751system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2975645 # number of ReadReq MSHR misses 752system.cpu0.dcache.ReadReq_mshr_misses::total 2975645 # number of ReadReq MSHR misses 753system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1349413 # number of WriteReq MSHR misses 754system.cpu0.dcache.WriteReq_mshr_misses::total 1349413 # number of WriteReq MSHR misses 755system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 629920 # number of SoftPFReq MSHR misses 756system.cpu0.dcache.SoftPFReq_mshr_misses::total 629920 # number of SoftPFReq MSHR misses 757system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 782263 # number of WriteLineReq MSHR misses 758system.cpu0.dcache.WriteLineReq_mshr_misses::total 782263 # number of WriteLineReq MSHR misses 759system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121291 # number of LoadLockedReq MSHR misses 760system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121291 # number of LoadLockedReq MSHR misses 761system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197269 # number of StoreCondReq MSHR misses 762system.cpu0.dcache.StoreCondReq_mshr_misses::total 197269 # number of StoreCondReq MSHR misses 763system.cpu0.dcache.demand_mshr_misses::cpu0.data 4325058 # number of demand (read+write) MSHR misses 764system.cpu0.dcache.demand_mshr_misses::total 4325058 # number of demand (read+write) MSHR misses 765system.cpu0.dcache.overall_mshr_misses::cpu0.data 4954978 # number of overall MSHR misses 766system.cpu0.dcache.overall_mshr_misses::total 4954978 # number of overall MSHR misses 767system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable 768system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17296 # number of ReadReq MSHR uncacheable 769system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable 770system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable 771system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses 772system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35915 # number of overall MSHR uncacheable misses 773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46589316500 # number of ReadReq MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46589316500 # number of ReadReq MSHR miss cycles 775system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30941514500 # number of WriteReq MSHR miss cycles 776system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30941514500 # number of WriteReq MSHR miss cycles 777system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17872150500 # number of SoftPFReq MSHR miss cycles 778system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17872150500 # number of SoftPFReq MSHR miss cycles 779system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64919038500 # number of WriteLineReq MSHR miss cycles 780system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64919038500 # number of WriteLineReq MSHR miss cycles 781system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795061500 # number of LoadLockedReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795061500 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4668993000 # number of StoreCondReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4668993000 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77530831000 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 77530831000 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 95402981500 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 95402981500 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2879350000 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2879350000 # number of ReadReq MSHR uncacheable cycles 793system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3091479000 # number of WriteReq MSHR uncacheable cycles 794system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3091479000 # number of WriteReq MSHR uncacheable cycles 795system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5970829000 # number of overall MSHR uncacheable cycles 796system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5970829000 # number of overall MSHR uncacheable cycles 797system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037057 # mshr miss rate for ReadReq accesses 798system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037057 # mshr miss rate for ReadReq accesses 799system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018408 # mshr miss rate for WriteReq accesses 800system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018408 # mshr miss rate for WriteReq accesses 801system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763424 # mshr miss rate for SoftPFReq accesses 802system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763424 # mshr miss rate for SoftPFReq accesses 803system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.861665 # mshr miss rate for WriteLineReq accesses 804system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.861665 # mshr miss rate for WriteLineReq accesses 805system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063883 # mshr miss rate for LoadLockedReq accesses 806system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063883 # mshr miss rate for LoadLockedReq accesses 807system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103988 # mshr miss rate for StoreCondReq accesses 808system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103988 # mshr miss rate for StoreCondReq accesses 809system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028157 # mshr miss rate for demand accesses 810system.cpu0.dcache.demand_mshr_miss_rate::total 0.028157 # mshr miss rate for demand accesses 811system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032086 # mshr miss rate for overall accesses 812system.cpu0.dcache.overall_mshr_miss_rate::total 0.032086 # mshr miss rate for overall accesses 813system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937 # average ReadReq mshr miss latency 814system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937 # average ReadReq mshr miss latency 815system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505 # average WriteReq mshr miss latency 816system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505 # average WriteReq mshr miss latency 817system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663 # average SoftPFReq mshr miss latency 818system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663 # average SoftPFReq mshr miss latency 819system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731 # average WriteLineReq mshr miss latency 820system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731 # average WriteLineReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518 # average LoadLockedReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638 # average StoreCondReq mshr miss latency 824system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638 # average StoreCondReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 826system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305 # average overall mshr miss latency 828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718 # average overall mshr miss latency 830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718 # average overall mshr miss latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493 # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493 # average ReadReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719 # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719 # average WriteReq mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220 # average overall mshr uncacheable latency 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220 # average overall mshr uncacheable latency 837system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 838system.cpu0.icache.tags.replacements 5319178 # number of replacements 839system.cpu0.icache.tags.tagsinuse 511.824621 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 435885421 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 5319690 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 81.938124 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 59948153000 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.824621 # Average occupied blocks per requestor 845system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999657 # Average percentage of cache occupancy 846system.cpu0.icache.tags.occ_percent::total 0.999657 # Average percentage of cache occupancy 847system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 848system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 849system.cpu0.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 850system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 851system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 852system.cpu0.icache.tags.tag_accesses 887729927 # Number of tag accesses 853system.cpu0.icache.tags.data_accesses 887729927 # Number of data accesses 854system.cpu0.icache.ReadReq_hits::cpu0.inst 435885421 # number of ReadReq hits 855system.cpu0.icache.ReadReq_hits::total 435885421 # number of ReadReq hits 856system.cpu0.icache.demand_hits::cpu0.inst 435885421 # number of demand (read+write) hits 857system.cpu0.icache.demand_hits::total 435885421 # number of demand (read+write) hits 858system.cpu0.icache.overall_hits::cpu0.inst 435885421 # number of overall hits 859system.cpu0.icache.overall_hits::total 435885421 # number of overall hits 860system.cpu0.icache.ReadReq_misses::cpu0.inst 5319695 # number of ReadReq misses 861system.cpu0.icache.ReadReq_misses::total 5319695 # number of ReadReq misses 862system.cpu0.icache.demand_misses::cpu0.inst 5319695 # number of demand (read+write) misses 863system.cpu0.icache.demand_misses::total 5319695 # number of demand (read+write) misses 864system.cpu0.icache.overall_misses::cpu0.inst 5319695 # number of overall misses 865system.cpu0.icache.overall_misses::total 5319695 # number of overall misses 866system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 59521353000 # number of ReadReq miss cycles 867system.cpu0.icache.ReadReq_miss_latency::total 59521353000 # number of ReadReq miss cycles 868system.cpu0.icache.demand_miss_latency::cpu0.inst 59521353000 # number of demand (read+write) miss cycles 869system.cpu0.icache.demand_miss_latency::total 59521353000 # number of demand (read+write) miss cycles 870system.cpu0.icache.overall_miss_latency::cpu0.inst 59521353000 # number of overall miss cycles 871system.cpu0.icache.overall_miss_latency::total 59521353000 # number of overall miss cycles 872system.cpu0.icache.ReadReq_accesses::cpu0.inst 441205116 # number of ReadReq accesses(hits+misses) 873system.cpu0.icache.ReadReq_accesses::total 441205116 # number of ReadReq accesses(hits+misses) 874system.cpu0.icache.demand_accesses::cpu0.inst 441205116 # number of demand (read+write) accesses 875system.cpu0.icache.demand_accesses::total 441205116 # number of demand (read+write) accesses 876system.cpu0.icache.overall_accesses::cpu0.inst 441205116 # number of overall (read+write) accesses 877system.cpu0.icache.overall_accesses::total 441205116 # number of overall (read+write) accesses 878system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012057 # miss rate for ReadReq accesses 879system.cpu0.icache.ReadReq_miss_rate::total 0.012057 # miss rate for ReadReq accesses 880system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012057 # miss rate for demand accesses 881system.cpu0.icache.demand_miss_rate::total 0.012057 # miss rate for demand accesses 882system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012057 # miss rate for overall accesses 883system.cpu0.icache.overall_miss_rate::total 0.012057 # miss rate for overall accesses 884system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715 # average ReadReq miss latency 885system.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715 # average ReadReq miss latency 886system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency 887system.cpu0.icache.demand_avg_miss_latency::total 11188.865715 # average overall miss latency 888system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency 889system.cpu0.icache.overall_avg_miss_latency::total 11188.865715 # average overall miss latency 890system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 896system.cpu0.icache.fast_writes 0 # number of fast writes performed 897system.cpu0.icache.cache_copies 0 # number of cache copies performed 898system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5319695 # number of ReadReq MSHR misses 899system.cpu0.icache.ReadReq_mshr_misses::total 5319695 # number of ReadReq MSHR misses 900system.cpu0.icache.demand_mshr_misses::cpu0.inst 5319695 # number of demand (read+write) MSHR misses 901system.cpu0.icache.demand_mshr_misses::total 5319695 # number of demand (read+write) MSHR misses 902system.cpu0.icache.overall_mshr_misses::cpu0.inst 5319695 # number of overall MSHR misses 903system.cpu0.icache.overall_mshr_misses::total 5319695 # number of overall MSHR misses 904system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 905system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 906system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 907system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 908system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 56861505500 # number of ReadReq MSHR miss cycles 909system.cpu0.icache.ReadReq_mshr_miss_latency::total 56861505500 # number of ReadReq MSHR miss cycles 910system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 56861505500 # number of demand (read+write) MSHR miss cycles 911system.cpu0.icache.demand_mshr_miss_latency::total 56861505500 # number of demand (read+write) MSHR miss cycles 912system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 56861505500 # number of overall MSHR miss cycles 913system.cpu0.icache.overall_mshr_miss_latency::total 56861505500 # number of overall MSHR miss cycles 914system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of ReadReq MSHR uncacheable cycles 915system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5953877000 # number of ReadReq MSHR uncacheable cycles 916system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of overall MSHR uncacheable cycles 917system.cpu0.icache.overall_mshr_uncacheable_latency::total 5953877000 # number of overall MSHR uncacheable cycles 918system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for ReadReq accesses 919system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012057 # mshr miss rate for ReadReq accesses 920system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for demand accesses 921system.cpu0.icache.demand_mshr_miss_rate::total 0.012057 # mshr miss rate for demand accesses 922system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for overall accesses 923system.cpu0.icache.overall_mshr_miss_rate::total 0.012057 # mshr miss rate for overall accesses 924system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average ReadReq mshr miss latency 925system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715 # average ReadReq mshr miss latency 926system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency 927system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency 928system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency 929system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency 930system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average ReadReq mshr uncacheable latency 931system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942 # average ReadReq mshr uncacheable latency 932system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average overall mshr uncacheable latency 933system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942 # average overall mshr uncacheable latency 934system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.cpu0.l2cache.prefetcher.num_hwpf_issued 7344223 # number of hwpf issued 936system.cpu0.l2cache.prefetcher.pfIdentified 7344239 # number of prefetch candidates identified 937system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 938system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 939system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 940system.cpu0.l2cache.prefetcher.pfSpanPage 976449 # number of prefetches not generated due to page crossing 941system.cpu0.l2cache.tags.replacements 2329725 # number of replacements 942system.cpu0.l2cache.tags.tagsinuse 16186.065873 # Cycle average of tags in use 943system.cpu0.l2cache.tags.total_refs 18053337 # Total number of references to valid blocks. 944system.cpu0.l2cache.tags.sampled_refs 2345760 # Sample count of references to valid blocks. 945system.cpu0.l2cache.tags.avg_refs 7.696157 # Average number of references to valid blocks. 946system.cpu0.l2cache.tags.warmup_cycle 55834398000 # Cycle when the warmup percentage was hit. 947system.cpu0.l2cache.tags.occ_blocks::writebacks 6981.301122 # Average occupied blocks per requestor 948system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.056568 # Average occupied blocks per requestor 949system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 81.620115 # Average occupied blocks per requestor 950system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4075.206909 # Average occupied blocks per requestor 951system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4054.876060 # Average occupied blocks per requestor 952system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 929.005098 # Average occupied blocks per requestor 953system.cpu0.l2cache.tags.occ_percent::writebacks 0.426105 # Average percentage of cache occupancy 954system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003910 # Average percentage of cache occupancy 955system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004982 # Average percentage of cache occupancy 956system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.248731 # Average percentage of cache occupancy 957system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.247490 # Average percentage of cache occupancy 958system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056702 # Average percentage of cache occupancy 959system.cpu0.l2cache.tags.occ_percent::total 0.987919 # Average percentage of cache occupancy 960system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id 961system.cpu0.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 962system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14643 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 806 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4474 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5446 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3835 # Occupied blocks per task id 975system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082092 # Percentage of cache occupancy per task id 976system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.893738 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.tag_accesses 367456425 # Number of tag accesses 979system.cpu0.l2cache.tags.data_accesses 367456425 # Number of data accesses 980system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 210868 # number of ReadReq hits 981system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 144785 # number of ReadReq hits 982system.cpu0.l2cache.ReadReq_hits::total 355653 # number of ReadReq hits 983system.cpu0.l2cache.Writeback_hits::writebacks 3771244 # number of Writeback hits 984system.cpu0.l2cache.Writeback_hits::total 3771244 # number of Writeback hits 985system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 99488 # number of UpgradeReq hits 986system.cpu0.l2cache.UpgradeReq_hits::total 99488 # number of UpgradeReq hits 987system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31647 # number of SCUpgradeReq hits 988system.cpu0.l2cache.SCUpgradeReq_hits::total 31647 # number of SCUpgradeReq hits 989system.cpu0.l2cache.ReadExReq_hits::cpu0.data 896733 # number of ReadExReq hits 990system.cpu0.l2cache.ReadExReq_hits::total 896733 # number of ReadExReq hits 991system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4806679 # number of ReadCleanReq hits 992system.cpu0.l2cache.ReadCleanReq_hits::total 4806679 # number of ReadCleanReq hits 993system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2773726 # number of ReadSharedReq hits 994system.cpu0.l2cache.ReadSharedReq_hits::total 2773726 # number of ReadSharedReq hits 995system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 232290 # number of InvalidateReq hits 996system.cpu0.l2cache.InvalidateReq_hits::total 232290 # number of InvalidateReq hits 997system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 210868 # number of demand (read+write) hits 998system.cpu0.l2cache.demand_hits::cpu0.itb.walker 144785 # number of demand (read+write) hits 999system.cpu0.l2cache.demand_hits::cpu0.inst 4806679 # number of demand (read+write) hits 1000system.cpu0.l2cache.demand_hits::cpu0.data 3670459 # number of demand (read+write) hits 1001system.cpu0.l2cache.demand_hits::total 8832791 # number of demand (read+write) hits 1002system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 210868 # number of overall hits 1003system.cpu0.l2cache.overall_hits::cpu0.itb.walker 144785 # number of overall hits 1004system.cpu0.l2cache.overall_hits::cpu0.inst 4806679 # number of overall hits 1005system.cpu0.l2cache.overall_hits::cpu0.data 3670459 # number of overall hits 1006system.cpu0.l2cache.overall_hits::total 8832791 # number of overall hits 1007system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10391 # number of ReadReq misses 1008system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9054 # number of ReadReq misses 1009system.cpu0.l2cache.ReadReq_misses::total 19445 # number of ReadReq misses 1010system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121662 # number of UpgradeReq misses 1011system.cpu0.l2cache.UpgradeReq_misses::total 121662 # number of UpgradeReq misses 1012system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 165610 # number of SCUpgradeReq misses 1013system.cpu0.l2cache.SCUpgradeReq_misses::total 165610 # number of SCUpgradeReq misses 1014system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses 1015system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses 1016system.cpu0.l2cache.ReadExReq_misses::cpu0.data 248725 # number of ReadExReq misses 1017system.cpu0.l2cache.ReadExReq_misses::total 248725 # number of ReadExReq misses 1018system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 513016 # number of ReadCleanReq misses 1019system.cpu0.l2cache.ReadCleanReq_misses::total 513016 # number of ReadCleanReq misses 1020system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953130 # number of ReadSharedReq misses 1021system.cpu0.l2cache.ReadSharedReq_misses::total 953130 # number of ReadSharedReq misses 1022system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 548738 # number of InvalidateReq misses 1023system.cpu0.l2cache.InvalidateReq_misses::total 548738 # number of InvalidateReq misses 1024system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10391 # number of demand (read+write) misses 1025system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9054 # number of demand (read+write) misses 1026system.cpu0.l2cache.demand_misses::cpu0.inst 513016 # number of demand (read+write) misses 1027system.cpu0.l2cache.demand_misses::cpu0.data 1201855 # number of demand (read+write) misses 1028system.cpu0.l2cache.demand_misses::total 1734316 # number of demand (read+write) misses 1029system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10391 # number of overall misses 1030system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9054 # number of overall misses 1031system.cpu0.l2cache.overall_misses::cpu0.inst 513016 # number of overall misses 1032system.cpu0.l2cache.overall_misses::cpu0.data 1201855 # number of overall misses 1033system.cpu0.l2cache.overall_misses::total 1734316 # number of overall misses 1034system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 495108500 # number of ReadReq miss cycles 1035system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 493404500 # number of ReadReq miss cycles 1036system.cpu0.l2cache.ReadReq_miss_latency::total 988513000 # number of ReadReq miss cycles 1037system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3820404000 # number of UpgradeReq miss cycles 1038system.cpu0.l2cache.UpgradeReq_miss_latency::total 3820404000 # number of UpgradeReq miss cycles 1039system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3956624500 # number of SCUpgradeReq miss cycles 1040system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3956624500 # number of SCUpgradeReq miss cycles 1041system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3380498 # number of SCUpgradeFailReq miss cycles 1042system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3380498 # number of SCUpgradeFailReq miss cycles 1043system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16864079500 # number of ReadExReq miss cycles 1044system.cpu0.l2cache.ReadExReq_miss_latency::total 16864079500 # number of ReadExReq miss cycles 1045system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20224946500 # number of ReadCleanReq miss cycles 1046system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20224946500 # number of ReadCleanReq miss cycles 1047system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 42635415000 # number of ReadSharedReq miss cycles 1048system.cpu0.l2cache.ReadSharedReq_miss_latency::total 42635415000 # number of ReadSharedReq miss cycles 1049system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62221144000 # number of InvalidateReq miss cycles 1050system.cpu0.l2cache.InvalidateReq_miss_latency::total 62221144000 # number of InvalidateReq miss cycles 1051system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 495108500 # number of demand (read+write) miss cycles 1052system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 493404500 # number of demand (read+write) miss cycles 1053system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20224946500 # number of demand (read+write) miss cycles 1054system.cpu0.l2cache.demand_miss_latency::cpu0.data 59499494500 # number of demand (read+write) miss cycles 1055system.cpu0.l2cache.demand_miss_latency::total 80712954000 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 495108500 # number of overall miss cycles 1057system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 493404500 # number of overall miss cycles 1058system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20224946500 # number of overall miss cycles 1059system.cpu0.l2cache.overall_miss_latency::cpu0.data 59499494500 # number of overall miss cycles 1060system.cpu0.l2cache.overall_miss_latency::total 80712954000 # number of overall miss cycles 1061system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221259 # number of ReadReq accesses(hits+misses) 1062system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 153839 # number of ReadReq accesses(hits+misses) 1063system.cpu0.l2cache.ReadReq_accesses::total 375098 # number of ReadReq accesses(hits+misses) 1064system.cpu0.l2cache.Writeback_accesses::writebacks 3771244 # number of Writeback accesses(hits+misses) 1065system.cpu0.l2cache.Writeback_accesses::total 3771244 # number of Writeback accesses(hits+misses) 1066system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 221150 # number of UpgradeReq accesses(hits+misses) 1067system.cpu0.l2cache.UpgradeReq_accesses::total 221150 # number of UpgradeReq accesses(hits+misses) 1068system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197257 # number of SCUpgradeReq accesses(hits+misses) 1069system.cpu0.l2cache.SCUpgradeReq_accesses::total 197257 # number of SCUpgradeReq accesses(hits+misses) 1070system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses) 1071system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) 1072system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1145458 # number of ReadExReq accesses(hits+misses) 1073system.cpu0.l2cache.ReadExReq_accesses::total 1145458 # number of ReadExReq accesses(hits+misses) 1074system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5319695 # number of ReadCleanReq accesses(hits+misses) 1075system.cpu0.l2cache.ReadCleanReq_accesses::total 5319695 # number of ReadCleanReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3726856 # number of ReadSharedReq accesses(hits+misses) 1077system.cpu0.l2cache.ReadSharedReq_accesses::total 3726856 # number of ReadSharedReq accesses(hits+misses) 1078system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 781028 # number of InvalidateReq accesses(hits+misses) 1079system.cpu0.l2cache.InvalidateReq_accesses::total 781028 # number of InvalidateReq accesses(hits+misses) 1080system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221259 # number of demand (read+write) accesses 1081system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 153839 # number of demand (read+write) accesses 1082system.cpu0.l2cache.demand_accesses::cpu0.inst 5319695 # number of demand (read+write) accesses 1083system.cpu0.l2cache.demand_accesses::cpu0.data 4872314 # number of demand (read+write) accesses 1084system.cpu0.l2cache.demand_accesses::total 10567107 # number of demand (read+write) accesses 1085system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221259 # number of overall (read+write) accesses 1086system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 153839 # number of overall (read+write) accesses 1087system.cpu0.l2cache.overall_accesses::cpu0.inst 5319695 # number of overall (read+write) accesses 1088system.cpu0.l2cache.overall_accesses::cpu0.data 4872314 # number of overall (read+write) accesses 1089system.cpu0.l2cache.overall_accesses::total 10567107 # number of overall (read+write) accesses 1090system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for ReadReq accesses 1091system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058854 # miss rate for ReadReq accesses 1092system.cpu0.l2cache.ReadReq_miss_rate::total 0.051840 # miss rate for ReadReq accesses 1093system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550133 # miss rate for UpgradeReq accesses 1094system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550133 # miss rate for UpgradeReq accesses 1095system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.839565 # miss rate for SCUpgradeReq accesses 1096system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.839565 # miss rate for SCUpgradeReq accesses 1097system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1098system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1099system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217140 # miss rate for ReadExReq accesses 1100system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217140 # miss rate for ReadExReq accesses 1101system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096437 # miss rate for ReadCleanReq accesses 1102system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096437 # miss rate for ReadCleanReq accesses 1103system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255746 # miss rate for ReadSharedReq accesses 1104system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255746 # miss rate for ReadSharedReq accesses 1105system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.702584 # miss rate for InvalidateReq accesses 1106system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.702584 # miss rate for InvalidateReq accesses 1107system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for demand accesses 1108system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058854 # miss rate for demand accesses 1109system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096437 # miss rate for demand accesses 1110system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246670 # miss rate for demand accesses 1111system.cpu0.l2cache.demand_miss_rate::total 0.164124 # miss rate for demand accesses 1112system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for overall accesses 1113system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058854 # miss rate for overall accesses 1114system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096437 # miss rate for overall accesses 1115system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246670 # miss rate for overall accesses 1116system.cpu0.l2cache.overall_miss_rate::total 0.164124 # miss rate for overall accesses 1117system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average ReadReq miss latency 1118system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54495.747736 # average ReadReq miss latency 1119system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50836.358961 # average ReadReq miss latency 1120system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31401.785274 # average UpgradeReq miss latency 1121system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31401.785274 # average UpgradeReq miss latency 1122system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23891.217318 # average SCUpgradeReq miss latency 1123system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23891.217318 # average SCUpgradeReq miss latency 1124system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 281708.166667 # average SCUpgradeFailReq miss latency 1125system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 281708.166667 # average SCUpgradeFailReq miss latency 1126system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67802.108755 # average ReadExReq miss latency 1127system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67802.108755 # average ReadExReq miss latency 1128system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39423.617392 # average ReadCleanReq miss latency 1129system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39423.617392 # average ReadCleanReq miss latency 1130system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44732.004029 # average ReadSharedReq miss latency 1131system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44732.004029 # average ReadSharedReq miss latency 1132system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113389.530158 # average InvalidateReq miss latency 1133system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113389.530158 # average InvalidateReq miss latency 1134system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency 1135system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency 1136system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency 1137system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::total 46538.781860 # average overall miss latency 1139system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency 1140system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency 1141system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency 1142system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::total 46538.781860 # average overall miss latency 1144system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1145system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1146system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1147system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1148system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1149system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1150system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1151system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1152system.cpu0.l2cache.writebacks::writebacks 1299353 # number of writebacks 1153system.cpu0.l2cache.writebacks::total 1299353 # number of writebacks 1154system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4520 # number of ReadExReq MSHR hits 1155system.cpu0.l2cache.ReadExReq_mshr_hits::total 4520 # number of ReadExReq MSHR hits 1156system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 530 # number of ReadSharedReq MSHR hits 1157system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 530 # number of ReadSharedReq MSHR hits 1158system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5050 # number of demand (read+write) MSHR hits 1159system.cpu0.l2cache.demand_mshr_hits::total 5050 # number of demand (read+write) MSHR hits 1160system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5050 # number of overall MSHR hits 1161system.cpu0.l2cache.overall_mshr_hits::total 5050 # number of overall MSHR hits 1162system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10391 # number of ReadReq MSHR misses 1163system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9054 # number of ReadReq MSHR misses 1164system.cpu0.l2cache.ReadReq_mshr_misses::total 19445 # number of ReadReq MSHR misses 1165system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 93813 # number of CleanEvict MSHR misses 1166system.cpu0.l2cache.CleanEvict_mshr_misses::total 93813 # number of CleanEvict MSHR misses 1167system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of HardPFReq MSHR misses 1168system.cpu0.l2cache.HardPFReq_mshr_misses::total 630880 # number of HardPFReq MSHR misses 1169system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121662 # number of UpgradeReq MSHR misses 1170system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121662 # number of UpgradeReq MSHR misses 1171system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 165610 # number of SCUpgradeReq MSHR misses 1172system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 165610 # number of SCUpgradeReq MSHR misses 1173system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 12 # number of SCUpgradeFailReq MSHR misses 1174system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 12 # number of SCUpgradeFailReq MSHR misses 1175system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 244205 # number of ReadExReq MSHR misses 1176system.cpu0.l2cache.ReadExReq_mshr_misses::total 244205 # number of ReadExReq MSHR misses 1177system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 513016 # number of ReadCleanReq MSHR misses 1178system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 513016 # number of ReadCleanReq MSHR misses 1179system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 952600 # number of ReadSharedReq MSHR misses 1180system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 952600 # number of ReadSharedReq MSHR misses 1181system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 548738 # number of InvalidateReq MSHR misses 1182system.cpu0.l2cache.InvalidateReq_mshr_misses::total 548738 # number of InvalidateReq MSHR misses 1183system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10391 # number of demand (read+write) MSHR misses 1184system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9054 # number of demand (read+write) MSHR misses 1185system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 513016 # number of demand (read+write) MSHR misses 1186system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1196805 # number of demand (read+write) MSHR misses 1187system.cpu0.l2cache.demand_mshr_misses::total 1729266 # number of demand (read+write) MSHR misses 1188system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10391 # number of overall MSHR misses 1189system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9054 # number of overall MSHR misses 1190system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 513016 # number of overall MSHR misses 1191system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1196805 # number of overall MSHR misses 1192system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of overall MSHR misses 1193system.cpu0.l2cache.overall_mshr_misses::total 2360146 # number of overall MSHR misses 1194system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1195system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable 1196system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 60421 # number of ReadReq MSHR uncacheable 1197system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable 1198system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable 1199system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1200system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses 1201system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 79040 # number of overall MSHR uncacheable misses 1202system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of ReadReq MSHR miss cycles 1203system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 439080500 # number of ReadReq MSHR miss cycles 1204system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 871843000 # number of ReadReq MSHR miss cycles 1205system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of HardPFReq MSHR miss cycles 1206system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35559655965 # number of HardPFReq MSHR miss cycles 1207system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4486256000 # number of UpgradeReq MSHR miss cycles 1208system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4486256000 # number of UpgradeReq MSHR miss cycles 1209system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3173949000 # number of SCUpgradeReq MSHR miss cycles 1210system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3173949000 # number of SCUpgradeReq MSHR miss cycles 1211system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3140498 # number of SCUpgradeFailReq MSHR miss cycles 1212system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3140498 # number of SCUpgradeFailReq MSHR miss cycles 1213system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14883734000 # number of ReadExReq MSHR miss cycles 1214system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14883734000 # number of ReadExReq MSHR miss cycles 1215system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17146850500 # number of ReadCleanReq MSHR miss cycles 1216system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17146850500 # number of ReadCleanReq MSHR miss cycles 1217system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36873595000 # number of ReadSharedReq MSHR miss cycles 1218system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36873595000 # number of ReadSharedReq MSHR miss cycles 1219system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58928716000 # number of InvalidateReq MSHR miss cycles 1220system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58928716000 # number of InvalidateReq MSHR miss cycles 1221system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of demand (read+write) MSHR miss cycles 1222system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 439080500 # number of demand (read+write) MSHR miss cycles 1223system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17146850500 # number of demand (read+write) MSHR miss cycles 1224system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51757329000 # number of demand (read+write) MSHR miss cycles 1225system.cpu0.l2cache.demand_mshr_miss_latency::total 69776022500 # number of demand (read+write) MSHR miss cycles 1226system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of overall MSHR miss cycles 1227system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 439080500 # number of overall MSHR miss cycles 1228system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17146850500 # number of overall MSHR miss cycles 1229system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51757329000 # number of overall MSHR miss cycles 1230system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of overall MSHR miss cycles 1231system.cpu0.l2cache.overall_mshr_miss_latency::total 105335678465 # number of overall MSHR miss cycles 1232system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of ReadReq MSHR uncacheable cycles 1233system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2740982000 # number of ReadReq MSHR uncacheable cycles 1234system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8371421500 # number of ReadReq MSHR uncacheable cycles 1235system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2951836500 # number of WriteReq MSHR uncacheable cycles 1236system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2951836500 # number of WriteReq MSHR uncacheable cycles 1237system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of overall MSHR uncacheable cycles 1238system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5692818500 # number of overall MSHR uncacheable cycles 1239system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11323258000 # number of overall MSHR uncacheable cycles 1240system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for ReadReq accesses 1241system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for ReadReq accesses 1242system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.051840 # mshr miss rate for ReadReq accesses 1243system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1244system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1245system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1246system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1247system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550133 # mshr miss rate for UpgradeReq accesses 1248system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550133 # mshr miss rate for UpgradeReq accesses 1249system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.839565 # mshr miss rate for SCUpgradeReq accesses 1250system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839565 # mshr miss rate for SCUpgradeReq accesses 1251system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1252system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1253system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213194 # mshr miss rate for ReadExReq accesses 1254system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213194 # mshr miss rate for ReadExReq accesses 1255system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for ReadCleanReq accesses 1256system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096437 # mshr miss rate for ReadCleanReq accesses 1257system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255604 # mshr miss rate for ReadSharedReq accesses 1258system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255604 # mshr miss rate for ReadSharedReq accesses 1259system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.702584 # mshr miss rate for InvalidateReq accesses 1260system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.702584 # mshr miss rate for InvalidateReq accesses 1261system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for demand accesses 1262system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for demand accesses 1263system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for demand accesses 1264system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for demand accesses 1265system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163646 # mshr miss rate for demand accesses 1266system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for overall accesses 1267system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for overall accesses 1268system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for overall accesses 1269system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for overall accesses 1270system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1271system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223348 # mshr miss rate for overall accesses 1272system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average ReadReq mshr miss latency 1273system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average ReadReq mshr miss latency 1274system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961 # average ReadReq mshr miss latency 1275system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average HardPFReq mshr miss latency 1276system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062 # average HardPFReq mshr miss latency 1277system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360 # average UpgradeReq mshr miss latency 1278system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360 # average UpgradeReq mshr miss latency 1279system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377 # average SCUpgradeReq mshr miss latency 1280system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377 # average SCUpgradeReq mshr miss latency 1281system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667 # average SCUpgradeFailReq mshr miss latency 1282system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667 # average SCUpgradeFailReq mshr miss latency 1283system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773 # average ReadExReq mshr miss latency 1284system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773 # average ReadExReq mshr miss latency 1285system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average ReadCleanReq mshr miss latency 1286system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392 # average ReadCleanReq mshr miss latency 1287system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824 # average ReadSharedReq mshr miss latency 1288system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824 # average ReadSharedReq mshr miss latency 1289system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158 # average InvalidateReq mshr miss latency 1290system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158 # average InvalidateReq mshr miss latency 1291system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency 1292system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency 1293system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency 1294system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency 1295system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612 # average overall mshr miss latency 1296system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency 1297system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency 1298system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency 1299system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency 1300system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average overall mshr miss latency 1301system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991 # average overall mshr miss latency 1302system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average ReadReq mshr uncacheable latency 1303system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493 # average ReadReq mshr uncacheable latency 1304system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822 # average ReadReq mshr uncacheable latency 1305system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719 # average WriteReq mshr uncacheable latency 1306system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719 # average WriteReq mshr uncacheable latency 1307system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average overall mshr uncacheable latency 1308system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464 # average overall mshr uncacheable latency 1309system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117 # average overall mshr uncacheable latency 1310system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1311system.cpu0.toL2Bus.snoop_filter.tot_requests 22509328 # Total number of requests made to the snoop filter. 1312system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11536373 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1313system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 848 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1314system.cpu0.toL2Bus.snoop_filter.tot_snoops 485130 # Total number of snoops made to the snoop filter. 1315system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 485124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1316system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1317system.cpu0.toL2Bus.trans_dist::ReadReq 537841 # Transaction distribution 1318system.cpu0.toL2Bus.trans_dist::ReadResp 9675681 # Transaction distribution 1319system.cpu0.toL2Bus.trans_dist::WriteReq 18620 # Transaction distribution 1320system.cpu0.toL2Bus.trans_dist::WriteResp 18619 # Transaction distribution 1321system.cpu0.toL2Bus.trans_dist::Writeback 5107009 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::CleanEvict 8757288 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::HardPFReq 798537 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::UpgradeReq 405076 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363715 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::UpgradeResp 481157 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 40 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::ReadExReq 1220841 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::ReadExResp 1155337 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5319695 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4658319 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::InvalidateReq 788798 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::InvalidateResp 781028 # Transaction distribution 1335system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16044388 # Packet count per connected master and slave (bytes) 1336system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17944373 # Packet count per connected master and slave (bytes) 1337system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 336960 # Packet count per connected master and slave (bytes) 1338system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 515556 # Packet count per connected master and slave (bytes) 1339system.cpu0.toL2Bus.pkt_count::total 34841277 # Packet count per connected master and slave (bytes) 1340system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 340632980 # Cumulative packet size per connected master and slave (bytes) 1341system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 559762054 # Cumulative packet size per connected master and slave (bytes) 1342system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1230712 # Cumulative packet size per connected master and slave (bytes) 1343system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1770072 # Cumulative packet size per connected master and slave (bytes) 1344system.cpu0.toL2Bus.pkt_size::total 903395818 # Cumulative packet size per connected master and slave (bytes) 1345system.cpu0.toL2Bus.snoops 5410368 # Total snoops (count) 1346system.cpu0.toL2Bus.snoop_fanout::samples 27976627 # Request fanout histogram 1347system.cpu0.toL2Bus.snoop_fanout::mean 0.025738 # Request fanout histogram 1348system.cpu0.toL2Bus.snoop_fanout::stdev 0.158355 # Request fanout histogram 1349system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1350system.cpu0.toL2Bus.snoop_fanout::0 27256564 97.43% 97.43% # Request fanout histogram 1351system.cpu0.toL2Bus.snoop_fanout::1 720057 2.57% 100.00% # Request fanout histogram 1352system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 1353system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1354system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1355system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1356system.cpu0.toL2Bus.snoop_fanout::total 27976627 # Request fanout histogram 1357system.cpu0.toL2Bus.reqLayer0.occupancy 15196832497 # Layer occupancy (ticks) 1358system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1359system.cpu0.toL2Bus.snoopLayer0.occupancy 183439903 # Layer occupancy (ticks) 1360system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1361system.cpu0.toL2Bus.respLayer0.occupancy 8022667500 # Layer occupancy (ticks) 1362system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1363system.cpu0.toL2Bus.respLayer1.occupancy 7935130422 # Layer occupancy (ticks) 1364system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1365system.cpu0.toL2Bus.respLayer2.occupancy 183121000 # Layer occupancy (ticks) 1366system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1367system.cpu0.toL2Bus.respLayer3.occupancy 294297000 # Layer occupancy (ticks) 1368system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1369system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1370system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1371system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1372system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1373system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1374system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1375system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1376system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1377system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1378system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1379system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1380system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1381system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1382system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1383system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1384system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1385system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1386system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1387system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1388system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1389system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1390system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1391system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1392system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1393system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1394system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1395system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1396system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1397system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1398system.cpu1.dtb.walker.walks 111674 # Table walker walks requested 1399system.cpu1.dtb.walker.walksLong 111674 # Table walker walks initiated with long descriptors 1400system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10360 # Level at which table walker walks with long descriptors terminate 1401system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85053 # Level at which table walker walks with long descriptors terminate 1402system.cpu1.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting 1403system.cpu1.dtb.walker.walkWaitTime::samples 111653 # Table walker wait (enqueue to first request) latency 1404system.cpu1.dtb.walker.walkWaitTime::mean 0.241821 # Table walker wait (enqueue to first request) latency 1405system.cpu1.dtb.walker.walkWaitTime::stdev 61.696123 # Table walker wait (enqueue to first request) latency 1406system.cpu1.dtb.walker.walkWaitTime::0-2047 111651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1407system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1408system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1409system.cpu1.dtb.walker.walkWaitTime::total 111653 # Table walker wait (enqueue to first request) latency 1410system.cpu1.dtb.walker.walkCompletionTime::samples 95434 # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778 # Table walker service (enqueue to completion) latency 1412system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562 # Table walker service (enqueue to completion) latency 1413system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011 # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::0-65535 94629 99.16% 99.16% # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walkCompletionTime::65536-131071 150 0.16% 99.31% # Table walker service (enqueue to completion) latency 1416system.cpu1.dtb.walker.walkCompletionTime::131072-196607 551 0.58% 99.89% # Table walker service (enqueue to completion) latency 1417system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.91% # Table walker service (enqueue to completion) latency 1418system.cpu1.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.95% # Table walker service (enqueue to completion) latency 1419system.cpu1.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 99.96% # Table walker service (enqueue to completion) latency 1420system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 99.98% # Table walker service (enqueue to completion) latency 1421system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 1422system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1423system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1424system.cpu1.dtb.walker.walkCompletionTime::total 95434 # Table walker service (enqueue to completion) latency 1425system.cpu1.dtb.walker.walksPending::samples 10744163364 # Table walker pending requests distribution 1426system.cpu1.dtb.walker.walksPending::mean 1.061708 # Table walker pending requests distribution 1427system.cpu1.dtb.walker.walksPending::0 -663005280 -6.17% -6.17% # Table walker pending requests distribution 1428system.cpu1.dtb.walker.walksPending::1 11407168644 106.17% 100.00% # Table walker pending requests distribution 1429system.cpu1.dtb.walker.walksPending::total 10744163364 # Table walker pending requests distribution 1430system.cpu1.dtb.walker.walkPageSizes::4K 85053 89.14% 89.14% # Table walker page sizes translated 1431system.cpu1.dtb.walker.walkPageSizes::2M 10360 10.86% 100.00% # Table walker page sizes translated 1432system.cpu1.dtb.walker.walkPageSizes::total 95413 # Table walker page sizes translated 1433system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 111674 # Table walker requests started/completed, data/inst 1434system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1435system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 111674 # Table walker requests started/completed, data/inst 1436system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95413 # Table walker requests started/completed, data/inst 1437system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1438system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95413 # Table walker requests started/completed, data/inst 1439system.cpu1.dtb.walker.walkRequestOrigin::total 207087 # Table walker requests started/completed, data/inst 1440system.cpu1.dtb.inst_hits 0 # ITB inst hits 1441system.cpu1.dtb.inst_misses 0 # ITB inst misses 1442system.cpu1.dtb.read_hits 82869257 # DTB read hits 1443system.cpu1.dtb.read_misses 83659 # DTB read misses 1444system.cpu1.dtb.write_hits 74681159 # DTB write hits 1445system.cpu1.dtb.write_misses 28015 # DTB write misses 1446system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1447system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1448system.cpu1.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 1449system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1450system.cpu1.dtb.flush_entries 37721 # Number of entries that have been flushed from TLB 1451system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1452system.cpu1.dtb.prefetch_faults 4459 # Number of TLB faults due to prefetch 1453system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1454system.cpu1.dtb.perms_faults 10437 # Number of TLB faults due to permissions restrictions 1455system.cpu1.dtb.read_accesses 82952916 # DTB read accesses 1456system.cpu1.dtb.write_accesses 74709174 # DTB write accesses 1457system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1458system.cpu1.dtb.hits 157550416 # DTB hits 1459system.cpu1.dtb.misses 111674 # DTB misses 1460system.cpu1.dtb.accesses 157662090 # DTB accesses 1461system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1462system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1463system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1464system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1465system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1466system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1467system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1468system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1469system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1470system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1471system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1472system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1473system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1474system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1475system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1476system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1477system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1478system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1479system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1480system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1481system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1482system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1483system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1484system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1485system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1486system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1487system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1488system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1489system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1490system.cpu1.itb.walker.walks 54727 # Table walker walks requested 1491system.cpu1.itb.walker.walksLong 54727 # Table walker walks initiated with long descriptors 1492system.cpu1.itb.walker.walksLongTerminationLevel::Level2 669 # Level at which table walker walks with long descriptors terminate 1493system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48424 # Level at which table walker walks with long descriptors terminate 1494system.cpu1.itb.walker.walkWaitTime::samples 54727 # Table walker wait (enqueue to first request) latency 1495system.cpu1.itb.walker.walkWaitTime::0 54727 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1496system.cpu1.itb.walker.walkWaitTime::total 54727 # Table walker wait (enqueue to first request) latency 1497system.cpu1.itb.walker.walkCompletionTime::samples 49093 # Table walker service (enqueue to completion) latency 1498system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724 # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913 # Table walker service (enqueue to completion) latency 1500system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713 # Table walker service (enqueue to completion) latency 1501system.cpu1.itb.walker.walkCompletionTime::0-65535 48315 98.42% 98.42% # Table walker service (enqueue to completion) latency 1502system.cpu1.itb.walker.walkCompletionTime::65536-131071 33 0.07% 98.48% # Table walker service (enqueue to completion) latency 1503system.cpu1.itb.walker.walkCompletionTime::131072-196607 627 1.28% 99.76% # Table walker service (enqueue to completion) latency 1504system.cpu1.itb.walker.walkCompletionTime::196608-262143 24 0.05% 99.81% # Table walker service (enqueue to completion) latency 1505system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency 1506system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency 1507system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency 1508system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1509system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1510system.cpu1.itb.walker.walkCompletionTime::total 49093 # Table walker service (enqueue to completion) latency 1511system.cpu1.itb.walker.walksPending::samples -1309982220 # Table walker pending requests distribution 1512system.cpu1.itb.walker.walksPending::0 -1309982220 100.00% 100.00% # Table walker pending requests distribution 1513system.cpu1.itb.walker.walksPending::total -1309982220 # Table walker pending requests distribution 1514system.cpu1.itb.walker.walkPageSizes::4K 48424 98.64% 98.64% # Table walker page sizes translated 1515system.cpu1.itb.walker.walkPageSizes::2M 669 1.36% 100.00% # Table walker page sizes translated 1516system.cpu1.itb.walker.walkPageSizes::total 49093 # Table walker page sizes translated 1517system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1518system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54727 # Table walker requests started/completed, data/inst 1519system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54727 # Table walker requests started/completed, data/inst 1520system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1521system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49093 # Table walker requests started/completed, data/inst 1522system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49093 # Table walker requests started/completed, data/inst 1523system.cpu1.itb.walker.walkRequestOrigin::total 103820 # Table walker requests started/completed, data/inst 1524system.cpu1.itb.inst_hits 441006552 # ITB inst hits 1525system.cpu1.itb.inst_misses 54727 # ITB inst misses 1526system.cpu1.itb.read_hits 0 # DTB read hits 1527system.cpu1.itb.read_misses 0 # DTB read misses 1528system.cpu1.itb.write_hits 0 # DTB write hits 1529system.cpu1.itb.write_misses 0 # DTB write misses 1530system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1531system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1532system.cpu1.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 1533system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1534system.cpu1.itb.flush_entries 26047 # Number of entries that have been flushed from TLB 1535system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1536system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1537system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1538system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1539system.cpu1.itb.read_accesses 0 # DTB read accesses 1540system.cpu1.itb.write_accesses 0 # DTB write accesses 1541system.cpu1.itb.inst_accesses 441061279 # ITB inst accesses 1542system.cpu1.itb.hits 441006552 # DTB hits 1543system.cpu1.itb.misses 54727 # DTB misses 1544system.cpu1.itb.accesses 441061279 # DTB accesses 1545system.cpu1.numCycles 94949400719 # number of cpu cycles simulated 1546system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1547system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1548system.cpu1.committedInsts 440696565 # Number of instructions committed 1549system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed 1550system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses 1551system.cpu1.num_fp_alu_accesses 365483 # Number of float alu accesses 1552system.cpu1.num_func_calls 25816030 # number of times a function call or return occured 1553system.cpu1.num_conditional_control_insts 67531060 # number of instructions that are conditional controls 1554system.cpu1.num_int_insts 474820793 # number of integer instructions 1555system.cpu1.num_fp_insts 365483 # number of float instructions 1556system.cpu1.num_int_register_reads 694878928 # number of times the integer registers were read 1557system.cpu1.num_int_register_writes 377300064 # number of times the integer registers were written 1558system.cpu1.num_fp_register_reads 605102 # number of times the floating registers were read 1559system.cpu1.num_fp_register_writes 276864 # number of times the floating registers were written 1560system.cpu1.num_cc_register_reads 116712375 # number of times the CC registers were read 1561system.cpu1.num_cc_register_writes 116303175 # number of times the CC registers were written 1562system.cpu1.num_mem_refs 157542729 # number of memory refs 1563system.cpu1.num_load_insts 82867724 # Number of load instructions 1564system.cpu1.num_store_insts 74675005 # Number of store instructions 1565system.cpu1.num_idle_cycles 93871458813.181076 # Number of idle cycles 1566system.cpu1.num_busy_cycles 1077941905.818921 # Number of busy cycles 1567system.cpu1.not_idle_fraction 0.011353 # Percentage of non-idle cycles 1568system.cpu1.idle_fraction 0.988647 # Percentage of idle cycles 1569system.cpu1.Branches 98303933 # Number of branches fetched 1570system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1571system.cpu1.op_class::IntAlu 359137164 69.35% 69.35% # Class of executed instruction 1572system.cpu1.op_class::IntMult 1056908 0.20% 69.56% # Class of executed instruction 1573system.cpu1.op_class::IntDiv 59454 0.01% 69.57% # Class of executed instruction 1574system.cpu1.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction 1575system.cpu1.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction 1576system.cpu1.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction 1577system.cpu1.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction 1578system.cpu1.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction 1579system.cpu1.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction 1580system.cpu1.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction 1581system.cpu1.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction 1582system.cpu1.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction 1583system.cpu1.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction 1584system.cpu1.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction 1585system.cpu1.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction 1586system.cpu1.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction 1587system.cpu1.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction 1588system.cpu1.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction 1589system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction 1590system.cpu1.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction 1591system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction 1592system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction 1593system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction 1594system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction 1595system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction 1596system.cpu1.op_class::SimdFloatMisc 36204 0.01% 69.58% # Class of executed instruction 1597system.cpu1.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction 1598system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction 1599system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction 1600system.cpu1.op_class::MemRead 82867724 16.00% 85.58% # Class of executed instruction 1601system.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Class of executed instruction 1602system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1603system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1604system.cpu1.op_class::total 517832459 # Class of executed instruction 1605system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1606system.cpu1.kern.inst.quiesce 14490 # number of quiesce instructions executed 1607system.cpu1.dcache.tags.replacements 5147651 # number of replacements 1608system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use 1609system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks. 1610system.cpu1.dcache.tags.sampled_refs 5148159 # Sample count of references to valid blocks. 1611system.cpu1.dcache.tags.avg_refs 29.564853 # Average number of references to valid blocks. 1612system.cpu1.dcache.tags.warmup_cycle 8409197794000 # Cycle when the warmup percentage was hit. 1613system.cpu1.dcache.tags.occ_blocks::cpu1.data 420.489425 # Average occupied blocks per requestor 1614system.cpu1.dcache.tags.occ_percent::cpu1.data 0.821268 # Average percentage of cache occupancy 1615system.cpu1.dcache.tags.occ_percent::total 0.821268 # Average percentage of cache occupancy 1616system.cpu1.dcache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 1617system.cpu1.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 1618system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 1619system.cpu1.dcache.tags.age_task_id_blocks_1024::2 443 # Occupied blocks per task id 1620system.cpu1.dcache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 1621system.cpu1.dcache.tags.tag_accesses 320234661 # Number of tag accesses 1622system.cpu1.dcache.tags.data_accesses 320234661 # Number of data accesses 1623system.cpu1.dcache.ReadReq_hits::cpu1.data 77182580 # number of ReadReq hits 1624system.cpu1.dcache.ReadReq_hits::total 77182580 # number of ReadReq hits 1625system.cpu1.dcache.WriteReq_hits::cpu1.data 70763723 # number of WriteReq hits 1626system.cpu1.dcache.WriteReq_hits::total 70763723 # number of WriteReq hits 1627system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181716 # number of SoftPFReq hits 1628system.cpu1.dcache.SoftPFReq_hits::total 181716 # number of SoftPFReq hits 1629system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197136 # number of WriteLineReq hits 1630system.cpu1.dcache.WriteLineReq_hits::total 197136 # number of WriteLineReq hits 1631system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768276 # number of LoadLockedReq hits 1632system.cpu1.dcache.LoadLockedReq_hits::total 1768276 # number of LoadLockedReq hits 1633system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1725683 # number of StoreCondReq hits 1634system.cpu1.dcache.StoreCondReq_hits::total 1725683 # number of StoreCondReq hits 1635system.cpu1.dcache.demand_hits::cpu1.data 147946303 # number of demand (read+write) hits 1636system.cpu1.dcache.demand_hits::total 147946303 # number of demand (read+write) hits 1637system.cpu1.dcache.overall_hits::cpu1.data 148128019 # number of overall hits 1638system.cpu1.dcache.overall_hits::total 148128019 # number of overall hits 1639system.cpu1.dcache.ReadReq_misses::cpu1.data 2911211 # number of ReadReq misses 1640system.cpu1.dcache.ReadReq_misses::total 2911211 # number of ReadReq misses 1641system.cpu1.dcache.WriteReq_misses::cpu1.data 1304261 # number of WriteReq misses 1642system.cpu1.dcache.WriteReq_misses::total 1304261 # number of WriteReq misses 1643system.cpu1.dcache.SoftPFReq_misses::cpu1.data 646630 # number of SoftPFReq misses 1644system.cpu1.dcache.SoftPFReq_misses::total 646630 # number of SoftPFReq misses 1645system.cpu1.dcache.WriteLineReq_misses::cpu1.data 461157 # number of WriteLineReq misses 1646system.cpu1.dcache.WriteLineReq_misses::total 461157 # number of WriteLineReq misses 1647system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158092 # number of LoadLockedReq misses 1648system.cpu1.dcache.LoadLockedReq_misses::total 158092 # number of LoadLockedReq misses 1649system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198973 # number of StoreCondReq misses 1650system.cpu1.dcache.StoreCondReq_misses::total 198973 # number of StoreCondReq misses 1651system.cpu1.dcache.demand_misses::cpu1.data 4215472 # number of demand (read+write) misses 1652system.cpu1.dcache.demand_misses::total 4215472 # number of demand (read+write) misses 1653system.cpu1.dcache.overall_misses::cpu1.data 4862102 # number of overall misses 1654system.cpu1.dcache.overall_misses::total 4862102 # number of overall misses 1655system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46228111000 # number of ReadReq miss cycles 1656system.cpu1.dcache.ReadReq_miss_latency::total 46228111000 # number of ReadReq miss cycles 1657system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27445585000 # number of WriteReq miss cycles 1658system.cpu1.dcache.WriteReq_miss_latency::total 27445585000 # number of WriteReq miss cycles 1659system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22477695000 # number of WriteLineReq miss cycles 1660system.cpu1.dcache.WriteLineReq_miss_latency::total 22477695000 # number of WriteLineReq miss cycles 1661system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2400515000 # number of LoadLockedReq miss cycles 1662system.cpu1.dcache.LoadLockedReq_miss_latency::total 2400515000 # number of LoadLockedReq miss cycles 1663system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4867748500 # number of StoreCondReq miss cycles 1664system.cpu1.dcache.StoreCondReq_miss_latency::total 4867748500 # number of StoreCondReq miss cycles 1665system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2101500 # number of StoreCondFailReq miss cycles 1666system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2101500 # number of StoreCondFailReq miss cycles 1667system.cpu1.dcache.demand_miss_latency::cpu1.data 73673696000 # number of demand (read+write) miss cycles 1668system.cpu1.dcache.demand_miss_latency::total 73673696000 # number of demand (read+write) miss cycles 1669system.cpu1.dcache.overall_miss_latency::cpu1.data 73673696000 # number of overall miss cycles 1670system.cpu1.dcache.overall_miss_latency::total 73673696000 # number of overall miss cycles 1671system.cpu1.dcache.ReadReq_accesses::cpu1.data 80093791 # number of ReadReq accesses(hits+misses) 1672system.cpu1.dcache.ReadReq_accesses::total 80093791 # number of ReadReq accesses(hits+misses) 1673system.cpu1.dcache.WriteReq_accesses::cpu1.data 72067984 # number of WriteReq accesses(hits+misses) 1674system.cpu1.dcache.WriteReq_accesses::total 72067984 # number of WriteReq accesses(hits+misses) 1675system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828346 # number of SoftPFReq accesses(hits+misses) 1676system.cpu1.dcache.SoftPFReq_accesses::total 828346 # number of SoftPFReq accesses(hits+misses) 1677system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 658293 # number of WriteLineReq accesses(hits+misses) 1678system.cpu1.dcache.WriteLineReq_accesses::total 658293 # number of WriteLineReq accesses(hits+misses) 1679system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1926368 # number of LoadLockedReq accesses(hits+misses) 1680system.cpu1.dcache.LoadLockedReq_accesses::total 1926368 # number of LoadLockedReq accesses(hits+misses) 1681system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1924656 # number of StoreCondReq accesses(hits+misses) 1682system.cpu1.dcache.StoreCondReq_accesses::total 1924656 # number of StoreCondReq accesses(hits+misses) 1683system.cpu1.dcache.demand_accesses::cpu1.data 152161775 # number of demand (read+write) accesses 1684system.cpu1.dcache.demand_accesses::total 152161775 # number of demand (read+write) accesses 1685system.cpu1.dcache.overall_accesses::cpu1.data 152990121 # number of overall (read+write) accesses 1686system.cpu1.dcache.overall_accesses::total 152990121 # number of overall (read+write) accesses 1687system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036348 # miss rate for ReadReq accesses 1688system.cpu1.dcache.ReadReq_miss_rate::total 0.036348 # miss rate for ReadReq accesses 1689system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018098 # miss rate for WriteReq accesses 1690system.cpu1.dcache.WriteReq_miss_rate::total 0.018098 # miss rate for WriteReq accesses 1691system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780628 # miss rate for SoftPFReq accesses 1692system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780628 # miss rate for SoftPFReq accesses 1693system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.700535 # miss rate for WriteLineReq accesses 1694system.cpu1.dcache.WriteLineReq_miss_rate::total 0.700535 # miss rate for WriteLineReq accesses 1695system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082067 # miss rate for LoadLockedReq accesses 1696system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082067 # miss rate for LoadLockedReq accesses 1697system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103381 # miss rate for StoreCondReq accesses 1698system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103381 # miss rate for StoreCondReq accesses 1699system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027704 # miss rate for demand accesses 1700system.cpu1.dcache.demand_miss_rate::total 0.027704 # miss rate for demand accesses 1701system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031780 # miss rate for overall accesses 1702system.cpu1.dcache.overall_miss_rate::total 0.031780 # miss rate for overall accesses 1703system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591 # average ReadReq miss latency 1704system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591 # average ReadReq miss latency 1705system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930 # average WriteReq miss latency 1706system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930 # average WriteReq miss latency 1707system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728 # average WriteLineReq miss latency 1708system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728 # average WriteLineReq miss latency 1709system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425 # average LoadLockedReq miss latency 1710system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425 # average LoadLockedReq miss latency 1711system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025 # average StoreCondReq miss latency 1712system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025 # average StoreCondReq miss latency 1713system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1714system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1715system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346 # average overall miss latency 1716system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346 # average overall miss latency 1717system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034 # average overall miss latency 1718system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034 # average overall miss latency 1719system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1720system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1721system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1722system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1723system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1724system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1725system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1726system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1727system.cpu1.dcache.writebacks::writebacks 3396408 # number of writebacks 1728system.cpu1.dcache.writebacks::total 3396408 # number of writebacks 1729system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16912 # number of ReadReq MSHR hits 1730system.cpu1.dcache.ReadReq_mshr_hits::total 16912 # number of ReadReq MSHR hits 1731system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 462 # number of WriteReq MSHR hits 1732system.cpu1.dcache.WriteReq_mshr_hits::total 462 # number of WriteReq MSHR hits 1733system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41725 # number of LoadLockedReq MSHR hits 1734system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41725 # number of LoadLockedReq MSHR hits 1735system.cpu1.dcache.demand_mshr_hits::cpu1.data 17374 # number of demand (read+write) MSHR hits 1736system.cpu1.dcache.demand_mshr_hits::total 17374 # number of demand (read+write) MSHR hits 1737system.cpu1.dcache.overall_mshr_hits::cpu1.data 17374 # number of overall MSHR hits 1738system.cpu1.dcache.overall_mshr_hits::total 17374 # number of overall MSHR hits 1739system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2894299 # number of ReadReq MSHR misses 1740system.cpu1.dcache.ReadReq_mshr_misses::total 2894299 # number of ReadReq MSHR misses 1741system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1303799 # number of WriteReq MSHR misses 1742system.cpu1.dcache.WriteReq_mshr_misses::total 1303799 # number of WriteReq MSHR misses 1743system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 646630 # number of SoftPFReq MSHR misses 1744system.cpu1.dcache.SoftPFReq_mshr_misses::total 646630 # number of SoftPFReq MSHR misses 1745system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 461157 # number of WriteLineReq MSHR misses 1746system.cpu1.dcache.WriteLineReq_mshr_misses::total 461157 # number of WriteLineReq MSHR misses 1747system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116367 # number of LoadLockedReq MSHR misses 1748system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116367 # number of LoadLockedReq MSHR misses 1749system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198973 # number of StoreCondReq MSHR misses 1750system.cpu1.dcache.StoreCondReq_mshr_misses::total 198973 # number of StoreCondReq MSHR misses 1751system.cpu1.dcache.demand_mshr_misses::cpu1.data 4198098 # number of demand (read+write) MSHR misses 1752system.cpu1.dcache.demand_mshr_misses::total 4198098 # number of demand (read+write) MSHR misses 1753system.cpu1.dcache.overall_mshr_misses::cpu1.data 4844728 # number of overall MSHR misses 1754system.cpu1.dcache.overall_mshr_misses::total 4844728 # number of overall MSHR misses 1755system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable 1756system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20770 # number of ReadReq MSHR uncacheable 1757system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable 1758system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable 1759system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses 1760system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40100 # number of overall MSHR uncacheable misses 1761system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41851387000 # number of ReadReq MSHR miss cycles 1762system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41851387000 # number of ReadReq MSHR miss cycles 1763system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26109084500 # number of WriteReq MSHR miss cycles 1764system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26109084500 # number of WriteReq MSHR miss cycles 1765system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14515592000 # number of SoftPFReq MSHR miss cycles 1766system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14515592000 # number of SoftPFReq MSHR miss cycles 1767system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 22016538000 # number of WriteLineReq MSHR miss cycles 1768system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 22016538000 # number of WriteLineReq MSHR miss cycles 1769system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587242500 # number of LoadLockedReq MSHR miss cycles 1770system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587242500 # number of LoadLockedReq MSHR miss cycles 1771system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4668803500 # number of StoreCondReq MSHR miss cycles 1772system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4668803500 # number of StoreCondReq MSHR miss cycles 1773system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2073500 # number of StoreCondFailReq MSHR miss cycles 1774system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2073500 # number of StoreCondFailReq MSHR miss cycles 1775system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67960471500 # number of demand (read+write) MSHR miss cycles 1776system.cpu1.dcache.demand_mshr_miss_latency::total 67960471500 # number of demand (read+write) MSHR miss cycles 1777system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 82476063500 # number of overall MSHR miss cycles 1778system.cpu1.dcache.overall_mshr_miss_latency::total 82476063500 # number of overall MSHR miss cycles 1779system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3614060000 # number of ReadReq MSHR uncacheable cycles 1780system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3614060000 # number of ReadReq MSHR uncacheable cycles 1781system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3361466500 # number of WriteReq MSHR uncacheable cycles 1782system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3361466500 # number of WriteReq MSHR uncacheable cycles 1783system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975526500 # number of overall MSHR uncacheable cycles 1784system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6975526500 # number of overall MSHR uncacheable cycles 1785system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036136 # mshr miss rate for ReadReq accesses 1786system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036136 # mshr miss rate for ReadReq accesses 1787system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses 1788system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses 1789system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780628 # mshr miss rate for SoftPFReq accesses 1790system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780628 # mshr miss rate for SoftPFReq accesses 1791system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.700535 # mshr miss rate for WriteLineReq accesses 1792system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.700535 # mshr miss rate for WriteLineReq accesses 1793system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060407 # mshr miss rate for LoadLockedReq accesses 1794system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060407 # mshr miss rate for LoadLockedReq accesses 1795system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103381 # mshr miss rate for StoreCondReq accesses 1796system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103381 # mshr miss rate for StoreCondReq accesses 1797system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027590 # mshr miss rate for demand accesses 1798system.cpu1.dcache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses 1799system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031667 # mshr miss rate for overall accesses 1800system.cpu1.dcache.overall_mshr_miss_rate::total 0.031667 # mshr miss rate for overall accesses 1801system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004 # average ReadReq mshr miss latency 1802system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004 # average ReadReq mshr miss latency 1803system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800 # average WriteReq mshr miss latency 1804system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800 # average WriteReq mshr miss latency 1805system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581 # average SoftPFReq mshr miss latency 1806system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581 # average SoftPFReq mshr miss latency 1807system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728 # average WriteLineReq mshr miss latency 1808system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728 # average WriteLineReq mshr miss latency 1809system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954 # average LoadLockedReq mshr miss latency 1810system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954 # average LoadLockedReq mshr miss latency 1811system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747 # average StoreCondReq mshr miss latency 1812system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747 # average StoreCondReq mshr miss latency 1813system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1814system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1815system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673 # average overall mshr miss latency 1816system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673 # average overall mshr miss latency 1817system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050 # average overall mshr miss latency 1818system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050 # average overall mshr miss latency 1819system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709 # average ReadReq mshr uncacheable latency 1820system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709 # average ReadReq mshr uncacheable latency 1821system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472 # average WriteReq mshr uncacheable latency 1822system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472 # average WriteReq mshr uncacheable latency 1823system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302 # average overall mshr uncacheable latency 1824system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302 # average overall mshr uncacheable latency 1825system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1826system.cpu1.icache.tags.replacements 4679241 # number of replacements 1827system.cpu1.icache.tags.tagsinuse 495.918258 # Cycle average of tags in use 1828system.cpu1.icache.tags.total_refs 436326798 # Total number of references to valid blocks. 1829system.cpu1.icache.tags.sampled_refs 4679753 # Sample count of references to valid blocks. 1830system.cpu1.icache.tags.avg_refs 93.237143 # Average number of references to valid blocks. 1831system.cpu1.icache.tags.warmup_cycle 8409166313000 # Cycle when the warmup percentage was hit. 1832system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.918258 # Average occupied blocks per requestor 1833system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968590 # Average percentage of cache occupancy 1834system.cpu1.icache.tags.occ_percent::total 0.968590 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1836system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 1837system.cpu1.icache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id 1839system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1840system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1841system.cpu1.icache.tags.tag_accesses 886692857 # Number of tag accesses 1842system.cpu1.icache.tags.data_accesses 886692857 # Number of data accesses 1843system.cpu1.icache.ReadReq_hits::cpu1.inst 436326798 # number of ReadReq hits 1844system.cpu1.icache.ReadReq_hits::total 436326798 # number of ReadReq hits 1845system.cpu1.icache.demand_hits::cpu1.inst 436326798 # number of demand (read+write) hits 1846system.cpu1.icache.demand_hits::total 436326798 # number of demand (read+write) hits 1847system.cpu1.icache.overall_hits::cpu1.inst 436326798 # number of overall hits 1848system.cpu1.icache.overall_hits::total 436326798 # number of overall hits 1849system.cpu1.icache.ReadReq_misses::cpu1.inst 4679754 # number of ReadReq misses 1850system.cpu1.icache.ReadReq_misses::total 4679754 # number of ReadReq misses 1851system.cpu1.icache.demand_misses::cpu1.inst 4679754 # number of demand (read+write) misses 1852system.cpu1.icache.demand_misses::total 4679754 # number of demand (read+write) misses 1853system.cpu1.icache.overall_misses::cpu1.inst 4679754 # number of overall misses 1854system.cpu1.icache.overall_misses::total 4679754 # number of overall misses 1855system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52951180000 # number of ReadReq miss cycles 1856system.cpu1.icache.ReadReq_miss_latency::total 52951180000 # number of ReadReq miss cycles 1857system.cpu1.icache.demand_miss_latency::cpu1.inst 52951180000 # number of demand (read+write) miss cycles 1858system.cpu1.icache.demand_miss_latency::total 52951180000 # number of demand (read+write) miss cycles 1859system.cpu1.icache.overall_miss_latency::cpu1.inst 52951180000 # number of overall miss cycles 1860system.cpu1.icache.overall_miss_latency::total 52951180000 # number of overall miss cycles 1861system.cpu1.icache.ReadReq_accesses::cpu1.inst 441006552 # number of ReadReq accesses(hits+misses) 1862system.cpu1.icache.ReadReq_accesses::total 441006552 # number of ReadReq accesses(hits+misses) 1863system.cpu1.icache.demand_accesses::cpu1.inst 441006552 # number of demand (read+write) accesses 1864system.cpu1.icache.demand_accesses::total 441006552 # number of demand (read+write) accesses 1865system.cpu1.icache.overall_accesses::cpu1.inst 441006552 # number of overall (read+write) accesses 1866system.cpu1.icache.overall_accesses::total 441006552 # number of overall (read+write) accesses 1867system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010612 # miss rate for ReadReq accesses 1868system.cpu1.icache.ReadReq_miss_rate::total 0.010612 # miss rate for ReadReq accesses 1869system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010612 # miss rate for demand accesses 1870system.cpu1.icache.demand_miss_rate::total 0.010612 # miss rate for demand accesses 1871system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010612 # miss rate for overall accesses 1872system.cpu1.icache.overall_miss_rate::total 0.010612 # miss rate for overall accesses 1873system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461 # average ReadReq miss latency 1874system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461 # average ReadReq miss latency 1875system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency 1876system.cpu1.icache.demand_avg_miss_latency::total 11314.949461 # average overall miss latency 1877system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::total 11314.949461 # average overall miss latency 1879system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1885system.cpu1.icache.fast_writes 0 # number of fast writes performed 1886system.cpu1.icache.cache_copies 0 # number of cache copies performed 1887system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4679754 # number of ReadReq MSHR misses 1888system.cpu1.icache.ReadReq_mshr_misses::total 4679754 # number of ReadReq MSHR misses 1889system.cpu1.icache.demand_mshr_misses::cpu1.inst 4679754 # number of demand (read+write) MSHR misses 1890system.cpu1.icache.demand_mshr_misses::total 4679754 # number of demand (read+write) MSHR misses 1891system.cpu1.icache.overall_mshr_misses::cpu1.inst 4679754 # number of overall MSHR misses 1892system.cpu1.icache.overall_mshr_misses::total 4679754 # number of overall MSHR misses 1893system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1894system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1895system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1896system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1897system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50611303500 # number of ReadReq MSHR miss cycles 1898system.cpu1.icache.ReadReq_mshr_miss_latency::total 50611303500 # number of ReadReq MSHR miss cycles 1899system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50611303500 # number of demand (read+write) MSHR miss cycles 1900system.cpu1.icache.demand_mshr_miss_latency::total 50611303500 # number of demand (read+write) MSHR miss cycles 1901system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50611303500 # number of overall MSHR miss cycles 1902system.cpu1.icache.overall_mshr_miss_latency::total 50611303500 # number of overall MSHR miss cycles 1903system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14521500 # number of ReadReq MSHR uncacheable cycles 1904system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14521500 # number of ReadReq MSHR uncacheable cycles 1905system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14521500 # number of overall MSHR uncacheable cycles 1906system.cpu1.icache.overall_mshr_uncacheable_latency::total 14521500 # number of overall MSHR uncacheable cycles 1907system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for ReadReq accesses 1908system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010612 # mshr miss rate for ReadReq accesses 1909system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for demand accesses 1910system.cpu1.icache.demand_mshr_miss_rate::total 0.010612 # mshr miss rate for demand accesses 1911system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for overall accesses 1912system.cpu1.icache.overall_mshr_miss_rate::total 0.010612 # mshr miss rate for overall accesses 1913system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average ReadReq mshr miss latency 1914system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568 # average ReadReq mshr miss latency 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency 1919system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average ReadReq mshr uncacheable latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average overall mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364 # average overall mshr uncacheable latency 1923system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1924system.cpu1.l2cache.prefetcher.num_hwpf_issued 7337880 # number of hwpf issued 1925system.cpu1.l2cache.prefetcher.pfIdentified 7337888 # number of prefetch candidates identified 1926system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 1927system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1928system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1929system.cpu1.l2cache.prefetcher.pfSpanPage 899040 # number of prefetches not generated due to page crossing 1930system.cpu1.l2cache.tags.replacements 2034185 # number of replacements 1931system.cpu1.l2cache.tags.tagsinuse 13437.783654 # Cycle average of tags in use 1932system.cpu1.l2cache.tags.total_refs 16644740 # Total number of references to valid blocks. 1933system.cpu1.l2cache.tags.sampled_refs 2049737 # Sample count of references to valid blocks. 1934system.cpu1.l2cache.tags.avg_refs 8.120427 # Average number of references to valid blocks. 1935system.cpu1.l2cache.tags.warmup_cycle 9820320151000 # Cycle when the warmup percentage was hit. 1936system.cpu1.l2cache.tags.occ_blocks::writebacks 6510.894270 # Average occupied blocks per requestor 1937system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.649917 # Average occupied blocks per requestor 1938system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 96.755911 # Average occupied blocks per requestor 1939system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2809.884427 # Average occupied blocks per requestor 1940system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3040.183540 # Average occupied blocks per requestor 1941system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 908.415590 # Average occupied blocks per requestor 1942system.cpu1.l2cache.tags.occ_percent::writebacks 0.397393 # Average percentage of cache occupancy 1943system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004373 # Average percentage of cache occupancy 1944system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005906 # Average percentage of cache occupancy 1945system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.171502 # Average percentage of cache occupancy 1946system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.185558 # Average percentage of cache occupancy 1947system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055445 # Average percentage of cache occupancy 1948system.cpu1.l2cache.tags.occ_percent::total 0.820177 # Average percentage of cache occupancy 1949system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id 1950system.cpu1.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 1951system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13928 # Occupied blocks per task id 1952system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 1953system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 636 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1956system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id 1958system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1959system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 1960system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2599 # Occupied blocks per task id 1961system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5864 # Occupied blocks per task id 1962system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5395 # Occupied blocks per task id 1963system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id 1964system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1965system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id 1966system.cpu1.l2cache.tags.tag_accesses 332457854 # Number of tag accesses 1967system.cpu1.l2cache.tags.data_accesses 332457854 # Number of data accesses 1968system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236423 # number of ReadReq hits 1969system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 125548 # number of ReadReq hits 1970system.cpu1.l2cache.ReadReq_hits::total 361971 # number of ReadReq hits 1971system.cpu1.l2cache.Writeback_hits::writebacks 3396406 # number of Writeback hits 1972system.cpu1.l2cache.Writeback_hits::total 3396406 # number of Writeback hits 1973system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 63344 # number of UpgradeReq hits 1974system.cpu1.l2cache.UpgradeReq_hits::total 63344 # number of UpgradeReq hits 1975system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31004 # number of SCUpgradeReq hits 1976system.cpu1.l2cache.SCUpgradeReq_hits::total 31004 # number of SCUpgradeReq hits 1977system.cpu1.l2cache.ReadExReq_hits::cpu1.data 898756 # number of ReadExReq hits 1978system.cpu1.l2cache.ReadExReq_hits::total 898756 # number of ReadExReq hits 1979system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4166985 # number of ReadCleanReq hits 1980system.cpu1.l2cache.ReadCleanReq_hits::total 4166985 # number of ReadCleanReq hits 1981system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2749875 # number of ReadSharedReq hits 1982system.cpu1.l2cache.ReadSharedReq_hits::total 2749875 # number of ReadSharedReq hits 1983system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193932 # number of InvalidateReq hits 1984system.cpu1.l2cache.InvalidateReq_hits::total 193932 # number of InvalidateReq hits 1985system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236423 # number of demand (read+write) hits 1986system.cpu1.l2cache.demand_hits::cpu1.itb.walker 125548 # number of demand (read+write) hits 1987system.cpu1.l2cache.demand_hits::cpu1.inst 4166985 # number of demand (read+write) hits 1988system.cpu1.l2cache.demand_hits::cpu1.data 3648631 # number of demand (read+write) hits 1989system.cpu1.l2cache.demand_hits::total 8177587 # number of demand (read+write) hits 1990system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236423 # number of overall hits 1991system.cpu1.l2cache.overall_hits::cpu1.itb.walker 125548 # number of overall hits 1992system.cpu1.l2cache.overall_hits::cpu1.inst 4166985 # number of overall hits 1993system.cpu1.l2cache.overall_hits::cpu1.data 3648631 # number of overall hits 1994system.cpu1.l2cache.overall_hits::total 8177587 # number of overall hits 1995system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9552 # number of ReadReq misses 1996system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7233 # number of ReadReq misses 1997system.cpu1.l2cache.ReadReq_misses::total 16785 # number of ReadReq misses 1998system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1999system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 2000system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 123356 # number of UpgradeReq misses 2001system.cpu1.l2cache.UpgradeReq_misses::total 123356 # number of UpgradeReq misses 2002system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167961 # number of SCUpgradeReq misses 2003system.cpu1.l2cache.SCUpgradeReq_misses::total 167961 # number of SCUpgradeReq misses 2004system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses 2005system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 2006system.cpu1.l2cache.ReadExReq_misses::cpu1.data 219942 # number of ReadExReq misses 2007system.cpu1.l2cache.ReadExReq_misses::total 219942 # number of ReadExReq misses 2008system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 512769 # number of ReadCleanReq misses 2009system.cpu1.l2cache.ReadCleanReq_misses::total 512769 # number of ReadCleanReq misses 2010system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 907421 # number of ReadSharedReq misses 2011system.cpu1.l2cache.ReadSharedReq_misses::total 907421 # number of ReadSharedReq misses 2012system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265828 # number of InvalidateReq misses 2013system.cpu1.l2cache.InvalidateReq_misses::total 265828 # number of InvalidateReq misses 2014system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9552 # number of demand (read+write) misses 2015system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7233 # number of demand (read+write) misses 2016system.cpu1.l2cache.demand_misses::cpu1.inst 512769 # number of demand (read+write) misses 2017system.cpu1.l2cache.demand_misses::cpu1.data 1127363 # number of demand (read+write) misses 2018system.cpu1.l2cache.demand_misses::total 1656917 # number of demand (read+write) misses 2019system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9552 # number of overall misses 2020system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7233 # number of overall misses 2021system.cpu1.l2cache.overall_misses::cpu1.inst 512769 # number of overall misses 2022system.cpu1.l2cache.overall_misses::cpu1.data 1127363 # number of overall misses 2023system.cpu1.l2cache.overall_misses::total 1656917 # number of overall misses 2024system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 404155000 # number of ReadReq miss cycles 2025system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 336372500 # number of ReadReq miss cycles 2026system.cpu1.l2cache.ReadReq_miss_latency::total 740527500 # number of ReadReq miss cycles 2027system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3749073000 # number of UpgradeReq miss cycles 2028system.cpu1.l2cache.UpgradeReq_miss_latency::total 3749073000 # number of UpgradeReq miss cycles 2029system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 4008183000 # number of SCUpgradeReq miss cycles 2030system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 4008183000 # number of SCUpgradeReq miss cycles 2031system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2030999 # number of SCUpgradeFailReq miss cycles 2032system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2030999 # number of SCUpgradeFailReq miss cycles 2033system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12972852500 # number of ReadExReq miss cycles 2034system.cpu1.l2cache.ReadExReq_miss_latency::total 12972852500 # number of ReadExReq miss cycles 2035system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18777464000 # number of ReadCleanReq miss cycles 2036system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18777464000 # number of ReadCleanReq miss cycles 2037system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34592386500 # number of ReadSharedReq miss cycles 2038system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34592386500 # number of ReadSharedReq miss cycles 2039system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 20042243500 # number of InvalidateReq miss cycles 2040system.cpu1.l2cache.InvalidateReq_miss_latency::total 20042243500 # number of InvalidateReq miss cycles 2041system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 404155000 # number of demand (read+write) miss cycles 2042system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 336372500 # number of demand (read+write) miss cycles 2043system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18777464000 # number of demand (read+write) miss cycles 2044system.cpu1.l2cache.demand_miss_latency::cpu1.data 47565239000 # number of demand (read+write) miss cycles 2045system.cpu1.l2cache.demand_miss_latency::total 67083230500 # number of demand (read+write) miss cycles 2046system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 404155000 # number of overall miss cycles 2047system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 336372500 # number of overall miss cycles 2048system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18777464000 # number of overall miss cycles 2049system.cpu1.l2cache.overall_miss_latency::cpu1.data 47565239000 # number of overall miss cycles 2050system.cpu1.l2cache.overall_miss_latency::total 67083230500 # number of overall miss cycles 2051system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 245975 # number of ReadReq accesses(hits+misses) 2052system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 132781 # number of ReadReq accesses(hits+misses) 2053system.cpu1.l2cache.ReadReq_accesses::total 378756 # number of ReadReq accesses(hits+misses) 2054system.cpu1.l2cache.Writeback_accesses::writebacks 3396407 # number of Writeback accesses(hits+misses) 2055system.cpu1.l2cache.Writeback_accesses::total 3396407 # number of Writeback accesses(hits+misses) 2056system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186700 # number of UpgradeReq accesses(hits+misses) 2057system.cpu1.l2cache.UpgradeReq_accesses::total 186700 # number of UpgradeReq accesses(hits+misses) 2058system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198965 # number of SCUpgradeReq accesses(hits+misses) 2059system.cpu1.l2cache.SCUpgradeReq_accesses::total 198965 # number of SCUpgradeReq accesses(hits+misses) 2060system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 2061system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1118698 # number of ReadExReq accesses(hits+misses) 2063system.cpu1.l2cache.ReadExReq_accesses::total 1118698 # number of ReadExReq accesses(hits+misses) 2064system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4679754 # number of ReadCleanReq accesses(hits+misses) 2065system.cpu1.l2cache.ReadCleanReq_accesses::total 4679754 # number of ReadCleanReq accesses(hits+misses) 2066system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3657296 # number of ReadSharedReq accesses(hits+misses) 2067system.cpu1.l2cache.ReadSharedReq_accesses::total 3657296 # number of ReadSharedReq accesses(hits+misses) 2068system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 459760 # number of InvalidateReq accesses(hits+misses) 2069system.cpu1.l2cache.InvalidateReq_accesses::total 459760 # number of InvalidateReq accesses(hits+misses) 2070system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 245975 # number of demand (read+write) accesses 2071system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 132781 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::cpu1.inst 4679754 # number of demand (read+write) accesses 2073system.cpu1.l2cache.demand_accesses::cpu1.data 4775994 # number of demand (read+write) accesses 2074system.cpu1.l2cache.demand_accesses::total 9834504 # number of demand (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 245975 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 132781 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::cpu1.inst 4679754 # number of overall (read+write) accesses 2078system.cpu1.l2cache.overall_accesses::cpu1.data 4775994 # number of overall (read+write) accesses 2079system.cpu1.l2cache.overall_accesses::total 9834504 # number of overall (read+write) accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.054473 # miss rate for ReadReq accesses 2082system.cpu1.l2cache.ReadReq_miss_rate::total 0.044316 # miss rate for ReadReq accesses 2083system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 2084system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 2085system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660718 # miss rate for UpgradeReq accesses 2086system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660718 # miss rate for UpgradeReq accesses 2087system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.844174 # miss rate for SCUpgradeReq accesses 2088system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.844174 # miss rate for SCUpgradeReq accesses 2089system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2090system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2091system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.196605 # miss rate for ReadExReq accesses 2092system.cpu1.l2cache.ReadExReq_miss_rate::total 0.196605 # miss rate for ReadExReq accesses 2093system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.109572 # miss rate for ReadCleanReq accesses 2094system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.109572 # miss rate for ReadCleanReq accesses 2095system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248113 # miss rate for ReadSharedReq accesses 2096system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248113 # miss rate for ReadSharedReq accesses 2097system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.578189 # miss rate for InvalidateReq accesses 2098system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.578189 # miss rate for InvalidateReq accesses 2099system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for demand accesses 2100system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.054473 # miss rate for demand accesses 2101system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109572 # miss rate for demand accesses 2102system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.236048 # miss rate for demand accesses 2103system.cpu1.l2cache.demand_miss_rate::total 0.168480 # miss rate for demand accesses 2104system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for overall accesses 2105system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.054473 # miss rate for overall accesses 2106system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109572 # miss rate for overall accesses 2107system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.236048 # miss rate for overall accesses 2108system.cpu1.l2cache.overall_miss_rate::total 0.168480 # miss rate for overall accesses 2109system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average ReadReq miss latency 2110system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46505.253698 # average ReadReq miss latency 2111system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44118.409294 # average ReadReq miss latency 2112system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30392.303577 # average UpgradeReq miss latency 2113system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30392.303577 # average UpgradeReq miss latency 2114system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23863.771947 # average SCUpgradeReq miss latency 2115system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23863.771947 # average SCUpgradeReq miss latency 2116system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 253874.875000 # average SCUpgradeFailReq miss latency 2117system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 253874.875000 # average SCUpgradeFailReq miss latency 2118system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58983.061443 # average ReadExReq miss latency 2119system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58983.061443 # average ReadExReq miss latency 2120system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36619.733252 # average ReadCleanReq miss latency 2121system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36619.733252 # average ReadCleanReq miss latency 2122system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38121.650810 # average ReadSharedReq miss latency 2123system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38121.650810 # average ReadSharedReq miss latency 2124system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 75395.532073 # average InvalidateReq miss latency 2125system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 75395.532073 # average InvalidateReq miss latency 2126system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency 2127system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency 2128system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency 2129system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency 2130system.cpu1.l2cache.demand_avg_miss_latency::total 40486.777853 # average overall miss latency 2131system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency 2132system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency 2133system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency 2134system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency 2135system.cpu1.l2cache.overall_avg_miss_latency::total 40486.777853 # average overall miss latency 2136system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2137system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2138system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2139system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2140system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2141system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2142system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2143system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2144system.cpu1.l2cache.writebacks::writebacks 1015409 # number of writebacks 2145system.cpu1.l2cache.writebacks::total 1015409 # number of writebacks 2146system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7242 # number of ReadExReq MSHR hits 2147system.cpu1.l2cache.ReadExReq_mshr_hits::total 7242 # number of ReadExReq MSHR hits 2148system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 595 # number of ReadSharedReq MSHR hits 2149system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 595 # number of ReadSharedReq MSHR hits 2150system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 2151system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 2152system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7837 # number of demand (read+write) MSHR hits 2153system.cpu1.l2cache.demand_mshr_hits::total 7837 # number of demand (read+write) MSHR hits 2154system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7837 # number of overall MSHR hits 2155system.cpu1.l2cache.overall_mshr_hits::total 7837 # number of overall MSHR hits 2156system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9552 # number of ReadReq MSHR misses 2157system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7233 # number of ReadReq MSHR misses 2158system.cpu1.l2cache.ReadReq_mshr_misses::total 16785 # number of ReadReq MSHR misses 2159system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 2160system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 2161system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 96130 # number of CleanEvict MSHR misses 2162system.cpu1.l2cache.CleanEvict_mshr_misses::total 96130 # number of CleanEvict MSHR misses 2163system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of HardPFReq MSHR misses 2164system.cpu1.l2cache.HardPFReq_mshr_misses::total 687356 # number of HardPFReq MSHR misses 2165system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 123356 # number of UpgradeReq MSHR misses 2166system.cpu1.l2cache.UpgradeReq_mshr_misses::total 123356 # number of UpgradeReq MSHR misses 2167system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167961 # number of SCUpgradeReq MSHR misses 2168system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167961 # number of SCUpgradeReq MSHR misses 2169system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses 2170system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 2171system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 212700 # number of ReadExReq MSHR misses 2172system.cpu1.l2cache.ReadExReq_mshr_misses::total 212700 # number of ReadExReq MSHR misses 2173system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 512769 # number of ReadCleanReq MSHR misses 2174system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 512769 # number of ReadCleanReq MSHR misses 2175system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 906826 # number of ReadSharedReq MSHR misses 2176system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 906826 # number of ReadSharedReq MSHR misses 2177system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 265827 # number of InvalidateReq MSHR misses 2178system.cpu1.l2cache.InvalidateReq_mshr_misses::total 265827 # number of InvalidateReq MSHR misses 2179system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9552 # number of demand (read+write) MSHR misses 2180system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7233 # number of demand (read+write) MSHR misses 2181system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 512769 # number of demand (read+write) MSHR misses 2182system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1119526 # number of demand (read+write) MSHR misses 2183system.cpu1.l2cache.demand_mshr_misses::total 1649080 # number of demand (read+write) MSHR misses 2184system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9552 # number of overall MSHR misses 2185system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7233 # number of overall MSHR misses 2186system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 512769 # number of overall MSHR misses 2187system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1119526 # number of overall MSHR misses 2188system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of overall MSHR misses 2189system.cpu1.l2cache.overall_mshr_misses::total 2336436 # number of overall MSHR misses 2190system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2191system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable 2192system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 20880 # number of ReadReq MSHR uncacheable 2193system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable 2194system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable 2195system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2196system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses 2197system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40210 # number of overall MSHR uncacheable misses 2198system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of ReadReq MSHR miss cycles 2199system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 292974500 # number of ReadReq MSHR miss cycles 2200system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 639817500 # number of ReadReq MSHR miss cycles 2201system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of HardPFReq MSHR miss cycles 2202system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44220457933 # number of HardPFReq MSHR miss cycles 2203system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4206113500 # number of UpgradeReq MSHR miss cycles 2204system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4206113500 # number of UpgradeReq MSHR miss cycles 2205system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3161211000 # number of SCUpgradeReq MSHR miss cycles 2206system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3161211000 # number of SCUpgradeReq MSHR miss cycles 2207system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1862999 # number of SCUpgradeFailReq MSHR miss cycles 2208system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1862999 # number of SCUpgradeFailReq MSHR miss cycles 2209system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10724509000 # number of ReadExReq MSHR miss cycles 2210system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10724509000 # number of ReadExReq MSHR miss cycles 2211system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15700856000 # number of ReadCleanReq MSHR miss cycles 2212system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15700856000 # number of ReadCleanReq MSHR miss cycles 2213system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29099850500 # number of ReadSharedReq MSHR miss cycles 2214system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29099850500 # number of ReadSharedReq MSHR miss cycles 2215system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 18447195500 # number of InvalidateReq MSHR miss cycles 2216system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 18447195500 # number of InvalidateReq MSHR miss cycles 2217system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of demand (read+write) MSHR miss cycles 2218system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 292974500 # number of demand (read+write) MSHR miss cycles 2219system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15700856000 # number of demand (read+write) MSHR miss cycles 2220system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39824359500 # number of demand (read+write) MSHR miss cycles 2221system.cpu1.l2cache.demand_mshr_miss_latency::total 56165033000 # number of demand (read+write) MSHR miss cycles 2222system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of overall MSHR miss cycles 2223system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 292974500 # number of overall MSHR miss cycles 2224system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15700856000 # number of overall MSHR miss cycles 2225system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39824359500 # number of overall MSHR miss cycles 2226system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of overall MSHR miss cycles 2227system.cpu1.l2cache.overall_mshr_miss_latency::total 100385490933 # number of overall MSHR miss cycles 2228system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13696500 # number of ReadReq MSHR uncacheable cycles 2229system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3447900000 # number of ReadReq MSHR uncacheable cycles 2230system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3461596500 # number of ReadReq MSHR uncacheable cycles 2231system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3216491500 # number of WriteReq MSHR uncacheable cycles 2232system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3216491500 # number of WriteReq MSHR uncacheable cycles 2233system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13696500 # number of overall MSHR uncacheable cycles 2234system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6664391500 # number of overall MSHR uncacheable cycles 2235system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6678088000 # number of overall MSHR uncacheable cycles 2236system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for ReadReq accesses 2237system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for ReadReq accesses 2238system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044316 # mshr miss rate for ReadReq accesses 2239system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 2240system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 2241system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2242system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2243system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2244system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2245system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660718 # mshr miss rate for UpgradeReq accesses 2246system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660718 # mshr miss rate for UpgradeReq accesses 2247system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.844174 # mshr miss rate for SCUpgradeReq accesses 2248system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.844174 # mshr miss rate for SCUpgradeReq accesses 2249system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2250system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2251system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.190132 # mshr miss rate for ReadExReq accesses 2252system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.190132 # mshr miss rate for ReadExReq accesses 2253system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for ReadCleanReq accesses 2254system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109572 # mshr miss rate for ReadCleanReq accesses 2255system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247950 # mshr miss rate for ReadSharedReq accesses 2256system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247950 # mshr miss rate for ReadSharedReq accesses 2257system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578186 # mshr miss rate for InvalidateReq accesses 2258system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578186 # mshr miss rate for InvalidateReq accesses 2259system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for demand accesses 2260system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for demand accesses 2261system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for demand accesses 2262system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for demand accesses 2263system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167683 # mshr miss rate for demand accesses 2264system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for overall accesses 2265system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for overall accesses 2266system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for overall accesses 2267system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for overall accesses 2268system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2269system.cpu1.l2cache.overall_mshr_miss_rate::total 0.237575 # mshr miss rate for overall accesses 2270system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average ReadReq mshr miss latency 2271system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average ReadReq mshr miss latency 2272system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294 # average ReadReq mshr miss latency 2273system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average HardPFReq mshr miss latency 2274system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163 # average HardPFReq mshr miss latency 2275system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432 # average UpgradeReq mshr miss latency 2276system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432 # average UpgradeReq mshr miss latency 2277system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327 # average SCUpgradeReq mshr miss latency 2278system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327 # average SCUpgradeReq mshr miss latency 2279system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000 # average SCUpgradeFailReq mshr miss latency 2280system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000 # average SCUpgradeFailReq mshr miss latency 2281system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755 # average ReadExReq mshr miss latency 2282system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755 # average ReadExReq mshr miss latency 2283system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average ReadCleanReq mshr miss latency 2284system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953 # average ReadCleanReq mshr miss latency 2285system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038 # average ReadSharedReq mshr miss latency 2286system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038 # average ReadSharedReq mshr miss latency 2287system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181 # average InvalidateReq mshr miss latency 2288system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181 # average InvalidateReq mshr miss latency 2289system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency 2290system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency 2291system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency 2292system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency 2293system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080 # average overall mshr miss latency 2294system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency 2295system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency 2296system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency 2297system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency 2298system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average overall mshr miss latency 2299system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788 # average overall mshr miss latency 2300system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average ReadReq mshr uncacheable latency 2301system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709 # average ReadReq mshr uncacheable latency 2302system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989 # average ReadReq mshr uncacheable latency 2303system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472 # average WriteReq mshr uncacheable latency 2304system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472 # average WriteReq mshr uncacheable latency 2305system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average overall mshr uncacheable latency 2306system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746 # average overall mshr uncacheable latency 2307system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538 # average overall mshr uncacheable latency 2308system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2309system.cpu1.toL2Bus.snoop_filter.tot_requests 20369965 # Total number of requests made to the snoop filter. 2310system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10454543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2311system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2312system.cpu1.toL2Bus.snoop_filter.tot_snoops 477453 # Total number of snoops made to the snoop filter. 2313system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 477447 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2314system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2315system.cpu1.toL2Bus.trans_dist::ReadReq 508237 # Transaction distribution 2316system.cpu1.toL2Bus.trans_dist::ReadResp 8929000 # Transaction distribution 2317system.cpu1.toL2Bus.trans_dist::WriteReq 19330 # Transaction distribution 2318system.cpu1.toL2Bus.trans_dist::WriteResp 19330 # Transaction distribution 2319system.cpu1.toL2Bus.trans_dist::Writeback 4444983 # Transaction distribution 2320system.cpu1.toL2Bus.trans_dist::CleanEvict 8042862 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::HardPFReq 852297 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::UpgradeReq 366971 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363003 # Transaction distribution 2324system.cpu1.toL2Bus.trans_dist::UpgradeResp 446864 # Transaction distribution 2325system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution 2326system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 2327system.cpu1.toL2Bus.trans_dist::ReadExReq 1185291 # Transaction distribution 2328system.cpu1.toL2Bus.trans_dist::ReadExResp 1125998 # Transaction distribution 2329system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4679754 # Transaction distribution 2330system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4554667 # Transaction distribution 2331system.cpu1.toL2Bus.trans_dist::InvalidateReq 467005 # Transaction distribution 2332system.cpu1.toL2Bus.trans_dist::InvalidateResp 459760 # Transaction distribution 2333system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14038440 # Packet count per connected master and slave (bytes) 2334system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16622497 # Packet count per connected master and slave (bytes) 2335system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 296146 # Packet count per connected master and slave (bytes) 2336system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 569967 # Packet count per connected master and slave (bytes) 2337system.cpu1.toL2Bus.pkt_count::total 31527050 # Packet count per connected master and slave (bytes) 2338system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 299504632 # Cumulative packet size per connected master and slave (bytes) 2339system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 528992733 # Cumulative packet size per connected master and slave (bytes) 2340system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1062248 # Cumulative packet size per connected master and slave (bytes) 2341system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1967800 # Cumulative packet size per connected master and slave (bytes) 2342system.cpu1.toL2Bus.pkt_size::total 831527413 # Cumulative packet size per connected master and slave (bytes) 2343system.cpu1.toL2Bus.snoops 5090691 # Total snoops (count) 2344system.cpu1.toL2Bus.snoop_fanout::samples 25485456 # Request fanout histogram 2345system.cpu1.toL2Bus.snoop_fanout::mean 0.028305 # Request fanout histogram 2346system.cpu1.toL2Bus.snoop_fanout::stdev 0.165844 # Request fanout histogram 2347system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2348system.cpu1.toL2Bus.snoop_fanout::0 24764094 97.17% 97.17% # Request fanout histogram 2349system.cpu1.toL2Bus.snoop_fanout::1 721356 2.83% 100.00% # Request fanout histogram 2350system.cpu1.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 2351system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2352system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2353system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2354system.cpu1.toL2Bus.snoop_fanout::total 25485456 # Request fanout histogram 2355system.cpu1.toL2Bus.reqLayer0.occupancy 13733891999 # Layer occupancy (ticks) 2356system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2357system.cpu1.toL2Bus.snoopLayer0.occupancy 167318993 # Layer occupancy (ticks) 2358system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2359system.cpu1.toL2Bus.respLayer0.occupancy 7019739500 # Layer occupancy (ticks) 2360system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2361system.cpu1.toL2Bus.respLayer1.occupancy 7617418010 # Layer occupancy (ticks) 2362system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2363system.cpu1.toL2Bus.respLayer2.occupancy 163365000 # Layer occupancy (ticks) 2364system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2365system.cpu1.toL2Bus.respLayer3.occupancy 323992499 # Layer occupancy (ticks) 2366system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2367system.iobus.trans_dist::ReadReq 40317 # Transaction distribution 2368system.iobus.trans_dist::ReadResp 40317 # Transaction distribution 2369system.iobus.trans_dist::WriteReq 136619 # Transaction distribution 2370system.iobus.trans_dist::WriteResp 136619 # Transaction distribution 2371system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47666 # Packet count per connected master and slave (bytes) 2372system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2373system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2374system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2375system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2376system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2377system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2378system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2379system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2380system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2382system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2383system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2384system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2385system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2386system.iobus.pkt_count_system.bridge.master::total 122600 # Packet count per connected master and slave (bytes) 2387system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) 2388system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) 2389system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2390system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2391system.iobus.pkt_count::total 353872 # Packet count per connected master and slave (bytes) 2392system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47686 # Cumulative packet size per connected master and slave (bytes) 2393system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2394system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2395system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2396system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2397system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2398system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2399system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2400system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2401system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2402system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2403system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2404system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2405system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2406system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2407system.iobus.pkt_size_system.bridge.master::total 155707 # Cumulative packet size per connected master and slave (bytes) 2408system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) 2409system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) 2410system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2411system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2412system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) 2413system.iobus.reqLayer0.occupancy 36194000 # Layer occupancy (ticks) 2414system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2415system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2416system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2417system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2418system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2419system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2420system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2421system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2422system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2423system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2424system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2425system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2426system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2427system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2428system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2429system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2430system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2431system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2432system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2433system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 2434system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2435system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2436system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2437system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2438system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2439system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2440system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2441system.iobus.reqLayer27.occupancy 565735913 # Layer occupancy (ticks) 2442system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2443system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2444system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2445system.iobus.respLayer0.occupancy 92712000 # Layer occupancy (ticks) 2446system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2447system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) 2448system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2449system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2450system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2451system.iocache.tags.replacements 115577 # number of replacements 2452system.iocache.tags.tagsinuse 11.281807 # Cycle average of tags in use 2453system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2454system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. 2455system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2456system.iocache.tags.warmup_cycle 9206321837000 # Cycle when the warmup percentage was hit. 2457system.iocache.tags.occ_blocks::realview.ethernet 3.831702 # Average occupied blocks per requestor 2458system.iocache.tags.occ_blocks::realview.ide 7.450105 # Average occupied blocks per requestor 2459system.iocache.tags.occ_percent::realview.ethernet 0.239481 # Average percentage of cache occupancy 2460system.iocache.tags.occ_percent::realview.ide 0.465632 # Average percentage of cache occupancy 2461system.iocache.tags.occ_percent::total 0.705113 # Average percentage of cache occupancy 2462system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2463system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2464system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2465system.iocache.tags.tag_accesses 1040721 # Number of tag accesses 2466system.iocache.tags.data_accesses 1040721 # Number of data accesses 2467system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2468system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses 2469system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses 2470system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2471system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2472system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2473system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2474system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2475system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses 2476system.iocache.demand_misses::total 8908 # number of demand (read+write) misses 2477system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2478system.iocache.overall_misses::realview.ide 8868 # number of overall misses 2479system.iocache.overall_misses::total 8908 # number of overall misses 2480system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2481system.iocache.ReadReq_miss_latency::realview.ide 1668103306 # number of ReadReq miss cycles 2482system.iocache.ReadReq_miss_latency::total 1673298306 # number of ReadReq miss cycles 2483system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2484system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2485system.iocache.WriteLineReq_miss_latency::realview.ide 13929903607 # number of WriteLineReq miss cycles 2486system.iocache.WriteLineReq_miss_latency::total 13929903607 # number of WriteLineReq miss cycles 2487system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2488system.iocache.demand_miss_latency::realview.ide 1668103306 # number of demand (read+write) miss cycles 2489system.iocache.demand_miss_latency::total 1673667306 # number of demand (read+write) miss cycles 2490system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2491system.iocache.overall_miss_latency::realview.ide 1668103306 # number of overall miss cycles 2492system.iocache.overall_miss_latency::total 1673667306 # number of overall miss cycles 2493system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2494system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) 2495system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) 2496system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2497system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2498system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2499system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2500system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2501system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses 2502system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses 2503system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2504system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses 2505system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses 2506system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2507system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2508system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2509system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2510system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2511system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2512system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2513system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2514system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2515system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2516system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2517system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2518system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2519system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2520system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539 # average ReadReq miss latency 2521system.iocache.ReadReq_avg_miss_latency::total 187905.480741 # average ReadReq miss latency 2522system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2523system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2524system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581 # average WriteLineReq miss latency 2525system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581 # average WriteLineReq miss latency 2526system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2527system.iocache.demand_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency 2528system.iocache.demand_avg_miss_latency::total 187883.622137 # average overall miss latency 2529system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2530system.iocache.overall_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency 2531system.iocache.overall_avg_miss_latency::total 187883.622137 # average overall miss latency 2532system.iocache.blocked_cycles::no_mshrs 33272 # number of cycles access was blocked 2533system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2534system.iocache.blocked::no_mshrs 3491 # number of cycles access was blocked 2535system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2536system.iocache.avg_blocked_cycles::no_mshrs 9.530793 # average number of cycles each access was blocked 2537system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2538system.iocache.fast_writes 0 # number of fast writes performed 2539system.iocache.cache_copies 0 # number of cache copies performed 2540system.iocache.writebacks::writebacks 106694 # number of writebacks 2541system.iocache.writebacks::total 106694 # number of writebacks 2542system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2543system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses 2544system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses 2545system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2546system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2547system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2548system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2549system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2550system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses 2551system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses 2552system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2553system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses 2554system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses 2555system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2556system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224703306 # number of ReadReq MSHR miss cycles 2557system.iocache.ReadReq_mshr_miss_latency::total 1228048306 # number of ReadReq MSHR miss cycles 2558system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2559system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2560system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8593503607 # number of WriteLineReq MSHR miss cycles 2561system.iocache.WriteLineReq_mshr_miss_latency::total 8593503607 # number of WriteLineReq MSHR miss cycles 2562system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2563system.iocache.demand_mshr_miss_latency::realview.ide 1224703306 # number of demand (read+write) MSHR miss cycles 2564system.iocache.demand_mshr_miss_latency::total 1228267306 # number of demand (read+write) MSHR miss cycles 2565system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2566system.iocache.overall_mshr_miss_latency::realview.ide 1224703306 # number of overall MSHR miss cycles 2567system.iocache.overall_mshr_miss_latency::total 1228267306 # number of overall MSHR miss cycles 2568system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2569system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2570system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2571system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2572system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2573system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2574system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2575system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2576system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2577system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2578system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2579system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2580system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2581system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2582system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539 # average ReadReq mshr miss latency 2583system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741 # average ReadReq mshr miss latency 2584system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2585system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2586system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581 # average WriteLineReq mshr miss latency 2587system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581 # average WriteLineReq mshr miss latency 2588system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2589system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency 2590system.iocache.demand_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency 2591system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2592system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency 2593system.iocache.overall_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency 2594system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2595system.l2c.tags.replacements 1400633 # number of replacements 2596system.l2c.tags.tagsinuse 63705.794368 # Cycle average of tags in use 2597system.l2c.tags.total_refs 5028924 # Total number of references to valid blocks. 2598system.l2c.tags.sampled_refs 1460176 # Sample count of references to valid blocks. 2599system.l2c.tags.avg_refs 3.444053 # Average number of references to valid blocks. 2600system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2601system.l2c.tags.occ_blocks::writebacks 18928.346727 # Average occupied blocks per requestor 2602system.l2c.tags.occ_blocks::cpu0.dtb.walker 167.390384 # Average occupied blocks per requestor 2603system.l2c.tags.occ_blocks::cpu0.itb.walker 216.986390 # Average occupied blocks per requestor 2604system.l2c.tags.occ_blocks::cpu0.inst 4428.367994 # Average occupied blocks per requestor 2605system.l2c.tags.occ_blocks::cpu0.data 11717.643832 # Average occupied blocks per requestor 2606system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344 # Average occupied blocks per requestor 2607system.l2c.tags.occ_blocks::cpu1.dtb.walker 156.822011 # Average occupied blocks per requestor 2608system.l2c.tags.occ_blocks::cpu1.itb.walker 230.353384 # Average occupied blocks per requestor 2609system.l2c.tags.occ_blocks::cpu1.inst 2614.971757 # Average occupied blocks per requestor 2610system.l2c.tags.occ_blocks::cpu1.data 4665.203250 # Average occupied blocks per requestor 2611system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9239.567296 # Average occupied blocks per requestor 2612system.l2c.tags.occ_percent::writebacks 0.288824 # Average percentage of cache occupancy 2613system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002554 # Average percentage of cache occupancy 2614system.l2c.tags.occ_percent::cpu0.itb.walker 0.003311 # Average percentage of cache occupancy 2615system.l2c.tags.occ_percent::cpu0.inst 0.067572 # Average percentage of cache occupancy 2616system.l2c.tags.occ_percent::cpu0.data 0.178797 # Average percentage of cache occupancy 2617system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173037 # Average percentage of cache occupancy 2618system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002393 # Average percentage of cache occupancy 2619system.l2c.tags.occ_percent::cpu1.itb.walker 0.003515 # Average percentage of cache occupancy 2620system.l2c.tags.occ_percent::cpu1.inst 0.039901 # Average percentage of cache occupancy 2621system.l2c.tags.occ_percent::cpu1.data 0.071185 # Average percentage of cache occupancy 2622system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140985 # Average percentage of cache occupancy 2623system.l2c.tags.occ_percent::total 0.972073 # Average percentage of cache occupancy 2624system.l2c.tags.occ_task_id_blocks::1022 10769 # Occupied blocks per task id 2625system.l2c.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id 2626system.l2c.tags.occ_task_id_blocks::1024 48480 # Occupied blocks per task id 2627system.l2c.tags.age_task_id_blocks_1022::2 265 # Occupied blocks per task id 2628system.l2c.tags.age_task_id_blocks_1022::3 409 # Occupied blocks per task id 2629system.l2c.tags.age_task_id_blocks_1022::4 10095 # Occupied blocks per task id 2630system.l2c.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id 2631system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 2632system.l2c.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 2633system.l2c.tags.age_task_id_blocks_1024::2 1411 # Occupied blocks per task id 2634system.l2c.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id 2635system.l2c.tags.age_task_id_blocks_1024::4 41942 # Occupied blocks per task id 2636system.l2c.tags.occ_task_id_percent::1022 0.164322 # Percentage of cache occupancy per task id 2637system.l2c.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id 2638system.l2c.tags.occ_task_id_percent::1024 0.739746 # Percentage of cache occupancy per task id 2639system.l2c.tags.tag_accesses 64230359 # Number of tag accesses 2640system.l2c.tags.data_accesses 64230359 # Number of data accesses 2641system.l2c.Writeback_hits::writebacks 2314762 # number of Writeback hits 2642system.l2c.Writeback_hits::total 2314762 # number of Writeback hits 2643system.l2c.UpgradeReq_hits::cpu0.data 28623 # number of UpgradeReq hits 2644system.l2c.UpgradeReq_hits::cpu1.data 30874 # number of UpgradeReq hits 2645system.l2c.UpgradeReq_hits::total 59497 # number of UpgradeReq hits 2646system.l2c.SCUpgradeReq_hits::cpu0.data 6079 # number of SCUpgradeReq hits 2647system.l2c.SCUpgradeReq_hits::cpu1.data 5789 # number of SCUpgradeReq hits 2648system.l2c.SCUpgradeReq_hits::total 11868 # number of SCUpgradeReq hits 2649system.l2c.ReadExReq_hits::cpu0.data 160432 # number of ReadExReq hits 2650system.l2c.ReadExReq_hits::cpu1.data 145801 # number of ReadExReq hits 2651system.l2c.ReadExReq_hits::total 306233 # number of ReadExReq hits 2652system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5516 # number of ReadSharedReq hits 2653system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4550 # number of ReadSharedReq hits 2654system.l2c.ReadSharedReq_hits::cpu0.inst 461560 # number of ReadSharedReq hits 2655system.l2c.ReadSharedReq_hits::cpu0.data 521601 # number of ReadSharedReq hits 2656system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 265120 # number of ReadSharedReq hits 2657system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 4769 # number of ReadSharedReq hits 2658system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3407 # number of ReadSharedReq hits 2659system.l2c.ReadSharedReq_hits::cpu1.inst 473807 # number of ReadSharedReq hits 2660system.l2c.ReadSharedReq_hits::cpu1.data 524703 # number of ReadSharedReq hits 2661system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 267683 # number of ReadSharedReq hits 2662system.l2c.ReadSharedReq_hits::total 2532716 # number of ReadSharedReq hits 2663system.l2c.demand_hits::cpu0.dtb.walker 5516 # number of demand (read+write) hits 2664system.l2c.demand_hits::cpu0.itb.walker 4550 # number of demand (read+write) hits 2665system.l2c.demand_hits::cpu0.inst 461560 # number of demand (read+write) hits 2666system.l2c.demand_hits::cpu0.data 682033 # number of demand (read+write) hits 2667system.l2c.demand_hits::cpu0.l2cache.prefetcher 265120 # number of demand (read+write) hits 2668system.l2c.demand_hits::cpu1.dtb.walker 4769 # number of demand (read+write) hits 2669system.l2c.demand_hits::cpu1.itb.walker 3407 # number of demand (read+write) hits 2670system.l2c.demand_hits::cpu1.inst 473807 # number of demand (read+write) hits 2671system.l2c.demand_hits::cpu1.data 670504 # number of demand (read+write) hits 2672system.l2c.demand_hits::cpu1.l2cache.prefetcher 267683 # number of demand (read+write) hits 2673system.l2c.demand_hits::total 2838949 # number of demand (read+write) hits 2674system.l2c.overall_hits::cpu0.dtb.walker 5516 # number of overall hits 2675system.l2c.overall_hits::cpu0.itb.walker 4550 # number of overall hits 2676system.l2c.overall_hits::cpu0.inst 461560 # number of overall hits 2677system.l2c.overall_hits::cpu0.data 682033 # number of overall hits 2678system.l2c.overall_hits::cpu0.l2cache.prefetcher 265120 # number of overall hits 2679system.l2c.overall_hits::cpu1.dtb.walker 4769 # number of overall hits 2680system.l2c.overall_hits::cpu1.itb.walker 3407 # number of overall hits 2681system.l2c.overall_hits::cpu1.inst 473807 # number of overall hits 2682system.l2c.overall_hits::cpu1.data 670504 # number of overall hits 2683system.l2c.overall_hits::cpu1.l2cache.prefetcher 267683 # number of overall hits 2684system.l2c.overall_hits::total 2838949 # number of overall hits 2685system.l2c.UpgradeReq_misses::cpu0.data 45739 # number of UpgradeReq misses 2686system.l2c.UpgradeReq_misses::cpu1.data 41402 # number of UpgradeReq misses 2687system.l2c.UpgradeReq_misses::total 87141 # number of UpgradeReq misses 2688system.l2c.SCUpgradeReq_misses::cpu0.data 10551 # number of SCUpgradeReq misses 2689system.l2c.SCUpgradeReq_misses::cpu1.data 10041 # number of SCUpgradeReq misses 2690system.l2c.SCUpgradeReq_misses::total 20592 # number of SCUpgradeReq misses 2691system.l2c.ReadExReq_misses::cpu0.data 478288 # number of ReadExReq misses 2692system.l2c.ReadExReq_misses::cpu1.data 167740 # number of ReadExReq misses 2693system.l2c.ReadExReq_misses::total 646028 # number of ReadExReq misses 2694system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq misses 2695system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2246 # number of ReadSharedReq misses 2696system.l2c.ReadSharedReq_misses::cpu0.inst 51456 # number of ReadSharedReq misses 2697system.l2c.ReadSharedReq_misses::cpu0.data 156048 # number of ReadSharedReq misses 2698system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq misses 2699system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1431 # number of ReadSharedReq misses 2700system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1351 # number of ReadSharedReq misses 2701system.l2c.ReadSharedReq_misses::cpu1.inst 38962 # number of ReadSharedReq misses 2702system.l2c.ReadSharedReq_misses::cpu1.data 102025 # number of ReadSharedReq misses 2703system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 234272 # number of ReadSharedReq misses 2704system.l2c.ReadSharedReq_misses::total 778714 # number of ReadSharedReq misses 2705system.l2c.demand_misses::cpu0.dtb.walker 1990 # number of demand (read+write) misses 2706system.l2c.demand_misses::cpu0.itb.walker 2246 # number of demand (read+write) misses 2707system.l2c.demand_misses::cpu0.inst 51456 # number of demand (read+write) misses 2708system.l2c.demand_misses::cpu0.data 634336 # number of demand (read+write) misses 2709system.l2c.demand_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) misses 2710system.l2c.demand_misses::cpu1.dtb.walker 1431 # number of demand (read+write) misses 2711system.l2c.demand_misses::cpu1.itb.walker 1351 # number of demand (read+write) misses 2712system.l2c.demand_misses::cpu1.inst 38962 # number of demand (read+write) misses 2713system.l2c.demand_misses::cpu1.data 269765 # number of demand (read+write) misses 2714system.l2c.demand_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) misses 2715system.l2c.demand_misses::total 1424742 # number of demand (read+write) misses 2716system.l2c.overall_misses::cpu0.dtb.walker 1990 # number of overall misses 2717system.l2c.overall_misses::cpu0.itb.walker 2246 # number of overall misses 2718system.l2c.overall_misses::cpu0.inst 51456 # number of overall misses 2719system.l2c.overall_misses::cpu0.data 634336 # number of overall misses 2720system.l2c.overall_misses::cpu0.l2cache.prefetcher 188933 # number of overall misses 2721system.l2c.overall_misses::cpu1.dtb.walker 1431 # number of overall misses 2722system.l2c.overall_misses::cpu1.itb.walker 1351 # number of overall misses 2723system.l2c.overall_misses::cpu1.inst 38962 # number of overall misses 2724system.l2c.overall_misses::cpu1.data 269765 # number of overall misses 2725system.l2c.overall_misses::cpu1.l2cache.prefetcher 234272 # number of overall misses 2726system.l2c.overall_misses::total 1424742 # number of overall misses 2727system.l2c.UpgradeReq_miss_latency::cpu0.data 656419000 # number of UpgradeReq miss cycles 2728system.l2c.UpgradeReq_miss_latency::cpu1.data 602429500 # number of UpgradeReq miss cycles 2729system.l2c.UpgradeReq_miss_latency::total 1258848500 # number of UpgradeReq miss cycles 2730system.l2c.SCUpgradeReq_miss_latency::cpu0.data 138505500 # number of SCUpgradeReq miss cycles 2731system.l2c.SCUpgradeReq_miss_latency::cpu1.data 121106000 # number of SCUpgradeReq miss cycles 2732system.l2c.SCUpgradeReq_miss_latency::total 259611500 # number of SCUpgradeReq miss cycles 2733system.l2c.ReadExReq_miss_latency::cpu0.data 64575954000 # number of ReadExReq miss cycles 2734system.l2c.ReadExReq_miss_latency::cpu1.data 22241696500 # number of ReadExReq miss cycles 2735system.l2c.ReadExReq_miss_latency::total 86817650500 # number of ReadExReq miss cycles 2736system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 275343500 # number of ReadSharedReq miss cycles 2737system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 312648500 # number of ReadSharedReq miss cycles 2738system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6939841000 # number of ReadSharedReq miss cycles 2739system.l2c.ReadSharedReq_miss_latency::cpu0.data 21911323500 # number of ReadSharedReq miss cycles 2740system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of ReadSharedReq miss cycles 2741system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 199825500 # number of ReadSharedReq miss cycles 2742system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 189752500 # number of ReadSharedReq miss cycles 2743system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5267042000 # number of ReadSharedReq miss cycles 2744system.l2c.ReadSharedReq_miss_latency::cpu1.data 14361628000 # number of ReadSharedReq miss cycles 2745system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of ReadSharedReq miss cycles 2746system.l2c.ReadSharedReq_miss_latency::total 119572711026 # number of ReadSharedReq miss cycles 2747system.l2c.demand_miss_latency::cpu0.dtb.walker 275343500 # number of demand (read+write) miss cycles 2748system.l2c.demand_miss_latency::cpu0.itb.walker 312648500 # number of demand (read+write) miss cycles 2749system.l2c.demand_miss_latency::cpu0.inst 6939841000 # number of demand (read+write) miss cycles 2750system.l2c.demand_miss_latency::cpu0.data 86487277500 # number of demand (read+write) miss cycles 2751system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of demand (read+write) miss cycles 2752system.l2c.demand_miss_latency::cpu1.dtb.walker 199825500 # number of demand (read+write) miss cycles 2753system.l2c.demand_miss_latency::cpu1.itb.walker 189752500 # number of demand (read+write) miss cycles 2754system.l2c.demand_miss_latency::cpu1.inst 5267042000 # number of demand (read+write) miss cycles 2755system.l2c.demand_miss_latency::cpu1.data 36603324500 # number of demand (read+write) miss cycles 2756system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of demand (read+write) miss cycles 2757system.l2c.demand_miss_latency::total 206390361526 # number of demand (read+write) miss cycles 2758system.l2c.overall_miss_latency::cpu0.dtb.walker 275343500 # number of overall miss cycles 2759system.l2c.overall_miss_latency::cpu0.itb.walker 312648500 # number of overall miss cycles 2760system.l2c.overall_miss_latency::cpu0.inst 6939841000 # number of overall miss cycles 2761system.l2c.overall_miss_latency::cpu0.data 86487277500 # number of overall miss cycles 2762system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of overall miss cycles 2763system.l2c.overall_miss_latency::cpu1.dtb.walker 199825500 # number of overall miss cycles 2764system.l2c.overall_miss_latency::cpu1.itb.walker 189752500 # number of overall miss cycles 2765system.l2c.overall_miss_latency::cpu1.inst 5267042000 # number of overall miss cycles 2766system.l2c.overall_miss_latency::cpu1.data 36603324500 # number of overall miss cycles 2767system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of overall miss cycles 2768system.l2c.overall_miss_latency::total 206390361526 # number of overall miss cycles 2769system.l2c.Writeback_accesses::writebacks 2314762 # number of Writeback accesses(hits+misses) 2770system.l2c.Writeback_accesses::total 2314762 # number of Writeback accesses(hits+misses) 2771system.l2c.UpgradeReq_accesses::cpu0.data 74362 # number of UpgradeReq accesses(hits+misses) 2772system.l2c.UpgradeReq_accesses::cpu1.data 72276 # number of UpgradeReq accesses(hits+misses) 2773system.l2c.UpgradeReq_accesses::total 146638 # number of UpgradeReq accesses(hits+misses) 2774system.l2c.SCUpgradeReq_accesses::cpu0.data 16630 # number of SCUpgradeReq accesses(hits+misses) 2775system.l2c.SCUpgradeReq_accesses::cpu1.data 15830 # number of SCUpgradeReq accesses(hits+misses) 2776system.l2c.SCUpgradeReq_accesses::total 32460 # number of SCUpgradeReq accesses(hits+misses) 2777system.l2c.ReadExReq_accesses::cpu0.data 638720 # number of ReadExReq accesses(hits+misses) 2778system.l2c.ReadExReq_accesses::cpu1.data 313541 # number of ReadExReq accesses(hits+misses) 2779system.l2c.ReadExReq_accesses::total 952261 # number of ReadExReq accesses(hits+misses) 2780system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7506 # number of ReadSharedReq accesses(hits+misses) 2781system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6796 # number of ReadSharedReq accesses(hits+misses) 2782system.l2c.ReadSharedReq_accesses::cpu0.inst 513016 # number of ReadSharedReq accesses(hits+misses) 2783system.l2c.ReadSharedReq_accesses::cpu0.data 677649 # number of ReadSharedReq accesses(hits+misses) 2784system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 454053 # number of ReadSharedReq accesses(hits+misses) 2785system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6200 # number of ReadSharedReq accesses(hits+misses) 2786system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 4758 # number of ReadSharedReq accesses(hits+misses) 2787system.l2c.ReadSharedReq_accesses::cpu1.inst 512769 # number of ReadSharedReq accesses(hits+misses) 2788system.l2c.ReadSharedReq_accesses::cpu1.data 626728 # number of ReadSharedReq accesses(hits+misses) 2789system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 501955 # number of ReadSharedReq accesses(hits+misses) 2790system.l2c.ReadSharedReq_accesses::total 3311430 # number of ReadSharedReq accesses(hits+misses) 2791system.l2c.demand_accesses::cpu0.dtb.walker 7506 # number of demand (read+write) accesses 2792system.l2c.demand_accesses::cpu0.itb.walker 6796 # number of demand (read+write) accesses 2793system.l2c.demand_accesses::cpu0.inst 513016 # number of demand (read+write) accesses 2794system.l2c.demand_accesses::cpu0.data 1316369 # number of demand (read+write) accesses 2795system.l2c.demand_accesses::cpu0.l2cache.prefetcher 454053 # number of demand (read+write) accesses 2796system.l2c.demand_accesses::cpu1.dtb.walker 6200 # number of demand (read+write) accesses 2797system.l2c.demand_accesses::cpu1.itb.walker 4758 # number of demand (read+write) accesses 2798system.l2c.demand_accesses::cpu1.inst 512769 # number of demand (read+write) accesses 2799system.l2c.demand_accesses::cpu1.data 940269 # number of demand (read+write) accesses 2800system.l2c.demand_accesses::cpu1.l2cache.prefetcher 501955 # number of demand (read+write) accesses 2801system.l2c.demand_accesses::total 4263691 # number of demand (read+write) accesses 2802system.l2c.overall_accesses::cpu0.dtb.walker 7506 # number of overall (read+write) accesses 2803system.l2c.overall_accesses::cpu0.itb.walker 6796 # number of overall (read+write) accesses 2804system.l2c.overall_accesses::cpu0.inst 513016 # number of overall (read+write) accesses 2805system.l2c.overall_accesses::cpu0.data 1316369 # number of overall (read+write) accesses 2806system.l2c.overall_accesses::cpu0.l2cache.prefetcher 454053 # number of overall (read+write) accesses 2807system.l2c.overall_accesses::cpu1.dtb.walker 6200 # number of overall (read+write) accesses 2808system.l2c.overall_accesses::cpu1.itb.walker 4758 # number of overall (read+write) accesses 2809system.l2c.overall_accesses::cpu1.inst 512769 # number of overall (read+write) accesses 2810system.l2c.overall_accesses::cpu1.data 940269 # number of overall (read+write) accesses 2811system.l2c.overall_accesses::cpu1.l2cache.prefetcher 501955 # number of overall (read+write) accesses 2812system.l2c.overall_accesses::total 4263691 # number of overall (read+write) accesses 2813system.l2c.UpgradeReq_miss_rate::cpu0.data 0.615086 # miss rate for UpgradeReq accesses 2814system.l2c.UpgradeReq_miss_rate::cpu1.data 0.572832 # miss rate for UpgradeReq accesses 2815system.l2c.UpgradeReq_miss_rate::total 0.594259 # miss rate for UpgradeReq accesses 2816system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634456 # miss rate for SCUpgradeReq accesses 2817system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.634302 # miss rate for SCUpgradeReq accesses 2818system.l2c.SCUpgradeReq_miss_rate::total 0.634381 # miss rate for SCUpgradeReq accesses 2819system.l2c.ReadExReq_miss_rate::cpu0.data 0.748823 # miss rate for ReadExReq accesses 2820system.l2c.ReadExReq_miss_rate::cpu1.data 0.534986 # miss rate for ReadExReq accesses 2821system.l2c.ReadExReq_miss_rate::total 0.678415 # miss rate for ReadExReq accesses 2822system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for ReadSharedReq accesses 2823system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.330489 # miss rate for ReadSharedReq accesses 2824system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100301 # miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.230279 # miss rate for ReadSharedReq accesses 2826system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for ReadSharedReq accesses 2827system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for ReadSharedReq accesses 2828system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.283943 # miss rate for ReadSharedReq accesses 2829system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075984 # miss rate for ReadSharedReq accesses 2830system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162790 # miss rate for ReadSharedReq accesses 2831system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for ReadSharedReq accesses 2832system.l2c.ReadSharedReq_miss_rate::total 0.235159 # miss rate for ReadSharedReq accesses 2833system.l2c.demand_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for demand accesses 2834system.l2c.demand_miss_rate::cpu0.itb.walker 0.330489 # miss rate for demand accesses 2835system.l2c.demand_miss_rate::cpu0.inst 0.100301 # miss rate for demand accesses 2836system.l2c.demand_miss_rate::cpu0.data 0.481883 # miss rate for demand accesses 2837system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for demand accesses 2838system.l2c.demand_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for demand accesses 2839system.l2c.demand_miss_rate::cpu1.itb.walker 0.283943 # miss rate for demand accesses 2840system.l2c.demand_miss_rate::cpu1.inst 0.075984 # miss rate for demand accesses 2841system.l2c.demand_miss_rate::cpu1.data 0.286902 # miss rate for demand accesses 2842system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for demand accesses 2843system.l2c.demand_miss_rate::total 0.334157 # miss rate for demand accesses 2844system.l2c.overall_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for overall accesses 2845system.l2c.overall_miss_rate::cpu0.itb.walker 0.330489 # miss rate for overall accesses 2846system.l2c.overall_miss_rate::cpu0.inst 0.100301 # miss rate for overall accesses 2847system.l2c.overall_miss_rate::cpu0.data 0.481883 # miss rate for overall accesses 2848system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for overall accesses 2849system.l2c.overall_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for overall accesses 2850system.l2c.overall_miss_rate::cpu1.itb.walker 0.283943 # miss rate for overall accesses 2851system.l2c.overall_miss_rate::cpu1.inst 0.075984 # miss rate for overall accesses 2852system.l2c.overall_miss_rate::cpu1.data 0.286902 # miss rate for overall accesses 2853system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for overall accesses 2854system.l2c.overall_miss_rate::total 0.334157 # miss rate for overall accesses 2855system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14351.406896 # average UpgradeReq miss latency 2856system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14550.734264 # average UpgradeReq miss latency 2857system.l2c.UpgradeReq_avg_miss_latency::total 14446.110327 # average UpgradeReq miss latency 2858system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13127.239124 # average SCUpgradeReq miss latency 2859system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12061.149288 # average SCUpgradeReq miss latency 2860system.l2c.SCUpgradeReq_avg_miss_latency::total 12607.396076 # average SCUpgradeReq miss latency 2861system.l2c.ReadExReq_avg_miss_latency::cpu0.data 135014.790252 # average ReadExReq miss latency 2862system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132596.259091 # average ReadExReq miss latency 2863system.l2c.ReadExReq_avg_miss_latency::total 134386.823017 # average ReadExReq miss latency 2864system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average ReadSharedReq miss latency 2865system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 139202.359751 # average ReadSharedReq miss latency 2866system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134869.422419 # average ReadSharedReq miss latency 2867system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140413.997616 # average ReadSharedReq miss latency 2868system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average ReadSharedReq miss latency 2869system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average ReadSharedReq miss latency 2870system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140453.367876 # average ReadSharedReq miss latency 2871system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135184.076793 # average ReadSharedReq miss latency 2872system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140765.773095 # average ReadSharedReq miss latency 2873system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average ReadSharedReq miss latency 2874system.l2c.ReadSharedReq_avg_miss_latency::total 153551.510601 # average ReadSharedReq miss latency 2875system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency 2876system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency 2877system.l2c.demand_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency 2878system.l2c.demand_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency 2879system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency 2880system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency 2881system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency 2882system.l2c.demand_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency 2883system.l2c.demand_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency 2884system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency 2885system.l2c.demand_avg_miss_latency::total 144861.568990 # average overall miss latency 2886system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency 2887system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency 2888system.l2c.overall_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency 2889system.l2c.overall_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency 2890system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency 2891system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency 2892system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency 2893system.l2c.overall_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency 2894system.l2c.overall_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency 2895system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency 2896system.l2c.overall_avg_miss_latency::total 144861.568990 # average overall miss latency 2897system.l2c.blocked_cycles::no_mshrs 455 # number of cycles access was blocked 2898system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2899system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 2900system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2901system.l2c.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked 2902system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2903system.l2c.fast_writes 0 # number of fast writes performed 2904system.l2c.cache_copies 0 # number of cache copies performed 2905system.l2c.writebacks::writebacks 1097098 # number of writebacks 2906system.l2c.writebacks::total 1097098 # number of writebacks 2907system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 101 # number of ReadSharedReq MSHR hits 2908system.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits 2909system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 79 # number of ReadSharedReq MSHR hits 2910system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits 2911system.l2c.ReadSharedReq_mshr_hits::total 220 # number of ReadSharedReq MSHR hits 2912system.l2c.demand_mshr_hits::cpu0.inst 101 # number of demand (read+write) MSHR hits 2913system.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits 2914system.l2c.demand_mshr_hits::cpu1.inst 79 # number of demand (read+write) MSHR hits 2915system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits 2916system.l2c.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits 2917system.l2c.overall_mshr_hits::cpu0.inst 101 # number of overall MSHR hits 2918system.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits 2919system.l2c.overall_mshr_hits::cpu1.inst 79 # number of overall MSHR hits 2920system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits 2921system.l2c.overall_mshr_hits::total 220 # number of overall MSHR hits 2922system.l2c.CleanEvict_mshr_misses::writebacks 44502 # number of CleanEvict MSHR misses 2923system.l2c.CleanEvict_mshr_misses::total 44502 # number of CleanEvict MSHR misses 2924system.l2c.UpgradeReq_mshr_misses::cpu0.data 45739 # number of UpgradeReq MSHR misses 2925system.l2c.UpgradeReq_mshr_misses::cpu1.data 41402 # number of UpgradeReq MSHR misses 2926system.l2c.UpgradeReq_mshr_misses::total 87141 # number of UpgradeReq MSHR misses 2927system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10551 # number of SCUpgradeReq MSHR misses 2928system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10041 # number of SCUpgradeReq MSHR misses 2929system.l2c.SCUpgradeReq_mshr_misses::total 20592 # number of SCUpgradeReq MSHR misses 2930system.l2c.ReadExReq_mshr_misses::cpu0.data 478288 # number of ReadExReq MSHR misses 2931system.l2c.ReadExReq_mshr_misses::cpu1.data 167740 # number of ReadExReq MSHR misses 2932system.l2c.ReadExReq_mshr_misses::total 646028 # number of ReadExReq MSHR misses 2933system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq MSHR misses 2934system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2246 # number of ReadSharedReq MSHR misses 2935system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 51355 # number of ReadSharedReq MSHR misses 2936system.l2c.ReadSharedReq_mshr_misses::cpu0.data 156019 # number of ReadSharedReq MSHR misses 2937system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq MSHR misses 2938system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1431 # 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number of demand (read+write) MSHR misses 2950system.l2c.demand_mshr_misses::cpu1.itb.walker 1351 # number of demand (read+write) MSHR misses 2951system.l2c.demand_mshr_misses::cpu1.inst 38883 # number of demand (read+write) MSHR misses 2952system.l2c.demand_mshr_misses::cpu1.data 269754 # number of demand (read+write) MSHR misses 2953system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) MSHR misses 2954system.l2c.demand_mshr_misses::total 1424522 # number of demand (read+write) MSHR misses 2955system.l2c.overall_mshr_misses::cpu0.dtb.walker 1990 # number of overall MSHR misses 2956system.l2c.overall_mshr_misses::cpu0.itb.walker 2246 # number of overall MSHR misses 2957system.l2c.overall_mshr_misses::cpu0.inst 51355 # number of overall MSHR misses 2958system.l2c.overall_mshr_misses::cpu0.data 634307 # number of overall MSHR misses 2959system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of overall MSHR misses 2960system.l2c.overall_mshr_misses::cpu1.dtb.walker 1431 # number of overall MSHR misses 2961system.l2c.overall_mshr_misses::cpu1.itb.walker 1351 # number of overall MSHR misses 2962system.l2c.overall_mshr_misses::cpu1.inst 38883 # number of overall MSHR misses 2963system.l2c.overall_mshr_misses::cpu1.data 269754 # number of overall MSHR misses 2964system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of overall MSHR misses 2965system.l2c.overall_mshr_misses::total 1424522 # number of overall MSHR misses 2966system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 2967system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable 2968system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2969system.l2c.ReadReq_mshr_uncacheable::cpu1.data 20768 # number of ReadReq MSHR uncacheable 2970system.l2c.ReadReq_mshr_uncacheable::total 81299 # number of ReadReq MSHR uncacheable 2971system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable 2972system.l2c.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable 2973system.l2c.WriteReq_mshr_uncacheable::total 37949 # number of WriteReq MSHR uncacheable 2974system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 2975system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses 2976system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2977system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40098 # number of overall MSHR uncacheable misses 2978system.l2c.overall_mshr_uncacheable_misses::total 119248 # number of overall MSHR uncacheable misses 2979system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3380760500 # number of UpgradeReq MSHR miss cycles 2980system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3033576500 # number of UpgradeReq MSHR miss cycles 2981system.l2c.UpgradeReq_mshr_miss_latency::total 6414337000 # number of UpgradeReq MSHR miss cycles 2982system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 808671000 # 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number of demand (read+write) MSHR miss cycles 3002system.l2c.demand_mshr_miss_latency::cpu0.data 80140634500 # number of demand (read+write) MSHR miss cycles 3003system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28894811526 # number of demand (read+write) MSHR miss cycles 3004system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 185515500 # number of demand (read+write) MSHR miss cycles 3005system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 176242500 # number of demand (read+write) MSHR miss cycles 3006system.l2c.demand_mshr_miss_latency::cpu1.inst 4869464500 # number of demand (read+write) MSHR miss cycles 3007system.l2c.demand_mshr_miss_latency::cpu1.data 33904653500 # number of demand (read+write) MSHR miss cycles 3008system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 36988445000 # number of demand (read+write) MSHR miss cycles 3009system.l2c.demand_mshr_miss_latency::total 192119736026 # number of demand (read+write) MSHR miss cycles 3010system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 255443500 # number of overall MSHR miss cycles 3011system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 290188500 # number of overall MSHR miss cycles 3012system.l2c.overall_mshr_miss_latency::cpu0.inst 6414337000 # number of overall MSHR miss cycles 3013system.l2c.overall_mshr_miss_latency::cpu0.data 80140634500 # number of overall MSHR miss cycles 3014system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28894811526 # number of overall MSHR miss cycles 3015system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 185515500 # number of overall MSHR miss cycles 3016system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 176242500 # number of overall MSHR miss cycles 3017system.l2c.overall_mshr_miss_latency::cpu1.inst 4869464500 # number of overall MSHR miss cycles 3018system.l2c.overall_mshr_miss_latency::cpu1.data 33904653500 # number of overall MSHR miss cycles 3019system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36988445000 # number of overall MSHR miss cycles 3020system.l2c.overall_mshr_miss_latency::total 192119736026 # number of overall MSHR miss cycles 3021system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854189000 # number of ReadReq MSHR uncacheable cycles 3022system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2429636000 # number of ReadReq MSHR uncacheable cycles 3023system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11716500 # number of ReadReq MSHR uncacheable cycles 3024system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3074041000 # number of ReadReq MSHR uncacheable cycles 3025system.l2c.ReadReq_mshr_uncacheable_latency::total 10369582500 # number of ReadReq MSHR uncacheable cycles 3026system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2635303500 # number of WriteReq MSHR uncacheable cycles 3027system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2887877500 # number of WriteReq MSHR uncacheable cycles 3028system.l2c.WriteReq_mshr_uncacheable_latency::total 5523181000 # number of WriteReq MSHR uncacheable cycles 3029system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854189000 # number of overall MSHR uncacheable cycles 3030system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5064939500 # number of overall MSHR uncacheable cycles 3031system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11716500 # number of overall MSHR uncacheable cycles 3032system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5961918500 # number of overall MSHR uncacheable cycles 3033system.l2c.overall_mshr_uncacheable_latency::total 15892763500 # number of overall MSHR uncacheable cycles 3034system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3035system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3036system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.615086 # mshr miss rate for UpgradeReq accesses 3037system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.572832 # mshr miss rate for UpgradeReq accesses 3038system.l2c.UpgradeReq_mshr_miss_rate::total 0.594259 # mshr miss rate for UpgradeReq accesses 3039system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.634456 # mshr miss rate for SCUpgradeReq accesses 3040system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.634302 # mshr miss rate for SCUpgradeReq accesses 3041system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.634381 # mshr miss rate for SCUpgradeReq accesses 3042system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.748823 # mshr miss rate for ReadExReq accesses 3043system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534986 # mshr miss rate for ReadExReq accesses 3044system.l2c.ReadExReq_mshr_miss_rate::total 0.678415 # mshr miss rate for ReadExReq accesses 3045system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for ReadSharedReq accesses 3046system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for ReadSharedReq accesses 3047system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for ReadSharedReq accesses 3048system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.230236 # mshr miss rate for ReadSharedReq accesses 3049system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for ReadSharedReq accesses 3050system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for ReadSharedReq accesses 3051system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for ReadSharedReq accesses 3052system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for ReadSharedReq accesses 3053system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162772 # mshr miss rate for ReadSharedReq accesses 3054system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for ReadSharedReq accesses 3055system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235093 # mshr miss rate for ReadSharedReq accesses 3056system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for demand accesses 3057system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for demand accesses 3058system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for demand accesses 3059system.l2c.demand_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for demand accesses 3060system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for demand accesses 3061system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for demand accesses 3062system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for demand accesses 3063system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for demand accesses 3064system.l2c.demand_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for demand accesses 3065system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for demand accesses 3066system.l2c.demand_mshr_miss_rate::total 0.334105 # mshr miss rate for demand accesses 3067system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for overall accesses 3068system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for overall accesses 3069system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for overall accesses 3070system.l2c.overall_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for overall accesses 3071system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for overall accesses 3072system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for overall accesses 3073system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for overall accesses 3074system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for overall accesses 3075system.l2c.overall_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for overall accesses 3076system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for overall accesses 3077system.l2c.overall_mshr_miss_rate::total 0.334105 # mshr miss rate for overall accesses 3078system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086 # average UpgradeReq mshr miss latency 3079system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012 # average UpgradeReq mshr miss latency 3080system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612 # average UpgradeReq mshr miss latency 3081system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785 # average SCUpgradeReq mshr miss latency 3082system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636 # average SCUpgradeReq mshr miss latency 3083system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371 # average SCUpgradeReq mshr miss latency 3084system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252 # average ReadExReq mshr miss latency 3085system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091 # average ReadExReq mshr miss latency 3086system.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017 # average ReadExReq mshr miss latency 3087system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average ReadSharedReq mshr miss latency 3088system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average ReadSharedReq mshr miss latency 3089system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average ReadSharedReq mshr miss latency 3090system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983 # average ReadSharedReq mshr miss latency 3091system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average ReadSharedReq mshr miss latency 3092system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average ReadSharedReq mshr miss latency 3093system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average ReadSharedReq mshr miss latency 3094system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average ReadSharedReq mshr miss latency 3095system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921 # average ReadSharedReq mshr miss latency 3096system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average ReadSharedReq mshr miss latency 3097system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621 # average ReadSharedReq mshr miss latency 3098system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency 3099system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency 3100system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency 3101system.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency 3102system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency 3103system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency 3104system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency 3105system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency 3106system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency 3107system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency 3108system.l2c.demand_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency 3109system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency 3110system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency 3111system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency 3112system.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency 3113system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency 3114system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency 3115system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency 3116system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency 3117system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency 3118system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency 3119system.l2c.overall_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency 3120system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average ReadReq mshr uncacheable latency 3121system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790 # average ReadReq mshr uncacheable latency 3122system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average ReadReq mshr uncacheable latency 3123system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928 # average ReadReq mshr uncacheable latency 3124system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086 # average ReadReq mshr uncacheable latency 3125system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633 # average WriteReq mshr uncacheable latency 3126system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540 # average WriteReq mshr uncacheable latency 3127system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376 # average WriteReq mshr uncacheable latency 3128system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average overall mshr uncacheable latency 3129system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334 # average overall mshr uncacheable latency 3130system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average overall mshr uncacheable latency 3131system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466 # average overall mshr uncacheable latency 3132system.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113 # average overall mshr uncacheable latency 3133system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3134system.membus.trans_dist::ReadReq 81299 # Transaction distribution 3135system.membus.trans_dist::ReadResp 868698 # Transaction distribution 3136system.membus.trans_dist::WriteReq 37949 # Transaction distribution 3137system.membus.trans_dist::WriteResp 37949 # Transaction distribution 3138system.membus.trans_dist::Writeback 1203792 # Transaction distribution 3139system.membus.trans_dist::CleanEvict 220565 # Transaction distribution 3140system.membus.trans_dist::UpgradeReq 376258 # Transaction distribution 3141system.membus.trans_dist::SCUpgradeReq 321655 # Transaction distribution 3142system.membus.trans_dist::UpgradeResp 113911 # Transaction distribution 3143system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3144system.membus.trans_dist::ReadExReq 660250 # Transaction distribution 3145system.membus.trans_dist::ReadExResp 639853 # Transaction distribution 3146system.membus.trans_dist::ReadSharedReq 787399 # Transaction distribution 3147system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3148system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3149system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122600 # Packet count per connected master and slave (bytes) 3150system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3151system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24206 # Packet count per connected master and slave (bytes) 3152system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5071225 # Packet count per connected master and slave (bytes) 3153system.membus.pkt_count_system.l2c.mem_side::total 5218123 # Packet count per connected master and slave (bytes) 3154system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341689 # Packet count per connected master and slave (bytes) 3155system.membus.pkt_count_system.iocache.mem_side::total 341689 # Packet count per connected master and slave (bytes) 3156system.membus.pkt_count::total 5559812 # Packet count per connected master and slave (bytes) 3157system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155707 # Cumulative packet size per connected master and slave (bytes) 3158system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3159system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48412 # Cumulative packet size per connected master and slave (bytes) 3160system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 161136300 # Cumulative packet size per connected master and slave (bytes) 3161system.membus.pkt_size_system.l2c.mem_side::total 161340623 # Cumulative packet size per connected master and slave (bytes) 3162system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7239232 # Cumulative packet size per connected master and slave (bytes) 3163system.membus.pkt_size_system.iocache.mem_side::total 7239232 # Cumulative packet size per connected master and slave (bytes) 3164system.membus.pkt_size::total 168579855 # Cumulative packet size per connected master and slave (bytes) 3165system.membus.snoops 607627 # Total snoops (count) 3166system.membus.snoop_fanout::samples 3798608 # Request fanout histogram 3167system.membus.snoop_fanout::mean 1 # Request fanout histogram 3168system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3169system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3170system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3171system.membus.snoop_fanout::1 3798608 100.00% 100.00% # Request fanout histogram 3172system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3173system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3174system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3175system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3176system.membus.snoop_fanout::total 3798608 # Request fanout histogram 3177system.membus.reqLayer0.occupancy 101169498 # Layer occupancy (ticks) 3178system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3179system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3180system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3181system.membus.reqLayer2.occupancy 20972999 # Layer occupancy (ticks) 3182system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3183system.membus.reqLayer5.occupancy 8203462570 # Layer occupancy (ticks) 3184system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3185system.membus.respLayer2.occupancy 7924808506 # Layer occupancy (ticks) 3186system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3187system.membus.respLayer3.occupancy 230064369 # Layer occupancy (ticks) 3188system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3189system.realview.ethernet.txBytes 966 # Bytes Transmitted 3190system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3191system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3192system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3193system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3194system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3195system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3196system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3197system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3198system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3199system.realview.ethernet.totPackets 3 # Total Packets 3200system.realview.ethernet.totBytes 966 # Total Bytes 3201system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3202system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3203system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3204system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3205system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3206system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3207system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3208system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3209system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3210system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3211system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3212system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3213system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3214system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3215system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3216system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3217system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3218system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3219system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3220system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3221system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3222system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3223system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3224system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3225system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3226system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3227system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3228system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3229system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3230system.realview.ethernet.droppedPackets 0 # number of packets dropped 3231system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3232system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3233system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3234system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3235system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3236system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3237system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3238system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3239system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3240system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3241system.toL2Bus.snoop_filter.tot_requests 10304168 # Total number of requests made to the snoop filter. 3242system.toL2Bus.snoop_filter.hit_single_requests 5242935 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3243system.toL2Bus.snoop_filter.hit_multi_requests 1823032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3244system.toL2Bus.snoop_filter.tot_snoops 155703 # Total number of snoops made to the snoop filter. 3245system.toL2Bus.snoop_filter.hit_single_snoops 143721 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3246system.toL2Bus.snoop_filter.hit_multi_snoops 11982 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3247system.toL2Bus.trans_dist::ReadReq 81301 # Transaction distribution 3248system.toL2Bus.trans_dist::ReadResp 4203748 # Transaction distribution 3249system.toL2Bus.trans_dist::WriteReq 37949 # Transaction distribution 3250system.toL2Bus.trans_dist::WriteResp 37949 # Transaction distribution 3251system.toL2Bus.trans_dist::Writeback 3518592 # Transaction distribution 3252system.toL2Bus.trans_dist::CleanEvict 1268318 # Transaction distribution 3253system.toL2Bus.trans_dist::UpgradeReq 429580 # Transaction distribution 3254system.toL2Bus.trans_dist::SCUpgradeReq 333523 # Transaction distribution 3255system.toL2Bus.trans_dist::UpgradeResp 763103 # Transaction distribution 3256system.toL2Bus.trans_dist::SCUpgradeFailReq 68 # Transaction distribution 3257system.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 3258system.toL2Bus.trans_dist::ReadExReq 1086913 # Transaction distribution 3259system.toL2Bus.trans_dist::ReadExResp 1086913 # Transaction distribution 3260system.toL2Bus.trans_dist::ReadSharedReq 4129694 # Transaction distribution 3261system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3262system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7476293 # Packet count per connected master and slave (bytes) 3263system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6448186 # Packet count per connected master and slave (bytes) 3264system.toL2Bus.pkt_count::total 13924479 # Packet count per connected master and slave (bytes) 3265system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230559242 # Cumulative packet size per connected master and slave (bytes) 3266system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190965829 # Cumulative packet size per connected master and slave (bytes) 3267system.toL2Bus.pkt_size::total 421525071 # Cumulative packet size per connected master and slave (bytes) 3268system.toL2Bus.snoops 3161630 # Total snoops (count) 3269system.toL2Bus.snoop_fanout::samples 12055300 # Request fanout histogram 3270system.toL2Bus.snoop_fanout::mean 0.328437 # Request fanout histogram 3271system.toL2Bus.snoop_fanout::stdev 0.471756 # Request fanout histogram 3272system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3273system.toL2Bus.snoop_fanout::0 8107870 67.26% 67.26% # Request fanout histogram 3274system.toL2Bus.snoop_fanout::1 3935448 32.64% 99.90% # Request fanout histogram 3275system.toL2Bus.snoop_fanout::2 11982 0.10% 100.00% # Request fanout histogram 3276system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3277system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3278system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3279system.toL2Bus.snoop_fanout::total 12055300 # Request fanout histogram 3280system.toL2Bus.reqLayer0.occupancy 7945670452 # Layer occupancy (ticks) 3281system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3282system.toL2Bus.snoopLayer0.occupancy 2561165 # Layer occupancy (ticks) 3283system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3284system.toL2Bus.respLayer0.occupancy 4404072117 # Layer occupancy (ticks) 3285system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3286system.toL2Bus.respLayer1.occupancy 3899520231 # Layer occupancy (ticks) 3287system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3288 3289---------- End Simulation Statistics ---------- 3290