stats.txt revision 11103
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.456680 # Number of seconds simulated 4sim_ticks 47456679626500 # Number of ticks simulated 5final_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 503190 # Simulator instruction rate (inst/s) 8host_op_rate 591944 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27602071667 # Simulator tick rate (ticks/s) 10host_mem_usage 755208 # Number of bytes of host memory used 11host_seconds 1719.32 # Real time elapsed on the host 12sim_insts 865142471 # Number of instructions simulated 13sim_ops 1017738631 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 51904 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 48448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 2877620 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 38342664 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 11776896 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 153536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 163840 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2826616 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 16120336 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 11259712 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory 27system.physmem.bytes_read::total 84057220 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 2877620 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2826616 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 5704236 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 70891776 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 70912360 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 811 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 757 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 85370 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 599117 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 184014 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2399 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2560 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 44254 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 251893 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 175933 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1353915 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1107684 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1110258 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1094 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1021 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 60637 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 807951 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 248161 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3235 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3452 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 59562 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 339685 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 237263 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9180 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1771241 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 60637 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 59562 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 120199 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1493821 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1494255 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1493821 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1094 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1021 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 60637 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 808384 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 248161 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3235 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3452 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 59562 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 339685 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 237263 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9180 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3265496 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1353915 # Number of read requests accepted 84system.physmem.writeReqs 1110258 # Number of write requests accepted 85system.physmem.readBursts 1353915 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1110258 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 86619200 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue 89system.physmem.bytesWritten 70911104 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 84057220 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 70912360 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 220771 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 83838 # Per bank write bursts 96system.physmem.perBankRdBursts::1 89540 # Per bank write bursts 97system.physmem.perBankRdBursts::2 77326 # Per bank write bursts 98system.physmem.perBankRdBursts::3 81695 # Per bank write bursts 99system.physmem.perBankRdBursts::4 84097 # Per bank write bursts 100system.physmem.perBankRdBursts::5 94926 # Per bank write bursts 101system.physmem.perBankRdBursts::6 83322 # Per bank write bursts 102system.physmem.perBankRdBursts::7 86179 # Per bank write bursts 103system.physmem.perBankRdBursts::8 76741 # Per bank write bursts 104system.physmem.perBankRdBursts::9 125350 # Per bank write bursts 105system.physmem.perBankRdBursts::10 75788 # Per bank write bursts 106system.physmem.perBankRdBursts::11 81366 # Per bank write bursts 107system.physmem.perBankRdBursts::12 76482 # Per bank write bursts 108system.physmem.perBankRdBursts::13 81797 # Per bank write bursts 109system.physmem.perBankRdBursts::14 77630 # Per bank write bursts 110system.physmem.perBankRdBursts::15 77348 # Per bank write bursts 111system.physmem.perBankWrBursts::0 68540 # Per bank write bursts 112system.physmem.perBankWrBursts::1 72321 # Per bank write bursts 113system.physmem.perBankWrBursts::2 65671 # Per bank write bursts 114system.physmem.perBankWrBursts::3 69464 # Per bank write bursts 115system.physmem.perBankWrBursts::4 70371 # Per bank write bursts 116system.physmem.perBankWrBursts::5 77894 # Per bank write bursts 117system.physmem.perBankWrBursts::6 70312 # Per bank write bursts 118system.physmem.perBankWrBursts::7 72647 # Per bank write bursts 119system.physmem.perBankWrBursts::8 65746 # Per bank write bursts 120system.physmem.perBankWrBursts::9 72323 # Per bank write bursts 121system.physmem.perBankWrBursts::10 65450 # Per bank write bursts 122system.physmem.perBankWrBursts::11 68291 # Per bank write bursts 123system.physmem.perBankWrBursts::12 65769 # Per bank write bursts 124system.physmem.perBankWrBursts::13 69040 # Per bank write bursts 125system.physmem.perBankWrBursts::14 66651 # Per bank write bursts 126system.physmem.perBankWrBursts::15 67496 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 71 # Number of times write queue was full causing retry 129system.physmem.totGap 47456676566000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1310690 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1107684 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 1123748 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 74620 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 32556 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 27437 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 23297 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 20472 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 17890 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 14951 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 12831 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2528 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 983 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 550 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 416 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 288 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 209 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 175 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 158 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 16504 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 19352 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 48877 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 56560 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 60723 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 62814 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 63983 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 67411 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 68337 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 71503 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 71245 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 72329 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 70408 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 71228 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 74472 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 69249 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 66307 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 64601 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1352 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1011 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 616 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 534 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 469 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 470 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 437 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 403 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 372 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 344 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 308 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 386 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 390 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 345 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 285 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 247 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 283 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 156 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 109 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 115 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 100 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 238 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 850568 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 185.205557 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 113.971853 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 243.835447 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 513606 60.38% 60.38% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 167161 19.65% 80.04% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 54824 6.45% 86.48% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 28166 3.31% 89.79% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 18449 2.17% 91.96% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11525 1.35% 93.32% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 9338 1.10% 94.42% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 9545 1.12% 95.54% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 37954 4.46% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 850568 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 62842 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.536775 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 323.180031 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 62840 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 62842 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 62842 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 17.631298 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 17.120021 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 6.777595 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 59398 94.52% 94.52% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 1045 1.66% 96.18% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 473 0.75% 96.94% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 210 0.33% 97.27% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 336 0.53% 97.80% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 469 0.75% 98.55% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 106 0.17% 98.72% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 34 0.05% 98.77% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 31 0.05% 98.82% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 28 0.04% 98.87% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 37 0.06% 98.93% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 34 0.05% 98.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 449 0.71% 99.69% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 44 0.07% 99.76% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 47 0.07% 99.84% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 32 0.05% 99.89% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 9 0.01% 99.90% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::96-99 4 0.01% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::128-131 26 0.04% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::136-139 4 0.01% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 62842 # Writes before turning the bus around for reads 301system.physmem.totQLat 31787428314 # Total ticks spent queuing 302system.physmem.totMemAccLat 57164147064 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 6767125000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 23486.66 # Average queueing delay per DRAM burst 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 306system.physmem.avgMemAccLat 42236.66 # Average memory access latency per DRAM burst 307system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s 308system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 1.77 # Average system read bandwidth in MiByte/s 310system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 312system.physmem.busUtil 0.03 # Data bus utilization in percentage 313system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 315system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 24.28 # Average write queue length when enqueuing 317system.physmem.readRowHits 1086313 # Number of row buffer hits during reads 318system.physmem.writeRowHits 524528 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 80.26 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 47.34 # Row buffer hit rate for writes 321system.physmem.avgGap 19258662.67 # Average gap between requests 322system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined 323system.physmem_0.actEnergy 3335290560 # Energy for activate commands per rank (pJ) 324system.physmem_0.preEnergy 1819851000 # Energy for precharge commands per rank (pJ) 325system.physmem_0.readEnergy 5311160400 # Energy for read commands per rank (pJ) 326system.physmem_0.writeEnergy 3675585600 # Energy for write commands per rank (pJ) 327system.physmem_0.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) 328system.physmem_0.actBackEnergy 1204726391325 # Energy for active background per rank (pJ) 329system.physmem_0.preBackEnergy 27417225862500 # Energy for precharge background per rank (pJ) 330system.physmem_0.totalEnergy 31735733267865 # Total energy per rank (pJ) 331system.physmem_0.averagePower 668.730691 # Core power per rank (mW) 332system.physmem_0.memoryStateTime::IDLE 45610216470982 # Time in different power states 333system.physmem_0.memoryStateTime::REF 1584682580000 # Time in different power states 334system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 335system.physmem_0.memoryStateTime::ACT 261780130518 # Time in different power states 336system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 337system.physmem_1.actEnergy 3095003520 # Energy for activate commands per rank (pJ) 338system.physmem_1.preEnergy 1688742000 # Energy for precharge commands per rank (pJ) 339system.physmem_1.readEnergy 5245507800 # Energy for read commands per rank (pJ) 340system.physmem_1.writeEnergy 3504163680 # Energy for write commands per rank (pJ) 341system.physmem_1.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) 342system.physmem_1.actBackEnergy 1191482148060 # Energy for active background per rank (pJ) 343system.physmem_1.preBackEnergy 27428843611500 # Energy for precharge background per rank (pJ) 344system.physmem_1.totalEnergy 31733498303040 # Total energy per rank (pJ) 345system.physmem_1.averagePower 668.683596 # Core power per rank (mW) 346system.physmem_1.memoryStateTime::IDLE 45629577337540 # Time in different power states 347system.physmem_1.memoryStateTime::REF 1584682580000 # Time in different power states 348system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 349system.physmem_1.memoryStateTime::ACT 242414504460 # Time in different power states 350system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 351system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 356system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 357system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 358system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 359system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 364system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 377system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 378system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 379system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 380system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 381system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 382system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 393system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 394system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 395system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 396system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 397system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 408system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 409system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 410system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 411system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 412system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 413system.cpu0.dtb.walker.walks 105954 # Table walker walks requested 414system.cpu0.dtb.walker.walksLong 105954 # Table walker walks initiated with long descriptors 415system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10115 # Level at which table walker walks with long descriptors terminate 416system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80576 # Level at which table walker walks with long descriptors terminate 417system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting 418system.cpu0.dtb.walker.walkWaitTime::samples 105928 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::mean 0.169927 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::stdev 55.305347 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0-2047 105927 100.00% 100.00% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::total 105928 # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::0-32767 87482 96.43% 96.43% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2786 3.07% 99.51% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::65536-98303 233 0.26% 99.76% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::98304-131071 145 0.16% 99.92% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::131072-163839 15 0.02% 99.94% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::163840-196607 6 0.01% 99.94% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::196608-229375 19 0.02% 99.97% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::262144-294911 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walksPending::samples 9139568088 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::mean 1.172115 # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::0 -1573058396 -17.21% -17.21% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::1 10712626484 117.21% 100.00% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::total 9139568088 # Table walker pending requests distribution 447system.cpu0.dtb.walker.walkPageSizes::4K 80577 88.85% 88.85% # Table walker page sizes translated 448system.cpu0.dtb.walker.walkPageSizes::2M 10115 11.15% 100.00% # Table walker page sizes translated 449system.cpu0.dtb.walker.walkPageSizes::total 90692 # Table walker page sizes translated 450system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105954 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105954 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90692 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90692 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin::total 196646 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.inst_hits 0 # ITB inst hits 458system.cpu0.dtb.inst_misses 0 # ITB inst misses 459system.cpu0.dtb.read_hits 80457124 # DTB read hits 460system.cpu0.dtb.read_misses 79863 # DTB read misses 461system.cpu0.dtb.write_hits 72637408 # DTB write hits 462system.cpu0.dtb.write_misses 26091 # DTB write misses 463system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 464system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 465system.cpu0.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 466system.cpu0.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 467system.cpu0.dtb.flush_entries 34410 # Number of entries that have been flushed from TLB 468system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 469system.cpu0.dtb.prefetch_faults 3731 # Number of TLB faults due to prefetch 470system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 471system.cpu0.dtb.perms_faults 8741 # Number of TLB faults due to permissions restrictions 472system.cpu0.dtb.read_accesses 80536987 # DTB read accesses 473system.cpu0.dtb.write_accesses 72663499 # DTB write accesses 474system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 475system.cpu0.dtb.hits 153094532 # DTB hits 476system.cpu0.dtb.misses 105954 # DTB misses 477system.cpu0.dtb.accesses 153200486 # DTB accesses 478system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 487system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 488system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 489system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 490system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 491system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 493system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 494system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 496system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 497system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 498system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 499system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 500system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 501system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 502system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 503system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 504system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 505system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 506system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 507system.cpu0.itb.walker.walks 53482 # Table walker walks requested 508system.cpu0.itb.walker.walksLong 53482 # Table walker walks initiated with long descriptors 509system.cpu0.itb.walker.walksLongTerminationLevel::Level2 578 # Level at which table walker walks with long descriptors terminate 510system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47523 # Level at which table walker walks with long descriptors terminate 511system.cpu0.itb.walker.walkWaitTime::samples 53482 # Table walker wait (enqueue to first request) latency 512system.cpu0.itb.walker.walkWaitTime::0 53482 100.00% 100.00% # Table walker wait (enqueue to first request) latency 513system.cpu0.itb.walker.walkWaitTime::total 53482 # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkCompletionTime::samples 48101 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392 # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685 # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::0-32767 45094 93.75% 93.75% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::32768-65535 2542 5.28% 99.03% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::65536-98303 133 0.28% 99.31% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::98304-131071 277 0.58% 99.89% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::131072-163839 5 0.01% 99.90% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::163840-196607 6 0.01% 99.91% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::196608-229375 18 0.04% 99.95% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::229376-262143 2 0.00% 99.95% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.98% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::total 48101 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution 534system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution 535system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution 536system.cpu0.itb.walker.walkPageSizes::4K 47523 98.80% 98.80% # Table walker page sizes translated 537system.cpu0.itb.walker.walkPageSizes::2M 578 1.20% 100.00% # Table walker page sizes translated 538system.cpu0.itb.walker.walkPageSizes::total 48101 # Table walker page sizes translated 539system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53482 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53482 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48101 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48101 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin::total 101583 # Table walker requests started/completed, data/inst 546system.cpu0.itb.inst_hits 428491503 # ITB inst hits 547system.cpu0.itb.inst_misses 53482 # ITB inst misses 548system.cpu0.itb.read_hits 0 # DTB read hits 549system.cpu0.itb.read_misses 0 # DTB read misses 550system.cpu0.itb.write_hits 0 # DTB write hits 551system.cpu0.itb.write_misses 0 # DTB write misses 552system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 553system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 554system.cpu0.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 555system.cpu0.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 556system.cpu0.itb.flush_entries 24315 # Number of entries that have been flushed from TLB 557system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 558system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 559system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 560system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 561system.cpu0.itb.read_accesses 0 # DTB read accesses 562system.cpu0.itb.write_accesses 0 # DTB write accesses 563system.cpu0.itb.inst_accesses 428544985 # ITB inst accesses 564system.cpu0.itb.hits 428491503 # DTB hits 565system.cpu0.itb.misses 53482 # DTB misses 566system.cpu0.itb.accesses 428544985 # DTB accesses 567system.cpu0.numCycles 94913359253 # number of cpu cycles simulated 568system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 569system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 570system.cpu0.committedInsts 428232691 # Number of instructions committed 571system.cpu0.committedOps 502476550 # Number of ops (including micro ops) committed 572system.cpu0.num_int_alu_accesses 461534262 # Number of integer alu accesses 573system.cpu0.num_fp_alu_accesses 406829 # Number of float alu accesses 574system.cpu0.num_func_calls 25466680 # number of times a function call or return occured 575system.cpu0.num_conditional_control_insts 64818437 # number of instructions that are conditional controls 576system.cpu0.num_int_insts 461534262 # number of integer instructions 577system.cpu0.num_fp_insts 406829 # number of float instructions 578system.cpu0.num_int_register_reads 668961319 # number of times the integer registers were read 579system.cpu0.num_int_register_writes 366250009 # number of times the integer registers were written 580system.cpu0.num_fp_register_reads 674435 # number of times the floating registers were read 581system.cpu0.num_fp_register_writes 305880 # number of times the floating registers were written 582system.cpu0.num_cc_register_reads 111832425 # number of times the CC registers were read 583system.cpu0.num_cc_register_writes 111484776 # number of times the CC registers were written 584system.cpu0.num_mem_refs 153083738 # number of memory refs 585system.cpu0.num_load_insts 80450777 # Number of load instructions 586system.cpu0.num_store_insts 72632961 # Number of store instructions 587system.cpu0.num_idle_cycles 93826651579.898026 # Number of idle cycles 588system.cpu0.num_busy_cycles 1086707673.101977 # Number of busy cycles 589system.cpu0.not_idle_fraction 0.011449 # Percentage of non-idle cycles 590system.cpu0.idle_fraction 0.988551 # Percentage of idle cycles 591system.cpu0.Branches 95423987 # Number of branches fetched 592system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 593system.cpu0.op_class::IntAlu 348470598 69.31% 69.31% # Class of executed instruction 594system.cpu0.op_class::IntMult 1120076 0.22% 69.53% # Class of executed instruction 595system.cpu0.op_class::IntDiv 60052 0.01% 69.54% # Class of executed instruction 596system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 597system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 598system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 599system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 600system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 601system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 602system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 603system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 604system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 605system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 606system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 607system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 608system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 609system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 610system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 611system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 612system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 613system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 614system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 615system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 616system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 617system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 618system.cpu0.op_class::SimdFloatMisc 44021 0.01% 69.55% # Class of executed instruction 619system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 620system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 621system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 622system.cpu0.op_class::MemRead 80450777 16.00% 85.55% # Class of executed instruction 623system.cpu0.op_class::MemWrite 72632961 14.45% 100.00% # Class of executed instruction 624system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 625system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 626system.cpu0.op_class::total 502778486 # Class of executed instruction 627system.cpu0.kern.inst.arm 0 # number of arm instructions executed 628system.cpu0.kern.inst.quiesce 15090 # number of quiesce instructions executed 629system.cpu0.dcache.tags.replacements 5233253 # number of replacements 630system.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use 631system.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks. 632system.cpu0.dcache.tags.sampled_refs 5233765 # Sample count of references to valid blocks. 633system.cpu0.dcache.tags.avg_refs 28.202863 # Average number of references to valid blocks. 634system.cpu0.dcache.tags.warmup_cycle 3987157000 # Cycle when the warmup percentage was hit. 635system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.798924 # Average occupied blocks per requestor 636system.cpu0.dcache.tags.occ_percent::cpu0.data 0.939060 # Average percentage of cache occupancy 637system.cpu0.dcache.tags.occ_percent::total 0.939060 # Average percentage of cache occupancy 638system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 639system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 640system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 641system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 642system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 643system.cpu0.dcache.tags.tag_accesses 311404737 # Number of tag accesses 644system.cpu0.dcache.tags.data_accesses 311404737 # Number of data accesses 645system.cpu0.dcache.ReadReq_hits::cpu0.data 74943991 # number of ReadReq hits 646system.cpu0.dcache.ReadReq_hits::total 74943991 # number of ReadReq hits 647system.cpu0.dcache.WriteReq_hits::cpu0.data 68564818 # number of WriteReq hits 648system.cpu0.dcache.WriteReq_hits::total 68564818 # number of WriteReq hits 649system.cpu0.dcache.SoftPFReq_hits::cpu0.data 176894 # number of SoftPFReq hits 650system.cpu0.dcache.SoftPFReq_hits::total 176894 # number of SoftPFReq hits 651system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135340 # number of WriteLineReq hits 652system.cpu0.dcache.WriteLineReq_hits::total 135340 # number of WriteLineReq hits 653system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1719391 # number of LoadLockedReq hits 654system.cpu0.dcache.LoadLockedReq_hits::total 1719391 # number of LoadLockedReq hits 655system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1677698 # number of StoreCondReq hits 656system.cpu0.dcache.StoreCondReq_hits::total 1677698 # number of StoreCondReq hits 657system.cpu0.dcache.demand_hits::cpu0.data 143508809 # number of demand (read+write) hits 658system.cpu0.dcache.demand_hits::total 143508809 # number of demand (read+write) hits 659system.cpu0.dcache.overall_hits::cpu0.data 143685703 # number of overall hits 660system.cpu0.dcache.overall_hits::total 143685703 # number of overall hits 661system.cpu0.dcache.ReadReq_misses::cpu0.data 2840159 # number of ReadReq misses 662system.cpu0.dcache.ReadReq_misses::total 2840159 # number of ReadReq misses 663system.cpu0.dcache.WriteReq_misses::cpu0.data 1279764 # number of WriteReq misses 664system.cpu0.dcache.WriteReq_misses::total 1279764 # number of WriteReq misses 665system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601589 # number of SoftPFReq misses 666system.cpu0.dcache.SoftPFReq_misses::total 601589 # number of SoftPFReq misses 667system.cpu0.dcache.WriteLineReq_misses::cpu0.data 758772 # number of WriteLineReq misses 668system.cpu0.dcache.WriteLineReq_misses::total 758772 # number of WriteLineReq misses 669system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148889 # number of LoadLockedReq misses 670system.cpu0.dcache.LoadLockedReq_misses::total 148889 # number of LoadLockedReq misses 671system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188945 # number of StoreCondReq misses 672system.cpu0.dcache.StoreCondReq_misses::total 188945 # number of StoreCondReq misses 673system.cpu0.dcache.demand_misses::cpu0.data 4119923 # number of demand (read+write) misses 674system.cpu0.dcache.demand_misses::total 4119923 # number of demand (read+write) misses 675system.cpu0.dcache.overall_misses::cpu0.data 4721512 # number of overall misses 676system.cpu0.dcache.overall_misses::total 4721512 # number of overall misses 677system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41012776500 # number of ReadReq miss cycles 678system.cpu0.dcache.ReadReq_miss_latency::total 41012776500 # number of ReadReq miss cycles 679system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24489617000 # number of WriteReq miss cycles 680system.cpu0.dcache.WriteReq_miss_latency::total 24489617000 # number of WriteReq miss cycles 681system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46337666000 # number of WriteLineReq miss cycles 682system.cpu0.dcache.WriteLineReq_miss_latency::total 46337666000 # number of WriteLineReq miss cycles 683system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2203666500 # number of LoadLockedReq miss cycles 684system.cpu0.dcache.LoadLockedReq_miss_latency::total 2203666500 # number of LoadLockedReq miss cycles 685system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4074419000 # number of StoreCondReq miss cycles 686system.cpu0.dcache.StoreCondReq_miss_latency::total 4074419000 # number of StoreCondReq miss cycles 687system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2847000 # number of StoreCondFailReq miss cycles 688system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2847000 # number of StoreCondFailReq miss cycles 689system.cpu0.dcache.demand_miss_latency::cpu0.data 65502393500 # number of demand (read+write) miss cycles 690system.cpu0.dcache.demand_miss_latency::total 65502393500 # number of demand (read+write) miss cycles 691system.cpu0.dcache.overall_miss_latency::cpu0.data 65502393500 # number of overall miss cycles 692system.cpu0.dcache.overall_miss_latency::total 65502393500 # number of overall miss cycles 693system.cpu0.dcache.ReadReq_accesses::cpu0.data 77784150 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.ReadReq_accesses::total 77784150 # number of ReadReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::cpu0.data 69844582 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.WriteReq_accesses::total 69844582 # number of WriteReq accesses(hits+misses) 697system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 778483 # number of SoftPFReq accesses(hits+misses) 698system.cpu0.dcache.SoftPFReq_accesses::total 778483 # number of SoftPFReq accesses(hits+misses) 699system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894112 # number of WriteLineReq accesses(hits+misses) 700system.cpu0.dcache.WriteLineReq_accesses::total 894112 # number of WriteLineReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1868280 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::total 1868280 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1866643 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::total 1866643 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.demand_accesses::cpu0.data 147628732 # number of demand (read+write) accesses 706system.cpu0.dcache.demand_accesses::total 147628732 # number of demand (read+write) accesses 707system.cpu0.dcache.overall_accesses::cpu0.data 148407215 # number of overall (read+write) accesses 708system.cpu0.dcache.overall_accesses::total 148407215 # number of overall (read+write) accesses 709system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036513 # miss rate for ReadReq accesses 710system.cpu0.dcache.ReadReq_miss_rate::total 0.036513 # miss rate for ReadReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018323 # miss rate for WriteReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::total 0.018323 # miss rate for WriteReq accesses 713system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772771 # miss rate for SoftPFReq accesses 714system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772771 # miss rate for SoftPFReq accesses 715system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.848632 # miss rate for WriteLineReq accesses 716system.cpu0.dcache.WriteLineReq_miss_rate::total 0.848632 # miss rate for WriteLineReq accesses 717system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079693 # miss rate for LoadLockedReq accesses 718system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079693 # miss rate for LoadLockedReq accesses 719system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101222 # miss rate for StoreCondReq accesses 720system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101222 # miss rate for StoreCondReq accesses 721system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027907 # miss rate for demand accesses 722system.cpu0.dcache.demand_miss_rate::total 0.027907 # miss rate for demand accesses 723system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses 724system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses 725system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14440.310032 # average ReadReq miss latency 726system.cpu0.dcache.ReadReq_avg_miss_latency::total 14440.310032 # average ReadReq miss latency 727system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19136.041489 # average WriteReq miss latency 728system.cpu0.dcache.WriteReq_avg_miss_latency::total 19136.041489 # average WriteReq miss latency 729system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61069.288271 # average WriteLineReq miss latency 730system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61069.288271 # average WriteLineReq miss latency 731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14800.734104 # average LoadLockedReq miss latency 732system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14800.734104 # average LoadLockedReq miss latency 733system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21564.047739 # average StoreCondReq miss latency 734system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21564.047739 # average StoreCondReq miss latency 735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 736system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 737system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339 # average overall miss latency 738system.cpu0.dcache.demand_avg_miss_latency::total 15898.936339 # average overall miss latency 739system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621 # average overall miss latency 740system.cpu0.dcache.overall_avg_miss_latency::total 13873.181621 # average overall miss latency 741system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu0.dcache.fast_writes 0 # number of fast writes performed 748system.cpu0.dcache.cache_copies 0 # number of cache copies performed 749system.cpu0.dcache.writebacks::writebacks 3560219 # number of writebacks 750system.cpu0.dcache.writebacks::total 3560219 # number of writebacks 751system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30162 # number of ReadReq MSHR hits 752system.cpu0.dcache.ReadReq_mshr_hits::total 30162 # number of ReadReq MSHR hits 753system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21215 # number of WriteReq MSHR hits 754system.cpu0.dcache.WriteReq_mshr_hits::total 21215 # number of WriteReq MSHR hits 755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39917 # number of LoadLockedReq MSHR hits 756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39917 # number of LoadLockedReq MSHR hits 757system.cpu0.dcache.demand_mshr_hits::cpu0.data 51377 # number of demand (read+write) MSHR hits 758system.cpu0.dcache.demand_mshr_hits::total 51377 # number of demand (read+write) MSHR hits 759system.cpu0.dcache.overall_mshr_hits::cpu0.data 51377 # number of overall MSHR hits 760system.cpu0.dcache.overall_mshr_hits::total 51377 # number of overall MSHR hits 761system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2809997 # number of ReadReq MSHR misses 762system.cpu0.dcache.ReadReq_mshr_misses::total 2809997 # number of ReadReq MSHR misses 763system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1258549 # number of WriteReq MSHR misses 764system.cpu0.dcache.WriteReq_mshr_misses::total 1258549 # number of WriteReq MSHR misses 765system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595949 # number of SoftPFReq MSHR misses 766system.cpu0.dcache.SoftPFReq_mshr_misses::total 595949 # number of SoftPFReq MSHR misses 767system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 758772 # number of WriteLineReq MSHR misses 768system.cpu0.dcache.WriteLineReq_mshr_misses::total 758772 # number of WriteLineReq MSHR misses 769system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108972 # number of LoadLockedReq MSHR misses 770system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108972 # number of LoadLockedReq MSHR misses 771system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188945 # number of StoreCondReq MSHR misses 772system.cpu0.dcache.StoreCondReq_mshr_misses::total 188945 # number of StoreCondReq MSHR misses 773system.cpu0.dcache.demand_mshr_misses::cpu0.data 4068546 # number of demand (read+write) MSHR misses 774system.cpu0.dcache.demand_mshr_misses::total 4068546 # number of demand (read+write) MSHR misses 775system.cpu0.dcache.overall_mshr_misses::cpu0.data 4664495 # number of overall MSHR misses 776system.cpu0.dcache.overall_mshr_misses::total 4664495 # number of overall MSHR misses 777system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable 778system.cpu0.dcache.ReadReq_mshr_uncacheable::total 26231 # number of ReadReq MSHR uncacheable 779system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable 780system.cpu0.dcache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable 781system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses 782system.cpu0.dcache.overall_mshr_uncacheable_misses::total 51684 # number of overall MSHR uncacheable misses 783system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36991828000 # number of ReadReq MSHR miss cycles 784system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36991828000 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22707525500 # number of WriteReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22707525500 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12844611500 # number of SoftPFReq MSHR miss cycles 788system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12844611500 # number of SoftPFReq MSHR miss cycles 789system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45578894000 # number of WriteLineReq MSHR miss cycles 790system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45578894000 # number of WriteLineReq MSHR miss cycles 791system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1445565000 # number of LoadLockedReq MSHR miss cycles 792system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1445565000 # number of LoadLockedReq MSHR miss cycles 793system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3885534000 # number of StoreCondReq MSHR miss cycles 794system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3885534000 # number of StoreCondReq MSHR miss cycles 795system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2787000 # number of StoreCondFailReq MSHR miss cycles 796system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2787000 # number of StoreCondFailReq MSHR miss cycles 797system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 59699353500 # number of demand (read+write) MSHR miss cycles 798system.cpu0.dcache.demand_mshr_miss_latency::total 59699353500 # number of demand (read+write) MSHR miss cycles 799system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 72543965000 # number of overall MSHR miss cycles 800system.cpu0.dcache.overall_mshr_miss_latency::total 72543965000 # number of overall MSHR miss cycles 801system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4455810500 # number of ReadReq MSHR uncacheable cycles 802system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4455810500 # number of ReadReq MSHR uncacheable cycles 803system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4073355500 # number of WriteReq MSHR uncacheable cycles 804system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4073355500 # number of WriteReq MSHR uncacheable cycles 805system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8529166000 # number of overall MSHR uncacheable cycles 806system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8529166000 # number of overall MSHR uncacheable cycles 807system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036126 # mshr miss rate for ReadReq accesses 808system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses 809system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018019 # mshr miss rate for WriteReq accesses 810system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses 811system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765526 # mshr miss rate for SoftPFReq accesses 812system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765526 # mshr miss rate for SoftPFReq accesses 813system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.848632 # mshr miss rate for WriteLineReq accesses 814system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.848632 # mshr miss rate for WriteLineReq accesses 815system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058327 # mshr miss rate for LoadLockedReq accesses 816system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058327 # mshr miss rate for LoadLockedReq accesses 817system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101222 # mshr miss rate for StoreCondReq accesses 818system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101222 # mshr miss rate for StoreCondReq accesses 819system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027559 # mshr miss rate for demand accesses 820system.cpu0.dcache.demand_mshr_miss_rate::total 0.027559 # mshr miss rate for demand accesses 821system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031430 # mshr miss rate for overall accesses 822system.cpu0.dcache.overall_mshr_miss_rate::total 0.031430 # mshr miss rate for overall accesses 823system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656 # average ReadReq mshr miss latency 824system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656 # average ReadReq mshr miss latency 825system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291 # average WriteReq mshr miss latency 826system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291 # average WriteReq mshr miss latency 827system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895 # average SoftPFReq mshr miss latency 828system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895 # average SoftPFReq mshr miss latency 829system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271 # average WriteLineReq mshr miss latency 830system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271 # average WriteLineReq mshr miss latency 831system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864 # average LoadLockedReq mshr miss latency 832system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864 # average LoadLockedReq mshr miss latency 833system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291 # average StoreCondReq mshr miss latency 834system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291 # average StoreCondReq mshr miss latency 835system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 836system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 837system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864 # average overall mshr miss latency 838system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864 # average overall mshr miss latency 839system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765 # average overall mshr miss latency 840system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765 # average overall mshr miss latency 841system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064 # average ReadReq mshr uncacheable latency 842system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064 # average ReadReq mshr uncacheable latency 843system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731 # average WriteReq mshr uncacheable latency 844system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731 # average WriteReq mshr uncacheable latency 845system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942 # average overall mshr uncacheable latency 846system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942 # average overall mshr uncacheable latency 847system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 848system.cpu0.icache.tags.replacements 4666970 # number of replacements 849system.cpu0.icache.tags.tagsinuse 511.880807 # Cycle average of tags in use 850system.cpu0.icache.tags.total_refs 423824020 # Total number of references to valid blocks. 851system.cpu0.icache.tags.sampled_refs 4667482 # Sample count of references to valid blocks. 852system.cpu0.icache.tags.avg_refs 90.803568 # Average number of references to valid blocks. 853system.cpu0.icache.tags.warmup_cycle 42558943000 # Cycle when the warmup percentage was hit. 854system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.880807 # Average occupied blocks per requestor 855system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999767 # Average percentage of cache occupancy 856system.cpu0.icache.tags.occ_percent::total 0.999767 # Average percentage of cache occupancy 857system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 858system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 859system.cpu0.icache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 860system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id 861system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 862system.cpu0.icache.tags.tag_accesses 861650489 # Number of tag accesses 863system.cpu0.icache.tags.data_accesses 861650489 # Number of data accesses 864system.cpu0.icache.ReadReq_hits::cpu0.inst 423824020 # number of ReadReq hits 865system.cpu0.icache.ReadReq_hits::total 423824020 # number of ReadReq hits 866system.cpu0.icache.demand_hits::cpu0.inst 423824020 # number of demand (read+write) hits 867system.cpu0.icache.demand_hits::total 423824020 # number of demand (read+write) hits 868system.cpu0.icache.overall_hits::cpu0.inst 423824020 # number of overall hits 869system.cpu0.icache.overall_hits::total 423824020 # number of overall hits 870system.cpu0.icache.ReadReq_misses::cpu0.inst 4667483 # number of ReadReq misses 871system.cpu0.icache.ReadReq_misses::total 4667483 # number of ReadReq misses 872system.cpu0.icache.demand_misses::cpu0.inst 4667483 # number of demand (read+write) misses 873system.cpu0.icache.demand_misses::total 4667483 # number of demand (read+write) misses 874system.cpu0.icache.overall_misses::cpu0.inst 4667483 # number of overall misses 875system.cpu0.icache.overall_misses::total 4667483 # number of overall misses 876system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48694088500 # number of ReadReq miss cycles 877system.cpu0.icache.ReadReq_miss_latency::total 48694088500 # number of ReadReq miss cycles 878system.cpu0.icache.demand_miss_latency::cpu0.inst 48694088500 # number of demand (read+write) miss cycles 879system.cpu0.icache.demand_miss_latency::total 48694088500 # number of demand (read+write) miss cycles 880system.cpu0.icache.overall_miss_latency::cpu0.inst 48694088500 # number of overall miss cycles 881system.cpu0.icache.overall_miss_latency::total 48694088500 # number of overall miss cycles 882system.cpu0.icache.ReadReq_accesses::cpu0.inst 428491503 # number of ReadReq accesses(hits+misses) 883system.cpu0.icache.ReadReq_accesses::total 428491503 # number of ReadReq accesses(hits+misses) 884system.cpu0.icache.demand_accesses::cpu0.inst 428491503 # number of demand (read+write) accesses 885system.cpu0.icache.demand_accesses::total 428491503 # number of demand (read+write) accesses 886system.cpu0.icache.overall_accesses::cpu0.inst 428491503 # number of overall (read+write) accesses 887system.cpu0.icache.overall_accesses::total 428491503 # number of overall (read+write) accesses 888system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010893 # miss rate for ReadReq accesses 889system.cpu0.icache.ReadReq_miss_rate::total 0.010893 # miss rate for ReadReq accesses 890system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010893 # miss rate for demand accesses 891system.cpu0.icache.demand_miss_rate::total 0.010893 # miss rate for demand accesses 892system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010893 # miss rate for overall accesses 893system.cpu0.icache.overall_miss_rate::total 0.010893 # miss rate for overall accesses 894system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572 # average ReadReq miss latency 895system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572 # average ReadReq miss latency 896system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency 897system.cpu0.icache.demand_avg_miss_latency::total 10432.622572 # average overall miss latency 898system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency 899system.cpu0.icache.overall_avg_miss_latency::total 10432.622572 # average overall miss latency 900system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 901system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 903system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 905system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu0.icache.fast_writes 0 # number of fast writes performed 907system.cpu0.icache.cache_copies 0 # number of cache copies performed 908system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4667483 # number of ReadReq MSHR misses 909system.cpu0.icache.ReadReq_mshr_misses::total 4667483 # number of ReadReq MSHR misses 910system.cpu0.icache.demand_mshr_misses::cpu0.inst 4667483 # number of demand (read+write) MSHR misses 911system.cpu0.icache.demand_mshr_misses::total 4667483 # number of demand (read+write) MSHR misses 912system.cpu0.icache.overall_mshr_misses::cpu0.inst 4667483 # number of overall MSHR misses 913system.cpu0.icache.overall_mshr_misses::total 4667483 # number of overall MSHR misses 914system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 915system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 916system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 917system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 918system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 46360347000 # number of ReadReq MSHR miss cycles 919system.cpu0.icache.ReadReq_mshr_miss_latency::total 46360347000 # number of ReadReq MSHR miss cycles 920system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 46360347000 # number of demand (read+write) MSHR miss cycles 921system.cpu0.icache.demand_mshr_miss_latency::total 46360347000 # number of demand (read+write) MSHR miss cycles 922system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 46360347000 # number of overall MSHR miss cycles 923system.cpu0.icache.overall_mshr_miss_latency::total 46360347000 # number of overall MSHR miss cycles 924system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles 925system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles 926system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles 927system.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles 928system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for ReadReq accesses 929system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010893 # mshr miss rate for ReadReq accesses 930system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for demand accesses 931system.cpu0.icache.demand_mshr_miss_rate::total 0.010893 # mshr miss rate for demand accesses 932system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for overall accesses 933system.cpu0.icache.overall_mshr_miss_rate::total 0.010893 # mshr miss rate for overall accesses 934system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average ReadReq mshr miss latency 935system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.622572 # average ReadReq mshr miss latency 936system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency 937system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency 938system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency 939system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency 940system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency 941system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency 942system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency 943system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency 944system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 945system.cpu0.l2cache.prefetcher.num_hwpf_issued 7039817 # number of hwpf issued 946system.cpu0.l2cache.prefetcher.pfIdentified 7039817 # number of prefetch candidates identified 947system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 948system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 949system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 950system.cpu0.l2cache.prefetcher.pfSpanPage 925071 # number of prefetches not generated due to page crossing 951system.cpu0.l2cache.tags.replacements 2212798 # number of replacements 952system.cpu0.l2cache.tags.tagsinuse 16140.904175 # Cycle average of tags in use 953system.cpu0.l2cache.tags.total_refs 16304400 # Total number of references to valid blocks. 954system.cpu0.l2cache.tags.sampled_refs 2228972 # Sample count of references to valid blocks. 955system.cpu0.l2cache.tags.avg_refs 7.314762 # Average number of references to valid blocks. 956system.cpu0.l2cache.tags.warmup_cycle 38965596000 # Cycle when the warmup percentage was hit. 957system.cpu0.l2cache.tags.occ_blocks::writebacks 7022.512638 # Average occupied blocks per requestor 958system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.899316 # Average occupied blocks per requestor 959system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.792978 # Average occupied blocks per requestor 960system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3705.081021 # Average occupied blocks per requestor 961system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4185.062005 # Average occupied blocks per requestor 962system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1103.556217 # Average occupied blocks per requestor 963system.cpu0.l2cache.tags.occ_percent::writebacks 0.428620 # Average percentage of cache occupancy 964system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy 965system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003833 # Average percentage of cache occupancy 966system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226140 # Average percentage of cache occupancy 967system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.255436 # Average percentage of cache occupancy 968system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.067356 # Average percentage of cache occupancy 969system.cpu0.l2cache.tags.occ_percent::total 0.985163 # Average percentage of cache occupancy 970system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1459 # Occupied blocks per task id 971system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id 972system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 603 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id 977system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id 978system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id 979system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 980system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 981system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 957 # Occupied blocks per task id 982system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4495 # Occupied blocks per task id 983system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id 984system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id 985system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089050 # Percentage of cache occupancy per task id 986system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 987system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id 988system.cpu0.l2cache.tags.tag_accesses 335472623 # Number of tag accesses 989system.cpu0.l2cache.tags.data_accesses 335472623 # Number of data accesses 990system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224520 # number of ReadReq hits 991system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122258 # number of ReadReq hits 992system.cpu0.l2cache.ReadReq_hits::total 346778 # number of ReadReq hits 993system.cpu0.l2cache.Writeback_hits::writebacks 3560218 # number of Writeback hits 994system.cpu0.l2cache.Writeback_hits::total 3560218 # number of Writeback hits 995system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 92512 # number of UpgradeReq hits 996system.cpu0.l2cache.UpgradeReq_hits::total 92512 # number of UpgradeReq hits 997system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 28864 # number of SCUpgradeReq hits 998system.cpu0.l2cache.SCUpgradeReq_hits::total 28864 # number of SCUpgradeReq hits 999system.cpu0.l2cache.ReadExReq_hits::cpu0.data 829198 # number of ReadExReq hits 1000system.cpu0.l2cache.ReadExReq_hits::total 829198 # number of ReadExReq hits 1001system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4185639 # number of ReadCleanReq hits 1002system.cpu0.l2cache.ReadCleanReq_hits::total 4185639 # number of ReadCleanReq hits 1003system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2620915 # number of ReadSharedReq hits 1004system.cpu0.l2cache.ReadSharedReq_hits::total 2620915 # number of ReadSharedReq hits 1005system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 197417 # number of InvalidateReq hits 1006system.cpu0.l2cache.InvalidateReq_hits::total 197417 # number of InvalidateReq hits 1007system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224520 # number of demand (read+write) hits 1008system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122258 # number of demand (read+write) hits 1009system.cpu0.l2cache.demand_hits::cpu0.inst 4185639 # number of demand (read+write) hits 1010system.cpu0.l2cache.demand_hits::cpu0.data 3450113 # number of demand (read+write) hits 1011system.cpu0.l2cache.demand_hits::total 7982530 # number of demand (read+write) hits 1012system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224520 # number of overall hits 1013system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122258 # number of overall hits 1014system.cpu0.l2cache.overall_hits::cpu0.inst 4185639 # number of overall hits 1015system.cpu0.l2cache.overall_hits::cpu0.data 3450113 # number of overall hits 1016system.cpu0.l2cache.overall_hits::total 7982530 # number of overall hits 1017system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8873 # number of ReadReq misses 1018system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6826 # number of ReadReq misses 1019system.cpu0.l2cache.ReadReq_misses::total 15699 # number of ReadReq misses 1020system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 123328 # number of UpgradeReq misses 1021system.cpu0.l2cache.UpgradeReq_misses::total 123328 # number of UpgradeReq misses 1022system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160077 # number of SCUpgradeReq misses 1023system.cpu0.l2cache.SCUpgradeReq_misses::total 160077 # number of SCUpgradeReq misses 1024system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1025system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1026system.cpu0.l2cache.ReadExReq_misses::cpu0.data 230435 # number of ReadExReq misses 1027system.cpu0.l2cache.ReadExReq_misses::total 230435 # number of ReadExReq misses 1028system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 481844 # number of ReadCleanReq misses 1029system.cpu0.l2cache.ReadCleanReq_misses::total 481844 # number of ReadCleanReq misses 1030system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 894003 # number of ReadSharedReq misses 1031system.cpu0.l2cache.ReadSharedReq_misses::total 894003 # number of ReadSharedReq misses 1032system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 560192 # number of InvalidateReq misses 1033system.cpu0.l2cache.InvalidateReq_misses::total 560192 # number of InvalidateReq misses 1034system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8873 # number of demand (read+write) misses 1035system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6826 # number of demand (read+write) misses 1036system.cpu0.l2cache.demand_misses::cpu0.inst 481844 # number of demand (read+write) misses 1037system.cpu0.l2cache.demand_misses::cpu0.data 1124438 # number of demand (read+write) misses 1038system.cpu0.l2cache.demand_misses::total 1621981 # number of demand (read+write) misses 1039system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8873 # number of overall misses 1040system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6826 # number of overall misses 1041system.cpu0.l2cache.overall_misses::cpu0.inst 481844 # number of overall misses 1042system.cpu0.l2cache.overall_misses::cpu0.data 1124438 # number of overall misses 1043system.cpu0.l2cache.overall_misses::total 1621981 # number of overall misses 1044system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 259670000 # number of ReadReq miss cycles 1045system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 210027000 # number of ReadReq miss cycles 1046system.cpu0.l2cache.ReadReq_miss_latency::total 469697000 # number of ReadReq miss cycles 1047system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2651049500 # number of UpgradeReq miss cycles 1048system.cpu0.l2cache.UpgradeReq_miss_latency::total 2651049500 # number of UpgradeReq miss cycles 1049system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3319563500 # number of SCUpgradeReq miss cycles 1050system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3319563500 # number of SCUpgradeReq miss cycles 1051system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2697000 # number of SCUpgradeFailReq miss cycles 1052system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2697000 # number of SCUpgradeFailReq miss cycles 1053system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11221935999 # number of ReadExReq miss cycles 1054system.cpu0.l2cache.ReadExReq_miss_latency::total 11221935999 # number of ReadExReq miss cycles 1055system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 14420808000 # number of ReadCleanReq miss cycles 1056system.cpu0.l2cache.ReadCleanReq_miss_latency::total 14420808000 # number of ReadCleanReq miss cycles 1057system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 28972230000 # number of ReadSharedReq miss cycles 1058system.cpu0.l2cache.ReadSharedReq_miss_latency::total 28972230000 # number of ReadSharedReq miss cycles 1059system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 43145750500 # number of InvalidateReq miss cycles 1060system.cpu0.l2cache.InvalidateReq_miss_latency::total 43145750500 # number of InvalidateReq miss cycles 1061system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 259670000 # number of demand (read+write) miss cycles 1062system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 210027000 # number of demand (read+write) miss cycles 1063system.cpu0.l2cache.demand_miss_latency::cpu0.inst 14420808000 # number of demand (read+write) miss cycles 1064system.cpu0.l2cache.demand_miss_latency::cpu0.data 40194165999 # number of demand (read+write) miss cycles 1065system.cpu0.l2cache.demand_miss_latency::total 55084670999 # number of demand (read+write) miss cycles 1066system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 259670000 # number of overall miss cycles 1067system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 210027000 # number of overall miss cycles 1068system.cpu0.l2cache.overall_miss_latency::cpu0.inst 14420808000 # number of overall miss cycles 1069system.cpu0.l2cache.overall_miss_latency::cpu0.data 40194165999 # number of overall miss cycles 1070system.cpu0.l2cache.overall_miss_latency::total 55084670999 # number of overall miss cycles 1071system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 233393 # number of ReadReq accesses(hits+misses) 1072system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 129084 # number of ReadReq accesses(hits+misses) 1073system.cpu0.l2cache.ReadReq_accesses::total 362477 # number of ReadReq accesses(hits+misses) 1074system.cpu0.l2cache.Writeback_accesses::writebacks 3560218 # number of Writeback accesses(hits+misses) 1075system.cpu0.l2cache.Writeback_accesses::total 3560218 # number of Writeback accesses(hits+misses) 1076system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 215840 # number of UpgradeReq accesses(hits+misses) 1077system.cpu0.l2cache.UpgradeReq_accesses::total 215840 # number of UpgradeReq accesses(hits+misses) 1078system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188941 # number of SCUpgradeReq accesses(hits+misses) 1079system.cpu0.l2cache.SCUpgradeReq_accesses::total 188941 # number of SCUpgradeReq accesses(hits+misses) 1080system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1081system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1082system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1059633 # number of ReadExReq accesses(hits+misses) 1083system.cpu0.l2cache.ReadExReq_accesses::total 1059633 # number of ReadExReq accesses(hits+misses) 1084system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4667483 # number of ReadCleanReq accesses(hits+misses) 1085system.cpu0.l2cache.ReadCleanReq_accesses::total 4667483 # number of ReadCleanReq accesses(hits+misses) 1086system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3514918 # number of ReadSharedReq accesses(hits+misses) 1087system.cpu0.l2cache.ReadSharedReq_accesses::total 3514918 # number of ReadSharedReq accesses(hits+misses) 1088system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 757609 # number of InvalidateReq accesses(hits+misses) 1089system.cpu0.l2cache.InvalidateReq_accesses::total 757609 # number of InvalidateReq accesses(hits+misses) 1090system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 233393 # number of demand (read+write) accesses 1091system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 129084 # number of demand (read+write) accesses 1092system.cpu0.l2cache.demand_accesses::cpu0.inst 4667483 # number of demand (read+write) accesses 1093system.cpu0.l2cache.demand_accesses::cpu0.data 4574551 # number of demand (read+write) accesses 1094system.cpu0.l2cache.demand_accesses::total 9604511 # number of demand (read+write) accesses 1095system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 233393 # number of overall (read+write) accesses 1096system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 129084 # number of overall (read+write) accesses 1097system.cpu0.l2cache.overall_accesses::cpu0.inst 4667483 # number of overall (read+write) accesses 1098system.cpu0.l2cache.overall_accesses::cpu0.data 4574551 # number of overall (read+write) accesses 1099system.cpu0.l2cache.overall_accesses::total 9604511 # number of overall (read+write) accesses 1100system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for ReadReq accesses 1101system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052880 # miss rate for ReadReq accesses 1102system.cpu0.l2cache.ReadReq_miss_rate::total 0.043310 # miss rate for ReadReq accesses 1103system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.571386 # miss rate for UpgradeReq accesses 1104system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.571386 # miss rate for UpgradeReq accesses 1105system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.847233 # miss rate for SCUpgradeReq accesses 1106system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.847233 # miss rate for SCUpgradeReq accesses 1107system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1108system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1109system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217467 # miss rate for ReadExReq accesses 1110system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217467 # miss rate for ReadExReq accesses 1111system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103234 # miss rate for ReadCleanReq accesses 1112system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103234 # miss rate for ReadCleanReq accesses 1113system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.254345 # miss rate for ReadSharedReq accesses 1114system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.254345 # miss rate for ReadSharedReq accesses 1115system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.739421 # miss rate for InvalidateReq accesses 1116system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.739421 # miss rate for InvalidateReq accesses 1117system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for demand accesses 1118system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052880 # miss rate for demand accesses 1119system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103234 # miss rate for demand accesses 1120system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.245803 # miss rate for demand accesses 1121system.cpu0.l2cache.demand_miss_rate::total 0.168877 # miss rate for demand accesses 1122system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for overall accesses 1123system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052880 # miss rate for overall accesses 1124system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103234 # miss rate for overall accesses 1125system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.245803 # miss rate for overall accesses 1126system.cpu0.l2cache.overall_miss_rate::total 0.168877 # miss rate for overall accesses 1127system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average ReadReq miss latency 1128system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 30768.678582 # average ReadReq miss latency 1129system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29918.912033 # average ReadReq miss latency 1130system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21495.925499 # average UpgradeReq miss latency 1131system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21495.925499 # average UpgradeReq miss latency 1132system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20737.292053 # average SCUpgradeReq miss latency 1133system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20737.292053 # average SCUpgradeReq miss latency 1134system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 674250 # average SCUpgradeFailReq miss latency 1135system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 674250 # average SCUpgradeFailReq miss latency 1136system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48698.921600 # average ReadExReq miss latency 1137system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48698.921600 # average ReadExReq miss latency 1138system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29928.375159 # average ReadCleanReq miss latency 1139system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29928.375159 # average ReadCleanReq miss latency 1140system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32407.307358 # average ReadSharedReq miss latency 1141system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32407.307358 # average ReadSharedReq miss latency 1142system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 77019.576324 # average InvalidateReq miss latency 1143system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 77019.576324 # average InvalidateReq miss latency 1144system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency 1145system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency 1146system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency 1147system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency 1148system.cpu0.l2cache.demand_avg_miss_latency::total 33961.354047 # average overall miss latency 1149system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency 1150system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency 1151system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency 1152system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency 1153system.cpu0.l2cache.overall_avg_miss_latency::total 33961.354047 # average overall miss latency 1154system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1155system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1156system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1157system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1158system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1159system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1160system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1161system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1162system.cpu0.l2cache.writebacks::writebacks 1248318 # number of writebacks 1163system.cpu0.l2cache.writebacks::total 1248318 # number of writebacks 1164system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3799 # number of ReadExReq MSHR hits 1165system.cpu0.l2cache.ReadExReq_mshr_hits::total 3799 # number of ReadExReq MSHR hits 1166system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 319 # number of ReadSharedReq MSHR hits 1167system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 319 # number of ReadSharedReq MSHR hits 1168system.cpu0.l2cache.demand_mshr_hits::cpu0.data 4118 # number of demand (read+write) MSHR hits 1169system.cpu0.l2cache.demand_mshr_hits::total 4118 # number of demand (read+write) MSHR hits 1170system.cpu0.l2cache.overall_mshr_hits::cpu0.data 4118 # number of overall MSHR hits 1171system.cpu0.l2cache.overall_mshr_hits::total 4118 # number of overall MSHR hits 1172system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8873 # number of ReadReq MSHR misses 1173system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6826 # number of ReadReq MSHR misses 1174system.cpu0.l2cache.ReadReq_mshr_misses::total 15699 # number of ReadReq MSHR misses 1175system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 86363 # number of CleanEvict MSHR misses 1176system.cpu0.l2cache.CleanEvict_mshr_misses::total 86363 # number of CleanEvict MSHR misses 1177system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 615430 # number of HardPFReq MSHR misses 1178system.cpu0.l2cache.HardPFReq_mshr_misses::total 615430 # number of HardPFReq MSHR misses 1179system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 123328 # number of UpgradeReq MSHR misses 1180system.cpu0.l2cache.UpgradeReq_mshr_misses::total 123328 # number of UpgradeReq MSHR misses 1181system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160077 # number of SCUpgradeReq MSHR misses 1182system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160077 # number of SCUpgradeReq MSHR misses 1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1185system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 226636 # number of ReadExReq MSHR misses 1186system.cpu0.l2cache.ReadExReq_mshr_misses::total 226636 # number of ReadExReq MSHR misses 1187system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 481844 # number of ReadCleanReq MSHR misses 1188system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 481844 # number of ReadCleanReq MSHR misses 1189system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 893684 # number of ReadSharedReq MSHR misses 1190system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 893684 # number of ReadSharedReq MSHR misses 1191system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 560192 # number of InvalidateReq MSHR misses 1192system.cpu0.l2cache.InvalidateReq_mshr_misses::total 560192 # number of InvalidateReq MSHR misses 1193system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8873 # number of demand (read+write) MSHR misses 1194system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6826 # number of demand (read+write) MSHR misses 1195system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 481844 # number of demand (read+write) MSHR misses 1196system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1120320 # number of demand (read+write) MSHR misses 1197system.cpu0.l2cache.demand_mshr_misses::total 1617863 # number of demand (read+write) MSHR misses 1198system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8873 # number of overall MSHR misses 1199system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6826 # number of overall MSHR misses 1200system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 481844 # number of overall MSHR misses 1201system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1120320 # number of overall MSHR misses 1202system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 615430 # number of overall MSHR misses 1203system.cpu0.l2cache.overall_mshr_misses::total 2233293 # number of overall MSHR misses 1204system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable 1206system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 69356 # number of ReadReq MSHR uncacheable 1207system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable 1208system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable 1209system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1210system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses 1211system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 94809 # number of overall MSHR uncacheable misses 1212system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of ReadReq MSHR miss cycles 1213system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 169071000 # number of ReadReq MSHR miss cycles 1214system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 375503000 # number of ReadReq MSHR miss cycles 1215system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of HardPFReq MSHR miss cycles 1216system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 25855371219 # number of HardPFReq MSHR miss cycles 1217system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2504859500 # number of UpgradeReq MSHR miss cycles 1218system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2504859500 # number of UpgradeReq MSHR miss cycles 1219system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2454464000 # number of SCUpgradeReq MSHR miss cycles 1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2454464000 # number of SCUpgradeReq MSHR miss cycles 1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2337000 # number of SCUpgradeFailReq MSHR miss cycles 1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2337000 # number of SCUpgradeFailReq MSHR miss cycles 1223system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9468370499 # number of ReadExReq MSHR miss cycles 1224system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9468370499 # number of ReadExReq MSHR miss cycles 1225system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 11529744000 # number of ReadCleanReq MSHR miss cycles 1226system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 11529744000 # number of ReadCleanReq MSHR miss cycles 1227system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 23586536500 # number of ReadSharedReq MSHR miss cycles 1228system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 23586536500 # number of ReadSharedReq MSHR miss cycles 1229system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39784598500 # number of InvalidateReq MSHR miss cycles 1230system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39784598500 # number of InvalidateReq MSHR miss cycles 1231system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of demand (read+write) MSHR miss cycles 1232system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 169071000 # number of demand (read+write) MSHR miss cycles 1233system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11529744000 # number of demand (read+write) MSHR miss cycles 1234system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 33054906999 # number of demand (read+write) MSHR miss cycles 1235system.cpu0.l2cache.demand_mshr_miss_latency::total 44960153999 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of overall MSHR miss cycles 1237system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 169071000 # number of overall MSHR miss cycles 1238system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11529744000 # number of overall MSHR miss cycles 1239system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 33054906999 # number of overall MSHR miss cycles 1240system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of overall MSHR miss cycles 1241system.cpu0.l2cache.overall_mshr_miss_latency::total 70815525218 # number of overall MSHR miss cycles 1242system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of ReadReq MSHR uncacheable cycles 1243system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4245962500 # number of ReadReq MSHR uncacheable cycles 1244system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7700240000 # number of ReadReq MSHR uncacheable cycles 1245system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3882458000 # number of WriteReq MSHR uncacheable cycles 1246system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3882458000 # number of WriteReq MSHR uncacheable cycles 1247system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of overall MSHR uncacheable cycles 1248system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8128420500 # number of overall MSHR uncacheable cycles 1249system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11582698000 # number of overall MSHR uncacheable cycles 1250system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for ReadReq accesses 1251system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for ReadReq accesses 1252system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043310 # mshr miss rate for ReadReq accesses 1253system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1254system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1255system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1256system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1257system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.571386 # mshr miss rate for UpgradeReq accesses 1258system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.571386 # mshr miss rate for UpgradeReq accesses 1259system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.847233 # mshr miss rate for SCUpgradeReq accesses 1260system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.847233 # mshr miss rate for SCUpgradeReq accesses 1261system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1262system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1263system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213882 # mshr miss rate for ReadExReq accesses 1264system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213882 # mshr miss rate for ReadExReq accesses 1265system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for ReadCleanReq accesses 1266system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103234 # mshr miss rate for ReadCleanReq accesses 1267system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254255 # mshr miss rate for ReadSharedReq accesses 1268system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254255 # mshr miss rate for ReadSharedReq accesses 1269system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.739421 # mshr miss rate for InvalidateReq accesses 1270system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.739421 # mshr miss rate for InvalidateReq accesses 1271system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for demand accesses 1272system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for demand accesses 1273system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for demand accesses 1274system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for demand accesses 1275system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168448 # mshr miss rate for demand accesses 1276system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for overall accesses 1277system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for overall accesses 1278system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for overall accesses 1279system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for overall accesses 1280system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1281system.cpu0.l2cache.overall_mshr_miss_rate::total 0.232525 # mshr miss rate for overall accesses 1282system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average ReadReq mshr miss latency 1283system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average ReadReq mshr miss latency 1284system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033 # average ReadReq mshr miss latency 1285system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average HardPFReq mshr miss latency 1286system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855 # average HardPFReq mshr miss latency 1287system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916 # average UpgradeReq mshr miss latency 1288system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916 # average UpgradeReq mshr miss latency 1289system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984 # average SCUpgradeReq mshr miss latency 1290system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984 # average SCUpgradeReq mshr miss latency 1291system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 584250 # average SCUpgradeFailReq mshr miss latency 1292system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 584250 # average SCUpgradeFailReq mshr miss latency 1293system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090 # average ReadExReq mshr miss latency 1294system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090 # average ReadExReq mshr miss latency 1295system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average ReadCleanReq mshr miss latency 1296system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159 # average ReadCleanReq mshr miss latency 1297system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333 # average ReadSharedReq mshr miss latency 1298system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333 # average ReadSharedReq mshr miss latency 1299system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324 # average InvalidateReq mshr miss latency 1300system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324 # average InvalidateReq mshr miss latency 1301system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency 1302system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency 1303system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency 1304system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency 1305system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054 # average overall mshr miss latency 1306system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency 1307system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency 1308system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency 1309system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency 1310system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average overall mshr miss latency 1311system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783 # average overall mshr miss latency 1312system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency 1313system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064 # average ReadReq mshr uncacheable latency 1314system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258 # average ReadReq mshr uncacheable latency 1315system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731 # average WriteReq mshr uncacheable latency 1316system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731 # average WriteReq mshr uncacheable latency 1317system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency 1318system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688 # average overall mshr uncacheable latency 1319system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350 # average overall mshr uncacheable latency 1320system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1321system.cpu0.toL2Bus.trans_dist::ReadReq 548810 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::ReadResp 8811478 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::WriteResp 25453 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::Writeback 6868539 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::CleanEvict 8637410 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::HardPFReq 769123 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::UpgradeReq 445989 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::UpgradeResp 473125 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::ReadExReq 1446257 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::ReadExResp 1069406 # Transaction distribution 1335system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4667483 # Transaction distribution 1336system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5564741 # Transaction distribution 1337system.cpu0.toL2Bus.trans_dist::InvalidateReq 864337 # Transaction distribution 1338system.cpu0.toL2Bus.trans_dist::InvalidateResp 757609 # Transaction distribution 1339system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14087759 # Packet count per connected master and slave (bytes) 1340system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16981197 # Packet count per connected master and slave (bytes) 1341system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 288818 # Packet count per connected master and slave (bytes) 1342system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 540500 # Packet count per connected master and slave (bytes) 1343system.cpu0.toL2Bus.pkt_count::total 31898274 # Packet count per connected master and slave (bytes) 1344system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 298891412 # Cumulative packet size per connected master and slave (bytes) 1345system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 527370978 # Cumulative packet size per connected master and slave (bytes) 1346system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1032672 # Cumulative packet size per connected master and slave (bytes) 1347system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1867144 # Cumulative packet size per connected master and slave (bytes) 1348system.cpu0.toL2Bus.pkt_size::total 829162206 # Cumulative packet size per connected master and slave (bytes) 1349system.cpu0.toL2Bus.snoops 9613339 # Total snoops (count) 1350system.cpu0.toL2Bus.snoop_fanout::samples 30204161 # Request fanout histogram 1351system.cpu0.toL2Bus.snoop_fanout::mean 1.324614 # Request fanout histogram 1352system.cpu0.toL2Bus.snoop_fanout::stdev 0.468231 # Request fanout histogram 1353system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1354system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1355system.cpu0.toL2Bus.snoop_fanout::1 20399459 67.54% 67.54% # Request fanout histogram 1356system.cpu0.toL2Bus.snoop_fanout::2 9804702 32.46% 100.00% # Request fanout histogram 1357system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1358system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1359system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1360system.cpu0.toL2Bus.snoop_fanout::total 30204161 # Request fanout histogram 1361system.cpu0.toL2Bus.reqLayer0.occupancy 14006094999 # Layer occupancy (ticks) 1362system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1363system.cpu0.toL2Bus.snoopLayer0.occupancy 188261483 # Layer occupancy (ticks) 1364system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1365system.cpu0.toL2Bus.respLayer0.occupancy 7044349500 # Layer occupancy (ticks) 1366system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1367system.cpu0.toL2Bus.respLayer1.occupancy 7482254107 # Layer occupancy (ticks) 1368system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1369system.cpu0.toL2Bus.respLayer2.occupancy 159734000 # Layer occupancy (ticks) 1370system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1371system.cpu0.toL2Bus.respLayer3.occupancy 307107000 # Layer occupancy (ticks) 1372system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1373system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1374system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1375system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1376system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1377system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1378system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1379system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1380system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1381system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1382system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1383system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1384system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1385system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1386system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1387system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1388system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1389system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1390system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1391system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1392system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1393system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1394system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1395system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1396system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1397system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1398system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1399system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1400system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1401system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1402system.cpu1.dtb.walker.walks 101352 # Table walker walks requested 1403system.cpu1.dtb.walker.walksLong 101352 # Table walker walks initiated with long descriptors 1404system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8872 # Level at which table walker walks with long descriptors terminate 1405system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77968 # Level at which table walker walks with long descriptors terminate 1406system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting 1407system.cpu1.dtb.walker.walkWaitTime::samples 101349 # Table walker wait (enqueue to first request) latency 1408system.cpu1.dtb.walker.walkWaitTime::mean 0.078935 # Table walker wait (enqueue to first request) latency 1409system.cpu1.dtb.walker.walkWaitTime::stdev 25.129292 # Table walker wait (enqueue to first request) latency 1410system.cpu1.dtb.walker.walkWaitTime::0-511 101348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1411system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1412system.cpu1.dtb.walker.walkWaitTime::total 101349 # Table walker wait (enqueue to first request) latency 1413system.cpu1.dtb.walker.walkCompletionTime::samples 86843 # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874 # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286 # Table walker service (enqueue to completion) latency 1416system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789 # Table walker service (enqueue to completion) latency 1417system.cpu1.dtb.walker.walkCompletionTime::0-65535 85298 98.22% 98.22% # Table walker service (enqueue to completion) latency 1418system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1315 1.51% 99.74% # Table walker service (enqueue to completion) latency 1419system.cpu1.dtb.walker.walkCompletionTime::131072-196607 45 0.05% 99.79% # Table walker service (enqueue to completion) latency 1420system.cpu1.dtb.walker.walkCompletionTime::196608-262143 84 0.10% 99.88% # Table walker service (enqueue to completion) latency 1421system.cpu1.dtb.walker.walkCompletionTime::262144-327679 70 0.08% 99.96% # Table walker service (enqueue to completion) latency 1422system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.99% # Table walker service (enqueue to completion) latency 1423system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1424system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1425system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1426system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1427system.cpu1.dtb.walker.walkCompletionTime::total 86843 # Table walker service (enqueue to completion) latency 1428system.cpu1.dtb.walker.walksPending::samples -857364308 # Table walker pending requests distribution 1429system.cpu1.dtb.walker.walksPending::mean -0.833676 # Table walker pending requests distribution 1430system.cpu1.dtb.walker.walksPending::0 -1572128036 183.37% 183.37% # Table walker pending requests distribution 1431system.cpu1.dtb.walker.walksPending::1 714763728 -83.37% 100.00% # Table walker pending requests distribution 1432system.cpu1.dtb.walker.walksPending::total -857364308 # Table walker pending requests distribution 1433system.cpu1.dtb.walker.walkPageSizes::4K 77968 89.78% 89.78% # Table walker page sizes translated 1434system.cpu1.dtb.walker.walkPageSizes::2M 8872 10.22% 100.00% # Table walker page sizes translated 1435system.cpu1.dtb.walker.walkPageSizes::total 86840 # Table walker page sizes translated 1436system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101352 # Table walker requests started/completed, data/inst 1437system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1438system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101352 # Table walker requests started/completed, data/inst 1439system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86840 # Table walker requests started/completed, data/inst 1440system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1441system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86840 # Table walker requests started/completed, data/inst 1442system.cpu1.dtb.walker.walkRequestOrigin::total 188192 # Table walker requests started/completed, data/inst 1443system.cpu1.dtb.inst_hits 0 # ITB inst hits 1444system.cpu1.dtb.inst_misses 0 # ITB inst misses 1445system.cpu1.dtb.read_hits 82714274 # DTB read hits 1446system.cpu1.dtb.read_misses 74721 # DTB read misses 1447system.cpu1.dtb.write_hits 75460503 # DTB write hits 1448system.cpu1.dtb.write_misses 26631 # DTB write misses 1449system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1450system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1451system.cpu1.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 1452system.cpu1.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 1453system.cpu1.dtb.flush_entries 38549 # Number of entries that have been flushed from TLB 1454system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1455system.cpu1.dtb.prefetch_faults 4418 # Number of TLB faults due to prefetch 1456system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1457system.cpu1.dtb.perms_faults 10567 # Number of TLB faults due to permissions restrictions 1458system.cpu1.dtb.read_accesses 82788995 # DTB read accesses 1459system.cpu1.dtb.write_accesses 75487134 # DTB write accesses 1460system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1461system.cpu1.dtb.hits 158174777 # DTB hits 1462system.cpu1.dtb.misses 101352 # DTB misses 1463system.cpu1.dtb.accesses 158276129 # DTB accesses 1464system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1465system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1466system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1467system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1468system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1469system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1470system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1471system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1472system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1473system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1474system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1475system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1476system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1477system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1478system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1479system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1480system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1481system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1482system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1483system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1484system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1485system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1486system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1487system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1488system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1489system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1490system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1491system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1492system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1493system.cpu1.itb.walker.walks 60693 # Table walker walks requested 1494system.cpu1.itb.walker.walksLong 60693 # Table walker walks initiated with long descriptors 1495system.cpu1.itb.walker.walksLongTerminationLevel::Level2 593 # Level at which table walker walks with long descriptors terminate 1496system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54830 # Level at which table walker walks with long descriptors terminate 1497system.cpu1.itb.walker.walkWaitTime::samples 60693 # Table walker wait (enqueue to first request) latency 1498system.cpu1.itb.walker.walkWaitTime::0 60693 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1499system.cpu1.itb.walker.walkWaitTime::total 60693 # Table walker wait (enqueue to first request) latency 1500system.cpu1.itb.walker.walkCompletionTime::samples 55423 # Table walker service (enqueue to completion) latency 1501system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480 # Table walker service (enqueue to completion) latency 1502system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042 # Table walker service (enqueue to completion) latency 1503system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821 # Table walker service (enqueue to completion) latency 1504system.cpu1.itb.walker.walkCompletionTime::0-32767 49924 90.08% 90.08% # Table walker service (enqueue to completion) latency 1505system.cpu1.itb.walker.walkCompletionTime::32768-65535 3716 6.70% 96.78% # Table walker service (enqueue to completion) latency 1506system.cpu1.itb.walker.walkCompletionTime::65536-98303 553 1.00% 97.78% # Table walker service (enqueue to completion) latency 1507system.cpu1.itb.walker.walkCompletionTime::98304-131071 965 1.74% 99.52% # Table walker service (enqueue to completion) latency 1508system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.06% 99.58% # Table walker service (enqueue to completion) latency 1509system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.63% # Table walker service (enqueue to completion) latency 1510system.cpu1.itb.walker.walkCompletionTime::196608-229375 86 0.16% 99.78% # Table walker service (enqueue to completion) latency 1511system.cpu1.itb.walker.walkCompletionTime::229376-262143 15 0.03% 99.81% # Table walker service (enqueue to completion) latency 1512system.cpu1.itb.walker.walkCompletionTime::262144-294911 45 0.08% 99.89% # Table walker service (enqueue to completion) latency 1513system.cpu1.itb.walker.walkCompletionTime::294912-327679 26 0.05% 99.94% # Table walker service (enqueue to completion) latency 1514system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.96% # Table walker service (enqueue to completion) latency 1515system.cpu1.itb.walker.walkCompletionTime::360448-393215 12 0.02% 99.98% # Table walker service (enqueue to completion) latency 1516system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1517system.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 1518system.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1519system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1520system.cpu1.itb.walker.walkCompletionTime::total 55423 # Table walker service (enqueue to completion) latency 1521system.cpu1.itb.walker.walksPending::samples -1656015036 # Table walker pending requests distribution 1522system.cpu1.itb.walker.walksPending::0 -1656015036 100.00% 100.00% # Table walker pending requests distribution 1523system.cpu1.itb.walker.walksPending::total -1656015036 # Table walker pending requests distribution 1524system.cpu1.itb.walker.walkPageSizes::4K 54830 98.93% 98.93% # Table walker page sizes translated 1525system.cpu1.itb.walker.walkPageSizes::2M 593 1.07% 100.00% # Table walker page sizes translated 1526system.cpu1.itb.walker.walkPageSizes::total 55423 # Table walker page sizes translated 1527system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1528system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60693 # Table walker requests started/completed, data/inst 1529system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60693 # Table walker requests started/completed, data/inst 1530system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1531system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55423 # Table walker requests started/completed, data/inst 1532system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55423 # Table walker requests started/completed, data/inst 1533system.cpu1.itb.walker.walkRequestOrigin::total 116116 # Table walker requests started/completed, data/inst 1534system.cpu1.itb.inst_hits 437193188 # ITB inst hits 1535system.cpu1.itb.inst_misses 60693 # ITB inst misses 1536system.cpu1.itb.read_hits 0 # DTB read hits 1537system.cpu1.itb.read_misses 0 # DTB read misses 1538system.cpu1.itb.write_hits 0 # DTB write hits 1539system.cpu1.itb.write_misses 0 # DTB write misses 1540system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1541system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1542system.cpu1.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 1543system.cpu1.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 1544system.cpu1.itb.flush_entries 27130 # Number of entries that have been flushed from TLB 1545system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1546system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1547system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1548system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1549system.cpu1.itb.read_accesses 0 # DTB read accesses 1550system.cpu1.itb.write_accesses 0 # DTB write accesses 1551system.cpu1.itb.inst_accesses 437253881 # ITB inst accesses 1552system.cpu1.itb.hits 437193188 # DTB hits 1553system.cpu1.itb.misses 60693 # DTB misses 1554system.cpu1.itb.accesses 437253881 # DTB accesses 1555system.cpu1.numCycles 94913359253 # number of cpu cycles simulated 1556system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1557system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1558system.cpu1.committedInsts 436909780 # Number of instructions committed 1559system.cpu1.committedOps 515262081 # Number of ops (including micro ops) committed 1560system.cpu1.num_int_alu_accesses 474007520 # Number of integer alu accesses 1561system.cpu1.num_fp_alu_accesses 488695 # Number of float alu accesses 1562system.cpu1.num_func_calls 26553696 # number of times a function call or return occured 1563system.cpu1.num_conditional_control_insts 66234119 # number of instructions that are conditional controls 1564system.cpu1.num_int_insts 474007520 # number of integer instructions 1565system.cpu1.num_fp_insts 488695 # number of float instructions 1566system.cpu1.num_int_register_reads 687449190 # number of times the integer registers were read 1567system.cpu1.num_int_register_writes 375811208 # number of times the integer registers were written 1568system.cpu1.num_fp_register_reads 781283 # number of times the floating registers were read 1569system.cpu1.num_fp_register_writes 430208 # number of times the floating registers were written 1570system.cpu1.num_cc_register_reads 112572477 # number of times the CC registers were read 1571system.cpu1.num_cc_register_writes 112287439 # number of times the CC registers were written 1572system.cpu1.num_mem_refs 158166235 # number of memory refs 1573system.cpu1.num_load_insts 82712263 # Number of load instructions 1574system.cpu1.num_store_insts 75453972 # Number of store instructions 1575system.cpu1.num_idle_cycles 93876093406.586029 # Number of idle cycles 1576system.cpu1.num_busy_cycles 1037265846.413978 # Number of busy cycles 1577system.cpu1.not_idle_fraction 0.010929 # Percentage of non-idle cycles 1578system.cpu1.idle_fraction 0.989071 # Percentage of idle cycles 1579system.cpu1.Branches 97493416 # Number of branches fetched 1580system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1581system.cpu1.op_class::IntAlu 356171607 69.09% 69.09% # Class of executed instruction 1582system.cpu1.op_class::IntMult 1079497 0.21% 69.30% # Class of executed instruction 1583system.cpu1.op_class::IntDiv 59940 0.01% 69.31% # Class of executed instruction 1584system.cpu1.op_class::FloatAdd 0 0.00% 69.31% # Class of executed instruction 1585system.cpu1.op_class::FloatCmp 0 0.00% 69.31% # Class of executed instruction 1586system.cpu1.op_class::FloatCvt 0 0.00% 69.31% # Class of executed instruction 1587system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction 1588system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction 1589system.cpu1.op_class::FloatSqrt 0 0.00% 69.31% # Class of executed instruction 1590system.cpu1.op_class::SimdAdd 0 0.00% 69.31% # Class of executed instruction 1591system.cpu1.op_class::SimdAddAcc 0 0.00% 69.31% # Class of executed instruction 1592system.cpu1.op_class::SimdAlu 0 0.00% 69.31% # Class of executed instruction 1593system.cpu1.op_class::SimdCmp 0 0.00% 69.31% # Class of executed instruction 1594system.cpu1.op_class::SimdCvt 0 0.00% 69.31% # Class of executed instruction 1595system.cpu1.op_class::SimdMisc 0 0.00% 69.31% # Class of executed instruction 1596system.cpu1.op_class::SimdMult 0 0.00% 69.31% # Class of executed instruction 1597system.cpu1.op_class::SimdMultAcc 0 0.00% 69.31% # Class of executed instruction 1598system.cpu1.op_class::SimdShift 0 0.00% 69.31% # Class of executed instruction 1599system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.31% # Class of executed instruction 1600system.cpu1.op_class::SimdSqrt 0 0.00% 69.31% # Class of executed instruction 1601system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.31% # Class of executed instruction 1602system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.31% # Class of executed instruction 1603system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.31% # Class of executed instruction 1604system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.31% # Class of executed instruction 1605system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.31% # Class of executed instruction 1606system.cpu1.op_class::SimdFloatMisc 68277 0.01% 69.32% # Class of executed instruction 1607system.cpu1.op_class::SimdFloatMult 0 0.00% 69.32% # Class of executed instruction 1608system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.32% # Class of executed instruction 1609system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.32% # Class of executed instruction 1610system.cpu1.op_class::MemRead 82712263 16.04% 85.36% # Class of executed instruction 1611system.cpu1.op_class::MemWrite 75453972 14.64% 100.00% # Class of executed instruction 1612system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1613system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1614system.cpu1.op_class::total 515545598 # Class of executed instruction 1615system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1616system.cpu1.kern.inst.quiesce 7070 # number of quiesce instructions executed 1617system.cpu1.dcache.tags.replacements 5176711 # number of replacements 1618system.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use 1619system.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks. 1620system.cpu1.dcache.tags.sampled_refs 5177218 # Sample count of references to valid blocks. 1621system.cpu1.dcache.tags.avg_refs 29.515202 # Average number of references to valid blocks. 1622system.cpu1.dcache.tags.warmup_cycle 8391490917000 # Cycle when the warmup percentage was hit. 1623system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.282743 # Average occupied blocks per requestor 1624system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893130 # Average percentage of cache occupancy 1625system.cpu1.dcache.tags.occ_percent::total 0.893130 # Average percentage of cache occupancy 1626system.cpu1.dcache.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id 1627system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1628system.cpu1.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 1629system.cpu1.dcache.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id 1630system.cpu1.dcache.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id 1631system.cpu1.dcache.tags.tag_accesses 321544722 # Number of tag accesses 1632system.cpu1.dcache.tags.data_accesses 321544722 # Number of data accesses 1633system.cpu1.dcache.ReadReq_hits::cpu1.data 77092949 # number of ReadReq hits 1634system.cpu1.dcache.ReadReq_hits::total 77092949 # number of ReadReq hits 1635system.cpu1.dcache.WriteReq_hits::cpu1.data 71608224 # number of WriteReq hits 1636system.cpu1.dcache.WriteReq_hits::total 71608224 # number of WriteReq hits 1637system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188155 # number of SoftPFReq hits 1638system.cpu1.dcache.SoftPFReq_hits::total 188155 # number of SoftPFReq hits 1639system.cpu1.dcache.WriteLineReq_hits::cpu1.data 187532 # number of WriteLineReq hits 1640system.cpu1.dcache.WriteLineReq_hits::total 187532 # number of WriteLineReq hits 1641system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684198 # number of LoadLockedReq hits 1642system.cpu1.dcache.LoadLockedReq_hits::total 1684198 # number of LoadLockedReq hits 1643system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1657450 # number of StoreCondReq hits 1644system.cpu1.dcache.StoreCondReq_hits::total 1657450 # number of StoreCondReq hits 1645system.cpu1.dcache.demand_hits::cpu1.data 148701173 # number of demand (read+write) hits 1646system.cpu1.dcache.demand_hits::total 148701173 # number of demand (read+write) hits 1647system.cpu1.dcache.overall_hits::cpu1.data 148889328 # number of overall hits 1648system.cpu1.dcache.overall_hits::total 148889328 # number of overall hits 1649system.cpu1.dcache.ReadReq_misses::cpu1.data 2950342 # number of ReadReq misses 1650system.cpu1.dcache.ReadReq_misses::total 2950342 # number of ReadReq misses 1651system.cpu1.dcache.WriteReq_misses::cpu1.data 1305907 # number of WriteReq misses 1652system.cpu1.dcache.WriteReq_misses::total 1305907 # number of WriteReq misses 1653system.cpu1.dcache.SoftPFReq_misses::cpu1.data 613815 # number of SoftPFReq misses 1654system.cpu1.dcache.SoftPFReq_misses::total 613815 # number of SoftPFReq misses 1655system.cpu1.dcache.WriteLineReq_misses::cpu1.data 479868 # number of WriteLineReq misses 1656system.cpu1.dcache.WriteLineReq_misses::total 479868 # number of WriteLineReq misses 1657system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172330 # number of LoadLockedReq misses 1658system.cpu1.dcache.LoadLockedReq_misses::total 172330 # number of LoadLockedReq misses 1659system.cpu1.dcache.StoreCondReq_misses::cpu1.data 197330 # number of StoreCondReq misses 1660system.cpu1.dcache.StoreCondReq_misses::total 197330 # number of StoreCondReq misses 1661system.cpu1.dcache.demand_misses::cpu1.data 4256249 # number of demand (read+write) misses 1662system.cpu1.dcache.demand_misses::total 4256249 # number of demand (read+write) misses 1663system.cpu1.dcache.overall_misses::cpu1.data 4870064 # number of overall misses 1664system.cpu1.dcache.overall_misses::total 4870064 # number of overall misses 1665system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42135771000 # number of ReadReq miss cycles 1666system.cpu1.dcache.ReadReq_miss_latency::total 42135771000 # number of ReadReq miss cycles 1667system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22153910000 # number of WriteReq miss cycles 1668system.cpu1.dcache.WriteReq_miss_latency::total 22153910000 # number of WriteReq miss cycles 1669system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 15218762000 # number of WriteLineReq miss cycles 1670system.cpu1.dcache.WriteLineReq_miss_latency::total 15218762000 # number of WriteLineReq miss cycles 1671system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2580362000 # number of LoadLockedReq miss cycles 1672system.cpu1.dcache.LoadLockedReq_miss_latency::total 2580362000 # number of LoadLockedReq miss cycles 1673system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4225919000 # number of StoreCondReq miss cycles 1674system.cpu1.dcache.StoreCondReq_miss_latency::total 4225919000 # number of StoreCondReq miss cycles 1675system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2953000 # number of StoreCondFailReq miss cycles 1676system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2953000 # number of StoreCondFailReq miss cycles 1677system.cpu1.dcache.demand_miss_latency::cpu1.data 64289681000 # number of demand (read+write) miss cycles 1678system.cpu1.dcache.demand_miss_latency::total 64289681000 # number of demand (read+write) miss cycles 1679system.cpu1.dcache.overall_miss_latency::cpu1.data 64289681000 # number of overall miss cycles 1680system.cpu1.dcache.overall_miss_latency::total 64289681000 # number of overall miss cycles 1681system.cpu1.dcache.ReadReq_accesses::cpu1.data 80043291 # number of ReadReq accesses(hits+misses) 1682system.cpu1.dcache.ReadReq_accesses::total 80043291 # number of ReadReq accesses(hits+misses) 1683system.cpu1.dcache.WriteReq_accesses::cpu1.data 72914131 # number of WriteReq accesses(hits+misses) 1684system.cpu1.dcache.WriteReq_accesses::total 72914131 # number of WriteReq accesses(hits+misses) 1685system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 801970 # number of SoftPFReq accesses(hits+misses) 1686system.cpu1.dcache.SoftPFReq_accesses::total 801970 # number of SoftPFReq accesses(hits+misses) 1687system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 667400 # number of WriteLineReq accesses(hits+misses) 1688system.cpu1.dcache.WriteLineReq_accesses::total 667400 # number of WriteLineReq accesses(hits+misses) 1689system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1856528 # number of LoadLockedReq accesses(hits+misses) 1690system.cpu1.dcache.LoadLockedReq_accesses::total 1856528 # number of LoadLockedReq accesses(hits+misses) 1691system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1854780 # number of StoreCondReq accesses(hits+misses) 1692system.cpu1.dcache.StoreCondReq_accesses::total 1854780 # number of StoreCondReq accesses(hits+misses) 1693system.cpu1.dcache.demand_accesses::cpu1.data 152957422 # number of demand (read+write) accesses 1694system.cpu1.dcache.demand_accesses::total 152957422 # number of demand (read+write) accesses 1695system.cpu1.dcache.overall_accesses::cpu1.data 153759392 # number of overall (read+write) accesses 1696system.cpu1.dcache.overall_accesses::total 153759392 # number of overall (read+write) accesses 1697system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036859 # miss rate for ReadReq accesses 1698system.cpu1.dcache.ReadReq_miss_rate::total 0.036859 # miss rate for ReadReq accesses 1699system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017910 # miss rate for WriteReq accesses 1700system.cpu1.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses 1701system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765384 # miss rate for SoftPFReq accesses 1702system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765384 # miss rate for SoftPFReq accesses 1703system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.719011 # miss rate for WriteLineReq accesses 1704system.cpu1.dcache.WriteLineReq_miss_rate::total 0.719011 # miss rate for WriteLineReq accesses 1705system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092824 # miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092824 # miss rate for LoadLockedReq accesses 1707system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106390 # miss rate for StoreCondReq accesses 1708system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106390 # miss rate for StoreCondReq accesses 1709system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027826 # miss rate for demand accesses 1710system.cpu1.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses 1711system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031673 # miss rate for overall accesses 1712system.cpu1.dcache.overall_miss_rate::total 0.031673 # miss rate for overall accesses 1713system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499 # average ReadReq miss latency 1714system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499 # average ReadReq miss latency 1715system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672 # average WriteReq miss latency 1716system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672 # average WriteReq miss latency 1717system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647 # average WriteLineReq miss latency 1718system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647 # average WriteLineReq miss latency 1719system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661 # average LoadLockedReq miss latency 1720system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661 # average LoadLockedReq miss latency 1721system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816 # average StoreCondReq miss latency 1722system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816 # average StoreCondReq miss latency 1723system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1724system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1725system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415 # average overall miss latency 1726system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415 # average overall miss latency 1727system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046 # average overall miss latency 1728system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046 # average overall miss latency 1729system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1730system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1731system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1732system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1733system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1734system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1735system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1736system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1737system.cpu1.dcache.writebacks::writebacks 3350646 # number of writebacks 1738system.cpu1.dcache.writebacks::total 3350646 # number of writebacks 1739system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17552 # number of ReadReq MSHR hits 1740system.cpu1.dcache.ReadReq_mshr_hits::total 17552 # number of ReadReq MSHR hits 1741system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 421 # number of WriteReq MSHR hits 1742system.cpu1.dcache.WriteReq_mshr_hits::total 421 # number of WriteReq MSHR hits 1743system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45020 # number of LoadLockedReq MSHR hits 1744system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45020 # number of LoadLockedReq MSHR hits 1745system.cpu1.dcache.demand_mshr_hits::cpu1.data 17973 # number of demand (read+write) MSHR hits 1746system.cpu1.dcache.demand_mshr_hits::total 17973 # number of demand (read+write) MSHR hits 1747system.cpu1.dcache.overall_mshr_hits::cpu1.data 17973 # number of overall MSHR hits 1748system.cpu1.dcache.overall_mshr_hits::total 17973 # number of overall MSHR hits 1749system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932790 # number of ReadReq MSHR misses 1750system.cpu1.dcache.ReadReq_mshr_misses::total 2932790 # number of ReadReq MSHR misses 1751system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1305486 # number of WriteReq MSHR misses 1752system.cpu1.dcache.WriteReq_mshr_misses::total 1305486 # number of WriteReq MSHR misses 1753system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 613815 # number of SoftPFReq MSHR misses 1754system.cpu1.dcache.SoftPFReq_mshr_misses::total 613815 # number of SoftPFReq MSHR misses 1755system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 479868 # number of WriteLineReq MSHR misses 1756system.cpu1.dcache.WriteLineReq_mshr_misses::total 479868 # number of WriteLineReq MSHR misses 1757system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127310 # number of LoadLockedReq MSHR misses 1758system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127310 # number of LoadLockedReq MSHR misses 1759system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 197330 # number of StoreCondReq MSHR misses 1760system.cpu1.dcache.StoreCondReq_mshr_misses::total 197330 # number of StoreCondReq MSHR misses 1761system.cpu1.dcache.demand_mshr_misses::cpu1.data 4238276 # number of demand (read+write) MSHR misses 1762system.cpu1.dcache.demand_mshr_misses::total 4238276 # number of demand (read+write) MSHR misses 1763system.cpu1.dcache.overall_mshr_misses::cpu1.data 4852091 # number of overall MSHR misses 1764system.cpu1.dcache.overall_mshr_misses::total 4852091 # number of overall MSHR misses 1765system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable 1766system.cpu1.dcache.ReadReq_mshr_uncacheable::total 12503 # number of ReadReq MSHR uncacheable 1767system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable 1768system.cpu1.dcache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable 1769system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses 1770system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25653 # number of overall MSHR uncacheable misses 1771system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38342874000 # number of ReadReq MSHR miss cycles 1772system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38342874000 # number of ReadReq MSHR miss cycles 1773system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20834838000 # number of WriteReq MSHR miss cycles 1774system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20834838000 # number of WriteReq MSHR miss cycles 1775system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12333914500 # number of SoftPFReq MSHR miss cycles 1776system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12333914500 # number of SoftPFReq MSHR miss cycles 1777system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14738894000 # number of WriteLineReq MSHR miss cycles 1778system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14738894000 # number of WriteLineReq MSHR miss cycles 1779system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690256500 # number of LoadLockedReq MSHR miss cycles 1780system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690256500 # number of LoadLockedReq MSHR miss cycles 1781system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4028650000 # number of StoreCondReq MSHR miss cycles 1782system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4028650000 # number of StoreCondReq MSHR miss cycles 1783system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2892000 # number of StoreCondFailReq MSHR miss cycles 1784system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2892000 # number of StoreCondFailReq MSHR miss cycles 1785system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59177712000 # number of demand (read+write) MSHR miss cycles 1786system.cpu1.dcache.demand_mshr_miss_latency::total 59177712000 # number of demand (read+write) MSHR miss cycles 1787system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71511626500 # number of overall MSHR miss cycles 1788system.cpu1.dcache.overall_mshr_miss_latency::total 71511626500 # number of overall MSHR miss cycles 1789system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2070021000 # number of ReadReq MSHR uncacheable cycles 1790system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2070021000 # number of ReadReq MSHR uncacheable cycles 1791system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2282534000 # number of WriteReq MSHR uncacheable cycles 1792system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2282534000 # number of WriteReq MSHR uncacheable cycles 1793system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4352555000 # number of overall MSHR uncacheable cycles 1794system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4352555000 # number of overall MSHR uncacheable cycles 1795system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036640 # mshr miss rate for ReadReq accesses 1796system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036640 # mshr miss rate for ReadReq accesses 1797system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017904 # mshr miss rate for WriteReq accesses 1798system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017904 # mshr miss rate for WriteReq accesses 1799system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765384 # mshr miss rate for SoftPFReq accesses 1800system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765384 # mshr miss rate for SoftPFReq accesses 1801system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.719011 # mshr miss rate for WriteLineReq accesses 1802system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.719011 # mshr miss rate for WriteLineReq accesses 1803system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068574 # mshr miss rate for LoadLockedReq accesses 1804system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068574 # mshr miss rate for LoadLockedReq accesses 1805system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106390 # mshr miss rate for StoreCondReq accesses 1806system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106390 # mshr miss rate for StoreCondReq accesses 1807system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027709 # mshr miss rate for demand accesses 1808system.cpu1.dcache.demand_mshr_miss_rate::total 0.027709 # mshr miss rate for demand accesses 1809system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031556 # mshr miss rate for overall accesses 1810system.cpu1.dcache.overall_mshr_miss_rate::total 0.031556 # mshr miss rate for overall accesses 1811system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953 # average ReadReq mshr miss latency 1812system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953 # average ReadReq mshr miss latency 1813system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584 # average WriteReq mshr miss latency 1814system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584 # average WriteReq mshr miss latency 1815system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972 # average SoftPFReq mshr miss latency 1816system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972 # average SoftPFReq mshr miss latency 1817system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647 # average WriteLineReq mshr miss latency 1818system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647 # average WriteLineReq mshr miss latency 1819system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610 # average LoadLockedReq mshr miss latency 1820system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610 # average LoadLockedReq mshr miss latency 1821system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943 # average StoreCondReq mshr miss latency 1822system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943 # average StoreCondReq mshr miss latency 1823system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1824system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1825system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828 # average overall mshr miss latency 1826system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828 # average overall mshr miss latency 1827system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070 # average overall mshr miss latency 1828system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070 # average overall mshr miss latency 1829system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133 # average ReadReq mshr uncacheable latency 1830system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133 # average ReadReq mshr uncacheable latency 1831system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038 # average WriteReq mshr uncacheable latency 1832system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038 # average WriteReq mshr uncacheable latency 1833system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919 # average overall mshr uncacheable latency 1834system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919 # average overall mshr uncacheable latency 1835system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1836system.cpu1.icache.tags.replacements 5209177 # number of replacements 1837system.cpu1.icache.tags.tagsinuse 496.272261 # Cycle average of tags in use 1838system.cpu1.icache.tags.total_refs 431983494 # Total number of references to valid blocks. 1839system.cpu1.icache.tags.sampled_refs 5209689 # Sample count of references to valid blocks. 1840system.cpu1.icache.tags.avg_refs 82.919248 # Average number of references to valid blocks. 1841system.cpu1.icache.tags.warmup_cycle 8391463454000 # Cycle when the warmup percentage was hit. 1842system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.272261 # Average occupied blocks per requestor 1843system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969282 # Average percentage of cache occupancy 1844system.cpu1.icache.tags.occ_percent::total 0.969282 # Average percentage of cache occupancy 1845system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1846system.cpu1.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 1847system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 1848system.cpu1.icache.tags.age_task_id_blocks_1024::2 440 # Occupied blocks per task id 1849system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1850system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1851system.cpu1.icache.tags.tag_accesses 879596070 # Number of tag accesses 1852system.cpu1.icache.tags.data_accesses 879596070 # Number of data accesses 1853system.cpu1.icache.ReadReq_hits::cpu1.inst 431983494 # number of ReadReq hits 1854system.cpu1.icache.ReadReq_hits::total 431983494 # number of ReadReq hits 1855system.cpu1.icache.demand_hits::cpu1.inst 431983494 # number of demand (read+write) hits 1856system.cpu1.icache.demand_hits::total 431983494 # number of demand (read+write) hits 1857system.cpu1.icache.overall_hits::cpu1.inst 431983494 # number of overall hits 1858system.cpu1.icache.overall_hits::total 431983494 # number of overall hits 1859system.cpu1.icache.ReadReq_misses::cpu1.inst 5209694 # number of ReadReq misses 1860system.cpu1.icache.ReadReq_misses::total 5209694 # number of ReadReq misses 1861system.cpu1.icache.demand_misses::cpu1.inst 5209694 # number of demand (read+write) misses 1862system.cpu1.icache.demand_misses::total 5209694 # number of demand (read+write) misses 1863system.cpu1.icache.overall_misses::cpu1.inst 5209694 # number of overall misses 1864system.cpu1.icache.overall_misses::total 5209694 # number of overall misses 1865system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53989351000 # number of ReadReq miss cycles 1866system.cpu1.icache.ReadReq_miss_latency::total 53989351000 # number of ReadReq miss cycles 1867system.cpu1.icache.demand_miss_latency::cpu1.inst 53989351000 # number of demand (read+write) miss cycles 1868system.cpu1.icache.demand_miss_latency::total 53989351000 # number of demand (read+write) miss cycles 1869system.cpu1.icache.overall_miss_latency::cpu1.inst 53989351000 # number of overall miss cycles 1870system.cpu1.icache.overall_miss_latency::total 53989351000 # number of overall miss cycles 1871system.cpu1.icache.ReadReq_accesses::cpu1.inst 437193188 # number of ReadReq accesses(hits+misses) 1872system.cpu1.icache.ReadReq_accesses::total 437193188 # number of ReadReq accesses(hits+misses) 1873system.cpu1.icache.demand_accesses::cpu1.inst 437193188 # number of demand (read+write) accesses 1874system.cpu1.icache.demand_accesses::total 437193188 # number of demand (read+write) accesses 1875system.cpu1.icache.overall_accesses::cpu1.inst 437193188 # number of overall (read+write) accesses 1876system.cpu1.icache.overall_accesses::total 437193188 # number of overall (read+write) accesses 1877system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011916 # miss rate for ReadReq accesses 1878system.cpu1.icache.ReadReq_miss_rate::total 0.011916 # miss rate for ReadReq accesses 1879system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011916 # miss rate for demand accesses 1880system.cpu1.icache.demand_miss_rate::total 0.011916 # miss rate for demand accesses 1881system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011916 # miss rate for overall accesses 1882system.cpu1.icache.overall_miss_rate::total 0.011916 # miss rate for overall accesses 1883system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014 # average ReadReq miss latency 1884system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014 # average ReadReq miss latency 1885system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency 1886system.cpu1.icache.demand_avg_miss_latency::total 10363.248014 # average overall miss latency 1887system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency 1888system.cpu1.icache.overall_avg_miss_latency::total 10363.248014 # average overall miss latency 1889system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1890system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1891system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1892system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1893system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1894system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1895system.cpu1.icache.fast_writes 0 # number of fast writes performed 1896system.cpu1.icache.cache_copies 0 # number of cache copies performed 1897system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5209694 # number of ReadReq MSHR misses 1898system.cpu1.icache.ReadReq_mshr_misses::total 5209694 # number of ReadReq MSHR misses 1899system.cpu1.icache.demand_mshr_misses::cpu1.inst 5209694 # number of demand (read+write) MSHR misses 1900system.cpu1.icache.demand_mshr_misses::total 5209694 # number of demand (read+write) MSHR misses 1901system.cpu1.icache.overall_mshr_misses::cpu1.inst 5209694 # number of overall MSHR misses 1902system.cpu1.icache.overall_mshr_misses::total 5209694 # number of overall MSHR misses 1903system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1904system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1905system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1906system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1907system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51384504000 # number of ReadReq MSHR miss cycles 1908system.cpu1.icache.ReadReq_mshr_miss_latency::total 51384504000 # number of ReadReq MSHR miss cycles 1909system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51384504000 # number of demand (read+write) MSHR miss cycles 1910system.cpu1.icache.demand_mshr_miss_latency::total 51384504000 # number of demand (read+write) MSHR miss cycles 1911system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51384504000 # number of overall MSHR miss cycles 1912system.cpu1.icache.overall_mshr_miss_latency::total 51384504000 # number of overall MSHR miss cycles 1913system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9739500 # number of ReadReq MSHR uncacheable cycles 1914system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9739500 # number of ReadReq MSHR uncacheable cycles 1915system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9739500 # number of overall MSHR uncacheable cycles 1916system.cpu1.icache.overall_mshr_uncacheable_latency::total 9739500 # number of overall MSHR uncacheable cycles 1917system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for ReadReq accesses 1918system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011916 # mshr miss rate for ReadReq accesses 1919system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for demand accesses 1920system.cpu1.icache.demand_mshr_miss_rate::total 0.011916 # mshr miss rate for demand accesses 1921system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for overall accesses 1922system.cpu1.icache.overall_mshr_miss_rate::total 0.011916 # mshr miss rate for overall accesses 1923system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average ReadReq mshr miss latency 1924system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9863.248014 # average ReadReq mshr miss latency 1925system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency 1926system.cpu1.icache.demand_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency 1927system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency 1928system.cpu1.icache.overall_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency 1929system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average ReadReq mshr uncacheable latency 1930system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091 # average ReadReq mshr uncacheable latency 1931system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average overall mshr uncacheable latency 1932system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091 # average overall mshr uncacheable latency 1933system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1934system.cpu1.l2cache.prefetcher.num_hwpf_issued 7168932 # number of hwpf issued 1935system.cpu1.l2cache.prefetcher.pfIdentified 7168932 # number of prefetch candidates identified 1936system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1937system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1938system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1939system.cpu1.l2cache.prefetcher.pfSpanPage 888356 # number of prefetches not generated due to page crossing 1940system.cpu1.l2cache.tags.replacements 2018400 # number of replacements 1941system.cpu1.l2cache.tags.tagsinuse 13471.145620 # Cycle average of tags in use 1942system.cpu1.l2cache.tags.total_refs 17736817 # Total number of references to valid blocks. 1943system.cpu1.l2cache.tags.sampled_refs 2034046 # Sample count of references to valid blocks. 1944system.cpu1.l2cache.tags.avg_refs 8.719968 # Average number of references to valid blocks. 1945system.cpu1.l2cache.tags.warmup_cycle 9876432033500 # Cycle when the warmup percentage was hit. 1946system.cpu1.l2cache.tags.occ_blocks::writebacks 5731.708202 # Average occupied blocks per requestor 1947system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.533292 # Average occupied blocks per requestor 1948system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 100.125774 # Average occupied blocks per requestor 1949system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3516.826700 # Average occupied blocks per requestor 1950system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3218.371115 # Average occupied blocks per requestor 1951system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 832.580536 # Average occupied blocks per requestor 1952system.cpu1.l2cache.tags.occ_percent::writebacks 0.349836 # Average percentage of cache occupancy 1953system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004366 # Average percentage of cache occupancy 1954system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006111 # Average percentage of cache occupancy 1955system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.214650 # Average percentage of cache occupancy 1956system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196434 # Average percentage of cache occupancy 1957system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050817 # Average percentage of cache occupancy 1958system.cpu1.l2cache.tags.occ_percent::total 0.822213 # Average percentage of cache occupancy 1959system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1631 # Occupied blocks per task id 1960system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id 1961system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id 1962system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id 1963system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id 1964system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id 1965system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 1966system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 1967system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 1968system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 1969system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id 1970system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2682 # Occupied blocks per task id 1971system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6101 # Occupied blocks per task id 1972system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5119 # Occupied blocks per task id 1973system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099548 # Percentage of cache occupancy per task id 1974system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id 1975system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id 1976system.cpu1.l2cache.tags.tag_accesses 350300692 # Number of tag accesses 1977system.cpu1.l2cache.tags.data_accesses 350300692 # Number of data accesses 1978system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 208719 # number of ReadReq hits 1979system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141350 # number of ReadReq hits 1980system.cpu1.l2cache.ReadReq_hits::total 350069 # number of ReadReq hits 1981system.cpu1.l2cache.Writeback_hits::writebacks 3350644 # number of Writeback hits 1982system.cpu1.l2cache.Writeback_hits::total 3350644 # number of Writeback hits 1983system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65287 # number of UpgradeReq hits 1984system.cpu1.l2cache.UpgradeReq_hits::total 65287 # number of UpgradeReq hits 1985system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34260 # number of SCUpgradeReq hits 1986system.cpu1.l2cache.SCUpgradeReq_hits::total 34260 # number of SCUpgradeReq hits 1987system.cpu1.l2cache.ReadExReq_hits::cpu1.data 879078 # number of ReadExReq hits 1988system.cpu1.l2cache.ReadExReq_hits::total 879078 # number of ReadExReq hits 1989system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4680645 # number of ReadCleanReq hits 1990system.cpu1.l2cache.ReadCleanReq_hits::total 4680645 # number of ReadCleanReq hits 1991system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2771065 # number of ReadSharedReq hits 1992system.cpu1.l2cache.ReadSharedReq_hits::total 2771065 # number of ReadSharedReq hits 1993system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 220708 # number of InvalidateReq hits 1994system.cpu1.l2cache.InvalidateReq_hits::total 220708 # number of InvalidateReq hits 1995system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 208719 # number of demand (read+write) hits 1996system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141350 # number of demand (read+write) hits 1997system.cpu1.l2cache.demand_hits::cpu1.inst 4680645 # number of demand (read+write) hits 1998system.cpu1.l2cache.demand_hits::cpu1.data 3650143 # number of demand (read+write) hits 1999system.cpu1.l2cache.demand_hits::total 8680857 # number of demand (read+write) hits 2000system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 208719 # number of overall hits 2001system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141350 # number of overall hits 2002system.cpu1.l2cache.overall_hits::cpu1.inst 4680645 # number of overall hits 2003system.cpu1.l2cache.overall_hits::cpu1.data 3650143 # number of overall hits 2004system.cpu1.l2cache.overall_hits::total 8680857 # number of overall hits 2005system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10729 # number of ReadReq misses 2006system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9390 # number of ReadReq misses 2007system.cpu1.l2cache.ReadReq_misses::total 20119 # number of ReadReq misses 2008system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 125786 # number of UpgradeReq misses 2009system.cpu1.l2cache.UpgradeReq_misses::total 125786 # number of UpgradeReq misses 2010system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 163059 # number of SCUpgradeReq misses 2011system.cpu1.l2cache.SCUpgradeReq_misses::total 163059 # number of SCUpgradeReq misses 2012system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses 2013system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 2014system.cpu1.l2cache.ReadExReq_misses::cpu1.data 237067 # number of ReadExReq misses 2015system.cpu1.l2cache.ReadExReq_misses::total 237067 # number of ReadExReq misses 2016system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 529049 # number of ReadCleanReq misses 2017system.cpu1.l2cache.ReadCleanReq_misses::total 529049 # number of ReadCleanReq misses 2018system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 902850 # number of ReadSharedReq misses 2019system.cpu1.l2cache.ReadSharedReq_misses::total 902850 # number of ReadSharedReq misses 2020system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 257687 # number of InvalidateReq misses 2021system.cpu1.l2cache.InvalidateReq_misses::total 257687 # number of InvalidateReq misses 2022system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10729 # number of demand (read+write) misses 2023system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9390 # number of demand (read+write) misses 2024system.cpu1.l2cache.demand_misses::cpu1.inst 529049 # number of demand (read+write) misses 2025system.cpu1.l2cache.demand_misses::cpu1.data 1139917 # number of demand (read+write) misses 2026system.cpu1.l2cache.demand_misses::total 1689085 # number of demand (read+write) misses 2027system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10729 # number of overall misses 2028system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9390 # number of overall misses 2029system.cpu1.l2cache.overall_misses::cpu1.inst 529049 # number of overall misses 2030system.cpu1.l2cache.overall_misses::cpu1.data 1139917 # number of overall misses 2031system.cpu1.l2cache.overall_misses::total 1689085 # number of overall misses 2032system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 428489500 # number of ReadReq miss cycles 2033system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 413569000 # number of ReadReq miss cycles 2034system.cpu1.l2cache.ReadReq_miss_latency::total 842058500 # number of ReadReq miss cycles 2035system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2736210500 # number of UpgradeReq miss cycles 2036system.cpu1.l2cache.UpgradeReq_miss_latency::total 2736210500 # number of UpgradeReq miss cycles 2037system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3427875000 # number of SCUpgradeReq miss cycles 2038system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3427875000 # number of SCUpgradeReq miss cycles 2039system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2800500 # number of SCUpgradeFailReq miss cycles 2040system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2800500 # number of SCUpgradeFailReq miss cycles 2041system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9388085997 # number of ReadExReq miss cycles 2042system.cpu1.l2cache.ReadExReq_miss_latency::total 9388085997 # number of ReadExReq miss cycles 2043system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15677246500 # number of ReadCleanReq miss cycles 2044system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15677246500 # number of ReadCleanReq miss cycles 2045system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28842829500 # number of ReadSharedReq miss cycles 2046system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28842829500 # number of ReadSharedReq miss cycles 2047system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 12565083500 # number of InvalidateReq miss cycles 2048system.cpu1.l2cache.InvalidateReq_miss_latency::total 12565083500 # number of InvalidateReq miss cycles 2049system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 428489500 # number of demand (read+write) miss cycles 2050system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 413569000 # number of demand (read+write) miss cycles 2051system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15677246500 # number of demand (read+write) miss cycles 2052system.cpu1.l2cache.demand_miss_latency::cpu1.data 38230915497 # number of demand (read+write) miss cycles 2053system.cpu1.l2cache.demand_miss_latency::total 54750220497 # number of demand (read+write) miss cycles 2054system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 428489500 # number of overall miss cycles 2055system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 413569000 # number of overall miss cycles 2056system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15677246500 # number of overall miss cycles 2057system.cpu1.l2cache.overall_miss_latency::cpu1.data 38230915497 # number of overall miss cycles 2058system.cpu1.l2cache.overall_miss_latency::total 54750220497 # number of overall miss cycles 2059system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 219448 # number of ReadReq accesses(hits+misses) 2060system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150740 # number of ReadReq accesses(hits+misses) 2061system.cpu1.l2cache.ReadReq_accesses::total 370188 # number of ReadReq accesses(hits+misses) 2062system.cpu1.l2cache.Writeback_accesses::writebacks 3350644 # number of Writeback accesses(hits+misses) 2063system.cpu1.l2cache.Writeback_accesses::total 3350644 # number of Writeback accesses(hits+misses) 2064system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 191073 # number of UpgradeReq accesses(hits+misses) 2065system.cpu1.l2cache.UpgradeReq_accesses::total 191073 # number of UpgradeReq accesses(hits+misses) 2066system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 197319 # number of SCUpgradeReq accesses(hits+misses) 2067system.cpu1.l2cache.SCUpgradeReq_accesses::total 197319 # number of SCUpgradeReq accesses(hits+misses) 2068system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 2069system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 2070system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116145 # number of ReadExReq accesses(hits+misses) 2071system.cpu1.l2cache.ReadExReq_accesses::total 1116145 # number of ReadExReq accesses(hits+misses) 2072system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5209694 # number of ReadCleanReq accesses(hits+misses) 2073system.cpu1.l2cache.ReadCleanReq_accesses::total 5209694 # number of ReadCleanReq accesses(hits+misses) 2074system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3673915 # number of ReadSharedReq accesses(hits+misses) 2075system.cpu1.l2cache.ReadSharedReq_accesses::total 3673915 # number of ReadSharedReq accesses(hits+misses) 2076system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 478395 # number of InvalidateReq accesses(hits+misses) 2077system.cpu1.l2cache.InvalidateReq_accesses::total 478395 # number of InvalidateReq accesses(hits+misses) 2078system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 219448 # number of demand (read+write) accesses 2079system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150740 # number of demand (read+write) accesses 2080system.cpu1.l2cache.demand_accesses::cpu1.inst 5209694 # number of demand (read+write) accesses 2081system.cpu1.l2cache.demand_accesses::cpu1.data 4790060 # number of demand (read+write) accesses 2082system.cpu1.l2cache.demand_accesses::total 10369942 # number of demand (read+write) accesses 2083system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 219448 # number of overall (read+write) accesses 2084system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150740 # number of overall (read+write) accesses 2085system.cpu1.l2cache.overall_accesses::cpu1.inst 5209694 # number of overall (read+write) accesses 2086system.cpu1.l2cache.overall_accesses::cpu1.data 4790060 # number of overall (read+write) accesses 2087system.cpu1.l2cache.overall_accesses::total 10369942 # number of overall (read+write) accesses 2088system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for ReadReq accesses 2089system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.062293 # miss rate for ReadReq accesses 2090system.cpu1.l2cache.ReadReq_miss_rate::total 0.054348 # miss rate for ReadReq accesses 2091system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.658314 # miss rate for UpgradeReq accesses 2092system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.658314 # miss rate for UpgradeReq accesses 2093system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826373 # miss rate for SCUpgradeReq accesses 2094system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826373 # miss rate for SCUpgradeReq accesses 2095system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2096system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2097system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.212398 # miss rate for ReadExReq accesses 2098system.cpu1.l2cache.ReadExReq_miss_rate::total 0.212398 # miss rate for ReadExReq accesses 2099system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.101551 # miss rate for ReadCleanReq accesses 2100system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.101551 # miss rate for ReadCleanReq accesses 2101system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245746 # miss rate for ReadSharedReq accesses 2102system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245746 # miss rate for ReadSharedReq accesses 2103system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.538649 # miss rate for InvalidateReq accesses 2104system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.538649 # miss rate for InvalidateReq accesses 2105system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for demand accesses 2106system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.062293 # miss rate for demand accesses 2107system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.101551 # miss rate for demand accesses 2108system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.237976 # miss rate for demand accesses 2109system.cpu1.l2cache.demand_miss_rate::total 0.162883 # miss rate for demand accesses 2110system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for overall accesses 2111system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.062293 # miss rate for overall accesses 2112system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.101551 # miss rate for overall accesses 2113system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.237976 # miss rate for overall accesses 2114system.cpu1.l2cache.overall_miss_rate::total 0.162883 # miss rate for overall accesses 2115system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average ReadReq miss latency 2116system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44043.556976 # average ReadReq miss latency 2117system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41853.894329 # average ReadReq miss latency 2118system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21752.901754 # average UpgradeReq miss latency 2119system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21752.901754 # average UpgradeReq miss latency 2120system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21022.298677 # average SCUpgradeReq miss latency 2121system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21022.298677 # average SCUpgradeReq miss latency 2122system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 254590.909091 # average SCUpgradeFailReq miss latency 2123system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 254590.909091 # average SCUpgradeFailReq miss latency 2124system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39600.981988 # average ReadExReq miss latency 2125system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39600.981988 # average ReadExReq miss latency 2126system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 29632.881831 # average ReadCleanReq miss latency 2127system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 29632.881831 # average ReadCleanReq miss latency 2128system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31946.424655 # average ReadSharedReq miss latency 2129system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31946.424655 # average ReadSharedReq miss latency 2130system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 48761.029854 # average InvalidateReq miss latency 2131system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 48761.029854 # average InvalidateReq miss latency 2132system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency 2133system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency 2134system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency 2135system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency 2136system.cpu1.l2cache.demand_avg_miss_latency::total 32414.129838 # average overall miss latency 2137system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency 2138system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency 2139system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency 2140system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency 2141system.cpu1.l2cache.overall_avg_miss_latency::total 32414.129838 # average overall miss latency 2142system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # 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number of HardPFReq MSHR misses 2166system.cpu1.l2cache.HardPFReq_mshr_misses::total 646749 # number of HardPFReq MSHR misses 2167system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 125786 # number of UpgradeReq MSHR misses 2168system.cpu1.l2cache.UpgradeReq_mshr_misses::total 125786 # number of UpgradeReq MSHR misses 2169system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 163059 # number of SCUpgradeReq MSHR misses 2170system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 163059 # number of SCUpgradeReq MSHR misses 2171system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses 2172system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 2173system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 233296 # number of ReadExReq MSHR misses 2174system.cpu1.l2cache.ReadExReq_mshr_misses::total 233296 # number of ReadExReq MSHR misses 2175system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 529049 # number of ReadCleanReq MSHR misses 2176system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 529049 # 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number of UpgradeReq MSHR miss cycles 2207system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2531997500 # number of SCUpgradeReq MSHR miss cycles 2208system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2531997500 # number of SCUpgradeReq MSHR miss cycles 2209system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2434500 # number of SCUpgradeFailReq MSHR miss cycles 2210system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2434500 # number of SCUpgradeFailReq MSHR miss cycles 2211system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7622486997 # number of ReadExReq MSHR miss cycles 2212system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7622486997 # number of ReadExReq MSHR miss cycles 2213system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12502952500 # number of ReadCleanReq MSHR miss cycles 2214system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12502952500 # number of ReadCleanReq MSHR miss cycles 2215system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23395380000 # 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number of overall MSHR miss cycles 2225system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 357229000 # number of overall MSHR miss cycles 2226system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12502952500 # number of overall MSHR miss cycles 2227system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31017866997 # number of overall MSHR miss cycles 2228system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24507257017 # number of overall MSHR miss cycles 2229system.cpu1.l2cache.overall_mshr_miss_latency::total 68749421014 # number of overall MSHR miss cycles 2230system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8914500 # number of ReadReq MSHR uncacheable cycles 2231system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1969997000 # number of ReadReq MSHR uncacheable cycles 2232system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1978911500 # number of ReadReq MSHR uncacheable cycles 2233system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2183909000 # number of WriteReq MSHR uncacheable cycles 2234system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2183909000 # number of WriteReq MSHR uncacheable cycles 2235system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8914500 # number of overall MSHR uncacheable cycles 2236system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4153906000 # number of overall MSHR uncacheable cycles 2237system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4162820500 # number of overall MSHR uncacheable cycles 2238system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for ReadReq accesses 2239system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for ReadReq accesses 2240system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.054348 # mshr miss rate for ReadReq accesses 2241system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2242system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2243system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2244system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2245system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.658314 # mshr miss rate for UpgradeReq accesses 2246system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.658314 # mshr miss rate for UpgradeReq accesses 2247system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826373 # mshr miss rate for SCUpgradeReq accesses 2248system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826373 # mshr miss rate for SCUpgradeReq accesses 2249system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2250system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2251system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.209019 # mshr miss rate for ReadExReq accesses 2252system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.209019 # mshr miss rate for ReadExReq accesses 2253system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for ReadCleanReq accesses 2254system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101551 # mshr miss rate for ReadCleanReq accesses 2255system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245659 # mshr miss rate for ReadSharedReq accesses 2256system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245659 # mshr miss rate for ReadSharedReq accesses 2257system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.538649 # mshr miss rate for InvalidateReq accesses 2258system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.538649 # mshr miss rate for InvalidateReq accesses 2259system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for demand accesses 2260system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for demand accesses 2261system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for demand accesses 2262system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for demand accesses 2263system.cpu1.l2cache.demand_mshr_miss_rate::total 0.162488 # mshr miss rate for demand accesses 2264system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for overall accesses 2265system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for overall accesses 2266system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for overall accesses 2267system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for overall accesses 2268system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2269system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224856 # mshr miss rate for overall accesses 2270system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average ReadReq mshr miss latency 2271system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average ReadReq mshr miss latency 2272system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329 # average ReadReq mshr miss latency 2273system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average HardPFReq mshr miss latency 2274system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609 # average HardPFReq mshr miss latency 2275system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833 # average UpgradeReq mshr miss latency 2276system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833 # average UpgradeReq mshr miss latency 2277system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391 # average SCUpgradeReq mshr miss latency 2278system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391 # average SCUpgradeReq mshr miss latency 2279system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818 # average SCUpgradeFailReq mshr miss latency 2280system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818 # average SCUpgradeFailReq mshr miss latency 2281system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100 # average ReadExReq mshr miss latency 2282system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100 # average ReadExReq mshr miss latency 2283system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average ReadCleanReq mshr miss latency 2284system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831 # average ReadCleanReq mshr miss latency 2285system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053 # average ReadSharedReq mshr miss latency 2286system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053 # average ReadSharedReq mshr miss latency 2287system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854 # average InvalidateReq mshr miss latency 2288system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854 # average InvalidateReq mshr miss latency 2289system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency 2290system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency 2291system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency 2292system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency 2293system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645 # average overall mshr miss latency 2294system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency 2295system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency 2296system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency 2297system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency 2298system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average overall mshr miss latency 2299system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120 # average overall mshr miss latency 2300system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average ReadReq mshr uncacheable latency 2301system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133 # average ReadReq mshr uncacheable latency 2302system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880 # average ReadReq mshr uncacheable latency 2303system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038 # average WriteReq mshr uncacheable latency 2304system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038 # average WriteReq mshr uncacheable latency 2305system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average overall mshr uncacheable latency 2306system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224 # average overall mshr uncacheable latency 2307system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985 # average overall mshr uncacheable latency 2308system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2309system.cpu1.toL2Bus.trans_dist::ReadReq 557907 # Transaction distribution 2310system.cpu1.toL2Bus.trans_dist::ReadResp 9467454 # Transaction distribution 2311system.cpu1.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 2312system.cpu1.toL2Bus.trans_dist::WriteResp 13150 # Transaction distribution 2313system.cpu1.toL2Bus.trans_dist::Writeback 6658964 # Transaction distribution 2314system.cpu1.toL2Bus.trans_dist::CleanEvict 9333240 # Transaction distribution 2315system.cpu1.toL2Bus.trans_dist::HardPFReq 797552 # Transaction distribution 2316system.cpu1.toL2Bus.trans_dist::UpgradeReq 400874 # Transaction distribution 2317system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 357340 # Transaction distribution 2318system.cpu1.toL2Bus.trans_dist::UpgradeResp 454404 # Transaction distribution 2319system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution 2320system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::ReadExReq 1816504 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::ReadExResp 1125838 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5209694 # Transaction distribution 2324system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5632852 # Transaction distribution 2325system.cpu1.toL2Bus.trans_dist::InvalidateReq 585123 # Transaction distribution 2326system.cpu1.toL2Bus.trans_dist::InvalidateResp 478395 # Transaction distribution 2327system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15628224 # Packet count per connected master and slave (bytes) 2328system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16712375 # Packet count per connected master and slave (bytes) 2329system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332083 # Packet count per connected master and slave (bytes) 2330system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 514043 # Packet count per connected master and slave (bytes) 2331system.cpu1.toL2Bus.pkt_count::total 33186725 # Packet count per connected master and slave (bytes) 2332system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333420856 # Cumulative packet size per connected master and slave (bytes) 2333system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 527793939 # Cumulative packet size per connected master and slave (bytes) 2334system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205920 # Cumulative packet size per connected master and slave (bytes) 2335system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1755584 # Cumulative packet size per connected master and slave (bytes) 2336system.cpu1.toL2Bus.pkt_size::total 864176299 # Cumulative packet size per connected master and slave (bytes) 2337system.cpu1.toL2Bus.snoops 9912470 # Total snoops (count) 2338system.cpu1.toL2Bus.snoop_fanout::samples 31389750 # Request fanout histogram 2339system.cpu1.toL2Bus.snoop_fanout::mean 1.322129 # Request fanout histogram 2340system.cpu1.toL2Bus.snoop_fanout::stdev 0.467292 # Request fanout histogram 2341system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2342system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2343system.cpu1.toL2Bus.snoop_fanout::1 21278201 67.79% 67.79% # Request fanout histogram 2344system.cpu1.toL2Bus.snoop_fanout::2 10111549 32.21% 100.00% # Request fanout histogram 2345system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2346system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2347system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2348system.cpu1.toL2Bus.snoop_fanout::total 31389750 # Request fanout histogram 2349system.cpu1.toL2Bus.reqLayer0.occupancy 14234291993 # Layer occupancy (ticks) 2350system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2351system.cpu1.toL2Bus.snoopLayer0.occupancy 190598993 # Layer occupancy (ticks) 2352system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2353system.cpu1.toL2Bus.respLayer0.occupancy 7814651000 # Layer occupancy (ticks) 2354system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2355system.cpu1.toL2Bus.respLayer1.occupancy 7637949368 # Layer occupancy (ticks) 2356system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2357system.cpu1.toL2Bus.respLayer2.occupancy 181343000 # Layer occupancy (ticks) 2358system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2359system.cpu1.toL2Bus.respLayer3.occupancy 294595499 # Layer occupancy (ticks) 2360system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2361system.iobus.trans_dist::ReadReq 40360 # Transaction distribution 2362system.iobus.trans_dist::ReadResp 40360 # Transaction distribution 2363system.iobus.trans_dist::WriteReq 136623 # Transaction distribution 2364system.iobus.trans_dist::WriteResp 136623 # Transaction distribution 2365system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes) 2366system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2367system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2368system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2369system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2370system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2371system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2372system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2373system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2374system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2375system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2376system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2377system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2378system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2379system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2380system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) 2382system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) 2383system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2384system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2385system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) 2386system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes) 2387system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2388system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2389system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2390system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2391system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2392system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2393system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2394system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2395system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2396system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2397system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2398system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2399system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2400system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2401system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes) 2402system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) 2403system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) 2404system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2405system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2406system.iobus.pkt_size::total 7496887 # Cumulative packet size per connected master and slave (bytes) 2407system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks) 2408system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2409system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2410system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2411system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2412system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2413system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2414system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2415system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2416system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2417system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2418system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2419system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2420system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2421system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2422system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2423system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2424system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2425system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2426system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2427system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 2428system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2429system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2430system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2431system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2432system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2433system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2434system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2435system.iobus.reqLayer27.occupancy 569839842 # Layer occupancy (ticks) 2436system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2437system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2438system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2439system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks) 2440system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2441system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) 2442system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2443system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2444system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2445system.iocache.tags.replacements 115629 # number of replacements 2446system.iocache.tags.tagsinuse 11.301329 # Cycle average of tags in use 2447system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2448system.iocache.tags.sampled_refs 115645 # Sample count of references to valid blocks. 2449system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2450system.iocache.tags.warmup_cycle 9148621285000 # Cycle when the warmup percentage was hit. 2451system.iocache.tags.occ_blocks::realview.ethernet 7.403816 # Average occupied blocks per requestor 2452system.iocache.tags.occ_blocks::realview.ide 3.897512 # Average occupied blocks per requestor 2453system.iocache.tags.occ_percent::realview.ethernet 0.462739 # Average percentage of cache occupancy 2454system.iocache.tags.occ_percent::realview.ide 0.243595 # Average percentage of cache occupancy 2455system.iocache.tags.occ_percent::total 0.706333 # Average percentage of cache occupancy 2456system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2457system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2458system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2459system.iocache.tags.tag_accesses 1041045 # Number of tag accesses 2460system.iocache.tags.data_accesses 1041045 # Number of data accesses 2461system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2462system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses 2463system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses 2464system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2465system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2466system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2467system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2468system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2469system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses 2470system.iocache.demand_misses::total 8944 # number of demand (read+write) misses 2471system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2472system.iocache.overall_misses::realview.ide 8904 # number of overall misses 2473system.iocache.overall_misses::total 8944 # number of overall misses 2474system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2475system.iocache.ReadReq_miss_latency::realview.ide 1656855076 # number of ReadReq miss cycles 2476system.iocache.ReadReq_miss_latency::total 1662050076 # number of ReadReq miss cycles 2477system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2478system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2479system.iocache.WriteLineReq_miss_latency::realview.ide 12632251766 # number of WriteLineReq miss cycles 2480system.iocache.WriteLineReq_miss_latency::total 12632251766 # number of WriteLineReq miss cycles 2481system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2482system.iocache.demand_miss_latency::realview.ide 1656855076 # number of demand (read+write) miss cycles 2483system.iocache.demand_miss_latency::total 1662419076 # number of demand (read+write) miss cycles 2484system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2485system.iocache.overall_miss_latency::realview.ide 1656855076 # number of overall miss cycles 2486system.iocache.overall_miss_latency::total 1662419076 # number of overall miss cycles 2487system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2488system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) 2489system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) 2490system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2491system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2492system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2493system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2494system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2495system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses 2496system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses 2497system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2498system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses 2499system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses 2500system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2501system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2502system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2503system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2504system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2505system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2506system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2507system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2508system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2509system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2510system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2511system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2512system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2513system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2514system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288 # average ReadReq miss latency 2515system.iocache.ReadReq_avg_miss_latency::total 185890.848451 # average ReadReq miss latency 2516system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2517system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2518system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707 # average WriteLineReq miss latency 2519system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707 # average WriteLineReq miss latency 2520system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2521system.iocache.demand_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency 2522system.iocache.demand_avg_miss_latency::total 185869.753578 # average overall miss latency 2523system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2524system.iocache.overall_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency 2525system.iocache.overall_avg_miss_latency::total 185869.753578 # average overall miss latency 2526system.iocache.blocked_cycles::no_mshrs 32671 # number of cycles access was blocked 2527system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2528system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked 2529system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2530system.iocache.avg_blocked_cycles::no_mshrs 9.525073 # average number of cycles each access was blocked 2531system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2532system.iocache.fast_writes 0 # number of fast writes performed 2533system.iocache.cache_copies 0 # number of cache copies performed 2534system.iocache.writebacks::writebacks 106695 # number of writebacks 2535system.iocache.writebacks::total 106695 # number of writebacks 2536system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2537system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses 2538system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses 2539system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2540system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2541system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2542system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2543system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2544system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses 2545system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses 2546system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2547system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses 2548system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses 2549system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2550system.iocache.ReadReq_mshr_miss_latency::realview.ide 1211655076 # number of ReadReq MSHR miss cycles 2551system.iocache.ReadReq_mshr_miss_latency::total 1215000076 # number of ReadReq MSHR miss cycles 2552system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2553system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2554system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7295851766 # number of WriteLineReq MSHR miss cycles 2555system.iocache.WriteLineReq_mshr_miss_latency::total 7295851766 # number of WriteLineReq MSHR miss cycles 2556system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2557system.iocache.demand_mshr_miss_latency::realview.ide 1211655076 # number of demand (read+write) MSHR miss cycles 2558system.iocache.demand_mshr_miss_latency::total 1215219076 # number of demand (read+write) MSHR miss cycles 2559system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2560system.iocache.overall_mshr_miss_latency::realview.ide 1211655076 # number of overall MSHR miss cycles 2561system.iocache.overall_mshr_miss_latency::total 1215219076 # number of overall MSHR miss cycles 2562system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2563system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2564system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2565system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2566system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2567system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2568system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2569system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2570system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2571system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2572system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2573system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2574system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2575system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2576system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288 # average ReadReq mshr miss latency 2577system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451 # average ReadReq mshr miss latency 2578system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2579system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2580system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707 # average WriteLineReq mshr miss latency 2581system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707 # average WriteLineReq mshr miss latency 2582system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2583system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency 2584system.iocache.demand_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency 2585system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2586system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency 2587system.iocache.overall_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency 2588system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2589system.l2c.tags.replacements 1275038 # number of replacements 2590system.l2c.tags.tagsinuse 63572.316878 # Cycle average of tags in use 2591system.l2c.tags.total_refs 4892898 # Total number of references to valid blocks. 2592system.l2c.tags.sampled_refs 1334308 # Sample count of references to valid blocks. 2593system.l2c.tags.avg_refs 3.666993 # Average number of references to valid blocks. 2594system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2595system.l2c.tags.occ_blocks::writebacks 18943.726739 # Average occupied blocks per requestor 2596system.l2c.tags.occ_blocks::cpu0.dtb.walker 66.506889 # Average occupied blocks per requestor 2597system.l2c.tags.occ_blocks::cpu0.itb.walker 88.082899 # Average occupied blocks per requestor 2598system.l2c.tags.occ_blocks::cpu0.inst 3576.388780 # Average occupied blocks per requestor 2599system.l2c.tags.occ_blocks::cpu0.data 7769.332592 # Average occupied blocks per requestor 2600system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6333.160086 # Average occupied blocks per requestor 2601system.l2c.tags.occ_blocks::cpu1.dtb.walker 237.192415 # Average occupied blocks per requestor 2602system.l2c.tags.occ_blocks::cpu1.itb.walker 333.040502 # Average occupied blocks per requestor 2603system.l2c.tags.occ_blocks::cpu1.inst 3918.032205 # Average occupied blocks per requestor 2604system.l2c.tags.occ_blocks::cpu1.data 9111.997525 # Average occupied blocks per requestor 2605system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246 # Average occupied blocks per requestor 2606system.l2c.tags.occ_percent::writebacks 0.289058 # Average percentage of cache occupancy 2607system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001015 # Average percentage of cache occupancy 2608system.l2c.tags.occ_percent::cpu0.itb.walker 0.001344 # Average percentage of cache occupancy 2609system.l2c.tags.occ_percent::cpu0.inst 0.054571 # Average percentage of cache occupancy 2610system.l2c.tags.occ_percent::cpu0.data 0.118551 # Average percentage of cache occupancy 2611system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.096636 # Average percentage of cache occupancy 2612system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003619 # Average percentage of cache occupancy 2613system.l2c.tags.occ_percent::cpu1.itb.walker 0.005082 # Average percentage of cache occupancy 2614system.l2c.tags.occ_percent::cpu1.inst 0.059784 # Average percentage of cache occupancy 2615system.l2c.tags.occ_percent::cpu1.data 0.139038 # Average percentage of cache occupancy 2616system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.201338 # Average percentage of cache occupancy 2617system.l2c.tags.occ_percent::total 0.970037 # Average percentage of cache occupancy 2618system.l2c.tags.occ_task_id_blocks::1022 10413 # Occupied blocks per task id 2619system.l2c.tags.occ_task_id_blocks::1023 223 # Occupied blocks per task id 2620system.l2c.tags.occ_task_id_blocks::1024 48634 # Occupied blocks per task id 2621system.l2c.tags.age_task_id_blocks_1022::2 260 # Occupied blocks per task id 2622system.l2c.tags.age_task_id_blocks_1022::3 499 # Occupied blocks per task id 2623system.l2c.tags.age_task_id_blocks_1022::4 9654 # Occupied blocks per task id 2624system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2625system.l2c.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id 2626system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 2627system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 2628system.l2c.tags.age_task_id_blocks_1024::2 1442 # Occupied blocks per task id 2629system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id 2630system.l2c.tags.age_task_id_blocks_1024::4 42029 # Occupied blocks per task id 2631system.l2c.tags.occ_task_id_percent::1022 0.158890 # Percentage of cache occupancy per task id 2632system.l2c.tags.occ_task_id_percent::1023 0.003403 # Percentage of cache occupancy per task id 2633system.l2c.tags.occ_task_id_percent::1024 0.742096 # Percentage of cache occupancy per task id 2634system.l2c.tags.tag_accesses 61952788 # Number of tag accesses 2635system.l2c.tags.data_accesses 61952788 # Number of data accesses 2636system.l2c.Writeback_hits::writebacks 2200570 # number of Writeback hits 2637system.l2c.Writeback_hits::total 2200570 # number of Writeback hits 2638system.l2c.UpgradeReq_hits::cpu0.data 25702 # number of UpgradeReq hits 2639system.l2c.UpgradeReq_hits::cpu1.data 29550 # number of UpgradeReq hits 2640system.l2c.UpgradeReq_hits::total 55252 # number of UpgradeReq hits 2641system.l2c.SCUpgradeReq_hits::cpu0.data 5421 # number of SCUpgradeReq hits 2642system.l2c.SCUpgradeReq_hits::cpu1.data 6216 # number of SCUpgradeReq hits 2643system.l2c.SCUpgradeReq_hits::total 11637 # number of SCUpgradeReq hits 2644system.l2c.ReadExReq_hits::cpu0.data 145994 # number of ReadExReq hits 2645system.l2c.ReadExReq_hits::cpu1.data 170556 # number of ReadExReq hits 2646system.l2c.ReadExReq_hits::total 316550 # number of ReadExReq hits 2647system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4694 # number of ReadSharedReq hits 2648system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3455 # number of ReadSharedReq hits 2649system.l2c.ReadSharedReq_hits::cpu0.inst 439478 # number of ReadSharedReq hits 2650system.l2c.ReadSharedReq_hits::cpu0.data 496055 # number of ReadSharedReq hits 2651system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 255928 # number of ReadSharedReq hits 2652system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5679 # number of ReadSharedReq hits 2653system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4922 # number of ReadSharedReq hits 2654system.l2c.ReadSharedReq_hits::cpu1.inst 484783 # number of ReadSharedReq hits 2655system.l2c.ReadSharedReq_hits::cpu1.data 520043 # number of ReadSharedReq hits 2656system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283587 # number of ReadSharedReq hits 2657system.l2c.ReadSharedReq_hits::total 2498624 # number of ReadSharedReq hits 2658system.l2c.demand_hits::cpu0.dtb.walker 4694 # number of demand (read+write) hits 2659system.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits 2660system.l2c.demand_hits::cpu0.inst 439478 # number of demand (read+write) hits 2661system.l2c.demand_hits::cpu0.data 642049 # number of demand (read+write) hits 2662system.l2c.demand_hits::cpu0.l2cache.prefetcher 255928 # number of demand (read+write) hits 2663system.l2c.demand_hits::cpu1.dtb.walker 5679 # number of demand (read+write) hits 2664system.l2c.demand_hits::cpu1.itb.walker 4922 # number of demand (read+write) hits 2665system.l2c.demand_hits::cpu1.inst 484783 # number of demand (read+write) hits 2666system.l2c.demand_hits::cpu1.data 690599 # number of demand (read+write) hits 2667system.l2c.demand_hits::cpu1.l2cache.prefetcher 283587 # number of demand (read+write) hits 2668system.l2c.demand_hits::total 2815174 # number of demand (read+write) hits 2669system.l2c.overall_hits::cpu0.dtb.walker 4694 # number of overall hits 2670system.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits 2671system.l2c.overall_hits::cpu0.inst 439478 # number of overall hits 2672system.l2c.overall_hits::cpu0.data 642049 # number of overall hits 2673system.l2c.overall_hits::cpu0.l2cache.prefetcher 255928 # number of overall hits 2674system.l2c.overall_hits::cpu1.dtb.walker 5679 # number of overall hits 2675system.l2c.overall_hits::cpu1.itb.walker 4922 # number of overall hits 2676system.l2c.overall_hits::cpu1.inst 484783 # number of overall hits 2677system.l2c.overall_hits::cpu1.data 690599 # number of overall hits 2678system.l2c.overall_hits::cpu1.l2cache.prefetcher 283587 # number of overall hits 2679system.l2c.overall_hits::total 2815174 # number of overall hits 2680system.l2c.UpgradeReq_misses::cpu0.data 41366 # number of UpgradeReq misses 2681system.l2c.UpgradeReq_misses::cpu1.data 45574 # number of UpgradeReq misses 2682system.l2c.UpgradeReq_misses::total 86940 # number of UpgradeReq misses 2683system.l2c.SCUpgradeReq_misses::cpu0.data 9742 # number of SCUpgradeReq misses 2684system.l2c.SCUpgradeReq_misses::cpu1.data 11031 # number of SCUpgradeReq misses 2685system.l2c.SCUpgradeReq_misses::total 20773 # number of SCUpgradeReq misses 2686system.l2c.ReadExReq_misses::cpu0.data 487808 # number of ReadExReq misses 2687system.l2c.ReadExReq_misses::cpu1.data 146598 # number of ReadExReq misses 2688system.l2c.ReadExReq_misses::total 634406 # number of ReadExReq misses 2689system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 811 # number of ReadSharedReq misses 2690system.l2c.ReadSharedReq_misses::cpu0.itb.walker 757 # number of ReadSharedReq misses 2691system.l2c.ReadSharedReq_misses::cpu0.inst 42366 # number of ReadSharedReq misses 2692system.l2c.ReadSharedReq_misses::cpu0.data 114531 # number of ReadSharedReq misses 2693system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq misses 2694system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq misses 2695system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2560 # number of ReadSharedReq misses 2696system.l2c.ReadSharedReq_misses::cpu1.inst 44266 # number of ReadSharedReq misses 2697system.l2c.ReadSharedReq_misses::cpu1.data 108963 # number of ReadSharedReq misses 2698system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq misses 2699system.l2c.ReadSharedReq_misses::total 676832 # number of ReadSharedReq misses 2700system.l2c.demand_misses::cpu0.dtb.walker 811 # number of demand (read+write) misses 2701system.l2c.demand_misses::cpu0.itb.walker 757 # number of demand (read+write) misses 2702system.l2c.demand_misses::cpu0.inst 42366 # number of demand (read+write) misses 2703system.l2c.demand_misses::cpu0.data 602339 # number of demand (read+write) misses 2704system.l2c.demand_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) misses 2705system.l2c.demand_misses::cpu1.dtb.walker 2399 # number of demand (read+write) misses 2706system.l2c.demand_misses::cpu1.itb.walker 2560 # number of demand (read+write) misses 2707system.l2c.demand_misses::cpu1.inst 44266 # number of demand (read+write) misses 2708system.l2c.demand_misses::cpu1.data 255561 # number of demand (read+write) misses 2709system.l2c.demand_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) misses 2710system.l2c.demand_misses::total 1311238 # number of demand (read+write) misses 2711system.l2c.overall_misses::cpu0.dtb.walker 811 # number of overall misses 2712system.l2c.overall_misses::cpu0.itb.walker 757 # number of overall misses 2713system.l2c.overall_misses::cpu0.inst 42366 # number of overall misses 2714system.l2c.overall_misses::cpu0.data 602339 # number of overall misses 2715system.l2c.overall_misses::cpu0.l2cache.prefetcher 184040 # number of overall misses 2716system.l2c.overall_misses::cpu1.dtb.walker 2399 # number of overall misses 2717system.l2c.overall_misses::cpu1.itb.walker 2560 # number of overall misses 2718system.l2c.overall_misses::cpu1.inst 44266 # number of overall misses 2719system.l2c.overall_misses::cpu1.data 255561 # number of overall misses 2720system.l2c.overall_misses::cpu1.l2cache.prefetcher 176139 # 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number of ReadSharedReq miss cycles 2732system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 67955000 # number of ReadSharedReq miss cycles 2733system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3540995500 # number of ReadSharedReq miss cycles 2734system.l2c.ReadSharedReq_miss_latency::cpu0.data 10155548500 # number of ReadSharedReq miss cycles 2735system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of ReadSharedReq miss cycles 2736system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 211977500 # number of ReadSharedReq miss cycles 2737system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 227366000 # number of ReadSharedReq miss cycles 2738system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3707983000 # number of ReadSharedReq miss cycles 2739system.l2c.ReadSharedReq_miss_latency::cpu1.data 9711131500 # number of ReadSharedReq miss cycles 2740system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of ReadSharedReq miss cycles 2741system.l2c.ReadSharedReq_miss_latency::total 68879114830 # number of ReadSharedReq miss cycles 2742system.l2c.demand_miss_latency::cpu0.dtb.walker 72944500 # number of demand (read+write) miss cycles 2743system.l2c.demand_miss_latency::cpu0.itb.walker 67955000 # number of demand (read+write) miss cycles 2744system.l2c.demand_miss_latency::cpu0.inst 3540995500 # number of demand (read+write) miss cycles 2745system.l2c.demand_miss_latency::cpu0.data 51046874000 # number of demand (read+write) miss cycles 2746system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of demand (read+write) miss cycles 2747system.l2c.demand_miss_latency::cpu1.dtb.walker 211977500 # number of demand (read+write) miss cycles 2748system.l2c.demand_miss_latency::cpu1.itb.walker 227366000 # number of demand (read+write) miss cycles 2749system.l2c.demand_miss_latency::cpu1.inst 3707983000 # number of demand (read+write) miss cycles 2750system.l2c.demand_miss_latency::cpu1.data 21620844500 # number of demand (read+write) miss cycles 2751system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of demand (read+write) miss cycles 2752system.l2c.demand_miss_latency::total 121680153330 # number of demand (read+write) miss cycles 2753system.l2c.overall_miss_latency::cpu0.dtb.walker 72944500 # number of overall miss cycles 2754system.l2c.overall_miss_latency::cpu0.itb.walker 67955000 # number of overall miss cycles 2755system.l2c.overall_miss_latency::cpu0.inst 3540995500 # number of overall miss cycles 2756system.l2c.overall_miss_latency::cpu0.data 51046874000 # number of overall miss cycles 2757system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of overall miss cycles 2758system.l2c.overall_miss_latency::cpu1.dtb.walker 211977500 # number of overall miss cycles 2759system.l2c.overall_miss_latency::cpu1.itb.walker 227366000 # number of overall miss cycles 2760system.l2c.overall_miss_latency::cpu1.inst 3707983000 # number of overall miss cycles 2761system.l2c.overall_miss_latency::cpu1.data 21620844500 # number of overall miss cycles 2762system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of overall miss cycles 2763system.l2c.overall_miss_latency::total 121680153330 # number of overall miss cycles 2764system.l2c.Writeback_accesses::writebacks 2200570 # number of Writeback accesses(hits+misses) 2765system.l2c.Writeback_accesses::total 2200570 # number of Writeback accesses(hits+misses) 2766system.l2c.UpgradeReq_accesses::cpu0.data 67068 # number of UpgradeReq accesses(hits+misses) 2767system.l2c.UpgradeReq_accesses::cpu1.data 75124 # number of UpgradeReq accesses(hits+misses) 2768system.l2c.UpgradeReq_accesses::total 142192 # number of UpgradeReq accesses(hits+misses) 2769system.l2c.SCUpgradeReq_accesses::cpu0.data 15163 # number of SCUpgradeReq accesses(hits+misses) 2770system.l2c.SCUpgradeReq_accesses::cpu1.data 17247 # number of SCUpgradeReq accesses(hits+misses) 2771system.l2c.SCUpgradeReq_accesses::total 32410 # number of SCUpgradeReq accesses(hits+misses) 2772system.l2c.ReadExReq_accesses::cpu0.data 633802 # number of ReadExReq accesses(hits+misses) 2773system.l2c.ReadExReq_accesses::cpu1.data 317154 # number of ReadExReq accesses(hits+misses) 2774system.l2c.ReadExReq_accesses::total 950956 # number of ReadExReq accesses(hits+misses) 2775system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5505 # number of ReadSharedReq accesses(hits+misses) 2776system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4212 # number of ReadSharedReq accesses(hits+misses) 2777system.l2c.ReadSharedReq_accesses::cpu0.inst 481844 # number of ReadSharedReq accesses(hits+misses) 2778system.l2c.ReadSharedReq_accesses::cpu0.data 610586 # number of ReadSharedReq accesses(hits+misses) 2779system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 439968 # number of ReadSharedReq accesses(hits+misses) 2780system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8078 # number of ReadSharedReq accesses(hits+misses) 2781system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7482 # number of ReadSharedReq accesses(hits+misses) 2782system.l2c.ReadSharedReq_accesses::cpu1.inst 529049 # number of ReadSharedReq accesses(hits+misses) 2783system.l2c.ReadSharedReq_accesses::cpu1.data 629006 # number of ReadSharedReq accesses(hits+misses) 2784system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 459726 # number of ReadSharedReq accesses(hits+misses) 2785system.l2c.ReadSharedReq_accesses::total 3175456 # number of ReadSharedReq accesses(hits+misses) 2786system.l2c.demand_accesses::cpu0.dtb.walker 5505 # number of demand (read+write) accesses 2787system.l2c.demand_accesses::cpu0.itb.walker 4212 # number of demand (read+write) accesses 2788system.l2c.demand_accesses::cpu0.inst 481844 # number of demand (read+write) accesses 2789system.l2c.demand_accesses::cpu0.data 1244388 # number of demand (read+write) accesses 2790system.l2c.demand_accesses::cpu0.l2cache.prefetcher 439968 # number of demand (read+write) accesses 2791system.l2c.demand_accesses::cpu1.dtb.walker 8078 # number of demand (read+write) accesses 2792system.l2c.demand_accesses::cpu1.itb.walker 7482 # number of demand (read+write) accesses 2793system.l2c.demand_accesses::cpu1.inst 529049 # number of demand (read+write) accesses 2794system.l2c.demand_accesses::cpu1.data 946160 # number of demand (read+write) accesses 2795system.l2c.demand_accesses::cpu1.l2cache.prefetcher 459726 # number of demand (read+write) accesses 2796system.l2c.demand_accesses::total 4126412 # number of demand (read+write) accesses 2797system.l2c.overall_accesses::cpu0.dtb.walker 5505 # number of overall (read+write) accesses 2798system.l2c.overall_accesses::cpu0.itb.walker 4212 # number of overall (read+write) accesses 2799system.l2c.overall_accesses::cpu0.inst 481844 # number of overall (read+write) accesses 2800system.l2c.overall_accesses::cpu0.data 1244388 # number of overall (read+write) accesses 2801system.l2c.overall_accesses::cpu0.l2cache.prefetcher 439968 # number of overall (read+write) accesses 2802system.l2c.overall_accesses::cpu1.dtb.walker 8078 # number of overall (read+write) accesses 2803system.l2c.overall_accesses::cpu1.itb.walker 7482 # number of overall (read+write) accesses 2804system.l2c.overall_accesses::cpu1.inst 529049 # number of overall (read+write) accesses 2805system.l2c.overall_accesses::cpu1.data 946160 # number of overall (read+write) accesses 2806system.l2c.overall_accesses::cpu1.l2cache.prefetcher 459726 # number of overall (read+write) accesses 2807system.l2c.overall_accesses::total 4126412 # number of overall (read+write) accesses 2808system.l2c.UpgradeReq_miss_rate::cpu0.data 0.616777 # miss rate for UpgradeReq accesses 2809system.l2c.UpgradeReq_miss_rate::cpu1.data 0.606650 # miss rate for UpgradeReq accesses 2810system.l2c.UpgradeReq_miss_rate::total 0.611427 # miss rate for UpgradeReq accesses 2811system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.642485 # miss rate for SCUpgradeReq accesses 2812system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639589 # miss rate for SCUpgradeReq accesses 2813system.l2c.SCUpgradeReq_miss_rate::total 0.640944 # miss rate for SCUpgradeReq accesses 2814system.l2c.ReadExReq_miss_rate::cpu0.data 0.769654 # miss rate for ReadExReq accesses 2815system.l2c.ReadExReq_miss_rate::cpu1.data 0.462230 # miss rate for ReadExReq accesses 2816system.l2c.ReadExReq_miss_rate::total 0.667124 # miss rate for ReadExReq accesses 2817system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for ReadSharedReq accesses 2818system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.179725 # miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.087925 # miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187576 # miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for ReadSharedReq accesses 2822system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for ReadSharedReq accesses 2823system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.342155 # miss rate for ReadSharedReq accesses 2824system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.083671 # miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173230 # miss rate for ReadSharedReq accesses 2826system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for ReadSharedReq accesses 2827system.l2c.ReadSharedReq_miss_rate::total 0.213145 # miss rate for ReadSharedReq accesses 2828system.l2c.demand_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for demand accesses 2829system.l2c.demand_miss_rate::cpu0.itb.walker 0.179725 # miss rate for demand accesses 2830system.l2c.demand_miss_rate::cpu0.inst 0.087925 # miss rate for demand accesses 2831system.l2c.demand_miss_rate::cpu0.data 0.484044 # miss rate for demand accesses 2832system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for demand accesses 2833system.l2c.demand_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for demand accesses 2834system.l2c.demand_miss_rate::cpu1.itb.walker 0.342155 # miss rate for demand accesses 2835system.l2c.demand_miss_rate::cpu1.inst 0.083671 # miss rate for demand accesses 2836system.l2c.demand_miss_rate::cpu1.data 0.270103 # miss rate for demand accesses 2837system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for demand accesses 2838system.l2c.demand_miss_rate::total 0.317767 # miss rate for demand accesses 2839system.l2c.overall_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for overall accesses 2840system.l2c.overall_miss_rate::cpu0.itb.walker 0.179725 # miss rate for overall accesses 2841system.l2c.overall_miss_rate::cpu0.inst 0.087925 # miss rate for overall accesses 2842system.l2c.overall_miss_rate::cpu0.data 0.484044 # miss rate for overall accesses 2843system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for overall accesses 2844system.l2c.overall_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for overall accesses 2845system.l2c.overall_miss_rate::cpu1.itb.walker 0.342155 # miss rate for overall accesses 2846system.l2c.overall_miss_rate::cpu1.inst 0.083671 # miss rate for overall accesses 2847system.l2c.overall_miss_rate::cpu1.data 0.270103 # miss rate for overall accesses 2848system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for overall accesses 2849system.l2c.overall_miss_rate::total 0.317767 # miss rate for overall accesses 2850system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5452.666441 # average UpgradeReq miss latency 2851system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5150.634133 # average UpgradeReq miss latency 2852system.l2c.UpgradeReq_avg_miss_latency::total 5294.340925 # average UpgradeReq miss latency 2853system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5023.763088 # average SCUpgradeReq miss latency 2854system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4913.607107 # average SCUpgradeReq miss latency 2855system.l2c.SCUpgradeReq_avg_miss_latency::total 4965.267414 # average SCUpgradeReq miss latency 2856system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83826.680784 # average ReadExReq miss latency 2857system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81240.624019 # average ReadExReq miss latency 2858system.l2c.ReadExReq_avg_miss_latency::total 83229.096982 # average ReadExReq miss latency 2859system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average ReadSharedReq miss latency 2860system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89768.824306 # average ReadSharedReq miss latency 2861system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83581.067365 # average ReadSharedReq miss latency 2862system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88670.739800 # average ReadSharedReq miss latency 2863system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average ReadSharedReq miss latency 2864system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average ReadSharedReq miss latency 2865system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88814.843750 # average ReadSharedReq miss latency 2866system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83765.937740 # average ReadSharedReq miss latency 2867system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89123.202371 # average ReadSharedReq miss latency 2868system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average ReadSharedReq miss latency 2869system.l2c.ReadSharedReq_avg_miss_latency::total 101766.930095 # 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average overall miss latency 2880system.l2c.demand_avg_miss_latency::total 92797.915657 # average overall miss latency 2881system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average overall miss latency 2882system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89768.824306 # average overall miss latency 2883system.l2c.overall_avg_miss_latency::cpu0.inst 83581.067365 # average overall miss latency 2884system.l2c.overall_avg_miss_latency::cpu0.data 84747.748361 # average overall miss latency 2885system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average overall miss latency 2886system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average overall miss latency 2887system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88814.843750 # average overall miss latency 2888system.l2c.overall_avg_miss_latency::cpu1.inst 83765.937740 # average overall miss latency 2889system.l2c.overall_avg_miss_latency::cpu1.data 84601.502185 # average overall miss latency 2890system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average overall miss latency 2891system.l2c.overall_avg_miss_latency::total 92797.915657 # average overall miss latency 2892system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2893system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2894system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2895system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2896system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2897system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2898system.l2c.fast_writes 0 # number of fast writes performed 2899system.l2c.cache_copies 0 # number of cache copies performed 2900system.l2c.writebacks::writebacks 1000989 # number of writebacks 2901system.l2c.writebacks::total 1000989 # number of writebacks 2902system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 84 # number of ReadSharedReq MSHR hits 2903system.l2c.ReadSharedReq_mshr_hits::cpu0.data 16 # number of ReadSharedReq MSHR hits 2904system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 106 # number of ReadSharedReq MSHR hits 2905system.l2c.ReadSharedReq_mshr_hits::cpu1.data 84 # number of ReadSharedReq MSHR hits 2906system.l2c.ReadSharedReq_mshr_hits::total 290 # number of ReadSharedReq MSHR hits 2907system.l2c.demand_mshr_hits::cpu0.inst 84 # number of demand (read+write) MSHR hits 2908system.l2c.demand_mshr_hits::cpu0.data 16 # number of demand (read+write) MSHR hits 2909system.l2c.demand_mshr_hits::cpu1.inst 106 # number of demand (read+write) MSHR hits 2910system.l2c.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits 2911system.l2c.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits 2912system.l2c.overall_mshr_hits::cpu0.inst 84 # number of overall MSHR hits 2913system.l2c.overall_mshr_hits::cpu0.data 16 # number of overall MSHR hits 2914system.l2c.overall_mshr_hits::cpu1.inst 106 # number of overall MSHR hits 2915system.l2c.overall_mshr_hits::cpu1.data 84 # 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number of overall MSHR miss cycles 3010system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187987500 # number of overall MSHR miss cycles 3011system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 201766000 # number of overall MSHR miss cycles 3012system.l2c.overall_mshr_miss_latency::cpu1.inst 3258945500 # number of overall MSHR miss cycles 3013system.l2c.overall_mshr_miss_latency::cpu1.data 19059744500 # number of overall MSHR miss cycles 3014system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17949267061 # number of overall MSHR miss cycles 3015system.l2c.overall_mshr_miss_latency::total 108549581330 # number of overall MSHR miss cycles 3016system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of ReadReq MSHR uncacheable cycles 3017system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3773796500 # number of ReadReq MSHR uncacheable cycles 3018system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6934000 # number of ReadReq MSHR uncacheable cycles 3019system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1744943000 # number of ReadReq MSHR uncacheable cycles 3020system.l2c.ReadReq_mshr_uncacheable_latency::total 8203700500 # number of ReadReq MSHR uncacheable cycles 3021system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3449741500 # number of WriteReq MSHR uncacheable cycles 3022system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1960350500 # number of WriteReq MSHR uncacheable cycles 3023system.l2c.WriteReq_mshr_uncacheable_latency::total 5410092000 # number of WriteReq MSHR uncacheable cycles 3024system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of overall MSHR uncacheable cycles 3025system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7223538000 # number of overall MSHR uncacheable cycles 3026system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6934000 # number of overall MSHR uncacheable cycles 3027system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3705293500 # number of overall MSHR uncacheable cycles 3028system.l2c.overall_mshr_uncacheable_latency::total 13613792500 # number of overall MSHR uncacheable cycles 3029system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3030system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3031system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.616777 # mshr miss rate for UpgradeReq accesses 3032system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.606650 # mshr miss rate for UpgradeReq accesses 3033system.l2c.UpgradeReq_mshr_miss_rate::total 0.611427 # mshr miss rate for UpgradeReq accesses 3034system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.642485 # mshr miss rate for SCUpgradeReq accesses 3035system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639589 # mshr miss rate for SCUpgradeReq accesses 3036system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.640944 # mshr miss rate for SCUpgradeReq accesses 3037system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.769654 # mshr miss rate for ReadExReq accesses 3038system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462230 # mshr miss rate for ReadExReq accesses 3039system.l2c.ReadExReq_mshr_miss_rate::total 0.667124 # mshr miss rate for ReadExReq accesses 3040system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for ReadSharedReq accesses 3041system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for ReadSharedReq accesses 3042system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for ReadSharedReq accesses 3043system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187549 # mshr miss rate for ReadSharedReq accesses 3044system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for ReadSharedReq accesses 3045system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for ReadSharedReq accesses 3046system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for ReadSharedReq accesses 3047system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for ReadSharedReq accesses 3048system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173097 # mshr miss rate for ReadSharedReq accesses 3049system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for ReadSharedReq accesses 3050system.l2c.ReadSharedReq_mshr_miss_rate::total 0.213053 # mshr miss rate for ReadSharedReq accesses 3051system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for demand accesses 3052system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for demand accesses 3053system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for demand accesses 3054system.l2c.demand_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for demand accesses 3055system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for demand accesses 3056system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for demand accesses 3057system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for demand accesses 3058system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for demand accesses 3059system.l2c.demand_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for demand accesses 3060system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for demand accesses 3061system.l2c.demand_mshr_miss_rate::total 0.317697 # mshr miss rate for demand accesses 3062system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for overall accesses 3063system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for overall accesses 3064system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for overall accesses 3065system.l2c.overall_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for overall accesses 3066system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for overall accesses 3067system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for overall accesses 3068system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for overall accesses 3069system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for overall accesses 3070system.l2c.overall_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for overall accesses 3071system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for overall accesses 3072system.l2c.overall_mshr_miss_rate::total 0.317697 # mshr miss rate for overall accesses 3073system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168 # average UpgradeReq mshr miss latency 3074system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918 # average UpgradeReq mshr miss latency 3075system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411 # average UpgradeReq mshr miss latency 3076system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782 # average SCUpgradeReq mshr miss latency 3077system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300 # average SCUpgradeReq mshr miss latency 3078system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566 # average SCUpgradeReq mshr miss latency 3079system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784 # average ReadExReq mshr miss latency 3080system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019 # average ReadExReq mshr miss latency 3081system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982 # average ReadExReq mshr miss latency 3082system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average ReadSharedReq mshr miss latency 3083system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average ReadSharedReq mshr miss latency 3084system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average ReadSharedReq mshr miss latency 3085system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155 # average ReadSharedReq mshr miss latency 3086system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average ReadSharedReq mshr miss latency 3087system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average ReadSharedReq mshr miss latency 3088system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average ReadSharedReq mshr miss latency 3089system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average ReadSharedReq mshr miss latency 3090system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868 # average ReadSharedReq mshr miss latency 3091system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average ReadSharedReq mshr miss latency 3092system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343 # average ReadSharedReq mshr miss latency 3093system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency 3094system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency 3095system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency 3096system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency 3097system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency 3098system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency 3099system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency 3100system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency 3101system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency 3102system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency 3103system.l2c.demand_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency 3104system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency 3105system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency 3106system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency 3107system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency 3108system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency 3109system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency 3110system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency 3111system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency 3112system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency 3113system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency 3114system.l2c.overall_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency 3115system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency 3116system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081 # average ReadReq mshr uncacheable latency 3117system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average ReadReq mshr uncacheable latency 3118system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258 # average ReadReq mshr uncacheable latency 3119system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322 # average ReadReq mshr uncacheable latency 3120system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766 # average WriteReq mshr uncacheable latency 3121system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650 # average WriteReq mshr uncacheable latency 3122system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586 # average WriteReq mshr uncacheable latency 3123system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency 3124system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495 # average overall mshr uncacheable latency 3125system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average overall mshr uncacheable latency 3126system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351 # average overall mshr uncacheable latency 3127system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123 # average overall mshr uncacheable latency 3128system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3129system.membus.trans_dist::ReadReq 81967 # Transaction distribution 3130system.membus.trans_dist::ReadResp 767450 # Transaction distribution 3131system.membus.trans_dist::WriteReq 38603 # Transaction distribution 3132system.membus.trans_dist::WriteResp 38603 # Transaction distribution 3133system.membus.trans_dist::Writeback 1107684 # Transaction distribution 3134system.membus.trans_dist::CleanEvict 202348 # Transaction distribution 3135system.membus.trans_dist::UpgradeReq 391044 # Transaction distribution 3136system.membus.trans_dist::SCUpgradeReq 311393 # Transaction distribution 3137system.membus.trans_dist::UpgradeResp 114065 # Transaction distribution 3138system.membus.trans_dist::ReadExReq 650749 # Transaction distribution 3139system.membus.trans_dist::ReadExResp 628057 # Transaction distribution 3140system.membus.trans_dist::ReadSharedReq 685483 # Transaction distribution 3141system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3142system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3143system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes) 3144system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3145system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26828 # Packet count per connected master and slave (bytes) 3146system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4735959 # Packet count per connected master and slave (bytes) 3147system.membus.pkt_count_system.l2c.mem_side::total 4885501 # Packet count per connected master and slave (bytes) 3148system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342529 # Packet count per connected master and slave (bytes) 3149system.membus.pkt_count_system.iocache.mem_side::total 342529 # Packet count per connected master and slave (bytes) 3150system.membus.pkt_count::total 5228030 # Packet count per connected master and slave (bytes) 3151system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes) 3152system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3153system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53656 # Cumulative packet size per connected master and slave (bytes) 3154system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147705452 # Cumulative packet size per connected master and slave (bytes) 3155system.membus.pkt_size_system.l2c.mem_side::total 147915041 # Cumulative packet size per connected master and slave (bytes) 3156system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264128 # Cumulative packet size per connected master and slave (bytes) 3157system.membus.pkt_size_system.iocache.mem_side::total 7264128 # Cumulative packet size per connected master and slave (bytes) 3158system.membus.pkt_size::total 155179169 # Cumulative packet size per connected master and slave (bytes) 3159system.membus.snoops 613936 # Total snoops (count) 3160system.membus.snoop_fanout::samples 3578377 # Request fanout histogram 3161system.membus.snoop_fanout::mean 1 # Request fanout histogram 3162system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3163system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3164system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3165system.membus.snoop_fanout::1 3578377 100.00% 100.00% # Request fanout histogram 3166system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3167system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3168system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3169system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3170system.membus.snoop_fanout::total 3578377 # Request fanout histogram 3171system.membus.reqLayer0.occupancy 101272500 # Layer occupancy (ticks) 3172system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3173system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 3174system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3175system.membus.reqLayer2.occupancy 23177500 # Layer occupancy (ticks) 3176system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3177system.membus.reqLayer5.occupancy 7575699049 # Layer occupancy (ticks) 3178system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3179system.membus.respLayer2.occupancy 7326536131 # Layer occupancy (ticks) 3180system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3181system.membus.respLayer3.occupancy 229377455 # Layer occupancy (ticks) 3182system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3183system.realview.ethernet.txBytes 966 # Bytes Transmitted 3184system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3185system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3186system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3187system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3188system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3189system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3190system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3191system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3192system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3193system.realview.ethernet.totPackets 3 # Total Packets 3194system.realview.ethernet.totBytes 966 # Total Bytes 3195system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3196system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3197system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3198system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3199system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3200system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3201system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3202system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3203system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3204system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3205system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3206system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3207system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3208system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3209system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3210system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3211system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3212system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3213system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3214system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3215system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3216system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3217system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3218system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3219system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3220system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3221system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3222system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3223system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3224system.realview.ethernet.droppedPackets 0 # number of packets dropped 3225system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3226system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3227system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3228system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3229system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3230system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3231system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3232system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3233system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3234system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3235system.toL2Bus.trans_dist::ReadReq 81969 # Transaction distribution 3236system.toL2Bus.trans_dist::ReadResp 4074898 # Transaction distribution 3237system.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 3238system.toL2Bus.trans_dist::WriteResp 38603 # Transaction distribution 3239system.toL2Bus.trans_dist::Writeback 3308322 # Transaction distribution 3240system.toL2Bus.trans_dist::CleanEvict 1226405 # Transaction distribution 3241system.toL2Bus.trans_dist::UpgradeReq 439947 # Transaction distribution 3242system.toL2Bus.trans_dist::SCUpgradeReq 323030 # Transaction distribution 3243system.toL2Bus.trans_dist::UpgradeResp 762977 # Transaction distribution 3244system.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution 3245system.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 3246system.toL2Bus.trans_dist::ReadExReq 1086983 # Transaction distribution 3247system.toL2Bus.trans_dist::ReadExResp 1086983 # Transaction distribution 3248system.toL2Bus.trans_dist::ReadSharedReq 4000171 # Transaction distribution 3249system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3250system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7169000 # Packet count per connected master and slave (bytes) 3251system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6360157 # Packet count per connected master and slave (bytes) 3252system.toL2Bus.pkt_count::total 13529157 # Packet count per connected master and slave (bytes) 3253system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 219530790 # Cumulative packet size per connected master and slave (bytes) 3254system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185908027 # Cumulative packet size per connected master and slave (bytes) 3255system.toL2Bus.pkt_size::total 405438817 # Cumulative packet size per connected master and slave (bytes) 3256system.toL2Bus.snoops 3048406 # Total snoops (count) 3257system.toL2Bus.snoop_fanout::samples 11669556 # Request fanout histogram 3258system.toL2Bus.snoop_fanout::mean 1.129089 # Request fanout histogram 3259system.toL2Bus.snoop_fanout::stdev 0.335298 # Request fanout histogram 3260system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3261system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3262system.toL2Bus.snoop_fanout::1 10163148 87.09% 87.09% # Request fanout histogram 3263system.toL2Bus.snoop_fanout::2 1506408 12.91% 100.00% # Request fanout histogram 3264system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3265system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3266system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3267system.toL2Bus.snoop_fanout::total 11669556 # Request fanout histogram 3268system.toL2Bus.reqLayer0.occupancy 7690985653 # Layer occupancy (ticks) 3269system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3270system.toL2Bus.snoopLayer0.occupancy 2550000 # Layer occupancy (ticks) 3271system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3272system.toL2Bus.respLayer0.occupancy 4244781764 # Layer occupancy (ticks) 3273system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3274system.toL2Bus.respLayer1.occupancy 3859650249 # Layer occupancy (ticks) 3275system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3276 3277---------- End Simulation Statistics ---------- 3278