stats.txt revision 11860
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 47.401371 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 47401370587500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 1122973 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 1337206 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 65940331964 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 757896 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 718.85 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 807251718 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 961253990 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory 2611860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory 2811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 51897028 # Number of bytes read from this memory 2911860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory 3011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory 3111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory 3211860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 70880488 # Number of bytes written to this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory 3811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory 3911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory 4011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory 4111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory 4211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory 4311860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory 4411860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory 4511860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory 4611860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory 4711860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 815412 # Number of read requests responded to by this memory 4811860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory 5211860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s) 5611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s) 5711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s) 5811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) 5911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s) 6011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s) 6111860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s) 6211860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s) 6311860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s) 6411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s) 6511860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s) 6611860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s) 6711860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s) 7111860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s) 7211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s) 7311860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s) 7411860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s) 7511860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s) 7611860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s) 7711860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s) 7811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) 7911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s) 8011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s) 8111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s) 8211860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s) 8311860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s) 8411860Sandreas.hansson@arm.comsystem.physmem.readReqs 815412 # Number of read requests accepted 8511860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1109760 # Number of write requests accepted 8611860Sandreas.hansson@arm.comsystem.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue 8711860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue 8811860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM 8911860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue 9011860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM 9111860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side 9211860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side 9311860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue 9411860Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 50443 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 58279 # Per bank write bursts 9811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 46176 # Per bank write bursts 9911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 52637 # Per bank write bursts 10011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 47826 # Per bank write bursts 10111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 55648 # Per bank write bursts 10211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 52176 # Per bank write bursts 10311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 51274 # Per bank write bursts 10411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 44248 # Per bank write bursts 10511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 55412 # Per bank write bursts 10611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43487 # Per bank write bursts 10711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 55151 # Per bank write bursts 10811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 50800 # Per bank write bursts 10911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 57431 # Per bank write bursts 11011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 46539 # Per bank write bursts 11111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 47507 # Per bank write bursts 11211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 68734 # Per bank write bursts 11311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 74075 # Per bank write bursts 11411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 65910 # Per bank write bursts 11511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 69531 # Per bank write bursts 11611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 66080 # Per bank write bursts 11711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 73115 # Per bank write bursts 11811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 69817 # Per bank write bursts 11911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 69743 # Per bank write bursts 12011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 63555 # Per bank write bursts 12111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 71485 # Per bank write bursts 12211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 64662 # Per bank write bursts 12311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 72406 # Per bank write bursts 12411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 68380 # Per bank write bursts 12511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 74722 # Per bank write bursts 12611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 65945 # Per bank write bursts 12711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 69295 # Per bank write bursts 12810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 463 # Number of times write queue was full causing retry 13011860Sandreas.hansson@arm.comsystem.physmem.totGap 47401367297000 # Total gap between requests 13110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13311860Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 4795 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 810587 # Read request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1107186 # Write request sizes (log2) 14511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see 14611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see 14711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see 14811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see 14911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see 15011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see 15111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see 15211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see 15311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see 15411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see 15511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see 15611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 789 # What read queue length does an incoming req see 15711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 635 # What read queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 471 # What read queue length does an incoming req see 15911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 255 # What read queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 170 # What read queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 27848 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 35713 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 46446 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 51674 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 57512 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 59733 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 61607 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 63717 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 66102 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 66334 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 69492 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 71245 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 67739 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 66506 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 67172 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 70520 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 64778 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 61855 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3835 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1949 # What write queue length does an incoming req see 21211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1570 # What write queue length does an incoming req see 21311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see 21411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see 21511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see 21611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see 21711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see 21811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see 21911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see 22011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see 22111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see 22211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see 22311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see 22411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see 22511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see 22611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see 22711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see 22811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see 22911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see 23011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see 23111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see 23211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see 23311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see 23411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see 23511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see 23611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see 23711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see 23811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see 23911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see 24011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see 24111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation 24211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation 24311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation 24411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation 24511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation 24611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation 24711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation 24811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation 24911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation 25011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation 25111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation 25211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation 25311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation 25411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation 25511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes 25611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes 25711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes 25811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes 25911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes 26011860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes 26111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 26211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes 26311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes 26411860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads 26711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads 26811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads 26911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads 27011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads 27111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads 27211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads 27311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads 27411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads 27511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads 27611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads 27711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads 27811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads 27911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads 28011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads 28111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads 28211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads 28311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads 28411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads 28511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads 28611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads 28711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads 28811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads 28911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads 29011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads 29111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads 29211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads 29311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads 29411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads 29511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads 29611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads 29711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads 29811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads 29911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads 30011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads 30111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads 30211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads 30311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads 30411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads 30511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads 30611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads 30711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads 30811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads 30911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads 31011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads 31111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 31211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads 31311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads 31411860Sandreas.hansson@arm.comsystem.physmem.totQLat 43191913053 # Total ticks spent queuing 31511860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM 31611860Sandreas.hansson@arm.comsystem.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers 31711860Sandreas.hansson@arm.comsystem.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst 31810515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31911860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst 32011860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s 32111860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s 32211860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s 32311860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s 32410515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32511374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32611201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32710892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32811754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing 32911860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing 33011860Sandreas.hansson@arm.comsystem.physmem.readRowHits 599171 # Number of row buffer hits during reads 33111860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 461094 # Number of row buffer hits during writes 33211860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads 33311860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes 33411860Sandreas.hansson@arm.comsystem.physmem.avgGap 24621886.93 # Average gap between requests 33511860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined 33611860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ) 33711860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ) 33811860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ) 33911860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ) 34011860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ) 34111860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ) 34211860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ) 34311860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ) 34411860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ) 34511860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ) 34611860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ) 34711860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 242.857940 # Core power per rank (mW) 34811860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank 34911860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states 35011860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states 35111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states 35211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states 35311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states 35411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states 35511860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ) 35611860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ) 35711860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ) 35811860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ) 35911860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ) 36011860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ) 36111860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ) 36211860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ) 36311860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ) 36411860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ) 36511860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ) 36611860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.880926 # Core power per rank (mW) 36711860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank 36811860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states 36911860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states 37011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states 37111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states 37211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states 37311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states 37411860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 37510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 37610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 37710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 37810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 37910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 38010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 38110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 38210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 38310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 38410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 38510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 38610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 38710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 38810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 38910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 39010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 39110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 39210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 39310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 39410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 39510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 39610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 39710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 39810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 39910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 40010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 40111860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 40211860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 40311860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 40410535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 40510535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 40610535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 40711680SCurtis.Dunham@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 40811680SCurtis.Dunham@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 40911680SCurtis.Dunham@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 41010515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 41111860Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 41210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 42010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 42210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 42310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 42410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 42510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 43010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 43110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 43210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 43310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 43410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 43510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 44010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 44111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 44211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 92556 # Table walker walks requested 44311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors 44411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate 44511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate 44611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting 44711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency 44811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency 44911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency 45011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency 45111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 45211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency 45311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency 45411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency 45511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency 45611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency 45711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency 45811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency 45911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency 46011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency 46111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency 46211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency 46311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 46411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 46511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 46611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency 46711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution 46811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution 46911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution 47011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution 47111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution 47211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution 47311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated 47411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated 47511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated 47611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst 47710628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst 47911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst 48010628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst 48211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst 48310535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 48410535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 48511860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 77415423 # DTB read hits 48611860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 69730 # DTB read misses 48711860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 70114940 # DTB write hits 48811860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 22826 # DTB write misses 48910535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 49010535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49111860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 49211860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 49311860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB 49410535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49511860Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch 49610535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 49711860Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions 49811860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 77485153 # DTB read accesses 49911860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 70137766 # DTB write accesses 50010535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 50111860Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 147530363 # DTB hits 50211860Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 92556 # DTB misses 50311860Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 147622919 # DTB accesses 50411860Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 50510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 50610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 50710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 50810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 51110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 51210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 51510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 51810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 52010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 52510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 52610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 52710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 53010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 53110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 53210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 53310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 53411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 53511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 51144 # Table walker walks requested 53611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors 53711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate 53811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate 53911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency 54011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency 54111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency 54211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency 54311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency 54411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency 54511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency 54611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency 54711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency 54811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency 54911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency 55011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency 55111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency 55211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency 55311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency 55411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency 55511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 55611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency 55711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution 55811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution 55911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution 56011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated 56111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated 56211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated 56310628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst 56511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst 56610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 56711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst 56811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst 56911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst 57011860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 385005651 # ITB inst hits 57111860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 51144 # ITB inst misses 57210535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 57310535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 57410535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 57510535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 57610535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 57710535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57811860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 57911860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 58011860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB 58110535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58210535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58310535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58410535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 58510535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 58610535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 58711860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 385056795 # ITB inst accesses 58811860Sandreas.hansson@arm.comsystem.cpu0.itb.hits 385005651 # DTB hits 58911860Sandreas.hansson@arm.comsystem.cpu0.itb.misses 51144 # DTB misses 59011860Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 385056795 # DTB accesses 59111860Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 8306 # Number of power state transitions 59211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state 59311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state 59411860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state 59511860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state 59611860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state 59711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state 59811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state 59911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 60011860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state 60111860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state 60211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state 60311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 60411860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state 60511860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 60611860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state 60711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state 60811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states 60911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states 61011860Sandreas.hansson@arm.comsystem.cpu0.numCycles 94802741175 # number of cpu cycles simulated 61110535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61210535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61311167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 61411860Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed 61511860Sandreas.hansson@arm.comsystem.cpu0.committedInsts 384730653 # Number of instructions committed 61611860Sandreas.hansson@arm.comsystem.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed 61711860Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses 61811860Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses 61911860Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 24795410 # number of times a function call or return occured 62011860Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls 62111860Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 424236423 # number of integer instructions 62211860Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 341428 # number of float instructions 62311860Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read 62411860Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written 62511860Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read 62611860Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written 62711860Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read 62811860Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written 62911860Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 147523428 # number of memory refs 63011860Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 77412307 # Number of load instructions 63111860Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 70111121 # Number of store instructions 63211860Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles 63311860Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles 63411860Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles 63511860Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.989623 # Percentage of idle cycles 63611860Sandreas.hansson@arm.comsystem.cpu0.Branches 84896632 # Number of branches fetched 63711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 63811860Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction 63911860Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction 64011860Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction 64111860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction 64211860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction 64311860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction 64411860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction 64511860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction 64611860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction 64711860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction 64811860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction 64911860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction 65011860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction 65111860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction 65211860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction 65311860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction 65411860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction 65511860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction 65611860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction 65711860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction 65811860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction 65911860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction 66011860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction 66111860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction 66211860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction 66311860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction 66411860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction 66511860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction 66611860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction 66711860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction 66811860Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction 66911860Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction 67011860Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction 67111860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction 67211860Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction 67310535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 67410535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 67511860Sandreas.hansson@arm.comsystem.cpu0.op_class::total 456691600 # Class of executed instruction 67611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 67711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5013046 # number of replacements 67811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use 67911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks. 68011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks. 68111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks. 68211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit. 68311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor 68411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy 68511860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy 68611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 68711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 68811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 68911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 69011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 69111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 69211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses 69311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses 69411860Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 69511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits 69611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits 69711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits 69811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits 69911860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits 70011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits 70111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits 70211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits 70311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits 70411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits 70511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits 70611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits 70711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits 70811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits 70911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits 71011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 138639484 # number of overall hits 71111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses 71211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses 71311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses 71411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses 71511860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses 71611860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses 71711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses 71811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses 71911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses 72011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses 72111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses 72211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses 72311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses 72411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses 72511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses 72611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5260909 # number of overall misses 72711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles 72811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles 72911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles 73011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles 73111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles 73211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles 73311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles 73411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles 73511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles 73611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles 73711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles 73811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles 73911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles 74011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles 74111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles 74211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles 74311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses) 74411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses) 74511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses) 74611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses) 74711860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses) 74811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses) 74911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses) 75011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses) 75111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses) 75211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses) 75311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses) 75411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses) 75511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses 75611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses 75711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses 75811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses 75911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses 76011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses 76111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses 76211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses 76311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses 76411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses 76511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses 76611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses 76711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses 76811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses 76911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses 77011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses 77111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses 77211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses 77311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses 77411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses 77511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency 77611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency 77711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency 77811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency 77911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency 78011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency 78111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency 78211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency 78311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency 78411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency 78510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 78610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 78711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency 78811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency 78911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency 79011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency 79110535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 79210535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 79310535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 79410535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 79510535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 79610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 79711860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks 79811860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5013046 # number of writebacks 79911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits 80011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits 80111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits 80211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits 80311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits 80411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits 80511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits 80611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits 80711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits 80811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits 80911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses 81011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses 81111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses 81211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses 81311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses 81411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses 81511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses 81611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses 81711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses 81811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses 81911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses 82011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses 82111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses 82211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses 82311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses 82411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses 82511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 82611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable 82711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 82811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable 82911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 83011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses 83111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles 83211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles 83311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles 83411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles 83511860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles 83611860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles 83711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles 83811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles 83911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles 84011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles 84111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles 84211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles 84311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles 84411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles 84511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles 84611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles 84711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles 84811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles 84911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles 85011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles 85111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles 85211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles 85311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses 85411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses 85511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses 85611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses 85711860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses 85811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses 85911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses 86011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses 86111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses 86211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses 86311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses 86411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses 86511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses 86611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses 86711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses 86811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses 86911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency 87011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency 87111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency 87211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency 87311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency 87411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency 87511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency 87611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency 87711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency 87811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency 87911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency 88011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency 88110535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 88210535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 88311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency 88411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency 88511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency 88611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency 88711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency 88811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency 88911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency 89011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency 89111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 89211860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 4327935 # number of replacements 89311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use 89411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks. 89511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks. 89611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks. 89711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit. 89811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor 89911860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy 90011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy 90110535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 90211860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 90311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 90411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 90511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 90610535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 90711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses 90811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses 90911860Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 91011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits 91111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits 91211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 380677204 # number of demand (read+write) hits 91311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits 91411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 380677204 # number of overall hits 91511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 380677204 # number of overall hits 91611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4328447 # number of ReadReq misses 91711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses 91811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4328447 # number of demand (read+write) misses 91911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses 92011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4328447 # number of overall misses 92111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 4328447 # number of overall misses 92211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47943054500 # number of ReadReq miss cycles 92311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles 92411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles 92511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles 92611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles 92711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles 92811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 385005651 # number of ReadReq accesses(hits+misses) 92911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses) 93011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses 93111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses 93211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 385005651 # number of overall (read+write) accesses 93311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses 93411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses 93511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses 93611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses 93711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses 93811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses 93911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses 94011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency 94111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency 94211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency 94311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency 94411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency 94511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency 94610535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 94710535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94810535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94910535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 95010535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 95110535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 95211860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks 95311860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 4327935 # number of writebacks 95411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses 95511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses 95611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses 95711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses 95811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses 95911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses 96011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 96111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable 96211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 96311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses 96411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45778831000 # number of ReadReq MSHR miss cycles 96511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 45778831000 # number of ReadReq MSHR miss cycles 96611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45778831000 # number of demand (read+write) MSHR miss cycles 96711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 45778831000 # number of demand (read+write) MSHR miss cycles 96811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45778831000 # number of overall MSHR miss cycles 96911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 45778831000 # number of overall MSHR miss cycles 97011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 463686000 # number of ReadReq MSHR uncacheable cycles 97111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 463686000 # number of ReadReq MSHR uncacheable cycles 97211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 463686000 # number of overall MSHR uncacheable cycles 97311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 463686000 # number of overall MSHR uncacheable cycles 97411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for ReadReq accesses 97511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011243 # mshr miss rate for ReadReq accesses 97611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for demand accesses 97711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.011243 # mshr miss rate for demand accesses 97811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for overall accesses 97911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.011243 # mshr miss rate for overall accesses 98011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average ReadReq mshr miss latency 98111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10576.271582 # average ReadReq mshr miss latency 98211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency 98311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency 98411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency 98511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency 98611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average ReadReq mshr uncacheable latency 98711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98134.603175 # average ReadReq mshr uncacheable latency 98811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average overall mshr uncacheable latency 98911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98134.603175 # average overall mshr uncacheable latency 99011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 99111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7077148 # number of hwpf issued 99211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7077156 # number of prefetch candidates identified 99311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 99410628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 99510628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 99611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 919708 # number of prefetches not generated due to page crossing 99711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 99811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2034832 # number of replacements 99911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15580.971228 # Cycle average of tags in use 100011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 7927218 # Total number of references to valid blocks. 100111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2050121 # Sample count of references to valid blocks. 100211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.866707 # Average number of references to valid blocks. 100311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1712003500 # Cycle when the warmup percentage was hit. 100411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15267.042973 # Average occupied blocks per requestor 100511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.154482 # Average occupied blocks per requestor 100611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 11.284107 # Average occupied blocks per requestor 100711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 280.489666 # Average occupied blocks per requestor 100811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.931826 # Average percentage of cache occupancy 100911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001352 # Average percentage of cache occupancy 101011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000689 # Average percentage of cache occupancy 101111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.017120 # Average percentage of cache occupancy 101211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.950987 # Average percentage of cache occupancy 101311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 305 # Occupied blocks per task id 101411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 101511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14912 # Occupied blocks per task id 101611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 65 # Occupied blocks per task id 101711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id 101811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 131 # Occupied blocks per task id 101911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 102011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 102111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 102211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 102311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 102411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 540 # Occupied blocks per task id 102511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4190 # Occupied blocks per task id 102611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7117 # Occupied blocks per task id 102711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2983 # Occupied blocks per task id 102811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018616 # Percentage of cache occupancy per task id 102911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 103011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.910156 # Percentage of cache occupancy per task id 103111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 322659786 # Number of tag accesses 103211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 322659786 # Number of data accesses 103311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 103411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 205975 # number of ReadReq hits 103511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128170 # number of ReadReq hits 103611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 334145 # number of ReadReq hits 103711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3330860 # number of WritebackDirty hits 103811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3330860 # number of WritebackDirty hits 103911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6009144 # number of WritebackClean hits 104011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6009144 # number of WritebackClean hits 104111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 802570 # number of ReadExReq hits 104211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 802570 # number of ReadExReq hits 104311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 3917036 # number of ReadCleanReq hits 104411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 3917036 # number of ReadCleanReq hits 104511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2528867 # number of ReadSharedReq hits 104611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2528867 # number of ReadSharedReq hits 104711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164054 # number of InvalidateReq hits 104811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 164054 # number of InvalidateReq hits 104911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 205975 # number of demand (read+write) hits 105011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 128170 # number of demand (read+write) hits 105111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 3917036 # number of demand (read+write) hits 105211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3331437 # number of demand (read+write) hits 105311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 7582618 # number of demand (read+write) hits 105411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 205975 # number of overall hits 105511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 128170 # number of overall hits 105611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 3917036 # number of overall hits 105711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3331437 # number of overall hits 105811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 7582618 # number of overall hits 105911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 15216 # number of ReadReq misses 106011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8071 # number of ReadReq misses 106111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 23287 # number of ReadReq misses 106211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 218667 # number of UpgradeReq misses 106311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 218667 # number of UpgradeReq misses 106411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 191059 # number of SCUpgradeReq misses 106511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 191059 # number of SCUpgradeReq misses 106611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 106711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 106811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 228793 # number of ReadExReq misses 106911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 228793 # number of ReadExReq misses 107011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 411411 # number of ReadCleanReq misses 107111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 411411 # number of ReadCleanReq misses 107211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 830772 # number of ReadSharedReq misses 107311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 830772 # number of ReadSharedReq misses 107411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 558166 # number of InvalidateReq misses 107511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 558166 # number of InvalidateReq misses 107611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 15216 # number of demand (read+write) misses 107711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8071 # number of demand (read+write) misses 107811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 411411 # number of demand (read+write) misses 107911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1059565 # number of demand (read+write) misses 108011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1494263 # number of demand (read+write) misses 108111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 15216 # number of overall misses 108211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8071 # number of overall misses 108311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 411411 # number of overall misses 108411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1059565 # number of overall misses 108511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1494263 # number of overall misses 108611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 436278500 # number of ReadReq miss cycles 108711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 272723500 # number of ReadReq miss cycles 108811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 709002000 # number of ReadReq miss cycles 108911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 867672000 # number of UpgradeReq miss cycles 109011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 867672000 # number of UpgradeReq miss cycles 109111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 318347000 # number of SCUpgradeReq miss cycles 109211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 318347000 # number of SCUpgradeReq miss cycles 109311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2656998 # number of SCUpgradeFailReq miss cycles 109411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2656998 # number of SCUpgradeFailReq miss cycles 109511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12612589500 # number of ReadExReq miss cycles 109611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12612589500 # number of ReadExReq miss cycles 109711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15771055500 # number of ReadCleanReq miss cycles 109811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 15771055500 # number of ReadCleanReq miss cycles 109911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30943358500 # number of ReadSharedReq miss cycles 110011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 30943358500 # number of ReadSharedReq miss cycles 110111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 436278500 # number of demand (read+write) miss cycles 110211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 272723500 # number of demand (read+write) miss cycles 110311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 15771055500 # number of demand (read+write) miss cycles 110411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 43555948000 # number of demand (read+write) miss cycles 110511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 60036005500 # number of demand (read+write) miss cycles 110611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 436278500 # number of overall miss cycles 110711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 272723500 # number of overall miss cycles 110811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 15771055500 # number of overall miss cycles 110911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 43555948000 # number of overall miss cycles 111011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 60036005500 # number of overall miss cycles 111111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221191 # number of ReadReq accesses(hits+misses) 111211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136241 # number of ReadReq accesses(hits+misses) 111311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 357432 # number of ReadReq accesses(hits+misses) 111411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3330860 # number of WritebackDirty accesses(hits+misses) 111511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3330860 # number of WritebackDirty accesses(hits+misses) 111611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6009144 # number of WritebackClean accesses(hits+misses) 111711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6009144 # number of WritebackClean accesses(hits+misses) 111811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218667 # number of UpgradeReq accesses(hits+misses) 111911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 218667 # number of UpgradeReq accesses(hits+misses) 112011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191059 # number of SCUpgradeReq accesses(hits+misses) 112111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 191059 # number of SCUpgradeReq accesses(hits+misses) 112211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 112311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 112411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1031363 # number of ReadExReq accesses(hits+misses) 112511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1031363 # number of ReadExReq accesses(hits+misses) 112611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4328447 # number of ReadCleanReq accesses(hits+misses) 112711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4328447 # number of ReadCleanReq accesses(hits+misses) 112811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3359639 # number of ReadSharedReq accesses(hits+misses) 112911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3359639 # number of ReadSharedReq accesses(hits+misses) 113011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 722220 # number of InvalidateReq accesses(hits+misses) 113111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 722220 # number of InvalidateReq accesses(hits+misses) 113211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221191 # number of demand (read+write) accesses 113311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136241 # number of demand (read+write) accesses 113411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4328447 # number of demand (read+write) accesses 113511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4391002 # number of demand (read+write) accesses 113611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 9076881 # number of demand (read+write) accesses 113711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221191 # number of overall (read+write) accesses 113811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136241 # number of overall (read+write) accesses 113911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4328447 # number of overall (read+write) accesses 114011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4391002 # number of overall (read+write) accesses 114111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 9076881 # number of overall (read+write) accesses 114211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for ReadReq accesses 114311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059241 # miss rate for ReadReq accesses 114411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.065151 # miss rate for ReadReq accesses 114511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 114611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 114711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 114811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 114910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 115010535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 115111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.221836 # miss rate for ReadExReq accesses 115211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.221836 # miss rate for ReadExReq accesses 115311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.095048 # miss rate for ReadCleanReq accesses 115411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.095048 # miss rate for ReadCleanReq accesses 115511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247280 # miss rate for ReadSharedReq accesses 115611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247280 # miss rate for ReadSharedReq accesses 115711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772848 # miss rate for InvalidateReq accesses 115811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772848 # miss rate for InvalidateReq accesses 115911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for demand accesses 116011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059241 # miss rate for demand accesses 116111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.095048 # miss rate for demand accesses 116211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241304 # miss rate for demand accesses 116311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.164623 # miss rate for demand accesses 116411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for overall accesses 116511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059241 # miss rate for overall accesses 116611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.095048 # miss rate for overall accesses 116711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241304 # miss rate for overall accesses 116811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.164623 # miss rate for overall accesses 116911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average ReadReq miss latency 117011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33790.546401 # average ReadReq miss latency 117111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 30446.257569 # average ReadReq miss latency 117211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3968.006146 # average UpgradeReq miss latency 117311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3968.006146 # average UpgradeReq miss latency 117411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1666.223523 # average SCUpgradeReq miss latency 117511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1666.223523 # average SCUpgradeReq miss latency 117611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 442833 # average SCUpgradeFailReq miss latency 117711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 442833 # average SCUpgradeFailReq miss latency 117811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55126.640675 # average ReadExReq miss latency 117911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55126.640675 # average ReadExReq miss latency 118011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38334.063746 # average ReadCleanReq miss latency 118111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38334.063746 # average ReadCleanReq miss latency 118211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37246.511076 # average ReadSharedReq miss latency 118311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37246.511076 # average ReadSharedReq miss latency 118411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency 118511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency 118611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency 118711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency 118811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 40177.669861 # average overall miss latency 118911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency 119011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency 119111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency 119211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency 119311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 40177.669861 # average overall miss latency 119410628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 119510535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119610628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 119710535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 119810628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 119910535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.unused_prefetches 34479 # number of HardPF blocks evicted w/o reference 120111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1361012 # number of writebacks 120211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1361012 # number of writebacks 120311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5370 # number of ReadExReq MSHR hits 120411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5370 # number of ReadExReq MSHR hits 120511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 489 # number of ReadSharedReq MSHR hits 120611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 489 # number of ReadSharedReq MSHR hits 120711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5859 # number of demand (read+write) MSHR hits 120811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5859 # number of demand (read+write) MSHR hits 120911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5859 # number of overall MSHR hits 121011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5859 # number of overall MSHR hits 121111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 15216 # number of ReadReq MSHR misses 121211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8071 # number of ReadReq MSHR misses 121311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 23287 # number of ReadReq MSHR misses 121411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of HardPFReq MSHR misses 121511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 675054 # number of HardPFReq MSHR misses 121611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 218667 # number of UpgradeReq MSHR misses 121711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 218667 # number of UpgradeReq MSHR misses 121811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 191059 # number of SCUpgradeReq MSHR misses 121911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 191059 # number of SCUpgradeReq MSHR misses 122011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 122111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 122211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 223423 # number of ReadExReq MSHR misses 122311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 223423 # number of ReadExReq MSHR misses 122411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 411411 # number of ReadCleanReq MSHR misses 122511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 411411 # number of ReadCleanReq MSHR misses 122611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 830283 # number of ReadSharedReq MSHR misses 122711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 830283 # number of ReadSharedReq MSHR misses 122811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 558166 # number of InvalidateReq MSHR misses 122911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 558166 # number of InvalidateReq MSHR misses 123011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 15216 # number of demand (read+write) MSHR misses 123111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8071 # number of demand (read+write) MSHR misses 123211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 411411 # number of demand (read+write) MSHR misses 123311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1053706 # number of demand (read+write) MSHR misses 123411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1488404 # number of demand (read+write) MSHR misses 123511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 15216 # number of overall MSHR misses 123611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8071 # number of overall MSHR misses 123711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 411411 # number of overall MSHR misses 123811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1053706 # number of overall MSHR misses 123911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of overall MSHR misses 124011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2163458 # number of overall MSHR misses 124111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 124211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 124311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20616 # number of ReadReq MSHR uncacheable 124411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 124511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable 124611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 124711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 124811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37416 # number of overall MSHR uncacheable misses 124911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of ReadReq MSHR miss cycles 125011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 224297500 # number of ReadReq MSHR miss cycles 125111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 569280000 # number of ReadReq MSHR miss cycles 125211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of HardPFReq MSHR miss cycles 125311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32033056811 # number of HardPFReq MSHR miss cycles 125411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4084370000 # number of UpgradeReq MSHR miss cycles 125511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4084370000 # number of UpgradeReq MSHR miss cycles 125611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2911469499 # number of SCUpgradeReq MSHR miss cycles 125711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2911469499 # number of SCUpgradeReq MSHR miss cycles 125811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2248998 # number of SCUpgradeFailReq MSHR miss cycles 125911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2248998 # number of SCUpgradeFailReq MSHR miss cycles 126011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10644364000 # number of ReadExReq MSHR miss cycles 126111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10644364000 # number of ReadExReq MSHR miss cycles 126211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13302589500 # number of ReadCleanReq MSHR miss cycles 126311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13302589500 # number of ReadCleanReq MSHR miss cycles 126411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 25893671500 # number of ReadSharedReq MSHR miss cycles 126511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 25893671500 # number of ReadSharedReq MSHR miss cycles 126611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 17612762500 # number of InvalidateReq MSHR miss cycles 126711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 17612762500 # number of InvalidateReq MSHR miss cycles 126811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of demand (read+write) MSHR miss cycles 126911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 224297500 # number of demand (read+write) MSHR miss cycles 127011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13302589500 # number of demand (read+write) MSHR miss cycles 127111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36538035500 # number of demand (read+write) MSHR miss cycles 127211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 50409905000 # number of demand (read+write) MSHR miss cycles 127311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of overall MSHR miss cycles 127411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 224297500 # number of overall MSHR miss cycles 127511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13302589500 # number of overall MSHR miss cycles 127611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles 127711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles 127811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles 127911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles 128011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles 128111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles 128211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles 128311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles 128411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles 128511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses 128611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses 128711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses 128810535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 128910535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 129011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 129111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 129211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 129311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 129410535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 129510535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 129611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses 129711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses 129811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses 129911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses 130011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses 130111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses 130211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses 130311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses 130411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses 130511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses 130611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses 130711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses 130811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses 130911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses 131011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses 131111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses 131211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses 131310535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 131411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses 131511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency 131611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency 131711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency 131811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency 131911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency 132011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency 132111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency 132211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency 132311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency 132411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency 132511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency 132611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency 132711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency 132811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency 132911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency 133011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency 133111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency 133211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency 133311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency 133411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency 133511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency 133611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency 133711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency 133811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency 133911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency 134011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency 134111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency 134211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency 134311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency 134411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency 134511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency 134611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency 134711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency 134811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency 134911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency 135011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency 135111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter. 135211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data. 135311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 135411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter. 135511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 135611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 135711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 135811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution 135911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution 136011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution 136111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution 136211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution 136311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution 136411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution 136511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution 136611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution 136711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution 136811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution 136911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 137011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 137111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution 137211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution 137311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution 137411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution 137511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution 137611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution 137711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes) 137811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes) 137911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes) 138011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes) 138111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes) 138211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes) 138311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes) 138411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes) 138511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes) 138611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes) 138711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 4847803 # Total snoops (count) 138811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes) 138911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram 139011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram 139111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram 139210535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 139311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram 139411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram 139511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 139610535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 139711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 139811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 139911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram 140011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks) 140110535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 140211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks) 140310535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 140411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks) 140510535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 140611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks) 140710535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 140811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks) 140910535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 141011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks) 141110535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 141211860Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 141310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 141410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 141510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 141710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 141810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 142010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 142110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 142210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 142310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 142410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 142510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 142610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 142710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 142810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 143110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 143210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 143310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 143410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 143510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 143710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 143810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 143910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 144010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 144110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 144211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 144311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 108097 # Table walker walks requested 144411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors 144511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate 144611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate 144711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting 144811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency 144911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency 145011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency 145111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency 145211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 145311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency 145411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency 145511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency 145611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency 145711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency 145811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency 145911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency 146011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency 146111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency 146211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency 146311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency 146411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency 146511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency 146611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 146711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency 146811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 146911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency 147011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution 147111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution 147211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution 147311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution 147411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution 147511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution 147611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated 147711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated 147811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated 147911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst 148010628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst 148211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst 148310628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 148411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst 148511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst 148610535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 148710535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 148811860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 86913541 # DTB read hits 148911860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 78813 # DTB read misses 149011860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 79382446 # DTB write hits 149111860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 29284 # DTB write misses 149210535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 149310535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149411860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 149511860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 149611860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB 149710535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 149811860Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch 149910535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 150011860Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions 150111860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 86992354 # DTB read accesses 150211860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 79411730 # DTB write accesses 150310535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 150411860Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 166295987 # DTB hits 150511860Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 108097 # DTB misses 150611860Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 166404084 # DTB accesses 150711860Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 150810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 151110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 151210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 151310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 151510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 151610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 151710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 151810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 151910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 152010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 152110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 152210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 152310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 152410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 152510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 152610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 152710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 152810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 152910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 153010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 153210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 153310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 153410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 153510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 153610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 153811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 67294 # Table walker walks requested 153911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors 154011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate 154111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate 154211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency 154311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency 154411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency 154511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency 154611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency 154711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency 154811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency 154911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency 155011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency 155111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency 155211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency 155311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency 155411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 155511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency 155611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency 155711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency 155811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 155911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency 156011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution 156111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution 156211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution 156311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated 156411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated 156511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated 156610628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 156711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst 156811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst 156910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 157011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst 157111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst 157211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst 157311860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 422829218 # ITB inst hits 157411860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 67294 # ITB inst misses 157510535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 157610535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 157710535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 157810535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 157910535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 158010535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 158111860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 158211860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 158311860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB 158410535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 158510535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 158610535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 158710535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 158810535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 158910535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 159011860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 422896512 # ITB inst accesses 159111860Sandreas.hansson@arm.comsystem.cpu1.itb.hits 422829218 # DTB hits 159211860Sandreas.hansson@arm.comsystem.cpu1.itb.misses 67294 # DTB misses 159311860Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 422896512 # DTB accesses 159411860Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 29136 # Number of power state transitions 159511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state 159611860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state 159711860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state 159811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state 159911860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state 160011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state 160111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 160211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 160311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 160411860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 160511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 160611860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 160711860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 160811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 160911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 161011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state 161111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state 161211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states 161311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states 161411860Sandreas.hansson@arm.comsystem.cpu1.numCycles 94802741175 # number of cpu cycles simulated 161510535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 161610535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 161711167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 161811860Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed 161911860Sandreas.hansson@arm.comsystem.cpu1.committedInsts 422521065 # Number of instructions committed 162011860Sandreas.hansson@arm.comsystem.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed 162111860Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses 162211860Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses 162311860Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 27792823 # number of times a function call or return occured 162411860Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls 162511860Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 470472983 # number of integer instructions 162611860Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 594254 # number of float instructions 162711860Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read 162811860Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written 162911860Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read 163011860Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written 163111860Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read 163211860Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written 163311860Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 166284311 # number of memory refs 163411860Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 86908703 # Number of load instructions 163511860Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 79375608 # Number of store instructions 163611860Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles 163711860Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles 163811860Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles 163911860Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988683 # Percentage of idle cycles 164011860Sandreas.hansson@arm.comsystem.cpu1.Branches 93458434 # Number of branches fetched 164111680SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 164211860Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction 164311860Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction 164411860Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction 164511860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction 164611860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction 164711860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction 164811860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction 164911860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction 165011860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction 165111860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction 165211860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction 165311860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction 165411860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction 165511860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction 165611860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction 165711860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction 165811860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction 165911860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction 166011860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction 166111860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction 166211860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction 166311860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction 166411860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction 166511860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction 166611860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction 166711860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction 166811860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction 166911860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction 167011860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction 167111860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction 167211860Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction 167311860Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction 167411860Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction 167511860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction 167611860Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction 167710535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 167810535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 167911860Sandreas.hansson@arm.comsystem.cpu1.op_class::total 505150374 # Class of executed instruction 168011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 168111860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5478037 # number of replacements 168211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use 168311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks. 168411860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks. 168511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks. 168611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit. 168711860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor 168811860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy 168911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy 169011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 169111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 169211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id 169311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 169411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 169511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses 169611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses 169711860Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 169811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits 169911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits 170011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits 170111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits 170211860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits 170311860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits 170411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits 170511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits 170611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits 170711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits 170811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits 170911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits 171011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits 171111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits 171211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits 171311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 156658996 # number of overall hits 171411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses 171511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses 171611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses 171711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses 171811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses 171911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses 172011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses 172111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses 172211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses 172311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses 172411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses 172511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses 172611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses 172711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses 172811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses 172911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5659360 # number of overall misses 173011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles 173111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles 173211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles 173311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles 173411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles 173511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles 173611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles 173711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles 173811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles 173911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles 174011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles 174111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 174211860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles 174311860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles 174411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles 174511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles 174611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses) 174711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses) 174811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses) 174911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses) 175011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses) 175111860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses) 175211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses) 175311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses) 175411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses) 175511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses) 175611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses) 175711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses) 175811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses 175911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses 176011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses 176111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses 176211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses 176311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses 176411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses 176511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses 176611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses 176711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses 176811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses 176911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses 177011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses 177111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses 177211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses 177311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses 177411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses 177511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses 177611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses 177711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses 177811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency 177911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency 178011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency 178111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency 178211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency 178311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency 178411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency 178511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency 178611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency 178711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency 178810535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 178910535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 179011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency 179111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency 179211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency 179311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency 179410535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179510535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179610535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 179710535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 179810535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179910535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180011860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks 180111860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5478037 # number of writebacks 180211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits 180311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits 180411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits 180511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits 180611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits 180711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits 180811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits 180911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits 181011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits 181111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits 181211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses 181311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses 181411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses 181511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses 181611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses 181711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses 181811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses 181911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses 182011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses 182111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses 182211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses 182311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses 182411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses 182511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses 182611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses 182711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses 182811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable 182911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable 183011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 183111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable 183211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses 183311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses 183411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles 183511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles 183611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles 183711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles 183811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles 183911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles 184011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles 184111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles 184211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles 184311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles 184411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles 184511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles 184611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles 184711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles 184811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles 184911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles 185011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles 185111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles 185211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles 185311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles 185411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles 185511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles 185611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses 185711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses 185811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses 185911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses 186011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses 186111860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses 186211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses 186311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses 186411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses 186511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses 186611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses 186711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses 186811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses 186911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses 187011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses 187111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses 187211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency 187311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency 187411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency 187511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency 187611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency 187711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency 187811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency 187911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency 188011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency 188111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency 188211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency 188311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency 188410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 188510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 188611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency 188711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency 188811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency 188911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency 189011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency 189111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency 189211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency 189311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency 189411860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 189511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 5778503 # number of replacements 189611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use 189711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks. 189811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks. 189911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks. 190011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit. 190111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor 190211860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy 190311860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy 190410535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 190511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 190611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 190711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id 190811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 190910535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 191011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses 191111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses 191211860Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 191311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 417050198 # number of ReadReq hits 191411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits 191511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 417050198 # number of demand (read+write) hits 191611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits 191711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 417050198 # number of overall hits 191811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 417050198 # number of overall hits 191911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5779020 # number of ReadReq misses 192011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 5779020 # number of ReadReq misses 192111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5779020 # number of demand (read+write) misses 192211860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 5779020 # number of demand (read+write) misses 192311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5779020 # number of overall misses 192411860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 5779020 # number of overall misses 192511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61138169500 # number of ReadReq miss cycles 192611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 61138169500 # number of ReadReq miss cycles 192711860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 61138169500 # number of demand (read+write) miss cycles 192811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 61138169500 # number of demand (read+write) miss cycles 192911860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 61138169500 # number of overall miss cycles 193011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 61138169500 # number of overall miss cycles 193111860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 422829218 # number of ReadReq accesses(hits+misses) 193211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 422829218 # number of ReadReq accesses(hits+misses) 193311860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 422829218 # number of demand (read+write) accesses 193411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 422829218 # number of demand (read+write) accesses 193511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 422829218 # number of overall (read+write) accesses 193611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 422829218 # number of overall (read+write) accesses 193711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013668 # miss rate for ReadReq accesses 193811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.013668 # miss rate for ReadReq accesses 193911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013668 # miss rate for demand accesses 194011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.013668 # miss rate for demand accesses 194111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013668 # miss rate for overall accesses 194211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.013668 # miss rate for overall accesses 194311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10579.331703 # average ReadReq miss latency 194411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency 194511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency 194611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10579.331703 # average overall miss latency 194711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency 194811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency 194910535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 195010535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195110535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195210535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 195310535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 195410535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 195511860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 5778503 # number of writebacks 195611860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 5778503 # number of writebacks 195711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5779020 # number of ReadReq MSHR misses 195811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses 195911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5779020 # number of demand (read+write) MSHR misses 196011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses 196111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5779020 # number of overall MSHR misses 196211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5779020 # number of overall MSHR misses 196310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 196410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 196510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 196610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 196711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58248659500 # number of ReadReq MSHR miss cycles 196811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 58248659500 # number of ReadReq MSHR miss cycles 196911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58248659500 # number of demand (read+write) MSHR miss cycles 197011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles 197111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles 197211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 58248659500 # number of overall MSHR miss cycles 197311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10594500 # number of ReadReq MSHR uncacheable cycles 197411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles 197511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles 197611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles 197711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for ReadReq accesses 197811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses 197911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses 198011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses 198111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses 198211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses 198311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency 198411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency 198511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency 198611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency 198711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency 198811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency 198911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency 199011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency 199111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency 199211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency 199311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 199411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued 199511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified 199611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 199710628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 199810628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 199911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing 200011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 200111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 1924030 # number of replacements 200211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use 200311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks. 200411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks. 200511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks. 200611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 200711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor 200811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor 200911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor 201011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor 201111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy 201211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy 201311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy 201411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy 201511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy 201611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id 201711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 201811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id 201911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 202011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id 202111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id 202211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id 202311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 202411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id 202511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 202611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 202711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 202811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id 202911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id 203011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id 203111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id 203211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020203 # Percentage of cache occupancy per task id 203311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 203411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id 203511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 387081443 # Number of tag accesses 203611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 387081443 # Number of data accesses 203711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 203811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 243745 # number of ReadReq hits 203911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 174457 # number of ReadReq hits 204011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 418202 # number of ReadReq hits 204111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3475258 # number of WritebackDirty hits 204211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3475258 # number of WritebackDirty hits 204311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 7780467 # number of WritebackClean hits 204411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 7780467 # number of WritebackClean hits 204511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 920068 # number of ReadExReq hits 204611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 920068 # number of ReadExReq hits 204711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5308980 # number of ReadCleanReq hits 204811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 5308980 # number of ReadCleanReq hits 204911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2962504 # number of ReadSharedReq hits 205011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2962504 # number of ReadSharedReq hits 205111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 264311 # number of InvalidateReq hits 205211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 264311 # number of InvalidateReq hits 205311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 243745 # number of demand (read+write) hits 205411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 174457 # number of demand (read+write) hits 205511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 5308980 # number of demand (read+write) hits 205611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3882572 # number of demand (read+write) hits 205711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 9609754 # number of demand (read+write) hits 205811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 243745 # number of overall hits 205911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 174457 # number of overall hits 206011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 5308980 # number of overall hits 206111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3882572 # number of overall hits 206211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 9609754 # number of overall hits 206311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18156 # number of ReadReq misses 206411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9553 # number of ReadReq misses 206511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 27709 # number of ReadReq misses 206611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208398 # number of UpgradeReq misses 206711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 208398 # number of UpgradeReq misses 206811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202605 # number of SCUpgradeReq misses 206911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 202605 # number of SCUpgradeReq misses 207011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 207111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 207211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 254808 # number of ReadExReq misses 207311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 254808 # number of ReadExReq misses 207411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470040 # number of ReadCleanReq misses 207511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 470040 # number of ReadCleanReq misses 207611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900637 # number of ReadSharedReq misses 207711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 900637 # number of ReadSharedReq misses 207811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261134 # number of InvalidateReq misses 207911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 261134 # number of InvalidateReq misses 208011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18156 # number of demand (read+write) misses 208111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9553 # number of demand (read+write) misses 208211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 470040 # number of demand (read+write) misses 208311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1155445 # number of demand (read+write) misses 208411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1653194 # number of demand (read+write) misses 208511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18156 # number of overall misses 208611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9553 # number of overall misses 208711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 470040 # number of overall misses 208811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1155445 # number of overall misses 208911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1653194 # number of overall misses 209011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 581758000 # number of ReadReq miss cycles 209111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 383665000 # number of ReadReq miss cycles 209211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 965423000 # number of ReadReq miss cycles 209311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 884282500 # number of UpgradeReq miss cycles 209411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 884282500 # number of UpgradeReq miss cycles 209511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 360962500 # number of SCUpgradeReq miss cycles 209611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 360962500 # number of SCUpgradeReq miss cycles 209711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2107498 # number of SCUpgradeFailReq miss cycles 209811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2107498 # number of SCUpgradeFailReq miss cycles 209911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11534187000 # number of ReadExReq miss cycles 210011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11534187000 # number of ReadExReq miss cycles 210111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17654070500 # number of ReadCleanReq miss cycles 210211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 17654070500 # number of ReadCleanReq miss cycles 210311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32780970500 # number of ReadSharedReq miss cycles 210411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 32780970500 # number of ReadSharedReq miss cycles 210511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 198500 # number of InvalidateReq miss cycles 210611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 198500 # number of InvalidateReq miss cycles 210711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 581758000 # number of demand (read+write) miss cycles 210811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 383665000 # number of demand (read+write) miss cycles 210911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 17654070500 # number of demand (read+write) miss cycles 211011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 44315157500 # number of demand (read+write) miss cycles 211111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 62934651000 # number of demand (read+write) miss cycles 211211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 581758000 # number of overall miss cycles 211311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 383665000 # number of overall miss cycles 211411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 17654070500 # number of overall miss cycles 211511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 44315157500 # number of overall miss cycles 211611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 62934651000 # number of overall miss cycles 211711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 261901 # number of ReadReq accesses(hits+misses) 211811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184010 # number of ReadReq accesses(hits+misses) 211911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 445911 # number of ReadReq accesses(hits+misses) 212011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3475258 # number of WritebackDirty accesses(hits+misses) 212111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3475258 # number of WritebackDirty accesses(hits+misses) 212211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 7780467 # number of WritebackClean accesses(hits+misses) 212311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 7780467 # number of WritebackClean accesses(hits+misses) 212411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208398 # number of UpgradeReq accesses(hits+misses) 212511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 208398 # number of UpgradeReq accesses(hits+misses) 212611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202605 # number of SCUpgradeReq accesses(hits+misses) 212711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 202605 # number of SCUpgradeReq accesses(hits+misses) 212811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 212911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 213011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1174876 # number of ReadExReq accesses(hits+misses) 213111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1174876 # number of ReadExReq accesses(hits+misses) 213211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5779020 # number of ReadCleanReq accesses(hits+misses) 213311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5779020 # number of ReadCleanReq accesses(hits+misses) 213411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3863141 # number of ReadSharedReq accesses(hits+misses) 213511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3863141 # number of ReadSharedReq accesses(hits+misses) 213611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 525445 # number of InvalidateReq accesses(hits+misses) 213711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 525445 # number of InvalidateReq accesses(hits+misses) 213811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 261901 # number of demand (read+write) accesses 213911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184010 # number of demand (read+write) accesses 214011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5779020 # number of demand (read+write) accesses 214111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5038017 # number of demand (read+write) accesses 214211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 11262948 # number of demand (read+write) accesses 214311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 261901 # number of overall (read+write) accesses 214411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184010 # number of overall (read+write) accesses 214511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5779020 # number of overall (read+write) accesses 214611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5038017 # number of overall (read+write) accesses 214711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 11262948 # number of overall (read+write) accesses 214811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for ReadReq accesses 214911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051916 # miss rate for ReadReq accesses 215011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.062140 # miss rate for ReadReq accesses 215111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 215211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 215311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 215411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 215510535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 215610535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 215711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.216881 # miss rate for ReadExReq accesses 215811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.216881 # miss rate for ReadExReq accesses 215911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081336 # miss rate for ReadCleanReq accesses 216011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081336 # miss rate for ReadCleanReq accesses 216111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.233136 # miss rate for ReadSharedReq accesses 216211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.233136 # miss rate for ReadSharedReq accesses 216311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.496977 # miss rate for InvalidateReq accesses 216411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.496977 # miss rate for InvalidateReq accesses 216511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for demand accesses 216611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051916 # miss rate for demand accesses 216711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081336 # miss rate for demand accesses 216811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.229345 # miss rate for demand accesses 216911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.146782 # miss rate for demand accesses 217011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for overall accesses 217111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051916 # miss rate for overall accesses 217211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081336 # miss rate for overall accesses 217311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.229345 # miss rate for overall accesses 217411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.146782 # miss rate for overall accesses 217511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average ReadReq miss latency 217611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40161.729300 # average ReadReq miss latency 217711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 34841.495543 # average ReadReq miss latency 217811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4243.238899 # average UpgradeReq miss latency 217911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4243.238899 # average UpgradeReq miss latency 218011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.607068 # average SCUpgradeReq miss latency 218111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1781.607068 # average SCUpgradeReq miss latency 218211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 351249.666667 # average SCUpgradeFailReq miss latency 218311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 351249.666667 # average SCUpgradeFailReq miss latency 218411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45266.188660 # average ReadExReq miss latency 218511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45266.188660 # average ReadExReq miss latency 218611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37558.655646 # average ReadCleanReq miss latency 218711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37558.655646 # average ReadCleanReq miss latency 218811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36397.539186 # average ReadSharedReq miss latency 218911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36397.539186 # average ReadSharedReq miss latency 219011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.760146 # average InvalidateReq miss latency 219111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.760146 # average InvalidateReq miss latency 219211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency 219311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency 219411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency 219511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency 219611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 38068.521299 # average overall miss latency 219711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency 219811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency 219911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency 220011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency 220111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 38068.521299 # average overall miss latency 220210628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220310535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220410628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 220510535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 220610628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 220710535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 220811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.unused_prefetches 40493 # number of HardPF blocks evicted w/o reference 220911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1134178 # number of writebacks 221011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1134178 # number of writebacks 221111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4642 # number of ReadExReq MSHR hits 221211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4642 # number of ReadExReq MSHR hits 221311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 415 # number of ReadSharedReq MSHR hits 221411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 415 # number of ReadSharedReq MSHR hits 221511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 221611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 221711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 5057 # number of demand (read+write) MSHR hits 221811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 5057 # number of demand (read+write) MSHR hits 221911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 5057 # number of overall MSHR hits 222011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 5057 # number of overall MSHR hits 222111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18156 # number of ReadReq MSHR misses 222211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9553 # number of ReadReq MSHR misses 222311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 27709 # number of ReadReq MSHR misses 222411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of HardPFReq MSHR misses 222511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 685885 # number of HardPFReq MSHR misses 222611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208398 # number of UpgradeReq MSHR misses 222711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 208398 # number of UpgradeReq MSHR misses 222811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202605 # number of SCUpgradeReq MSHR misses 222911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202605 # number of SCUpgradeReq MSHR misses 223011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 223111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 223211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 250166 # number of ReadExReq MSHR misses 223311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 250166 # number of ReadExReq MSHR misses 223411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 470040 # number of ReadCleanReq MSHR misses 223511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 470040 # number of ReadCleanReq MSHR misses 223611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 900222 # number of ReadSharedReq MSHR misses 223711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 900222 # number of ReadSharedReq MSHR misses 223811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261133 # number of InvalidateReq MSHR misses 223911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 261133 # number of InvalidateReq MSHR misses 224011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18156 # number of demand (read+write) MSHR misses 224111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9553 # number of demand (read+write) MSHR misses 224211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 470040 # number of demand (read+write) MSHR misses 224311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1150388 # number of demand (read+write) MSHR misses 224411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1648137 # number of demand (read+write) MSHR misses 224511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18156 # number of overall MSHR misses 224611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9553 # number of overall MSHR misses 224711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 470040 # number of overall MSHR misses 224811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1150388 # number of overall MSHR misses 224911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of overall MSHR misses 225011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2334022 # number of overall MSHR misses 225110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 225211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable 225311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22482 # number of ReadReq MSHR uncacheable 225411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 225511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable 225610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 225711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses 225811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43825 # number of overall MSHR uncacheable misses 225911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of ReadReq MSHR miss cycles 226011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 326347000 # number of ReadReq MSHR miss cycles 226111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 799169000 # number of ReadReq MSHR miss cycles 226211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of HardPFReq MSHR miss cycles 226311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28141665535 # number of HardPFReq MSHR miss cycles 226411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3910093000 # number of UpgradeReq MSHR miss cycles 226511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3910093000 # number of UpgradeReq MSHR miss cycles 226611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3115291500 # number of SCUpgradeReq MSHR miss cycles 226711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3115291500 # number of SCUpgradeReq MSHR miss cycles 226811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1777498 # number of SCUpgradeFailReq MSHR miss cycles 226911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1777498 # number of SCUpgradeFailReq MSHR miss cycles 227011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9489009000 # number of ReadExReq MSHR miss cycles 227111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9489009000 # number of ReadExReq MSHR miss cycles 227211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14833830500 # number of ReadCleanReq MSHR miss cycles 227311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14833830500 # number of ReadCleanReq MSHR miss cycles 227411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27315818000 # number of ReadSharedReq MSHR miss cycles 227511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27315818000 # number of ReadSharedReq MSHR miss cycles 227611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6163710000 # number of InvalidateReq MSHR miss cycles 227711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6163710000 # number of InvalidateReq MSHR miss cycles 227811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of demand (read+write) MSHR miss cycles 227911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 326347000 # number of demand (read+write) MSHR miss cycles 228011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14833830500 # number of demand (read+write) MSHR miss cycles 228111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36804827000 # number of demand (read+write) MSHR miss cycles 228211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 52437826500 # number of demand (read+write) MSHR miss cycles 228311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of overall MSHR miss cycles 228411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 326347000 # number of overall MSHR miss cycles 228511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14833830500 # number of overall MSHR miss cycles 228611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36804827000 # number of overall MSHR miss cycles 228711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of overall MSHR miss cycles 228811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 80579492035 # number of overall MSHR miss cycles 228911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9769500 # number of ReadReq MSHR uncacheable cycles 229011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3813749500 # number of ReadReq MSHR uncacheable cycles 229111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3823519000 # number of ReadReq MSHR uncacheable cycles 229211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9769500 # number of overall MSHR uncacheable cycles 229311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3813749500 # number of overall MSHR uncacheable cycles 229411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3823519000 # number of overall MSHR uncacheable cycles 229511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for ReadReq accesses 229611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for ReadReq accesses 229711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.062140 # mshr miss rate for ReadReq accesses 229810535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 229910535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 230011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 230111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 230211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 230311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 230410535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 230510535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 230611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212930 # mshr miss rate for ReadExReq accesses 230711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212930 # mshr miss rate for ReadExReq accesses 230811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for ReadCleanReq accesses 230911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081336 # mshr miss rate for ReadCleanReq accesses 231011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.233029 # mshr miss rate for ReadSharedReq accesses 231111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.233029 # mshr miss rate for ReadSharedReq accesses 231211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.496975 # mshr miss rate for InvalidateReq accesses 231311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.496975 # mshr miss rate for InvalidateReq accesses 231411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for demand accesses 231511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for demand accesses 231611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for demand accesses 231711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for demand accesses 231811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.146333 # mshr miss rate for demand accesses 231911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for overall accesses 232011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for overall accesses 232111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for overall accesses 232211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for overall accesses 232310535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 232411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.207230 # mshr miss rate for overall accesses 232511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency 232611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency 232711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency 232811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency 232911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency 233011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency 233111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency 233211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency 233311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency 233411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency 233511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency 233611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency 233711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency 233811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency 233911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency 234011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency 234111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency 234211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency 234311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency 234411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency 234511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency 234611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency 234711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency 234811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency 234911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency 235011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency 235111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency 235211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency 235311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency 235411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency 235511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency 235611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency 235711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency 235811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency 235911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency 236011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency 236111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter. 236211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data. 236311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 236411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter. 236511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 236611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 236711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 236811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution 236911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution 237011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution 237111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution 237211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution 237311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution 237411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution 237511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution 237611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution 237711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution 237811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution 237911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 238011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 238111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution 238211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution 238311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution 238411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution 238511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution 238611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution 238711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes) 238811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes) 238911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes) 239011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes) 239111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes) 239211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes) 239311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes) 239411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes) 239511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes) 239611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes) 239711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 4566671 # Total snoops (count) 239811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes) 239911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram 240011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram 240111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram 240210535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 240311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram 240411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram 240511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram 240610535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 240711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 240811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 240911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram 241011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks) 241110535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 241211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks) 241310535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 241411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks) 241510535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 241611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks) 241710535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 241811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks) 241910535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 242011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks) 242110535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 242211860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 242311860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40263 # Transaction distribution 242411860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40263 # Transaction distribution 242511860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136535 # Transaction distribution 242611860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136535 # Transaction distribution 242711860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes) 242810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 242911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 243010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 243110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 243210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 243310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 243410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 243510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 243610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 243710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 243811754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 243910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 244011860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes) 244111860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes) 244211860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes) 244310535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 244410535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 244511860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) 244611860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes) 244710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 244811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 244910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 245010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 245110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 245210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 245610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245711754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 245810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 245911860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes) 246011860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes) 246111860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes) 246210535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 246310535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 246411860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes) 246511860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks) 246610535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 246711860Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 246810535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 246911860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 247010535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 247111754Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 247210535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 247311860Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 247411245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 247510535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 247610535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 247711860Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 247810535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 247911860Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 248010535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 248111201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 248210535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 248311754Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 248410535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 248511570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 248610535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 248711860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks) 248810535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 248911860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks) 249010535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 249111860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks) 249210535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 249311860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks) 249410535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 249511860Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks) 249610535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 249710892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 249810535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 249911860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 250011860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115618 # number of replacements 250111860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use 250211336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 250311860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks. 250411336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 250511860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit. 250611860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor 250711860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor 250811860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy 250911860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy 251011860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy 251110535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 251210535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 251310535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 251411860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040955 # Number of tag accesses 251511860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040955 # Number of data accesses 251611860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 251710535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 251811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses 251911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8931 # number of ReadReq misses 252010535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 252110535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 252211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 252311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 252410535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 252511860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses 252611860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115662 # number of demand (read+write) misses 252710535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 252811860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115622 # number of overall misses 252911860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115662 # number of overall misses 253011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 253111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles 253211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles 253310726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 253410726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 253511860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles 253611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles 253711860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 253811860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles 253911860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles 254011860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 254111860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles 254211860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles 254310535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 254411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses) 254511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses) 254610535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 254710535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 254811680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 254911680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 255010535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 255111860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses 255211860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses 255310535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 255411860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses 255511860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses 255610535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 255710535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 255810535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 255910535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 256010535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 256111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 256211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 256310535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 256410535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 256510535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 256610535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 256710535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 256810535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 256911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 257011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency 257111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency 257210726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 257310726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 257411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125113.237276 # average WriteLineReq miss latency 257511860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency 257611860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 257711860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency 257811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency 257911860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 258011860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency 258111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency 258211860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked 258310535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 258411860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 258510535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 258611860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked 258710535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 258811754Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 258911754Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 259010535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 259111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses 259211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses 259310535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 259410535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 259511680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 259611680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 259710535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 259811860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses 259911860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses 260010535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 260111860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses 260211860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses 260311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 260411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1577555480 # number of ReadReq MSHR miss cycles 260511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1580900480 # number of ReadReq MSHR miss cycles 260610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 260710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 260811860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8010840420 # number of WriteLineReq MSHR miss cycles 260911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8010840420 # number of WriteLineReq MSHR miss cycles 261011860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 261111860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9588395900 # number of demand (read+write) MSHR miss cycles 261211860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9591959900 # number of demand (read+write) MSHR miss cycles 261311860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 261411860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9588395900 # number of overall MSHR miss cycles 261511860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9591959900 # number of overall MSHR miss cycles 261610535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 261710535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 261810535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 261910535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 262010535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 262111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 262211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 262310535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 262410535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 262510535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 262610535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 262710535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 262810535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 262911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 263011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177373.002024 # average ReadReq mshr miss latency 263111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 177012.706304 # average ReadReq mshr miss latency 263210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 263310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 263411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75058.470317 # average WriteLineReq mshr miss latency 263511860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75058.470317 # average WriteLineReq mshr miss latency 263611860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 263711860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency 263811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency 263911860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 264011860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency 264111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency 264211860Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 264311860Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1289685 # number of replacements 264411860Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use 264511860Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5723107 # Total number of references to valid blocks. 264611860Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks. 264711860Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks. 264811860Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit. 264911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor 265011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor 265111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor 265211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor 265311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor 265411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor 265511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor 265611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor 265711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor 265811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor 265911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor 266011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy 266111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy 266211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002120 # Average percentage of cache occupancy 266311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.051831 # Average percentage of cache occupancy 266411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy 266511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy 266611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004583 # Average percentage of cache occupancy 266711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.005325 # Average percentage of cache occupancy 266811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy 266911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy 267011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy 267111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy 267211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id 267311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id 267411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id 267511860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id 267611860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id 267711860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id 267811860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 267911860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id 268011860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 268111860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 268211860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id 268311860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id 268411860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id 268511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id 268611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id 268711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id 268811860Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 65194650 # Number of tag accesses 268911860Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 65194650 # Number of data accesses 269011860Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 269111860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits 269211860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits 269311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 165997 # number of UpgradeReq hits 269411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 157094 # number of UpgradeReq hits 269511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 323091 # number of UpgradeReq hits 269611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 44921 # number of SCUpgradeReq hits 269711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 51888 # number of SCUpgradeReq hits 269811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 96809 # number of SCUpgradeReq hits 269911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 41742 # number of ReadExReq hits 270011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 58696 # number of ReadExReq hits 270111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 100438 # number of ReadExReq hits 270211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7485 # number of ReadSharedReq hits 270311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3707 # number of ReadSharedReq hits 270411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 366128 # number of ReadSharedReq hits 270511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 471159 # number of ReadSharedReq hits 270611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 250331 # number of ReadSharedReq hits 270711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11134 # number of ReadSharedReq hits 270811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits 270911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 423879 # number of ReadSharedReq hits 271011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 535784 # number of ReadSharedReq hits 271111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283571 # number of ReadSharedReq hits 271211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2358374 # number of ReadSharedReq hits 271311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 108961 # number of InvalidateReq hits 271411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 126093 # number of InvalidateReq hits 271511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 235054 # number of InvalidateReq hits 271611860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 7485 # number of demand (read+write) hits 271711860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3707 # number of demand (read+write) hits 271811860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 366128 # number of demand (read+write) hits 271911860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 512901 # number of demand (read+write) hits 272011860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 250331 # number of demand (read+write) hits 272111860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 11134 # number of demand (read+write) hits 272211860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits 272311860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 423879 # number of demand (read+write) hits 272411860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 594480 # number of demand (read+write) hits 272511860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 283571 # number of demand (read+write) hits 272611860Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2458812 # number of demand (read+write) hits 272711860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 7485 # number of overall hits 272811860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3707 # number of overall hits 272911860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 366128 # number of overall hits 273011860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 512901 # number of overall hits 273111860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 250331 # number of overall hits 273211860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 11134 # number of overall hits 273311860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits 273411860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 423879 # number of overall hits 273511860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 594480 # number of overall hits 273611860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 283571 # number of overall hits 273711860Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2458812 # number of overall hits 273811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21704 # number of UpgradeReq misses 273911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 22525 # number of UpgradeReq misses 274011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 44229 # number of UpgradeReq misses 274111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 639 # number of SCUpgradeReq misses 274211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 868 # number of SCUpgradeReq misses 274311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1507 # number of SCUpgradeReq misses 274411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 68872 # number of ReadExReq misses 274511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 49716 # number of ReadExReq misses 274611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 118588 # number of ReadExReq misses 274711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 981 # number of ReadSharedReq misses 274811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 934 # number of ReadSharedReq misses 274911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 45283 # number of ReadSharedReq misses 275011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 111817 # number of ReadSharedReq misses 275111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 200821 # number of ReadSharedReq misses 275211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1691 # number of ReadSharedReq misses 275311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1806 # number of ReadSharedReq misses 275411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 46161 # number of ReadSharedReq misses 275511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 105560 # number of ReadSharedReq misses 275611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 172390 # number of ReadSharedReq misses 275711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 687444 # number of ReadSharedReq misses 275811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 412236 # number of InvalidateReq misses 275911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 90358 # number of InvalidateReq misses 276011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 502594 # number of InvalidateReq misses 276111860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 981 # number of demand (read+write) misses 276211860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 934 # number of demand (read+write) misses 276311860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 45283 # number of demand (read+write) misses 276411860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 180689 # number of demand (read+write) misses 276511860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 200821 # number of demand (read+write) misses 276611860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1691 # number of demand (read+write) misses 276711860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1806 # number of demand (read+write) misses 276811860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 46161 # number of demand (read+write) misses 276911860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 155276 # number of demand (read+write) misses 277011860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 172390 # number of demand (read+write) misses 277111860Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 806032 # number of demand (read+write) misses 277211860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 981 # number of overall misses 277311860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 934 # number of overall misses 277411860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 45283 # number of overall misses 277511860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 180689 # number of overall misses 277611860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 200821 # number of overall misses 277711860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1691 # number of overall misses 277811860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1806 # number of overall misses 277911860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 46161 # number of overall misses 278011860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 155276 # number of overall misses 278111860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 172390 # number of overall misses 278211860Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 806032 # number of overall misses 278311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 123357500 # number of UpgradeReq miss cycles 278411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 137680500 # number of UpgradeReq miss cycles 278511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 261038000 # number of UpgradeReq miss cycles 278611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 7905500 # number of SCUpgradeReq miss cycles 278711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 10002000 # number of SCUpgradeReq miss cycles 278811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 17907500 # number of SCUpgradeReq miss cycles 278911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7461780500 # number of ReadExReq miss cycles 279011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5660273500 # number of ReadExReq miss cycles 279111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 13122054000 # number of ReadExReq miss cycles 279211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 100552000 # number of ReadSharedReq miss cycles 279311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 104158000 # number of ReadSharedReq miss cycles 279411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 5195669500 # number of ReadSharedReq miss cycles 279511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 12454113000 # number of ReadSharedReq miss cycles 279611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of ReadSharedReq miss cycles 279711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 176942500 # number of ReadSharedReq miss cycles 279811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 186194000 # number of ReadSharedReq miss cycles 279911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5476488000 # number of ReadSharedReq miss cycles 280011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 12376112000 # number of ReadSharedReq miss cycles 280111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of ReadSharedReq miss cycles 280211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 86331961414 # number of ReadSharedReq miss cycles 280311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 100552000 # number of demand (read+write) miss cycles 280411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 104158000 # number of demand (read+write) miss cycles 280511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 5195669500 # number of demand (read+write) miss cycles 280611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 19915893500 # number of demand (read+write) miss cycles 280711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of demand (read+write) miss cycles 280811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 176942500 # number of demand (read+write) miss cycles 280911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 186194000 # number of demand (read+write) miss cycles 281011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5476488000 # number of demand (read+write) miss cycles 281111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 18036385500 # number of demand (read+write) miss cycles 281211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of demand (read+write) miss cycles 281311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 99454015414 # number of demand (read+write) miss cycles 281411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 100552000 # number of overall miss cycles 281511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 104158000 # number of overall miss cycles 281611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 5195669500 # number of overall miss cycles 281711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 19915893500 # number of overall miss cycles 281811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of overall miss cycles 281911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 176942500 # number of overall miss cycles 282011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 186194000 # number of overall miss cycles 282111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5476488000 # number of overall miss cycles 282211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 18036385500 # number of overall miss cycles 282311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of overall miss cycles 282411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 99454015414 # number of overall miss cycles 282511860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2495189 # number of WritebackDirty accesses(hits+misses) 282611860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2495189 # number of WritebackDirty accesses(hits+misses) 282711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 187701 # number of UpgradeReq accesses(hits+misses) 282811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 179619 # number of UpgradeReq accesses(hits+misses) 282911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 367320 # number of UpgradeReq accesses(hits+misses) 283011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 45560 # number of SCUpgradeReq accesses(hits+misses) 283111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 52756 # number of SCUpgradeReq accesses(hits+misses) 283211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 98316 # number of SCUpgradeReq accesses(hits+misses) 283311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 110614 # number of ReadExReq accesses(hits+misses) 283411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 108412 # number of ReadExReq accesses(hits+misses) 283511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 219026 # number of ReadExReq accesses(hits+misses) 283611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8466 # number of ReadSharedReq accesses(hits+misses) 283711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4641 # number of ReadSharedReq accesses(hits+misses) 283811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 411411 # number of ReadSharedReq accesses(hits+misses) 283911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 582976 # number of ReadSharedReq accesses(hits+misses) 284011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 451152 # number of ReadSharedReq accesses(hits+misses) 284111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12825 # number of ReadSharedReq accesses(hits+misses) 284211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7002 # number of ReadSharedReq accesses(hits+misses) 284311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 470040 # number of ReadSharedReq accesses(hits+misses) 284411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 641344 # number of ReadSharedReq accesses(hits+misses) 284511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 455961 # number of ReadSharedReq accesses(hits+misses) 284611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3045818 # number of ReadSharedReq accesses(hits+misses) 284711860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 521197 # number of InvalidateReq accesses(hits+misses) 284811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 216451 # number of InvalidateReq accesses(hits+misses) 284911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 737648 # number of InvalidateReq accesses(hits+misses) 285011860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8466 # number of demand (read+write) accesses 285111860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 4641 # number of demand (read+write) accesses 285211860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 411411 # number of demand (read+write) accesses 285311860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 693590 # number of demand (read+write) accesses 285411860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 451152 # number of demand (read+write) accesses 285511860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 12825 # number of demand (read+write) accesses 285611860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7002 # number of demand (read+write) accesses 285711860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 470040 # number of demand (read+write) accesses 285811860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 749756 # number of demand (read+write) accesses 285911860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 455961 # number of demand (read+write) accesses 286011860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3264844 # number of demand (read+write) accesses 286111860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8466 # number of overall (read+write) accesses 286211860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 4641 # number of overall (read+write) accesses 286311860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 411411 # number of overall (read+write) accesses 286411860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 693590 # number of overall (read+write) accesses 286511860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 451152 # number of overall (read+write) accesses 286611860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 12825 # number of overall (read+write) accesses 286711860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7002 # number of overall (read+write) accesses 286811860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 470040 # number of overall (read+write) accesses 286911860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 749756 # number of overall (read+write) accesses 287011860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 455961 # number of overall (read+write) accesses 287111860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3264844 # number of overall (read+write) accesses 287211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.115631 # miss rate for UpgradeReq accesses 287311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.125404 # miss rate for UpgradeReq accesses 287411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.120410 # miss rate for UpgradeReq accesses 287511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.014025 # miss rate for SCUpgradeReq accesses 287611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016453 # miss rate for SCUpgradeReq accesses 287711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.015328 # miss rate for SCUpgradeReq accesses 287811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.622634 # miss rate for ReadExReq accesses 287911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.458584 # miss rate for ReadExReq accesses 288011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.541433 # miss rate for ReadExReq accesses 288111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for ReadSharedReq accesses 288211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.201250 # miss rate for ReadSharedReq accesses 288311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110068 # miss rate for ReadSharedReq accesses 288411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191804 # miss rate for ReadSharedReq accesses 288511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for ReadSharedReq accesses 288611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for ReadSharedReq accesses 288711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.257926 # miss rate for ReadSharedReq accesses 288811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098207 # miss rate for ReadSharedReq accesses 288911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164592 # miss rate for ReadSharedReq accesses 289011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for ReadSharedReq accesses 289111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.225701 # miss rate for ReadSharedReq accesses 289211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.790941 # miss rate for InvalidateReq accesses 289311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.417452 # miss rate for InvalidateReq accesses 289411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.681347 # miss rate for InvalidateReq accesses 289511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for demand accesses 289611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.201250 # miss rate for demand accesses 289711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.110068 # miss rate for demand accesses 289811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.260513 # miss rate for demand accesses 289911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for demand accesses 290011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for demand accesses 290111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.257926 # miss rate for demand accesses 290211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.098207 # miss rate for demand accesses 290311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.207102 # miss rate for demand accesses 290411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for demand accesses 290511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.246882 # miss rate for demand accesses 290611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for overall accesses 290711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.201250 # miss rate for overall accesses 290811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.110068 # miss rate for overall accesses 290911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.260513 # miss rate for overall accesses 291011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for overall accesses 291111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for overall accesses 291211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.257926 # miss rate for overall accesses 291311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.098207 # miss rate for overall accesses 291411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.207102 # miss rate for overall accesses 291511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for overall accesses 291611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.246882 # miss rate for overall accesses 291711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5683.629746 # average UpgradeReq miss latency 291811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6112.341842 # average UpgradeReq miss latency 291911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 5901.964774 # average UpgradeReq miss latency 292011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12371.674491 # average SCUpgradeReq miss latency 292111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11523.041475 # average SCUpgradeReq miss latency 292211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 11882.879894 # average SCUpgradeReq miss latency 292311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 108342.729992 # average ReadExReq miss latency 292411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 113852.150213 # average ReadExReq miss latency 292511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 110652.460620 # average ReadExReq miss latency 292611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average ReadSharedReq miss latency 292711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 111518.201285 # average ReadSharedReq miss latency 292811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114737.749266 # average ReadSharedReq miss latency 292911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111379.423522 # average ReadSharedReq miss latency 293011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average ReadSharedReq miss latency 293111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average ReadSharedReq miss latency 293211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103097.452935 # average ReadSharedReq miss latency 293311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 118638.850978 # average ReadSharedReq miss latency 293411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117242.440318 # average ReadSharedReq miss latency 293511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average ReadSharedReq miss latency 293611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 125583.991444 # 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average overall miss latency 294511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency 294611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency 294711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 123387.179931 # average overall miss latency 294811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency 294911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency 295011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency 295111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency 295211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency 295311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency 295411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency 295511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency 295611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency 295711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency 295811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 123387.179931 # average overall miss latency 295911860Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 70 # number of cycles access was blocked 296010515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 296111754Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 296210515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 296311860Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked 296410515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 296511860Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1000492 # number of writebacks 296611860Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1000492 # number of writebacks 296711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 125 # number of ReadSharedReq MSHR hits 296811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 495 # number of ReadSharedReq MSHR hits 296911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadSharedReq MSHR hits 297011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 297111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 176 # number of ReadSharedReq MSHR hits 297211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 174 # number of ReadSharedReq MSHR hits 297311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 297411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 975 # number of ReadSharedReq MSHR hits 297511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 125 # number of demand (read+write) MSHR hits 297611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 495 # number of demand (read+write) MSHR hits 297711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 297811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 297911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 176 # number of demand (read+write) MSHR hits 298011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 174 # number of demand (read+write) MSHR hits 298111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 298211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 975 # number of demand (read+write) MSHR hits 298311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 125 # number of overall MSHR hits 298411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 495 # number of overall MSHR hits 298511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 298611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 298711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 176 # number of overall MSHR hits 298811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 174 # number of overall MSHR hits 298911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 299011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 975 # number of overall MSHR hits 299111860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 48951 # number of CleanEvict MSHR misses 299211860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 48951 # number of CleanEvict MSHR misses 299311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 21704 # number of UpgradeReq MSHR misses 299411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 22525 # number of UpgradeReq MSHR misses 299511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 44229 # number of UpgradeReq MSHR misses 299611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 639 # number of SCUpgradeReq MSHR misses 299711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 868 # number of SCUpgradeReq MSHR misses 299811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1507 # number of SCUpgradeReq MSHR misses 299911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 68872 # number of ReadExReq MSHR misses 300011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 49716 # number of ReadExReq MSHR misses 300111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 118588 # number of ReadExReq MSHR misses 300211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 981 # number of ReadSharedReq MSHR misses 300311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 934 # number of ReadSharedReq MSHR misses 300411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45158 # number of ReadSharedReq MSHR misses 300511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 111322 # number of ReadSharedReq MSHR misses 300611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of ReadSharedReq MSHR misses 300711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1690 # number of ReadSharedReq MSHR misses 300811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1806 # number of ReadSharedReq MSHR misses 300911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45985 # number of ReadSharedReq MSHR misses 301011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 105386 # number of ReadSharedReq MSHR misses 301111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of ReadSharedReq MSHR misses 301211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 686469 # number of ReadSharedReq MSHR misses 301311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 412236 # number of InvalidateReq MSHR misses 301411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 90358 # number of InvalidateReq MSHR misses 301511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 502594 # number of InvalidateReq MSHR misses 301611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 981 # number of demand (read+write) MSHR misses 301711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 934 # number of demand (read+write) MSHR misses 301811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 45158 # number of demand (read+write) MSHR misses 301911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 180194 # number of demand (read+write) MSHR misses 302011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of demand (read+write) MSHR misses 302111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1690 # number of demand (read+write) MSHR misses 302211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1806 # number of demand (read+write) MSHR misses 302311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 45985 # number of demand (read+write) MSHR misses 302411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 155102 # number of demand (read+write) MSHR misses 302511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of demand (read+write) MSHR misses 302611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 805057 # number of demand (read+write) MSHR misses 302711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 981 # number of overall MSHR misses 302811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 934 # number of overall MSHR misses 302911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 45158 # number of overall MSHR misses 303011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 180194 # number of overall MSHR misses 303111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of overall MSHR misses 303211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1690 # number of overall MSHR misses 303311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1806 # number of overall MSHR misses 303411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 45985 # number of overall MSHR misses 303511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 155102 # number of overall MSHR misses 303611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of overall MSHR misses 303711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 805057 # number of overall MSHR misses 303811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 303911860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 304010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 304111860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 22370 # number of ReadReq MSHR uncacheable 304211860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 43096 # number of ReadReq MSHR uncacheable 304311860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 304411860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 304511860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38143 # number of WriteReq MSHR uncacheable 304611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 304711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 304810827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 304911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 43713 # number of overall MSHR uncacheable misses 305011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 81239 # number of overall MSHR uncacheable misses 305111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437084000 # number of UpgradeReq MSHR miss cycles 305211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 466716500 # number of UpgradeReq MSHR miss cycles 305311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 903800500 # number of UpgradeReq MSHR miss cycles 305411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15328000 # number of SCUpgradeReq MSHR miss cycles 305511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21488000 # number of SCUpgradeReq MSHR miss cycles 305611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 36816000 # 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number of InvalidateReq MSHR miss cycles 307211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1724009500 # number of InvalidateReq MSHR miss cycles 307311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 9856919500 # number of InvalidateReq MSHR miss cycles 307411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of demand (read+write) MSHR miss cycles 307511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94817501 # number of demand (read+write) MSHR miss cycles 307611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 4733313024 # number of demand (read+write) MSHR miss cycles 307711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 18070516658 # number of demand (read+write) MSHR miss cycles 307811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of demand (read+write) MSHR miss cycles 307911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of demand (read+write) MSHR miss cycles 308011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168133501 # number of demand (read+write) MSHR miss cycles 308111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 5000535031 # number of demand (read+write) MSHR miss cycles 308211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 16469292724 # number of demand (read+write) MSHR miss cycles 308311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of demand (read+write) MSHR miss cycles 308411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 91316383578 # number of demand (read+write) MSHR miss cycles 308511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of overall MSHR miss cycles 308611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94817501 # number of overall MSHR miss cycles 308711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 4733313024 # number of overall MSHR miss cycles 308811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 18070516658 # number of overall MSHR miss cycles 308911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of overall MSHR miss cycles 309011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of overall MSHR miss cycles 309111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168133501 # number of overall MSHR miss cycles 309211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 5000535031 # number of overall MSHR miss cycles 309311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 16469292724 # number of overall MSHR miss cycles 309411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of overall MSHR miss cycles 309511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 91316383578 # number of overall MSHR miss cycles 309611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343198000 # number of ReadReq MSHR uncacheable cycles 309711860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2516105003 # number of ReadReq MSHR uncacheable cycles 309811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7788000 # number of ReadReq MSHR uncacheable cycles 309911860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3411021500 # number of ReadReq MSHR uncacheable cycles 310011860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 6278112503 # number of ReadReq MSHR uncacheable cycles 310111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343198000 # number of overall MSHR uncacheable cycles 310211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 2516105003 # number of overall MSHR uncacheable cycles 310311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7788000 # number of overall MSHR uncacheable cycles 310411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 3411021500 # number of overall MSHR uncacheable cycles 310511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 6278112503 # number of overall MSHR uncacheable cycles 310610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 310710892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 310811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses 310911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses 311011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses 311111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses 311211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses 311311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses 311411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses 311511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses 311611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses 311711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses 311811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses 311911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses 312011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses 312111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses 312211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses 312311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses 312411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses 312511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses 312611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses 312711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses 312811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses 312911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses 313011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses 313111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses 313211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses 313311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses 313411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses 313511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses 313611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses 313711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses 313811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses 313911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses 314011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses 314111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses 314211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses 314311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses 314411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses 314511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses 314611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses 314711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses 314811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses 314911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses 315011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses 315111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses 315211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses 315311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency 315411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency 315511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency 315611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23987.480438 # average SCUpgradeReq mshr miss latency 315711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency 315811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency 315911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98342.382231 # average ReadExReq mshr miss latency 316011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency 316111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency 316211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average ReadSharedReq mshr miss latency 316311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency 316411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency 316511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency 316611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average ReadSharedReq mshr miss latency 316711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency 316811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency 316911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency 317011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency 317111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average ReadSharedReq mshr miss latency 317211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency 317311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency 317411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency 317511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency 317611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency 317711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency 317811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency 317911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency 318011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency 318111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency 318211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency 318311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency 318411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency 318511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency 318611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency 318711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency 318811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency 318911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency 319011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency 319111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency 319211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency 319311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency 319411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency 319511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency 319611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency 319711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency 319811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency 319911860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency 320011860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency 320111860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency 320211860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency 320311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency 320411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency 320511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency 320611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency 320711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency 320811860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter. 320911860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data. 321011860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 321111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 321211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 321311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 321411860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 321511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 43096 # Transaction distribution 321611860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 738496 # Transaction distribution 321711860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38143 # Transaction distribution 321811860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38143 # Transaction distribution 321911860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution 322011860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 202416 # Transaction distribution 322111860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 304555 # Transaction distribution 322211860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution 322311754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 322411860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 322511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 135023 # Transaction distribution 322611860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 117908 # Transaction distribution 322711860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution 322811860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 620101 # Transaction distribution 322911860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 29545 # Transaction distribution 323011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes) 323110535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 323211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes) 323311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes) 323411860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes) 323511860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes) 323611860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes) 323711860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes) 323811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes) 323910535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 324011860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes) 324111860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes) 324211860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes) 324311860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes) 324411860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes) 324511860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes) 324611860Sandreas.hansson@arm.comsystem.membus.snoops 615067 # Total snoops (count) 324711860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 174144 # Total snoop traffic (bytes) 324811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2133066 # Request fanout histogram 324911860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.015313 # Request fanout histogram 325011860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram 325110535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 325211860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram 325311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram 325410535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 325510535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 325611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 325710535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 325811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2133066 # Request fanout histogram 325911860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks) 326010535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 326111754Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 326210535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 326311860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks) 326410535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 326511860Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks) 326610535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 326711860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks) 326810535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 326911860Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks) 327010535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 327111860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327211860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327311860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327411860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327511860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327611860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327711860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 327811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 327911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 328011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 328111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 328211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 328311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 328411860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 328511860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 328610515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 328710515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 328810515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 328910515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 329010515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 329110515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 329210515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 329310515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 329410515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 329511374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 329610515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 329710515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 329810515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 329911374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 330010515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 330110515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 330210515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 330310515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 330410515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 330510515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 330610515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 330710515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 330810515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 330910515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 331010515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 331110515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 331210515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 331310515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 331410515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 331510515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 331610515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 331710515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 331810515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 331910515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 332010515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 332110515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 332210515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 332310515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 332410515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 332510515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 332610515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 332710515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 332811860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 332911860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333011860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333111860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333211860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333311860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333411860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 333511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 333611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 333711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 333811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 333911860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334011860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334111860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334211860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334311860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334411860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334511860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334611860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334711860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334811860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 334911860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 335011860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 335111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter. 335211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data. 335311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 335411860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter. 335511860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 335611860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 335711860Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 335811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution 335911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution 336011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution 336111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution 336211860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution 336311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution 336411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution 336511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution 336611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution 336711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution 336811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 336911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution 337011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution 337111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution 337211860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution 337311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution 337411860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes) 337511860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes) 337611860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes) 337711860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes) 337811860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes) 337911860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes) 338011860Sandreas.hansson@arm.comsystem.toL2Bus.snoops 2787811 # Total snoops (count) 338111860Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes) 338211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram 338311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram 338411860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram 338510515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 338611860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram 338711860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram 338811860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram 338910515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 339011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 339110515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 339211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram 339311860Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks) 339410515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 339511860Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks) 339610515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 339711860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks) 339810515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 339911860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks) 340010515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 340110515SN/A 340210515SN/A---------- End Simulation Statistics ---------- 3403