stats.txt revision 11754
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311754Sandreas.hansson@arm.comsim_seconds 47.405081 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 47405080882500 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 1071981 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 57861452624 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 765552 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 819.29 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 878258906 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 1033075205 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory 2111754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory 2611754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory 2811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 56765124 # Number of bytes read from this memory 2911754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory 3011754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory 3111754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory 3211754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 74764392 # Number of bytes written to this memory 3611754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory 3711754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory 3811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory 3911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory 4011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory 4111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory 4211754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory 4311754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory 4411754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory 4511754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory 4611754Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory 4711754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 927476 # Number of read requests responded to by this memory 4811754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory 5211754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) 5511754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) 5611754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) 5711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) 5811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) 5911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) 6011754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) 6111754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) 6211754Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) 6311754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) 6411754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) 6511754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) 6611754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) 6711754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) 7111754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) 7211754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) 7311754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) 7411754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) 7511754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) 7611754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) 7711754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) 7811754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) 7911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) 8011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) 8111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) 8211754Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) 8311754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) 8411754Sandreas.hansson@arm.comsystem.physmem.readReqs 927476 # Number of read requests accepted 8511754Sandreas.hansson@arm.comsystem.physmem.writeReqs 1170446 # Number of write requests accepted 8611754Sandreas.hansson@arm.comsystem.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue 8711754Sandreas.hansson@arm.comsystem.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue 8811754Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM 8911754Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue 9011754Sandreas.hansson@arm.comsystem.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM 9111754Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side 9211754Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side 9311754Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue 9411754Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 53525 # Per bank write bursts 9711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 58700 # Per bank write bursts 9811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 53136 # Per bank write bursts 9911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 59915 # Per bank write bursts 10011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 57558 # Per bank write bursts 10111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 67025 # Per bank write bursts 10211754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 57593 # Per bank write bursts 10311754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 57551 # Per bank write bursts 10411754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 45941 # Per bank write bursts 10511754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 94599 # Per bank write bursts 10611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 49635 # Per bank write bursts 10711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 57294 # Per bank write bursts 10811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 48522 # Per bank write bursts 10911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 56965 # Per bank write bursts 11011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 52794 # Per bank write bursts 11111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 56368 # Per bank write bursts 11211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 71875 # Per bank write bursts 11311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 75753 # Per bank write bursts 11411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 71549 # Per bank write bursts 11511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 77042 # Per bank write bursts 11611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 73392 # Per bank write bursts 11711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 80022 # Per bank write bursts 11811754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 71461 # Per bank write bursts 11911754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 73088 # Per bank write bursts 12011754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 65465 # Per bank write bursts 12111754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 74249 # Per bank write bursts 12211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 70475 # Per bank write bursts 12311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 74236 # Per bank write bursts 12411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 69250 # Per bank write bursts 12511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 75271 # Per bank write bursts 12611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 70641 # Per bank write bursts 12711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 74378 # Per bank write bursts 12810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911754Sandreas.hansson@arm.comsystem.physmem.numWrRetry 399 # Number of times write queue was full causing retry 13011754Sandreas.hansson@arm.comsystem.physmem.totGap 47405077592000 # Total gap between requests 13110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711754Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 884251 # Read request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411754Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1167872 # Write request sizes (log2) 14511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see 14611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see 14711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see 14811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see 14911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see 15011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see 15111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see 15211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see 15311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see 15411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see 15511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see 15611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see 15711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see 15811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see 15911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see 16011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see 16111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see 16211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see 16311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see 16511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 16611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see 19311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see 19411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see 19511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see 19611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see 19711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see 19811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see 19911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see 20011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see 20111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see 20211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see 20311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see 20411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see 20511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see 20611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see 20711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see 20811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see 20911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see 21011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see 21111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see 21211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see 21311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see 21411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see 21511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see 21611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see 21711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see 21811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see 21911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see 22011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see 22111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see 22211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see 22311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see 22411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see 22511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see 22611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see 22711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see 22811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see 22911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see 23011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see 23111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see 23211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see 23311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see 23411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see 23511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see 23611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see 23711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see 23811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see 23911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see 24011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see 24111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation 24211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation 24311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation 24411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation 24511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation 24611754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation 24711754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation 24811754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation 24911754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation 25011754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation 25111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation 25211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation 25311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation 25411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation 25511754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes 25611754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes 25711754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes 25811754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26111754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes 26211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads 26311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads 26411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads 26511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads 26611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads 26711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads 26811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads 26911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads 27011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads 27111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads 27211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads 27311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads 27411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads 27511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads 27611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads 27711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads 27811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads 27911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads 28011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads 28111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads 28211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads 28311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads 28411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads 28511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads 28611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads 28711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads 28811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads 28911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 29011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 29111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads 29211754Sandreas.hansson@arm.comsystem.physmem.totQLat 46391884854 # Total ticks spent queuing 29311754Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM 29411754Sandreas.hansson@arm.comsystem.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers 29511754Sandreas.hansson@arm.comsystem.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst 29610515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 29711754Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst 29811502SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 29911606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 30011680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s 30111606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 30210515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 30311374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 30411201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 30510892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 30611754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing 30711754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing 30811754Sandreas.hansson@arm.comsystem.physmem.readRowHits 687053 # Number of row buffer hits during reads 30911754Sandreas.hansson@arm.comsystem.physmem.writeRowHits 479716 # Number of row buffer hits during writes 31011754Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads 31111754Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes 31211754Sandreas.hansson@arm.comsystem.physmem.avgGap 22596205.96 # Average gap between requests 31311680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined 31411754Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) 31511754Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) 31611754Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) 31711754Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) 31811754Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) 31911754Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) 32011754Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) 32111754Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) 32211754Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) 32311754Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) 32411754Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) 32511754Sandreas.hansson@arm.comsystem.physmem_0.averagePower 243.004907 # Core power per rank (mW) 32611754Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank 32711754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states 32811754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states 32911754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states 33011754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states 33111754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states 33211754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states 33311754Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) 33411754Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) 33511754Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) 33611754Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) 33711754Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) 33811754Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) 33911754Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) 34011754Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) 34111754Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) 34211754Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) 34311754Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) 34411754Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.918480 # Core power per rank (mW) 34511754Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank 34611754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states 34711754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states 34811754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states 34911754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states 35011754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states 35111754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states 35211754Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 35310515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35810515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35910515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 36010515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 36110515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36210515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36310515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36410515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36510515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36610515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37710515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37810515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37911754Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 38011754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 38111754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 38210535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38310535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38410535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38511680SCurtis.Dunham@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38611680SCurtis.Dunham@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38711680SCurtis.Dunham@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38810515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38911754Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 39010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 42011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 105104 # Table walker walks requested 42111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors 42211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate 42311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate 42411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting 42511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency 42611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency 42711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency 42811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency 43111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency 43211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency 43311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency 43411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency 43511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency 43611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency 43711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency 43811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency 43911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency 44011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency 44111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 44211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 44311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency 44411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 44511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency 44711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution 44811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution 44911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 45011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution 45111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution 45211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution 45311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated 45411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated 45511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated 45611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst 45710628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst 45911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst 46010628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst 46211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst 46310535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46410535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46511754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 85250979 # DTB read hits 46611754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 79026 # DTB read misses 46711754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 77401552 # DTB write hits 46811754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 26078 # DTB write misses 46910535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 47010535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47111754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID 47211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 47311754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB 47410535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 47511754Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch 47610535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47711754Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions 47811754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 85330005 # DTB read accesses 47911754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 77427630 # DTB write accesses 48010535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48111754Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 162652531 # DTB hits 48211754Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 105104 # DTB misses 48311754Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 162757635 # DTB accesses 48411754Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 48510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 51110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 51310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 51511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 55600 # Table walker walks requested 51611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors 51711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate 51811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate 51911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency 52011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency 52111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency 52211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency 52311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency 52411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency 52511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency 52611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency 52711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency 52811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency 52911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency 53011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency 53111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency 53211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency 53311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 53411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency 53511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 53611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency 53711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution 53811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution 53911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution 54011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated 54111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated 54211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated 54310628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst 54511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst 54610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst 54811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst 54911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst 55011754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 455710659 # ITB inst hits 55111754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 55600 # ITB inst misses 55210535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 55310535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 55410535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 55510535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 55610535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55710535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55811754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID 55911680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 56011754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB 56110535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56210535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56310535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56410535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56510535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 56610535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 56711754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 455766259 # ITB inst accesses 56811754Sandreas.hansson@arm.comsystem.cpu0.itb.hits 455710659 # DTB hits 56911754Sandreas.hansson@arm.comsystem.cpu0.itb.misses 55600 # DTB misses 57011754Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 455766259 # DTB accesses 57111754Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 25961 # Number of power state transitions 57211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state 57311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state 57411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state 57511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state 57611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state 57711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 57811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 57911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state 58011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 58111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 58211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 58311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 58411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state 58511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 58611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state 58711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state 58811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states 58911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states 59011754Sandreas.hansson@arm.comsystem.cpu0.numCycles 94809604801 # number of cpu cycles simulated 59110535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 59210535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 59311167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 59411754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed 59511754Sandreas.hansson@arm.comsystem.cpu0.committedInsts 455440444 # Number of instructions committed 59611754Sandreas.hansson@arm.comsystem.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed 59711754Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses 59811754Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses 59911754Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 27345084 # number of times a function call or return occured 60011754Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls 60111754Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 490602455 # number of integer instructions 60211754Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 409464 # number of float instructions 60311754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read 60411754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written 60511754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read 60611754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written 60711754Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read 60811754Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written 60911754Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 162644052 # number of memory refs 61011754Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 85246888 # Number of load instructions 61111754Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 77397164 # Number of store instructions 61211754Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles 61311754Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles 61411754Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles 61511754Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.988028 # Percentage of idle cycles 61611754Sandreas.hansson@arm.comsystem.cpu0.Branches 101837898 # Number of branches fetched 61711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 61811754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction 61911754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction 62011754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction 62111754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction 62211754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction 62311754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction 62411754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction 62511754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction 62611754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction 62711754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction 62811754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction 62911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction 63011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction 63111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction 63211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction 63311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction 63411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction 63511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction 63611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction 63711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction 63811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction 63911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction 64011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction 64111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction 64211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction 64311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction 64411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction 64511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction 64611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction 64711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction 64811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction 64911754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction 65011754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction 65111754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction 65211754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction 65310535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 65410535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 65511754Sandreas.hansson@arm.comsystem.cpu0.op_class::total 534571495 # Class of executed instruction 65611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 65711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5548235 # number of replacements 65811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use 65911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. 66011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. 66111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. 66211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. 66311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor 66411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy 66511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy 66611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 66711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id 66811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 66911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 67011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses 67111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses 67211754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 67311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits 67411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits 67511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits 67611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits 67711754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits 67811754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits 67911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits 68011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits 68111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits 68211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits 68311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits 68411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits 68511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits 68611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits 68711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits 68811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 152845533 # number of overall hits 68911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses 69011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses 69111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses 69211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses 69311754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses 69411754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses 69511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses 69611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses 69711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses 69811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses 69911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses 70011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses 70111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses 70211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses 70311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses 70411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5787416 # number of overall misses 70511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles 70611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles 70711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles 70811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles 70911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles 71011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles 71111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles 71211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles 71311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles 71411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles 71511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles 71611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles 71711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles 71811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles 71911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles 72011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles 72111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) 72211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) 72311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) 72411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) 72511754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) 72611754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) 72711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) 72811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) 72911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) 73011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) 73111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) 73211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) 73311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses 73411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses 73511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses 73611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses 73711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses 73811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses 73911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses 74011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses 74111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses 74211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses 74311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses 74411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses 74511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses 74611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses 74711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses 74811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses 74911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses 75011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses 75111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses 75211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses 75311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency 75411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency 75511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency 75611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency 75711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency 75811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency 75911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency 76011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency 76111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency 76211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency 76310535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 76410535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 76511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency 76611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency 76711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency 76811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency 76910535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77010535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77110535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 77210535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 77310535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77410535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77511754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks 77611754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5548235 # number of writebacks 77711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits 77811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits 77911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits 78011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits 78111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits 78211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits 78311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits 78411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits 78511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits 78611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits 78711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses 78811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses 78911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses 79011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses 79111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses 79211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses 79311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses 79411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses 79511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses 79611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses 79711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses 79811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses 79911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses 80011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses 80111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses 80211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses 80311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable 80411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable 80511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 80611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable 80711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses 80811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses 80911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles 81011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles 81111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles 81211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles 81311754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles 81411754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles 81511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles 81611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles 81711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles 81811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles 81911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles 82011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles 82111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles 82211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles 82311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles 82411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles 82511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles 82611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles 82711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles 82811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles 82911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles 83011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles 83111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses 83211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses 83311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses 83411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses 83511754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses 83611754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses 83711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses 83811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses 83911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses 84011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses 84111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses 84211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses 84311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses 84411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses 84511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses 84611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses 84711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency 84811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency 84911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency 85011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency 85111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency 85211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency 85311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency 85411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency 85511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency 85611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency 85711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency 85811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency 85910535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 86010535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 86111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency 86211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency 86311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency 86411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency 86511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency 86611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency 86711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency 86811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency 86911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 87011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 4928137 # number of replacements 87111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use 87211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. 87311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. 87411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. 87511754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. 87611754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor 87711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy 87811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy 87910535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id 88111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id 88210535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses 88411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses 88511754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 88611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits 88711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits 88811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits 88911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits 89011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits 89111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 450782010 # number of overall hits 89211754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses 89311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses 89411754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses 89511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses 89611754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses 89711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 4928649 # number of overall misses 89811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles 89911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles 90011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles 90111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles 90211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles 90311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles 90411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses) 90511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses) 90611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses 90711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses 90811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses 90911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses 91011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses 91111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses 91211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses 91311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses 91411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses 91511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses 91611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency 91711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency 91811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency 91911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency 92011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency 92111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency 92210535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92310535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92410535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 92510535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 92610535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92710535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92811754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks 92911754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 4928137 # number of writebacks 93011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses 93111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses 93211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses 93311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses 93411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses 93511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses 93610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 93710827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 93810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 93910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 94011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles 94111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles 94211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles 94311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles 94411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles 94511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles 94611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles 94711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles 94811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles 94911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles 95011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses 95111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses 95211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses 95311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses 95411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses 95511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses 95611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency 95711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency 95811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency 95911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency 96011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency 96111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency 96211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency 96311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency 96411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency 96511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency 96611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 96711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued 96811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified 96911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 97010628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97110628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing 97311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 97411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2238289 # number of replacements 97511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use 97611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks. 97711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks. 97811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks. 97911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit. 98011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor 98111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor 98211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor 98311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor 98411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy 98511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy 98611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy 98711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy 98811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy 98911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id 99011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 99111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id 99211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id 99311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id 99411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id 99511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 99611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id 99711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id 99811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id 99911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id 100011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id 100111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id 100211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 100311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id 100411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses 100511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses 100611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 100711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits 100811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits 100911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits 101011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits 101111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits 101211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits 101311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits 101411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits 101511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits 101611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits 101711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits 101811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits 101911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits 102011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits 102111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits 102211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits 102311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits 102411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits 102511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits 102611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits 102711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits 102811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits 102911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits 103011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits 103111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits 103211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses 103311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses 103411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses 103511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses 103611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses 103711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses 103811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses 103911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 104011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 104111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses 104211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses 104311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses 104411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses 104511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses 104611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses 104711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses 104811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses 104911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses 105011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses 105111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses 105211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses 105311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses 105411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses 105511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses 105611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses 105711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses 105811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses 105911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles 106011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles 106111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles 106211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles 106311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles 106411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles 106511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles 106611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles 106711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles 106811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles 106911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles 107011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles 107111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles 107211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles 107311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles 107411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles 107511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles 107611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles 107711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles 107811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles 107911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles 108011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles 108111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles 108211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles 108311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles 108411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles 108511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles 108611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses) 108711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses) 108811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses) 108911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses) 109011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses) 109111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses) 109211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses) 109311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses) 109411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses) 109511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses) 109611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses) 109711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 109811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 109911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses) 110011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses) 110111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses) 110211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses) 110311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses) 110411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses) 110511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses) 110611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses) 110711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses 110811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses 110911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses 111011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses 111111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses 111211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses 111311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses 111411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses 111511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses 111611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses 111711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses 111811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses 111911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses 112011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 112111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 112211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 112311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 112410535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 112510535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 112611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses 112711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses 112811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses 112911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses 113011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses 113111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses 113211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses 113311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses 113411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses 113511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses 113611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses 113711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses 113811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses 113911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses 114011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses 114111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses 114211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses 114311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses 114411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency 114511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency 114611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency 114711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency 114811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency 114911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency 115011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency 115111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency 115211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency 115311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency 115411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency 115511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency 115611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency 115711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency 115811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency 115911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency 116011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency 116111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency 116211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency 116311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency 116411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency 116511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency 116611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency 116711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency 116811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency 116911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency 117011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency 117110628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117210535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 117310628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 117410535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 117510628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 117610535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 117711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference 117811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks 117911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1501692 # number of writebacks 118011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits 118111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits 118211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits 118311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits 118411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits 118511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 118611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits 118711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits 118811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits 118911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits 119011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses 119111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses 119211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses 119311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses 119411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses 119511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses 119611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses 119711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses 119811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses 119911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 120011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 120111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses 120211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses 120311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses 120411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses 120511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses 120611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses 120711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses 120811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses 120911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses 121011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses 121111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses 121211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses 121311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses 121411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses 121511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses 121611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses 121711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses 121811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses 121911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses 122010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 122111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable 122211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable 122311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 122411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable 122510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 122611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses 122711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses 122811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles 122911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles 123011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles 123111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles 123211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles 123311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles 123411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles 123511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles 123611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles 123711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles 123811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles 123911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles 124011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles 124111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles 124211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles 124311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles 124411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles 124511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles 124611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles 124711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles 124811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles 124911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles 125011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles 125111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles 125211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles 125311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles 125411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles 125511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles 125611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles 125711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles 125811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles 125911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles 126011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles 126111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles 126211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles 126311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles 126411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses 126511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses 126611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses 126710535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 126810535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 126911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 127011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 127111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 127211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 127310535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 127410535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 127511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses 127611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses 127711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses 127811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses 127911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses 128011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses 128111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses 128211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses 128311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses 128411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses 128511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses 128611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses 128711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses 128811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses 128911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses 129011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses 129111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses 129210535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 129311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses 129411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency 129511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency 129611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency 129711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency 129811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency 129911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency 130011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency 130111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency 130211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency 130311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency 130411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency 130511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency 130611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency 130711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency 130811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency 130911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency 131011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency 131111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency 131211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency 131311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency 131411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency 131511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency 131611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency 131711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency 131811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency 131911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency 132011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency 132111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency 132211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency 132311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency 132411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency 132511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency 132611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency 132711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency 132811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency 132911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency 133011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. 133111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. 133211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 133311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. 133411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 133511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 133611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 133711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution 133811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution 133911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution 134011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution 134111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution 134211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution 134311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution 134411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution 134511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution 134611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution 134711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution 134811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 134911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 135011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution 135111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution 135211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution 135311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution 135411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution 135511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution 135611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) 135711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) 135811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) 135911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) 136011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) 136111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) 136211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) 136311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) 136411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) 136511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) 136611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) 136711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) 136811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram 136911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram 137011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram 137110535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram 137311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram 137411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 137510535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 137611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 137711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 137811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram 137911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) 138010535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 138111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) 138210535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 138311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) 138410535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 138511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) 138610535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 138711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) 138810535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 138911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) 139010535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 139111754Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 139210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 139310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 139410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 139510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 139610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 139710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 140110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 140210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 140310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 140410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 140510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 140610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 140710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 140810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 140910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 141010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 141110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 141210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 141310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 141410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 141510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 141610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 141710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 141810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 141910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 142010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 142111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 142211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 105151 # Table walker walks requested 142311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors 142411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate 142511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate 142611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 142711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency 142811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency 142911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency 143011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency 143111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 143211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency 143311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency 143411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency 143511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency 143611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency 143711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency 143811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency 143911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency 144011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency 144111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency 144211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency 144311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency 144411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency 144511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 144611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency 144711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 144811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency 144911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution 145011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution 145111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution 145211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution 145311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution 145411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution 145511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated 145611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated 145711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated 145811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst 145910628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst 146111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst 146210628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 146311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst 146411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst 146510535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 146610535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 146711754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 80227147 # DTB read hits 146811754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 76874 # DTB read misses 146911754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 72873093 # DTB write hits 147011754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 28277 # DTB write misses 147110535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 147210535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147311754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID 147411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 147511754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB 147610535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 147711754Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch 147810535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 147911754Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions 148011754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 80304021 # DTB read accesses 148111754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 72901370 # DTB write accesses 148210535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 148311754Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 153100240 # DTB hits 148411754Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 105151 # DTB misses 148511754Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 153205391 # DTB accesses 148611754Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 148710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 148810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 148910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 149010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 149110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 149210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 149310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 149410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 149510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 149610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 149710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 149810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 149910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 150010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 150110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 150210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 150610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 150710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 150810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 150910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 151010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 151110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 151210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 151310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 151410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 151510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 151611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 151711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 60537 # Table walker walks requested 151811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors 151911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate 152011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate 152111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency 152211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency 152311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency 152411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency 152511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency 152611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency 152711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency 152811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency 152911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency 153011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency 153111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency 153211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency 153311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency 153411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency 153511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 153611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency 153711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency 153811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 153911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency 154011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution 154111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution 154211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution 154311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated 154411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated 154511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated 154610628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 154711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst 154811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst 154910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 155011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst 155111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst 155211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst 155311754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 423099313 # ITB inst hits 155411754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 60537 # ITB inst misses 155510535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 155610535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 155710535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 155810535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 155910535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 156010535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 156111754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID 156211680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 156311754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB 156410535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 156510535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 156610535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 156710535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156810535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 156910535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 157011754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 423159850 # ITB inst accesses 157111754Sandreas.hansson@arm.comsystem.cpu1.itb.hits 423099313 # DTB hits 157211754Sandreas.hansson@arm.comsystem.cpu1.itb.misses 60537 # DTB misses 157311754Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 423159850 # DTB accesses 157411754Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 11486 # Number of power state transitions 157511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state 157611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state 157711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state 157811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state 157911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state 158011754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state 158111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state 158211754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state 158311754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state 158411754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state 158511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 158611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state 158711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state 158811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states 158911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states 159011754Sandreas.hansson@arm.comsystem.cpu1.numCycles 94810161765 # number of cpu cycles simulated 159110535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 159210535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 159311167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 159411754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed 159511754Sandreas.hansson@arm.comsystem.cpu1.committedInsts 422818462 # Number of instructions committed 159611754Sandreas.hansson@arm.comsystem.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed 159711754Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses 159811754Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses 159911754Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 25225246 # number of times a function call or return occured 160011754Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls 160111754Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 458669371 # number of integer instructions 160211754Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 488965 # number of float instructions 160311754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read 160411754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written 160511754Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read 160611754Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written 160711754Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read 160811754Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written 160911754Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 153090665 # number of memory refs 161011754Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 80223644 # Number of load instructions 161111754Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 72867021 # Number of store instructions 161211754Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles 161311754Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles 161411754Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles 161511754Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.989313 # Percentage of idle cycles 161611754Sandreas.hansson@arm.comsystem.cpu1.Branches 94103649 # Number of branches fetched 161711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 161811754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction 161911754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction 162011754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction 162111754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction 162211754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction 162311754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction 162411754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction 162511754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction 162611754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction 162711754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction 162811754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction 162911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction 163011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction 163111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction 163211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction 163311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction 163411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction 163511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction 163611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction 163711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction 163811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction 163911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction 164011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction 164111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction 164211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction 164311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction 164411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction 164511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction 164611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction 164711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction 164811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction 164911754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction 165011754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction 165111754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction 165211754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction 165310535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 165410535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 165511754Sandreas.hansson@arm.comsystem.cpu1.op_class::total 499098010 # Class of executed instruction 165611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 165711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5131141 # number of replacements 165811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use 165911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. 166011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. 166111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. 166211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. 166311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor 166411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy 166511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy 166611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 166711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 166811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 166911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 167011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 167111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses 167211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses 167311754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 167411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits 167511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits 167611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits 167711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits 167811754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits 167911754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits 168011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits 168111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits 168211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits 168311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits 168411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits 168511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits 168611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits 168711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits 168811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits 168911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 144074861 # number of overall hits 169011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses 169111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses 169211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses 169311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses 169411754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses 169511754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses 169611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses 169711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses 169811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses 169911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses 170011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses 170111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses 170211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses 170311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses 170411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses 170511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5314825 # number of overall misses 170611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles 170711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles 170811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles 170911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles 171011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles 171111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles 171211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles 171311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles 171411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles 171511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles 171611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles 171711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 171811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles 171911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles 172011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles 172111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles 172211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) 172311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) 172411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) 172511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) 172611754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) 172711754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) 172811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) 172911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) 173011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) 173111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) 173211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) 173311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) 173411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses 173511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses 173611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses 173711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses 173811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses 173911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses 174011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses 174111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses 174211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses 174311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses 174411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses 174511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses 174611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses 174711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses 174811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses 174911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses 175011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses 175111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses 175211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses 175311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses 175411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency 175511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency 175611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency 175711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency 175811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency 175911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency 176011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency 176111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency 176211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency 176311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency 176410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 176510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 176611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency 176711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency 176811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency 176911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency 177010535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 177110535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177210535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177310535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 177410535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 177510535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177611754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks 177711754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5131141 # number of writebacks 177811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits 177911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits 178011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits 178111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits 178211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits 178311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits 178411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits 178511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits 178611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits 178711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits 178811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses 178911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses 179011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses 179111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses 179211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses 179311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses 179411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses 179511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses 179611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses 179711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses 179811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses 179911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses 180011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses 180111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses 180211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses 180311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses 180411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable 180511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable 180611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 180711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable 180811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses 180911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses 181011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles 181111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles 181211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles 181311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles 181411754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles 181511754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles 181611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles 181711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles 181811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles 181911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles 182011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles 182111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles 182211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles 182311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles 182411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles 182511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles 182611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles 182711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles 182811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles 182911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles 183011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles 183111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles 183211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses 183311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses 183411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses 183511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses 183611754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses 183711754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses 183811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses 183911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses 184011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses 184111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses 184211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses 184311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses 184411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses 184511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses 184611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses 184711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses 184811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency 184911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency 185011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency 185111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency 185211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency 185311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency 185411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency 185511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency 185611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency 185711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency 185811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency 185911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency 186010535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 186110535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 186211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency 186311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency 186411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency 186511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency 186611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency 186711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency 186811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency 186911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency 187011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 187111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 5003710 # number of replacements 187211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use 187311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. 187411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. 187511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. 187611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. 187711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor 187811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy 187911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy 188010535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 188111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 188211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 188311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 188410535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 188511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses 188611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses 188711754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 188811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits 188911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits 189011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits 189111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits 189211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits 189311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 418095086 # number of overall hits 189411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses 189511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses 189611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses 189711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses 189811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses 189911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 5004227 # number of overall misses 190011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles 190111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles 190211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles 190311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles 190411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles 190511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles 190611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) 190711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) 190811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses 190911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses 191011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses 191111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses 191211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses 191311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses 191411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses 191511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses 191611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses 191711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses 191811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency 191911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency 192011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency 192111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency 192211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency 192311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency 192410535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 192510535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 192610535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 192710535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 192810535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 192910535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 193011754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks 193111754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 5003710 # number of writebacks 193211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses 193311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses 193411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses 193511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses 193611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses 193711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses 193810827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 193910827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 194010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 194110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 194211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles 194311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles 194411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles 194511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles 194611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles 194711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles 194811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles 194911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles 195011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles 195111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles 195211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses 195311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses 195411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses 195511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses 195611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses 195711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses 195811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency 195911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency 196011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency 196111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency 196211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency 196311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency 196411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency 196511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency 196611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency 196711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency 196811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 196911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued 197011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified 197111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 197210628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 197310628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 197411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing 197511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 197611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 1888854 # number of replacements 197711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use 197811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. 197911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. 198011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. 198111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 198211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor 198311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor 198411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor 198511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor 198611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy 198711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy 198811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy 198911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy 199011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy 199111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id 199211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id 199311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id 199411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 199511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 199611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id 199711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id 199811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 199911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id 200011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 200111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 200211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 200311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id 200411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id 200511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id 200611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id 200711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id 200811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id 200911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id 201011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses 201111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses 201211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 201311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits 201411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits 201511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits 201611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits 201711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits 201811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits 201911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits 202011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits 202111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits 202211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits 202311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits 202411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits 202511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits 202611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits 202711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits 202811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits 202911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits 203011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits 203111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits 203211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits 203311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits 203411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits 203511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits 203611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits 203711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits 203811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses 203911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses 204011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses 204111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses 204211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses 204311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses 204411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses 204511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 204611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 204711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses 204811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses 204911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses 205011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses 205111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses 205211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses 205311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses 205411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses 205511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses 205611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses 205711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses 205811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses 205911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses 206011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses 206111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses 206211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses 206311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses 206411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses 206511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles 206611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles 206711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles 206811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles 206911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles 207011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles 207111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles 207211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles 207311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles 207411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles 207511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles 207611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles 207711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles 207811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles 207911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles 208011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles 208111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles 208211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles 208311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles 208411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles 208511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles 208611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles 208711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles 208811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles 208911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles 209011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles 209111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles 209211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses) 209311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses) 209411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses) 209511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses) 209611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses) 209711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses) 209811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses) 209911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses) 210011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses) 210111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses) 210211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses) 210311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 210411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 210511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses) 210611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses) 210711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses) 210811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses) 210911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses) 211011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses) 211111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses) 211211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses) 211311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses 211411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses 211511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses 211611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses 211711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses 211811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses 211911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses 212011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses 212111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses 212211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses 212311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses 212411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses 212511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses 212611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 212711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 212811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 212911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 213010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 213110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 213211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses 213311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses 213411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses 213511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses 213611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses 213711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses 213811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses 213911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses 214011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses 214111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses 214211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses 214311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses 214411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses 214511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses 214611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses 214711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses 214811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses 214911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses 215011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency 215111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency 215211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency 215311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency 215411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency 215511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency 215611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency 215711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency 215811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency 215911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency 216011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency 216111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency 216211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency 216311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency 216411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency 216511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency 216611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency 216711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency 216811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency 216911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency 217011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency 217111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency 217211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency 217311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency 217411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency 217511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency 217611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency 217710628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217810535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 217910628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 218010535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 218110628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 218210535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 218311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference 218411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks 218511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1086447 # number of writebacks 218611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits 218711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits 218811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits 218911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits 219011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 219111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 219211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits 219311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits 219411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits 219511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits 219611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses 219711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses 219811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses 219911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses 220011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses 220111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses 220211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses 220311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses 220411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses 220511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 220611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 220711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses 220811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses 220911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses 221011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses 221111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses 221211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses 221311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses 221411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses 221511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses 221611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses 221711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses 221811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses 221911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses 222011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses 222111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses 222211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses 222311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses 222411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses 222511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses 222610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 222711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable 222811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable 222911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 223011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable 223110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 223211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses 223311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses 223411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles 223511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles 223611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles 223711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles 223811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles 223911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles 224011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles 224111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles 224211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles 224311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles 224411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles 224511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles 224611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles 224711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles 224811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles 224911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles 225011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles 225111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles 225211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles 225311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles 225411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles 225511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles 225611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles 225711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles 225811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles 225911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles 226011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles 226111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles 226211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles 226311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles 226411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles 226511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles 226611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles 226711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles 226811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles 226911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles 227011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses 227111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses 227211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses 227310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 227410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 227511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 227611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 227711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 227811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 227910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 228010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 228111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses 228211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses 228311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses 228411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses 228511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses 228611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses 228711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses 228811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses 228911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses 229011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses 229111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses 229211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses 229311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses 229411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses 229511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses 229611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses 229711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses 229810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 229911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses 230011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency 230111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency 230211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency 230311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency 230411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency 230511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency 230611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency 230711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency 230811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency 230911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency 231011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency 231111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency 231211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency 231311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency 231411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency 231511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency 231611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency 231711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency 231811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency 231911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency 232011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency 232111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency 232211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency 232311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency 232411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency 232511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency 232611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency 232711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency 232811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency 232911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency 233011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency 233111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency 233211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency 233311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency 233411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency 233511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency 233611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. 233711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. 233811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 233911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. 234011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 234111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 234211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 234311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution 234411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution 234511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution 234611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution 234711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution 234811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution 234911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution 235011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution 235111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution 235211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution 235311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution 235411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 235511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 235611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution 235711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution 235811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution 235911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution 236011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution 236111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution 236211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) 236311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) 236411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) 236511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) 236611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) 236711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) 236811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) 236911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) 237011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) 237111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) 237211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) 237311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) 237411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram 237511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram 237611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram 237710535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 237811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram 237911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram 238011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 238110535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 238211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 238311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 238411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram 238511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) 238610535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 238711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) 238810535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 238911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) 239010535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 239111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) 239210535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 239311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) 239410535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 239511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) 239610535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 239711754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 239811754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40383 # Transaction distribution 239911754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40383 # Transaction distribution 240011754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136636 # Transaction distribution 240111754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136636 # Transaction distribution 240211754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) 240310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 240411245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 240510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 240610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 240710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 240810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 240910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 241010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 241110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 241210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 241311754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 241410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 241511754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) 241611754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) 241711754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) 241810535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 241910535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 242011754Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) 242111754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) 242210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 242311245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 242410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 242510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 242610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 242710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 242810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 242910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 243010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 243110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 243211754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 243310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 243411754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) 243511754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) 243611754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) 243710535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 243810535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 243911754Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) 244011754Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) 244110535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 244211754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 244310535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 244411754Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) 244510535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 244611754Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 244710535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 244811754Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) 244911245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 245010535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 245110535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 245211754Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 245310535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 245411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 245510535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 245611201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 245710535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 245811754Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 245910535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 246011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 246110535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 246211754Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) 246310535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 246411754Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) 246510535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 246611754Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) 246710535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 246811754Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) 246910535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 247011754Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) 247110535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 247210892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 247310535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 247411754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 247511754Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115614 # number of replacements 247611754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use 247711336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 247811754Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. 247911336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 248011754Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. 248111754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor 248211754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor 248311754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy 248411754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy 248511754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy 248610535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 248710535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 248810535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 248911754Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1041054 # Number of tag accesses 249011754Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1041054 # Number of data accesses 249111754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 249210535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 249311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses 249411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8942 # number of ReadReq misses 249510535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 249610535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 249711680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 249811680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 249910535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 250011754Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses 250111754Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115673 # number of demand (read+write) misses 250210535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 250311754Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115633 # number of overall misses 250411754Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115673 # number of overall misses 250511754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 250611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles 250711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles 250810726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 250910726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 251011754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles 251111754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles 251211754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 251311754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles 251411754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles 251511754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 251611754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles 251711754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles 251810535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 251911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) 252011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) 252110535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 252210535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 252311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 252411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 252510535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 252611754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses 252711754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses 252810535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 252911754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses 253011754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses 253110535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 253210535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 253310535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 253410535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 253510535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 253611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 253711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 253810535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 253910535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 254010535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 254110535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 254210535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 254310535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 254411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 254511754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency 254611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency 254710726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 254810726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 254911754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency 255011754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency 255111754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 255211754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency 255311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency 255411754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 255511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency 255611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency 255711754Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked 255810535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 255911754Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked 256010535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 256111754Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked 256210535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 256311754Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 256411754Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 256510535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 256611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses 256711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses 256810535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 256910535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 257011680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 257111680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 257210535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 257311754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses 257411754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses 257510535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 257611754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses 257711754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses 257811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 257911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles 258011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles 258110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 258210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 258311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles 258411754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles 258511754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 258611754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles 258711754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles 258811754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 258911754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles 259011754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles 259110535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 259210535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 259310535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 259410535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 259510535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 259611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 259711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 259810535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 259910535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 260010535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 260110535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 260210535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 260310535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 260411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 260511754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency 260611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency 260710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 260810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 260911754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency 261011754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency 261111754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 261211754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency 261311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency 261411754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 261511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency 261611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency 261711754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 261811754Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1381741 # number of replacements 261911754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use 262011754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5923587 # Total number of references to valid blocks. 262111754Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks. 262211754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks. 262311754Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit. 262411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor 262511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor 262611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor 262711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor 262811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor 262911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor 263011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor 263111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor 263211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor 263311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor 263411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor 263511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy 263611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy 263711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy 263811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy 263911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy 264011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy 264111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy 264211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy 264311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy 264411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy 264511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy 264611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy 264711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id 264811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id 264911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id 265011754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id 265111754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id 265211754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id 265311754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 265411754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id 265511680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 265611754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 265711754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id 265811754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id 265911754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id 266011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id 266111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 266211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id 266311754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 67794643 # Number of tag accesses 266411754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 67794643 # Number of data accesses 266511754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 266611754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits 266711754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits 266811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits 266911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits 267011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits 267111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits 267211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits 267311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits 267411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits 267511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits 267611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits 267711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits 267811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits 267911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits 268011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits 268111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits 268211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits 268311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits 268411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits 268511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits 268611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits 268711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits 268811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits 268911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits 269011754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits 269111754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits 269211754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits 269311754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits 269411754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits 269511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits 269611754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits 269711754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits 269811754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits 269911754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits 270011754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits 270111754Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2537328 # number of demand (read+write) hits 270211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits 270311754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits 270411754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 389694 # number of overall hits 270511754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 556846 # number of overall hits 270611754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits 270711754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits 270811754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits 270911754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 424247 # number of overall hits 271011754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 597655 # number of overall hits 271111754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits 271211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2537328 # number of overall hits 271311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses 271411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses 271511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses 271611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses 271711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses 271811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses 271911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses 272011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses 272111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses 272211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses 272311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses 272411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses 272511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses 272611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses 272711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses 272811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses 272911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses 273011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses 273111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses 273211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses 273311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses 273411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses 273511754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses 273611754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses 273711754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses 273811754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses 273911754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses 274011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses 274111754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses 274211754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses 274311754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses 274411754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses 274511754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses 274611754Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 879096 # number of demand (read+write) misses 274711754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses 274811754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses 274911754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 53195 # number of overall misses 275011754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 218373 # number of overall misses 275111754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses 275211754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses 275311754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses 275411754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 39604 # number of overall misses 275511754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 151830 # number of overall misses 275611754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses 275711754Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 879096 # number of overall misses 275811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles 275911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles 276011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles 276111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles 276211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles 276311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles 276411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles 276511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles 276611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles 276711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles 276811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles 276911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles 277011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles 277111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles 277211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles 277311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles 277411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles 277511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles 277611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles 277711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles 277811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles 277911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles 278011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles 278111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles 278211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles 278311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles 278411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles 278511754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles 278611754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles 278711754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles 278811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles 278911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles 279011754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles 279111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles 279211754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles 279311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles 279411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles 279511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles 279611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles 279711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles 279811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles 279911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles 280011754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses) 280111754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses) 280211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses) 280311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses) 280411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses) 280511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses) 280611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses) 280711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses) 280811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses) 280911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses) 281011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses) 281111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses) 281211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses) 281311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses) 281411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses) 281511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses) 281611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses) 281711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses) 281811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses) 281911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses) 282011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses) 282111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses) 282211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses) 282311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses) 282411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses) 282511754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses 282611754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses 282711754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses 282811754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses 282911754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses 283011754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses 283111754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses 283211754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses 283311754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses 283411754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses 283511754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses 283611754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses 283711754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses 283811754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses 283911754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses 284011754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses 284111754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses 284211754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses 284311754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses 284411754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses 284511754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses 284611754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses 284711754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses 284811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses 284911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses 285011754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses 285111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses 285211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses 285311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses 285411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses 285511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses 285611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses 285711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses 285811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses 285911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses 286011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses 286111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses 286211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses 286311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses 286411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses 286511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses 286611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses 286711754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses 286811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses 286911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses 287011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses 287111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses 287211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses 287311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses 287411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses 287511754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses 287611754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses 287711754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses 287811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses 287911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses 288011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses 288111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses 288211754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses 288311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses 288411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses 288511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses 288611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses 288711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses 288811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses 288911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses 289011754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses 289111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses 289211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency 289311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency 289411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency 289511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency 289611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency 289711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency 289811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency 289911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency 290011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency 290111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency 290211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency 290311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency 290411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency 290511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency 290611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency 290711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency 290811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency 290911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency 291011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency 291111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency 291211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency 291311754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency 291411754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency 291511754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency 291611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency 291711754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency 291811754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency 291911754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency 292011754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency 292111754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency 292211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency 292311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency 292411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency 292511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency 292611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency 292711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency 292811754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency 292911754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency 293011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency 293111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency 293211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency 293311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency 293411754Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked 293510515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 293611754Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 293710515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 293811754Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked 293910515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 294011754Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1061178 # number of writebacks 294111754Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1061178 # number of writebacks 294211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits 294311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits 294411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits 294511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits 294611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits 294711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits 294811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits 294911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits 295011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits 295111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits 295211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits 295311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits 295411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits 295511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits 295611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits 295711754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses 295811754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses 295911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses 296011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses 296111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses 296211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses 296311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses 296411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses 296511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses 296611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses 296711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses 296811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses 296911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses 297011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses 297111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses 297211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses 297311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses 297411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses 297511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses 297611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses 297711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses 297811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses 297911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses 298011754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses 298111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses 298211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses 298311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses 298411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses 298511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses 298611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses 298711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses 298811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses 298911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses 299011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses 299111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses 299211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses 299311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses 299411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses 299511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses 299611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses 299711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses 299811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses 299911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses 300011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses 300111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses 300211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses 300311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses 300410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 300511754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable 300610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 300711754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable 300811754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable 300911754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 301011754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 301111754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable 301210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 301311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses 301410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 301511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses 301611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses 301711754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles 301811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles 301911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles 302011754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles 302111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles 302211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles 302311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles 302411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # number of ReadExReq MSHR miss cycles 302511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 12432086139 # number of ReadExReq MSHR miss cycles 302611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of ReadSharedReq MSHR miss cycles 302711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 140574501 # number of ReadSharedReq MSHR miss cycles 302811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5355219542 # number of ReadSharedReq MSHR miss cycles 302911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14279847185 # number of ReadSharedReq MSHR miss cycles 303011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of ReadSharedReq MSHR miss cycles 303111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of ReadSharedReq MSHR miss cycles 303211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 196268502 # number of ReadSharedReq MSHR miss cycles 303311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4312153532 # number of ReadSharedReq MSHR miss cycles 303411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles 303511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles 303611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles 303711754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles 303811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles 303911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles 304011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles 304111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles 304211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # number of demand (read+write) MSHR miss cycles 304311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 21714443231 # number of demand (read+write) MSHR miss cycles 304411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of demand (read+write) MSHR miss cycles 304511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of demand (read+write) MSHR miss cycles 304611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 196268502 # number of demand (read+write) MSHR miss cycles 304711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 4312153532 # number of demand (read+write) MSHR miss cycles 304811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 15765200265 # number of demand (read+write) MSHR miss cycles 304911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of demand (read+write) MSHR miss cycles 305011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 98637178589 # number of demand (read+write) MSHR miss cycles 305111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of overall MSHR miss cycles 305211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles 305311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles 305411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles 305511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles 305611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles 305711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles 305811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles 305911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles 306011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles 306111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles 306211680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles 306311754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4911881502 # number of ReadReq MSHR uncacheable cycles 306411754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 8111000 # number of ReadReq MSHR uncacheable cycles 306511754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1045413500 # number of ReadReq MSHR uncacheable cycles 306611754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8982252002 # number of ReadReq MSHR uncacheable cycles 306711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles 306811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles 306911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles 307011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles 307111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles 307210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 307310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 307411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses 307511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses 307611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses 307711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses 307811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses 307911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses 308011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses 308111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses 308211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses 308311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses 308411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses 308511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses 308611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses 308711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses 308811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses 308911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses 309011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses 309111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses 309211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses 309311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses 309411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses 309511754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses 309611754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses 309711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses 309811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses 309911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses 310011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses 310111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses 310211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses 310311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses 310411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses 310511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses 310611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses 310711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses 310811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses 310911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses 311011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses 311111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses 311211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses 311311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses 311411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses 311511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses 311611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses 311711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses 311811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses 311911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency 312011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency 312111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency 312211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency 312311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency 312411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency 312511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency 312611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency 312711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency 312811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency 312911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency 313011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency 313111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency 313211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency 313311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency 313411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency 313511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency 313611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency 313711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency 313811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency 313911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency 314011754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency 314111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency 314211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency 314311754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency 314411754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency 314511754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency 314611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency 314711754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency 314811754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency 314911754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency 315011754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency 315111754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency 315211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency 315311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency 315411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency 315511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency 315611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency 315711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency 315811754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency 315911754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency 316011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency 316111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency 316211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency 316311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency 316411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency 316511754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency 316611754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency 316711754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency 316811754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency 316911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency 317011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency 317111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency 317211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency 317311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency 317411754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. 317511754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. 317611754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 317711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 317811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 317911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 318011754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 318111754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 81785 # Transaction distribution 318211754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 843578 # Transaction distribution 318311754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38414 # Transaction distribution 318411754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38414 # Transaction distribution 318511754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution 318611754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 225685 # Transaction distribution 318711754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 305919 # Transaction distribution 318811754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution 318911754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 319011754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 319111754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 142258 # Transaction distribution 319211754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 125306 # Transaction distribution 319311754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution 319411754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 628104 # Transaction distribution 319511754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 29933 # Transaction distribution 319611754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) 319710535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 319811754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) 319911754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) 320011754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) 320111754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) 320211754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) 320311754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) 320411754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) 320510535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 320611754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) 320711754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) 320811754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) 320911754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) 321011754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) 321111754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) 321211754Sandreas.hansson@arm.comsystem.membus.snoops 601899 # Total snoops (count) 321311754Sandreas.hansson@arm.comsystem.membus.snoopTraffic 182272 # Total snoop traffic (bytes) 321411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2241138 # Request fanout histogram 321511754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.014818 # Request fanout histogram 321611754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram 321710535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 321811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram 321911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram 322010535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 322110535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 322211502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 322310535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 322411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2241138 # Request fanout histogram 322511754Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) 322610535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 322711754Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 322810535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 322911754Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) 323010535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 323111754Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) 323210535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 323311754Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) 323410535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 323511754Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) 323610535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 323711754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 323811754Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 323911754Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 324011754Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 324111754Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 324211754Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 324311754Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 324411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 324511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 324611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 324711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 324811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 324911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 325011754Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 325111754Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 325210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 325310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 325410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 325510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 325610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 325710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 325810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 325910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 326010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 326111374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 326210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 326310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 326410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 326511374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 326610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 326710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 326810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 326910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 327010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 327110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 327210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 327310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 327410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 327510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 327610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 327710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 327810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 327910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 328010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 328110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 328210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 328310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 328410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 328510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 328610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 328710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 328810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 328910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 329010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 329110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 329210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 329310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 329411754Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 329511754Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 329611754Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 329711754Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 329811754Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 329911754Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330011754Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 330211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 330311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 330411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 330511754Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330611754Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330711754Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330811754Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 330911754Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331011754Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331111754Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331211754Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331311754Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331411754Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331511754Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331611754Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 331711754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. 331811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. 331911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 332011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. 332111754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 332211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 332311754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 332411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution 332511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution 332611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution 332711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution 332811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution 332911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution 333011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution 333111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution 333211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution 333311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution 333411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 333511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution 333611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution 333711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution 333811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution 333911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution 334011754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) 334111754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) 334211754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) 334311754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) 334411754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) 334511754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) 334611754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 2851175 # Total snoops (count) 334711754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) 334811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram 334911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram 335011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram 335110515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 335211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram 335311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram 335411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram 335510515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 335611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 335710515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 335811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram 335911754Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) 336010515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 336111754Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) 336210515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 336311754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) 336410515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 336511754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) 336610515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 336710515SN/A 336810515SN/A---------- End Simulation Statistics ---------- 3369