stats.txt revision 11606
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 47.374315 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 47374315410500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 573964 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 675116 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 30496109280 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 762100 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 1553.45 # Real time elapsed on the host 1211606Sandreas.sandberg@arm.comsim_insts 891626325 # Number of instructions simulated 1311606Sandreas.sandberg@arm.comsim_ops 1048762579 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 56553028 # Number of bytes read from this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory 3011606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory 3211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 74853032 # Number of bytes written to this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory 3711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory 3811606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory 3911606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory 4011606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory 4111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory 4211606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory 4311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory 4411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory 4511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory 4611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory 4711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 924162 # Number of read requests responded to by this memory 4811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s) 5311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s) 5611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s) 5711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s) 5811606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) 5911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s) 6011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s) 6111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s) 6211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s) 6311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s) 6411606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s) 6511606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s) 6611606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s) 6711606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s) 7111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s) 7211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s) 7311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s) 7411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s) 7511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s) 7611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s) 7711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s) 7811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) 7911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s) 8011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s) 8111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s) 8211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s) 8311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s) 8411606Sandreas.sandberg@arm.comsystem.physmem.readReqs 924162 # Number of read requests accepted 8511606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 1171831 # Number of write requests accepted 8611606Sandreas.sandberg@arm.comsystem.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue 8711606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue 8811606Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM 8911606Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue 9011606Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM 9111606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side 9211606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side 9311606Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue 9411606Sandreas.sandberg@arm.comsystem.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 54791 # Per bank write bursts 9711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 60963 # Per bank write bursts 9811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 51680 # Per bank write bursts 9911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 61600 # Per bank write bursts 10011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 56399 # Per bank write bursts 10111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 67623 # Per bank write bursts 10211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 62592 # Per bank write bursts 10311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 58195 # Per bank write bursts 10411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 51047 # Per bank write bursts 10511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 95684 # Per bank write bursts 10611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 47816 # Per bank write bursts 10711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 53141 # Per bank write bursts 10811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 48535 # Per bank write bursts 10911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 54663 # Per bank write bursts 11011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 49130 # Per bank write bursts 11111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 49949 # Per bank write bursts 11211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 71660 # Per bank write bursts 11311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 78743 # Per bank write bursts 11411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 71851 # Per bank write bursts 11511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 78616 # Per bank write bursts 11611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 73485 # Per bank write bursts 11711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 81529 # Per bank write bursts 11811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 75635 # Per bank write bursts 11911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 74455 # Per bank write bursts 12011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 70456 # Per bank write bursts 12111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 72917 # Per bank write bursts 12211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 67611 # Per bank write bursts 12311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 70918 # Per bank write bursts 12411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 67621 # Per bank write bursts 12511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 71486 # Per bank write bursts 12611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 70570 # Per bank write bursts 12711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 72018 # Per bank write bursts 12810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911606Sandreas.sandberg@arm.comsystem.physmem.numWrRetry 85 # Number of times write queue was full causing retry 13011606Sandreas.sandberg@arm.comsystem.physmem.totGap 47374312061000 # Total gap between requests 13110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 880937 # Read request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 1169257 # Write request sizes (log2) 14511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see 14611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see 14711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see 14811606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see 14911606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see 15011606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see 15111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see 15211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see 15311606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see 15411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see 15511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see 15611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see 15711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see 15811606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see 15911606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see 16011606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see 16111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see 16211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see 16311606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see 16411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 16511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 16611502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see 19311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see 19411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see 19511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see 19611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see 19711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see 19811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see 19911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see 20011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see 20111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see 20211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see 20311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see 20411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see 20511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see 20611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see 20711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see 20811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see 20911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see 21011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see 21111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see 21211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see 21311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see 21411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see 21511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see 21611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see 21711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see 21811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see 21911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see 22011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see 22111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see 22211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see 22311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see 22411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see 22511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see 22611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see 22711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see 22811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see 22911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see 23011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see 23111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see 23211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see 23311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see 23411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see 23511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see 23611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see 23711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see 23811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see 23911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see 24011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see 24111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation 24211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation 24311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation 24411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation 24511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation 24611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation 24711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation 24811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation 24911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation 25011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation 25111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation 25211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation 25311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation 25411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation 25511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes 25611606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes 25711606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes 25811606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes 25911606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26211606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes 26311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads 26411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads 26511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads 26611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads 26711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads 26811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads 26911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads 27011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads 27111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads 27211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads 27311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads 27411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads 27511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads 27611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads 27711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads 27811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads 27911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads 28011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads 28111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads 28211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads 28311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads 28411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads 28511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads 28611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads 28711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads 28811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 28911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads 29011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads 29111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 29211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads 29311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads 29411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads 29511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 29611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads 29711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads 29811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads 29911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads 30011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads 30111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 30211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads 30311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 30411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 30511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads 30611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 30711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads 30811606Sandreas.sandberg@arm.comsystem.physmem.totQLat 30413749694 # Total ticks spent queuing 30911606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM 31011606Sandreas.sandberg@arm.comsystem.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers 31111606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst 31210515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31311606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst 31411502SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 31511606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 31611502SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s 31711606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 31810515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31911374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32011201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32110892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32211606Sandreas.sandberg@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 32311606Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing 32411606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 683627 # Number of row buffer hits during reads 32511606Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 482581 # Number of row buffer hits during writes 32611606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads 32711606Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes 32811606Sandreas.sandberg@arm.comsystem.physmem.avgGap 22602323.61 # Average gap between requests 32911606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined 33011606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ) 33111606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ) 33211606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ) 33311606Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ) 33411606Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) 33511606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ) 33611606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ) 33711606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ) 33811606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 668.688048 # Core power per rank (mW) 33911606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states 34011606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states 34110628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34211606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states 34310628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34411606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ) 34511606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ) 34611606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ) 34711606Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ) 34811606Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) 34911606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ) 35011606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ) 35111606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ) 35211606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 668.629051 # Core power per rank (mW) 35311606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states 35411606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states 35510628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35611606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states 35710628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35811606Sandreas.sandberg@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 35910515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 36010515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 36110515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 36210515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 36310515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 36410515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 36510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 36610515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 36710515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36810515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36910515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 37010515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 37110515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 37210515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 37710515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37810515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37910515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 38010515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 38110515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 38210515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 38310515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38410515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 38511606Sandreas.sandberg@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 38611606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 38711606Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 38810535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38910535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 39010535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 39111606Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 39211606Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 39311606Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 39410515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 39511606Sandreas.sandberg@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 39610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 42010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 42611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walks 101108 # Table walker walks requested 42711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors 42811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate 42911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate 43011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting 43111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency 43211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency 43311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency 43411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency 43511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency 43611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency 43711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency 43811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency 43911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency 44011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency 44111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency 44211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency 44311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency 44411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency 44511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency 44611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency 44711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency 44811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 44911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 45011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 45111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency 45411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution 45511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution 45611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution 45711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution 45811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution 45911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution 46011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated 46111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated 46211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated 46311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst 46410628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst 46611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst 46710628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst 46911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst 47010535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47110535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_hits 84046306 # DTB read hits 47311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_misses 73432 # DTB read misses 47411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_hits 77237834 # DTB write hits 47511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_misses 27676 # DTB write misses 47610535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 47710535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID 47911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 48011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB 48110535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 48211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch 48310535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions 48511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_accesses 84119738 # DTB read accesses 48611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_accesses 77265510 # DTB write accesses 48710535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.hits 161284140 # DTB hits 48911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.misses 101108 # DTB misses 49011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.accesses 161385248 # DTB accesses 49111606Sandreas.sandberg@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 49210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 51810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 52211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walks 58460 # Table walker walks requested 52311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors 52411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate 52511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate 52611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency 52711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency 52811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency 52911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency 53011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency 53111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency 53211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency 53311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency 53411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency 53511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency 53611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency 53711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency 53811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency 53911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency 54011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency 54111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency 54211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency 54311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 54411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 54511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 54611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 54711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 54811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency 54911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution 55011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution 55111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution 55211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated 55311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated 55411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated 55510628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst 55711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst 55810628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 55911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst 56011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst 56111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst 56211606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_hits 449335815 # ITB inst hits 56311606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_misses 58460 # ITB inst misses 56410535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 56510535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 56610535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 56710535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 56810535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 56910535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57011606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID 57111606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 57211606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB 57310535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57410535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57510535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57610535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57710535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 57810535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 57911606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_accesses 449394275 # ITB inst accesses 58011606Sandreas.sandberg@arm.comsystem.cpu0.itb.hits 449335815 # DTB hits 58111606Sandreas.sandberg@arm.comsystem.cpu0.itb.misses 58460 # DTB misses 58211606Sandreas.sandberg@arm.comsystem.cpu0.itb.accesses 449394275 # DTB accesses 58311606Sandreas.sandberg@arm.comsystem.cpu0.numPwrStateTransitions 8624 # Number of power state transitions 58411606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state 58511606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state 58611606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state 58711606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state 58811606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state 58911606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state 59011606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state 59111606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state 59211606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 59311606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state 59411606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state 59511606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state 59611606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state 59711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 59811606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state 59911606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state 60011606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states 60111606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states 60211606Sandreas.sandberg@arm.comsystem.cpu0.numCycles 94748630821 # number of cpu cycles simulated 60310535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 60410535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 60511167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 60611606Sandreas.sandberg@arm.comsystem.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed 60711606Sandreas.sandberg@arm.comsystem.cpu0.committedInsts 449083110 # Number of instructions committed 60811606Sandreas.sandberg@arm.comsystem.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed 60911606Sandreas.sandberg@arm.comsystem.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses 61011606Sandreas.sandberg@arm.comsystem.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses 61111606Sandreas.sandberg@arm.comsystem.cpu0.num_func_calls 26866500 # number of times a function call or return occured 61211606Sandreas.sandberg@arm.comsystem.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls 61311606Sandreas.sandberg@arm.comsystem.cpu0.num_int_insts 485390643 # number of integer instructions 61411606Sandreas.sandberg@arm.comsystem.cpu0.num_fp_insts 507449 # number of float instructions 61511606Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read 61611606Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written 61711606Sandreas.sandberg@arm.comsystem.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read 61811606Sandreas.sandberg@arm.comsystem.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written 61911606Sandreas.sandberg@arm.comsystem.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read 62011606Sandreas.sandberg@arm.comsystem.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written 62111606Sandreas.sandberg@arm.comsystem.cpu0.num_mem_refs 161276211 # number of memory refs 62211606Sandreas.sandberg@arm.comsystem.cpu0.num_load_insts 84042257 # Number of load instructions 62311606Sandreas.sandberg@arm.comsystem.cpu0.num_store_insts 77233954 # Number of store instructions 62411606Sandreas.sandberg@arm.comsystem.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles 62511606Sandreas.sandberg@arm.comsystem.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles 62611606Sandreas.sandberg@arm.comsystem.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles 62711606Sandreas.sandberg@arm.comsystem.cpu0.idle_fraction 0.988242 # Percentage of idle cycles 62811606Sandreas.sandberg@arm.comsystem.cpu0.Branches 100200450 # Number of branches fetched 62911606Sandreas.sandberg@arm.comsystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 63011606Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction 63111606Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction 63211606Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction 63311606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction 63411606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction 63511606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction 63611606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction 63711606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction 63811606Sandreas.sandberg@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction 63911606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction 64011606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction 64111606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction 64211606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction 64311606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction 64411606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction 64511606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction 64611606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction 64711606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction 64811606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction 64911606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction 65011606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction 65111606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction 65211606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction 65311606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction 65411606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction 65511606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction 65611606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction 65711606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction 65811606Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction 65911606Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction 66011606Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction 66110535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 66210535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 66311606Sandreas.sandberg@arm.comsystem.cpu0.op_class::total 528680248 # Class of executed instruction 66411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 66511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.replacements 5566798 # number of replacements 66611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use 66711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks. 66811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks. 66911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks. 67011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 67111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor 67211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy 67311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy 67411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 67511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 67611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id 67711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id 67811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 67911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses 68011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses 68111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 68211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits 68311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits 68411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits 68511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits 68611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits 68711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits 68811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits 68911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits 69011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits 69111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits 69211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits 69311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits 69411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits 69511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits 69611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits 69711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 151545934 # number of overall hits 69811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses 69911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses 70011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses 70111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses 70211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses 70311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses 70411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses 70511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses 70611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses 70711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses 70811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses 70911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses 71011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses 71111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses 71211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses 71311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 5837748 # number of overall misses 71411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles 71511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles 71611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles 71711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles 71811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles 71911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles 72011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles 72111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles 72211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles 72311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles 72411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles 72511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles 72611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles 72711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles 72811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles 72911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles 73011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses) 73111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses) 73211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses) 73311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses) 73411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses) 73511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses) 73611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses) 73711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses) 73811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses) 73911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses) 74011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses) 74111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses) 74211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses 74311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses 74411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses 74511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses 74611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses 74711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses 74811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses 74911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses 75011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses 75111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses 75211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses 75311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses 75411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses 75511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses 75611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses 75711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses 75811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses 75911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses 76011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses 76111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses 76211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency 76311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency 76411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency 76511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency 76611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency 76711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency 76811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency 76911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency 77011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency 77111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency 77210535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77310535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency 77511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency 77611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency 77711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency 77810535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77910535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78010535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78110535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78210535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78310535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks 78511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 5566798 # number of writebacks 78611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits 78711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits 78811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits 78911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits 79011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits 79111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits 79211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits 79311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits 79411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits 79511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits 79611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses 79711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses 79811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses 79911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses 80011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses 80111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses 80211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses 80311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses 80411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses 80511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses 80611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses 80711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses 80811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses 80911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses 81011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses 81111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses 81211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable 81311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable 81411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable 81511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable 81611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses 81711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses 81811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles 81911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles 82011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles 82111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles 82211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles 82311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles 82411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles 82511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles 82611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles 82711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles 82911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles 83011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles 83111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles 83211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles 83311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles 83411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles 83511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles 83611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles 83711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles 83811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles 83911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles 84011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses 84111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses 84211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses 84311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses 84411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses 84511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses 84611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses 84711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses 84811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses 84911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses 85011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses 85111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses 85211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses 85311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses 85411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses 85511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses 85611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency 85711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency 85811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency 85911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency 86011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency 86111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency 86211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency 86311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency 86411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency 86511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency 86611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency 86711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency 86810535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 86910535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 87011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency 87111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency 87211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency 87311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency 87411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency 87511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency 87611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency 87711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency 87811606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 87911606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.replacements 5174135 # number of replacements 88011606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use 88111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks. 88211606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks. 88311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks. 88411606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit. 88511606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor 88611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy 88711570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy 88810535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88911606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 89011606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id 89111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id 89210535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses 89411606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses 89511606Sandreas.sandberg@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 89611606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits 89711606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits 89811606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits 89911606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits 90011606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits 90111606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 444161163 # number of overall hits 90211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses 90311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses 90411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses 90511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::total 5174652 # number of demand (read+write) misses 90611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5174652 # number of overall misses 90711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::total 5174652 # number of overall misses 90811606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55704586500 # number of ReadReq miss cycles 90911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 55704586500 # number of ReadReq miss cycles 91011606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 55704586500 # number of demand (read+write) miss cycles 91111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::total 55704586500 # number of demand (read+write) miss cycles 91211606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles 91311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles 91411606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses) 91511606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses) 91611606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses 91711606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses 91811606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses 91911606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses 92011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses 92111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses 92211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses 92311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses 92411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses 92511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses 92611606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency 92711606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # average ReadReq miss latency 92811606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency 92911606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10764.895205 # average overall miss latency 93011606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency 93111606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10764.895205 # average overall miss latency 93210535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93310535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93410535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 93510535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 93610535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 93710535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 93811606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks 93911606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::total 5174135 # number of writebacks 94011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses 94111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses 94211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses 94311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses 94411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses 94511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses 94610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 94710827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 94810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 94910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 95011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 53117260500 # number of ReadReq MSHR miss cycles 95111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 53117260500 # number of ReadReq MSHR miss cycles 95211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 53117260500 # number of demand (read+write) MSHR miss cycles 95311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 53117260500 # number of demand (read+write) MSHR miss cycles 95411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles 95511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles 95611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles 95711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles 95811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles 95911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles 96011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for ReadReq accesses 96111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011516 # mshr miss rate for ReadReq accesses 96211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses 96311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses 96411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses 96511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses 96611606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency 96711606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency 96811606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency 96911606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency 97011606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency 97111606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency 97211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 97311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 97411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 97511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency 97611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 97711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued 97811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified 97911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 98010628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98110628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing 98311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 98411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.replacements 2342884 # number of replacements 98511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use 98611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks. 98711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks. 98811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks. 98911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 99011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor 99111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor 99211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor 99311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor 99411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy 99511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy 99611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy 99711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy 99811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy 99911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id 100011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 100111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id 100211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id 100311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id 100411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id 100511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id 100611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 100711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id 100811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id 100911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 101011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id 101111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id 101211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id 101311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id 101411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id 101511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 101611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933655 # Percentage of cache occupancy per task id 101711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tag_accesses 370311903 # Number of tag accesses 101811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.data_accesses 370311903 # Number of data accesses 101911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 102011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 225709 # number of ReadReq hits 102111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148168 # number of ReadReq hits 102211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 373877 # number of ReadReq hits 102311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3696575 # number of WritebackDirty hits 102411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3696575 # number of WritebackDirty hits 102511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7043197 # number of WritebackClean hits 102611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7043197 # number of WritebackClean hits 102711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 878685 # number of ReadExReq hits 102811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 878685 # number of ReadExReq hits 102911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695575 # number of ReadCleanReq hits 103011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4695575 # number of ReadCleanReq hits 103111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2752703 # number of ReadSharedReq hits 103211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2752703 # number of ReadSharedReq hits 103311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216682 # number of InvalidateReq hits 103411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 216682 # number of InvalidateReq hits 103511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 225709 # number of demand (read+write) hits 103611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 148168 # number of demand (read+write) hits 103711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4695575 # number of demand (read+write) hits 103811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3631388 # number of demand (read+write) hits 103911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::total 8700840 # number of demand (read+write) hits 104011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 225709 # number of overall hits 104111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 148168 # number of overall hits 104211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4695575 # number of overall hits 104311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3631388 # number of overall hits 104411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::total 8700840 # number of overall hits 104511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 18676 # number of ReadReq misses 104611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10607 # number of ReadReq misses 104711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 29283 # number of ReadReq misses 104811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 251664 # number of UpgradeReq misses 104911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 251664 # number of UpgradeReq misses 105011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202763 # number of SCUpgradeReq misses 105111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 202763 # number of SCUpgradeReq misses 105211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses 105311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses 105411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 278535 # number of ReadExReq misses 105511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 278535 # number of ReadExReq misses 105611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 479077 # number of ReadCleanReq misses 105711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 479077 # number of ReadCleanReq misses 105811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 955394 # number of ReadSharedReq misses 105911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 955394 # number of ReadSharedReq misses 106011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582714 # number of InvalidateReq misses 106111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 582714 # number of InvalidateReq misses 106211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 18676 # number of demand (read+write) misses 106311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10607 # number of demand (read+write) misses 106411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 479077 # number of demand (read+write) misses 106511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1233929 # number of demand (read+write) misses 106611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::total 1742289 # number of demand (read+write) misses 106711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 18676 # number of overall misses 106811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10607 # number of overall misses 106911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 479077 # number of overall misses 107011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1233929 # number of overall misses 107111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::total 1742289 # number of overall misses 107211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564732000 # number of ReadReq miss cycles 107311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 371950000 # number of ReadReq miss cycles 107411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 936682000 # number of ReadReq miss cycles 107511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 916815500 # number of UpgradeReq miss cycles 107611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 916815500 # number of UpgradeReq miss cycles 107711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 321936500 # number of SCUpgradeReq miss cycles 107811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 321936500 # number of SCUpgradeReq miss cycles 107911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2282499 # number of SCUpgradeFailReq miss cycles 108011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2282499 # number of SCUpgradeFailReq miss cycles 108111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12626438998 # number of ReadExReq miss cycles 108211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12626438998 # number of ReadExReq miss cycles 108311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17151939500 # number of ReadCleanReq miss cycles 108411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 17151939500 # number of ReadCleanReq miss cycles 108511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33121351500 # number of ReadSharedReq miss cycles 108611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 33121351500 # number of ReadSharedReq miss cycles 108711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 399249500 # number of InvalidateReq miss cycles 108811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 399249500 # number of InvalidateReq miss cycles 108911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564732000 # number of demand (read+write) miss cycles 109011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 371950000 # number of demand (read+write) miss cycles 109111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 17151939500 # number of demand (read+write) miss cycles 109211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 45747790498 # number of demand (read+write) miss cycles 109311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 63836411998 # number of demand (read+write) miss cycles 109411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564732000 # number of overall miss cycles 109511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 371950000 # number of overall miss cycles 109611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 17151939500 # number of overall miss cycles 109711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 45747790498 # number of overall miss cycles 109811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 63836411998 # number of overall miss cycles 109911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 244385 # number of ReadReq accesses(hits+misses) 110011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158775 # number of ReadReq accesses(hits+misses) 110111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 403160 # number of ReadReq accesses(hits+misses) 110211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3696575 # number of WritebackDirty accesses(hits+misses) 110311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3696575 # number of WritebackDirty accesses(hits+misses) 110411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7043197 # number of WritebackClean accesses(hits+misses) 110511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7043197 # number of WritebackClean accesses(hits+misses) 110611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251664 # number of UpgradeReq accesses(hits+misses) 110711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 251664 # number of UpgradeReq accesses(hits+misses) 110811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202763 # number of SCUpgradeReq accesses(hits+misses) 110911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 202763 # number of SCUpgradeReq accesses(hits+misses) 111011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses) 111111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) 111211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1157220 # number of ReadExReq accesses(hits+misses) 111311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1157220 # number of ReadExReq accesses(hits+misses) 111411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5174652 # number of ReadCleanReq accesses(hits+misses) 111511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5174652 # number of ReadCleanReq accesses(hits+misses) 111611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3708097 # number of ReadSharedReq accesses(hits+misses) 111711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3708097 # number of ReadSharedReq accesses(hits+misses) 111811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 799396 # number of InvalidateReq accesses(hits+misses) 111911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 799396 # number of InvalidateReq accesses(hits+misses) 112011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 244385 # number of demand (read+write) accesses 112111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 158775 # number of demand (read+write) accesses 112211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5174652 # number of demand (read+write) accesses 112311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4865317 # number of demand (read+write) accesses 112411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::total 10443129 # number of demand (read+write) accesses 112511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 244385 # number of overall (read+write) accesses 112611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 158775 # number of overall (read+write) accesses 112711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5174652 # number of overall (read+write) accesses 112811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4865317 # number of overall (read+write) accesses 112911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::total 10443129 # number of overall (read+write) accesses 113011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for ReadReq accesses 113111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.066805 # miss rate for ReadReq accesses 113211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.072634 # miss rate for ReadReq accesses 113311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 113411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 113511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 113611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 113710535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 113810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 113911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240693 # miss rate for ReadExReq accesses 114011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.240693 # miss rate for ReadExReq accesses 114111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092581 # miss rate for ReadCleanReq accesses 114211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092581 # miss rate for ReadCleanReq accesses 114311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.257651 # miss rate for ReadSharedReq accesses 114411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.257651 # miss rate for ReadSharedReq accesses 114511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728943 # miss rate for InvalidateReq accesses 114611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728943 # miss rate for InvalidateReq accesses 114711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for demand accesses 114811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.066805 # miss rate for demand accesses 114911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092581 # miss rate for demand accesses 115011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253617 # miss rate for demand accesses 115111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.166836 # miss rate for demand accesses 115211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for overall accesses 115311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.066805 # miss rate for overall accesses 115411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092581 # miss rate for overall accesses 115511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253617 # miss rate for overall accesses 115611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.166836 # miss rate for overall accesses 115711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average ReadReq miss latency 115811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35066.465542 # average ReadReq miss latency 115911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 31987.228085 # average ReadReq miss latency 116011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3643.014098 # average UpgradeReq miss latency 116111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3643.014098 # average UpgradeReq miss latency 116211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1587.747765 # average SCUpgradeReq miss latency 116311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1587.747765 # average SCUpgradeReq miss latency 116411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190208.250000 # average SCUpgradeFailReq miss latency 116511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190208.250000 # average SCUpgradeFailReq miss latency 116611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45331.606434 # average ReadExReq miss latency 116711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45331.606434 # average ReadExReq miss latency 116811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35802.051653 # average ReadCleanReq miss latency 116911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35802.051653 # average ReadCleanReq miss latency 117011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34667.740744 # average ReadSharedReq miss latency 117111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34667.740744 # average ReadSharedReq miss latency 117211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 685.155153 # average InvalidateReq miss latency 117311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 685.155153 # average InvalidateReq miss latency 117411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average overall miss latency 117511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency 117611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency 117711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37074.896933 # average overall miss latency 117811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 36639.393349 # average overall miss latency 117911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average overall miss latency 118011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency 118111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency 118211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37074.896933 # average overall miss latency 118311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 36639.393349 # average overall miss latency 118410628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118510535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118610628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 118710535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 118810628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118910535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.unused_prefetches 41508 # number of HardPF blocks evicted w/o reference 119111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1560695 # number of writebacks 119211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::total 1560695 # number of writebacks 119311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5412 # number of ReadExReq MSHR hits 119411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5412 # number of ReadExReq MSHR hits 119511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 417 # number of ReadSharedReq MSHR hits 119611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 417 # number of ReadSharedReq MSHR hits 119711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5829 # number of demand (read+write) MSHR hits 119811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5829 # number of demand (read+write) MSHR hits 119911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5829 # number of overall MSHR hits 120011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5829 # number of overall MSHR hits 120111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 18676 # number of ReadReq MSHR misses 120211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10607 # number of ReadReq MSHR misses 120311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 29283 # number of ReadReq MSHR misses 120411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726457 # number of HardPFReq MSHR misses 120511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 726457 # number of HardPFReq MSHR misses 120611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 251664 # number of UpgradeReq MSHR misses 120711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 251664 # number of UpgradeReq MSHR misses 120811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202763 # number of SCUpgradeReq MSHR misses 120911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202763 # number of SCUpgradeReq MSHR misses 121011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 12 # number of SCUpgradeFailReq MSHR misses 121111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 12 # number of SCUpgradeFailReq MSHR misses 121211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 273123 # number of ReadExReq MSHR misses 121311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 273123 # number of ReadExReq MSHR misses 121411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 479077 # number of ReadCleanReq MSHR misses 121511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 479077 # number of ReadCleanReq MSHR misses 121611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 954977 # number of ReadSharedReq MSHR misses 121711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 954977 # number of ReadSharedReq MSHR misses 121811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582714 # number of InvalidateReq MSHR misses 121911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 582714 # number of InvalidateReq MSHR misses 122011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 18676 # number of demand (read+write) MSHR misses 122111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10607 # number of demand (read+write) MSHR misses 122211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 479077 # number of demand (read+write) MSHR misses 122311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1228100 # number of demand (read+write) MSHR misses 122411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1736460 # number of demand (read+write) MSHR misses 122511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 18676 # number of overall MSHR misses 122611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10607 # number of overall MSHR misses 122711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 479077 # number of overall MSHR misses 122811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1228100 # number of overall MSHR misses 122911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726457 # number of overall MSHR misses 123011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2462917 # number of overall MSHR misses 123110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 123211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable 123311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 64150 # number of ReadReq MSHR uncacheable 123411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable 123511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable 123610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 123711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses 123811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86538 # number of overall MSHR uncacheable misses 123911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of ReadReq MSHR miss cycles 124011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308308000 # number of ReadReq MSHR miss cycles 124111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 760984000 # number of ReadReq MSHR miss cycles 124211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 31463015041 # number of HardPFReq MSHR miss cycles 124311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 31463015041 # number of HardPFReq MSHR miss cycles 124411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4662148500 # number of UpgradeReq MSHR miss cycles 124511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4662148500 # number of UpgradeReq MSHR miss cycles 124611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3097020500 # number of SCUpgradeReq MSHR miss cycles 124711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3097020500 # number of SCUpgradeReq MSHR miss cycles 124811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1964499 # number of SCUpgradeFailReq MSHR miss cycles 124911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1964499 # number of SCUpgradeFailReq MSHR miss cycles 125011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10454677998 # number of ReadExReq MSHR miss cycles 125111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10454677998 # number of ReadExReq MSHR miss cycles 125211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14277477500 # number of ReadCleanReq MSHR miss cycles 125311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14277477500 # number of ReadCleanReq MSHR miss cycles 125411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27353907000 # number of ReadSharedReq MSHR miss cycles 125511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27353907000 # number of ReadSharedReq MSHR miss cycles 125611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18732640000 # number of InvalidateReq MSHR miss cycles 125711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18732640000 # number of InvalidateReq MSHR miss cycles 125811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of demand (read+write) MSHR miss cycles 125911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308308000 # number of demand (read+write) MSHR miss cycles 126011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14277477500 # number of demand (read+write) MSHR miss cycles 126111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37808584998 # number of demand (read+write) MSHR miss cycles 126211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 52847046498 # number of demand (read+write) MSHR miss cycles 126311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of overall MSHR miss cycles 126411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308308000 # number of overall MSHR miss cycles 126511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14277477500 # number of overall MSHR miss cycles 126611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37808584998 # number of overall MSHR miss cycles 126711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31463015041 # number of overall MSHR miss cycles 126811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 84310061539 # number of overall MSHR miss cycles 126911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles 127011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820807000 # number of ReadReq MSHR uncacheable cycles 127111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7316839500 # number of ReadReq MSHR uncacheable cycles 127211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles 127311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3820807000 # number of overall MSHR uncacheable cycles 127411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7316839500 # number of overall MSHR uncacheable cycles 127511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for ReadReq accesses 127611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for ReadReq accesses 127711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.072634 # mshr miss rate for ReadReq accesses 127810535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 127910535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 128011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 128111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 128211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 128311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 128410535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 128510535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 128611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses 128711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses 128811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses 128911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses 129011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses 129111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses 129211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses 129311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses 129411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses 129511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses 129611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses 129711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses 129811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses 129911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses 130011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses 130111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses 130211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses 130310535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 130411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses 130511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency 130611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency 130711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency 130811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency 130911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency 131011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency 131111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency 131211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency 131311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency 131411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency 131511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency 131611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency 131711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency 131811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency 131911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency 132011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency 132111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency 132211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency 132311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency 132411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency 132511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency 132611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency 132711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency 132811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency 132911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency 133011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency 133111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency 133211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency 133311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency 133411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency 133511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency 133611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency 133711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency 133811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency 133911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency 134011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency 134111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter. 134211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data. 134311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 134411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter. 134511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 134611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 134711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 134811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution 134911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution 135011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution 135111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution 135211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution 135311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution 135411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution 135511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution 135611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution 135711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution 135811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution 135911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 136011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 136111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution 136211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution 136311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution 136411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution 136511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution 136611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution 136711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes) 136811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes) 136911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes) 137011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes) 137111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes) 137211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes) 137311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes) 137411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes) 137511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes) 137611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes) 137711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoops 5171785 # Total snoops (count) 137811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes) 137911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram 138011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram 138111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram 138210535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 138311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram 138411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram 138511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 138610535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 138810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 138911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram 139011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks) 139110535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 139211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks) 139310535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 139411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks) 139510535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 139611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks) 139710535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 139811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks) 139910535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 140011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks) 140110535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 140211606Sandreas.sandberg@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 140310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 140410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 140510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 140610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 140710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 140810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 140910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 141010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 141210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 141310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 141410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 141510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 141610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 141710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 141810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 141910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 142010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 142110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 142210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 142310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 142410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 142510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 142610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 142710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 142810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 142910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 143010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 143110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 143211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 143311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walks 113512 # Table walker walks requested 143411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors 143511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate 143611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate 143711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting 143811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency 143911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency 144011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency 144111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency 144211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 144311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 144411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency 144511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency 144611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency 144711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency 144811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency 144911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency 145011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency 145111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency 145211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency 145311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency 145411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency 145511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency 145611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency 145711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency 145811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency 145911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 146011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 146111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 146211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 146311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency 146411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution 146511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution 146611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution 146711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution 146811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution 146911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated 147011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated 147111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated 147211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst 147310628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 147411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst 147511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst 147610628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst 147811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst 147910535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 148010535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 148111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_hits 83873503 # DTB read hits 148211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_misses 85876 # DTB read misses 148311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_hits 75393075 # DTB write hits 148411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_misses 27636 # DTB write misses 148510535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 148610535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID 148811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 148911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB 149010535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 149111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch 149210535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 149311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions 149411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_accesses 83959379 # DTB read accesses 149511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_accesses 75420711 # DTB write accesses 149610535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 149711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.hits 159266578 # DTB hits 149811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.misses 113512 # DTB misses 149911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.accesses 159380090 # DTB accesses 150011606Sandreas.sandberg@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 150110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 150310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 150410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 150510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 150710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 150810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 150910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 151010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 151110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 151210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 151310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 151410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 151510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 151610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 151810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 152010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 152110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 152210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 152310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 152410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 152510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 152610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 152710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 152810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 152910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 153111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walks 59776 # Table walker walks requested 153211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors 153311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate 153411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate 153511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency 153611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency 153711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency 153811606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency 153911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency 154011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency 154111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency 154211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency 154311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency 154411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency 154511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency 154611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency 154711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency 154811606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 154911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 155011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 155111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency 155211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution 155311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution 155411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution 155511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated 155611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated 155711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated 155810628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst 156011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst 156110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 156211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst 156311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst 156411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst 156511606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_hits 442849873 # ITB inst hits 156611606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_misses 59776 # ITB inst misses 156710535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 156810535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 156910535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 157010535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 157110535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 157210535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 157311606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID 157411606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 157511606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB 157610535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 157710535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 157810535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 157910535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 158010535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 158110535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 158211606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_accesses 442909649 # ITB inst accesses 158311606Sandreas.sandberg@arm.comsystem.cpu1.itb.hits 442849873 # DTB hits 158411606Sandreas.sandberg@arm.comsystem.cpu1.itb.misses 59776 # DTB misses 158511606Sandreas.sandberg@arm.comsystem.cpu1.itb.accesses 442909649 # DTB accesses 158611606Sandreas.sandberg@arm.comsystem.cpu1.numPwrStateTransitions 28574 # Number of power state transitions 158711606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state 158811606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state 158911606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state 159011606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state 159111606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state 159211606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state 159311606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state 159411606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 159511606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 159611606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state 159711606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state 159811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 159911606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state 160011606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state 160111606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states 160211606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states 160311606Sandreas.sandberg@arm.comsystem.cpu1.numCycles 94748630821 # number of cpu cycles simulated 160410535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 160510535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 160611167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 160711606Sandreas.sandberg@arm.comsystem.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed 160811606Sandreas.sandberg@arm.comsystem.cpu1.committedInsts 442543215 # Number of instructions committed 160911606Sandreas.sandberg@arm.comsystem.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed 161011606Sandreas.sandberg@arm.comsystem.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses 161111606Sandreas.sandberg@arm.comsystem.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses 161211606Sandreas.sandberg@arm.comsystem.cpu1.num_func_calls 26483096 # number of times a function call or return occured 161311606Sandreas.sandberg@arm.comsystem.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls 161411606Sandreas.sandberg@arm.comsystem.cpu1.num_int_insts 478315040 # number of integer instructions 161511606Sandreas.sandberg@arm.comsystem.cpu1.num_fp_insts 404780 # number of float instructions 161611606Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read 161711606Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written 161811606Sandreas.sandberg@arm.comsystem.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read 161911606Sandreas.sandberg@arm.comsystem.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written 162011606Sandreas.sandberg@arm.comsystem.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read 162111606Sandreas.sandberg@arm.comsystem.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written 162211606Sandreas.sandberg@arm.comsystem.cpu1.num_mem_refs 159256484 # number of memory refs 162311606Sandreas.sandberg@arm.comsystem.cpu1.num_load_insts 83870110 # Number of load instructions 162411606Sandreas.sandberg@arm.comsystem.cpu1.num_store_insts 75386374 # Number of store instructions 162511606Sandreas.sandberg@arm.comsystem.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles 162611606Sandreas.sandberg@arm.comsystem.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles 162711606Sandreas.sandberg@arm.comsystem.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles 162811606Sandreas.sandberg@arm.comsystem.cpu1.idle_fraction 0.988993 # Percentage of idle cycles 162911606Sandreas.sandberg@arm.comsystem.cpu1.Branches 98643380 # Number of branches fetched 163011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 163111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction 163211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction 163311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction 163411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction 163511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction 163611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction 163711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction 163811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction 163911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction 164011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction 164111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction 164211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction 164311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction 164411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction 164511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction 164611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction 164711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction 164811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction 164911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction 165011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction 165111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction 165211606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction 165311606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction 165411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction 165511606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction 165611606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction 165711606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 165811606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 165911606Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 166011606Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction 166111606Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction 166210535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 166310535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 166411606Sandreas.sandberg@arm.comsystem.cpu1.op_class::total 520684927 # Class of executed instruction 166511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 166611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.replacements 5203972 # number of replacements 166711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use 166811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks. 166911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks. 167011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks. 167111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit. 167211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor 167311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy 167411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy 167511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 167611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 167711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 167811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 167911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 168011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 168111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses 168211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses 168311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 168411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits 168511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits 168611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits 168711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits 168811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits 168911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits 169011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits 169111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits 169211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits 169311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits 169411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits 169511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits 169611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits 169711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits 169811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits 169911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 149942310 # number of overall hits 170011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses 170111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses 170211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses 170311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses 170411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses 170511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses 170611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses 170711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses 170811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses 170911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses 171011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses 171111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses 171211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses 171311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses 171411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses 171511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 5392442 # number of overall misses 171611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles 171711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles 171811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles 171911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles 172011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles 172111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles 172211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles 172311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles 172411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles 172511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles 172611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles 172711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles 172811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles 172911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles 173011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles 173111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles 173211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses) 173311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses) 173411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses) 173511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses) 173611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses) 173711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses) 173811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses) 173911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses) 174011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses) 174111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses) 174211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses) 174311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses) 174411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses 174511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses 174611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses 174711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses 174811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses 174911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses 175011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses 175111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses 175211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses 175311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses 175411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses 175511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses 175611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses 175711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses 175811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses 175911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses 176011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses 176111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses 176211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses 176311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses 176411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency 176511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency 176611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency 176711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency 176811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency 176911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency 177011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency 177111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency 177211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency 177311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency 177410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 177510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 177611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency 177711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency 177811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency 177911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency 178010535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178110535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178210535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178310535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 178410535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178510535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 178611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks 178711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 5203972 # number of writebacks 178811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits 178911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits 179011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits 179111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits 179211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits 179311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits 179411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits 179511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits 179611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits 179711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits 179811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses 179911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses 180011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses 180111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses 180211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses 180311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses 180411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses 180511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses 180611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses 180711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses 180811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses 180911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses 181011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses 181111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses 181211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses 181311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses 181411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable 181511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable 181611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable 181711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable 181811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses 181911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses 182011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles 182111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles 182211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles 182311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles 182411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles 182511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles 182611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles 182711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles 182811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles 182911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles 183011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles 183111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles 183211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles 183311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles 183411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles 183511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles 183611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles 183711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles 183811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles 183911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles 184011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles 184111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles 184211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses 184311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses 184411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses 184511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses 184611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses 184711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses 184811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses 184911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses 185011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses 185111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses 185211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses 185311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses 185411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses 185511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses 185611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses 185711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses 185811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency 185911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency 186011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency 186111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency 186211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency 186311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency 186411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency 186511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency 186611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency 186711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency 186811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency 186911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency 187010535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 187110535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 187211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency 187311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency 187411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency 187511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency 187611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency 187711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency 187811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency 187911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency 188011606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 188111606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.replacements 4895837 # number of replacements 188211606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use 188311606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks. 188411606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks. 188511606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks. 188611606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit. 188711606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor 188811606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy 188911606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy 189010535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 189111606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 189211606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 189311606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 189411606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 189510535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 189611606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses 189711606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses 189811606Sandreas.sandberg@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 189911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits 190011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits 190111606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits 190211606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits 190311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits 190411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::total 437953524 # number of overall hits 190511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses 190611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses 190711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses 190811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses 190911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses 191011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::total 4896349 # number of overall misses 191111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles 191211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles 191311606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles 191411606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles 191511606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles 191611606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles 191711606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses) 191811606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses) 191911606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses 192011606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses 192111606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses 192211606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses 192311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses 192411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses 192511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses 192611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses 192711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses 192811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses 192911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency 193011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency 193111606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency 193211606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency 193311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency 193411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency 193510535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193610535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 193710535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 193810535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 193910535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 194010535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194111606Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::writebacks 4895837 # number of writebacks 194211606Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::total 4895837 # number of writebacks 194311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4896349 # number of ReadReq MSHR misses 194411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4896349 # number of ReadReq MSHR misses 194511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4896349 # number of demand (read+write) MSHR misses 194611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::total 4896349 # number of demand (read+write) MSHR misses 194711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4896349 # number of overall MSHR misses 194811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::total 4896349 # number of overall MSHR misses 194910827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 195010827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 195110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 195210827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 195311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48995995500 # number of ReadReq MSHR miss cycles 195411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 48995995500 # number of ReadReq MSHR miss cycles 195511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48995995500 # number of demand (read+write) MSHR miss cycles 195611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 48995995500 # number of demand (read+write) MSHR miss cycles 195711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48995995500 # number of overall MSHR miss cycles 195811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 48995995500 # number of overall MSHR miss cycles 195911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10402000 # number of ReadReq MSHR uncacheable cycles 196011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10402000 # number of ReadReq MSHR uncacheable cycles 196111606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10402000 # number of overall MSHR uncacheable cycles 196211606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10402000 # number of overall MSHR uncacheable cycles 196311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadReq accesses 196411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011056 # mshr miss rate for ReadReq accesses 196511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses 196611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011056 # mshr miss rate for demand accesses 196711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses 196811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011056 # mshr miss rate for overall accesses 196911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average ReadReq mshr miss latency 197011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722 # average ReadReq mshr miss latency 197111606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency 197211606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency 197311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency 197411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency 197511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average ReadReq mshr uncacheable latency 197611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency 197711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency 197811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency 197911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 198011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued 198111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified 198211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue 198310628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 198410628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 198511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 909185 # number of prefetches not generated due to page crossing 198611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 198711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.replacements 1859788 # number of replacements 198811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13078.836793 # Cycle average of tags in use 198911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.total_refs 8983696 # Total number of references to valid blocks. 199011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1875537 # Sample count of references to valid blocks. 199111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.789933 # Average number of references to valid blocks. 199211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935 # Average occupied blocks per requestor 199411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.493162 # Average occupied blocks per requestor 199511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.479573 # Average occupied blocks per requestor 199611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 226.246124 # Average occupied blocks per requestor 199711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.782692 # Average percentage of cache occupancy 199811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001068 # Average percentage of cache occupancy 199911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000701 # Average percentage of cache occupancy 200011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013809 # Average percentage of cache occupancy 200111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.798269 # Average percentage of cache occupancy 200211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id 200311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 200411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15409 # Occupied blocks per task id 200511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 200611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 107 # Occupied blocks per task id 200711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 144 # Occupied blocks per task id 200811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 23 # Occupied blocks per task id 200911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 201011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id 201111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 201211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 201311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id 201411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id 201511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id 201611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id 201711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id 201811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id 201911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id 202011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tag_accesses 348956442 # Number of tag accesses 202111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.data_accesses 348956442 # Number of data accesses 202211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 202311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 258658 # number of ReadReq hits 202411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151547 # number of ReadReq hits 202511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 410205 # number of ReadReq hits 202611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3266667 # number of WritebackDirty hits 202711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3266667 # number of WritebackDirty hits 202811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6832390 # number of WritebackClean hits 202911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6832390 # number of WritebackClean hits 203011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 881671 # number of ReadExReq hits 203111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 881671 # number of ReadExReq hits 203211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4452144 # number of ReadCleanReq hits 203311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4452144 # number of ReadCleanReq hits 203411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2841120 # number of ReadSharedReq hits 203511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2841120 # number of ReadSharedReq hits 203611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 192152 # number of InvalidateReq hits 203711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 192152 # number of InvalidateReq hits 203811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 258658 # number of demand (read+write) hits 203911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 151547 # number of demand (read+write) hits 204011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4452144 # number of demand (read+write) hits 204111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3722791 # number of demand (read+write) hits 204211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::total 8585140 # number of demand (read+write) hits 204311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 258658 # number of overall hits 204411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 151547 # number of overall hits 204511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4452144 # number of overall hits 204611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3722791 # number of overall hits 204711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::total 8585140 # number of overall hits 204811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18381 # number of ReadReq misses 204911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9249 # number of ReadReq misses 205011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 27630 # number of ReadReq misses 205111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207506 # number of UpgradeReq misses 205211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 207506 # number of UpgradeReq misses 205311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 205160 # number of SCUpgradeReq misses 205411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 205160 # number of SCUpgradeReq misses 205511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 205611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 205711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 235234 # number of ReadExReq misses 205811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 235234 # number of ReadExReq misses 205911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 444205 # number of ReadCleanReq misses 206011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 444205 # number of ReadCleanReq misses 206111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 895209 # number of ReadSharedReq misses 206211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 895209 # number of ReadSharedReq misses 206311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252043 # number of InvalidateReq misses 206411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 252043 # number of InvalidateReq misses 206511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18381 # number of demand (read+write) misses 206611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9249 # number of demand (read+write) misses 206711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 444205 # number of demand (read+write) misses 206811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1130443 # number of demand (read+write) misses 206911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::total 1602278 # number of demand (read+write) misses 207011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18381 # number of overall misses 207111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9249 # number of overall misses 207211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 444205 # number of overall misses 207311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1130443 # number of overall misses 207411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::total 1602278 # number of overall misses 207511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 560546000 # number of ReadReq miss cycles 207611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 349476500 # number of ReadReq miss cycles 207711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 910022500 # number of ReadReq miss cycles 207811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 940760500 # number of UpgradeReq miss cycles 207911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 940760500 # number of UpgradeReq miss cycles 208011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 308144500 # number of SCUpgradeReq miss cycles 208111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 308144500 # number of SCUpgradeReq miss cycles 208211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2058000 # number of SCUpgradeFailReq miss cycles 208311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2058000 # number of SCUpgradeFailReq miss cycles 208411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9879714999 # number of ReadExReq miss cycles 208511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9879714999 # number of ReadExReq miss cycles 208611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 14896666000 # number of ReadCleanReq miss cycles 208711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 14896666000 # number of ReadCleanReq miss cycles 208811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29710253000 # number of ReadSharedReq miss cycles 208911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 29710253000 # number of ReadSharedReq miss cycles 209011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 322403500 # number of InvalidateReq miss cycles 209111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 322403500 # number of InvalidateReq miss cycles 209211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 560546000 # number of demand (read+write) miss cycles 209311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 349476500 # number of demand (read+write) miss cycles 209411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 14896666000 # number of demand (read+write) miss cycles 209511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 39589967999 # number of demand (read+write) miss cycles 209611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 55396656499 # number of demand (read+write) miss cycles 209711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 560546000 # number of overall miss cycles 209811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 349476500 # number of overall miss cycles 209911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 14896666000 # number of overall miss cycles 210011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 39589967999 # number of overall miss cycles 210111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 55396656499 # number of overall miss cycles 210211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 277039 # number of ReadReq accesses(hits+misses) 210311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160796 # number of ReadReq accesses(hits+misses) 210411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 437835 # number of ReadReq accesses(hits+misses) 210511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3266667 # number of WritebackDirty accesses(hits+misses) 210611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3266667 # number of WritebackDirty accesses(hits+misses) 210711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6832390 # number of WritebackClean accesses(hits+misses) 210811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6832390 # number of WritebackClean accesses(hits+misses) 210911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207506 # number of UpgradeReq accesses(hits+misses) 211011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 207506 # number of UpgradeReq accesses(hits+misses) 211111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 205160 # number of SCUpgradeReq accesses(hits+misses) 211211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 205160 # number of SCUpgradeReq accesses(hits+misses) 211311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 211411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 211511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116905 # number of ReadExReq accesses(hits+misses) 211611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1116905 # number of ReadExReq accesses(hits+misses) 211711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4896349 # number of ReadCleanReq accesses(hits+misses) 211811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4896349 # number of ReadCleanReq accesses(hits+misses) 211911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3736329 # number of ReadSharedReq accesses(hits+misses) 212011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3736329 # number of ReadSharedReq accesses(hits+misses) 212111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 444195 # number of InvalidateReq accesses(hits+misses) 212211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 444195 # number of InvalidateReq accesses(hits+misses) 212311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 277039 # number of demand (read+write) accesses 212411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160796 # number of demand (read+write) accesses 212511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4896349 # number of demand (read+write) accesses 212611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4853234 # number of demand (read+write) accesses 212711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::total 10187418 # number of demand (read+write) accesses 212811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 277039 # number of overall (read+write) accesses 212911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160796 # number of overall (read+write) accesses 213011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4896349 # number of overall (read+write) accesses 213111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4853234 # number of overall (read+write) accesses 213211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::total 10187418 # number of overall (read+write) accesses 213311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for ReadReq accesses 213411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057520 # miss rate for ReadReq accesses 213511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.063106 # miss rate for ReadReq accesses 213611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 213711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 213811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 213911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 214010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 214110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 214211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210612 # miss rate for ReadExReq accesses 214311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.210612 # miss rate for ReadExReq accesses 214411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090722 # miss rate for ReadCleanReq accesses 214511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090722 # miss rate for ReadCleanReq accesses 214611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.239596 # miss rate for ReadSharedReq accesses 214711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.239596 # miss rate for ReadSharedReq accesses 214811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.567415 # miss rate for InvalidateReq accesses 214911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.567415 # miss rate for InvalidateReq accesses 215011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for demand accesses 215111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057520 # miss rate for demand accesses 215211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090722 # miss rate for demand accesses 215311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.232926 # miss rate for demand accesses 215411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.157280 # miss rate for demand accesses 215511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for overall accesses 215611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057520 # miss rate for overall accesses 215711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090722 # miss rate for overall accesses 215811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.232926 # miss rate for overall accesses 215911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.157280 # miss rate for overall accesses 216011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average ReadReq miss latency 216111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37785.328144 # average ReadReq miss latency 216211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 32936.029678 # average ReadReq miss latency 216311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4533.654449 # average UpgradeReq miss latency 216411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4533.654449 # average UpgradeReq miss latency 216511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1501.971632 # average SCUpgradeReq miss latency 216611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1501.971632 # average SCUpgradeReq miss latency 216711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 686000 # average SCUpgradeFailReq miss latency 216811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 686000 # average SCUpgradeFailReq miss latency 216911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41999.519623 # average ReadExReq miss latency 217011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41999.519623 # average ReadExReq miss latency 217111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33535.565786 # average ReadCleanReq miss latency 217211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33535.565786 # average ReadCleanReq miss latency 217311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33188.063346 # average ReadSharedReq miss latency 217411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33188.063346 # average ReadSharedReq miss latency 217511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1279.160699 # average InvalidateReq miss latency 217611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1279.160699 # average InvalidateReq miss latency 217711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency 217811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency 217911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency 218011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency 218111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 34573.686026 # average overall miss latency 218211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency 218311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency 218411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency 218511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency 218611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 34573.686026 # average overall miss latency 218710628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 218810535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 218910628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 219010535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 219110628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 219210535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 219311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.unused_prefetches 39888 # number of HardPF blocks evicted w/o reference 219411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1080406 # number of writebacks 219511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::total 1080406 # number of writebacks 219611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5355 # number of ReadExReq MSHR hits 219711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 5355 # number of ReadExReq MSHR hits 219811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 314 # number of ReadSharedReq MSHR hits 219911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 314 # number of ReadSharedReq MSHR hits 220011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits 220111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 220211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 5669 # number of demand (read+write) MSHR hits 220311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 5669 # number of demand (read+write) MSHR hits 220411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 5669 # number of overall MSHR hits 220511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 5669 # number of overall MSHR hits 220611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18381 # number of ReadReq MSHR misses 220711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9249 # number of ReadReq MSHR misses 220811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 27630 # number of ReadReq MSHR misses 220911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of HardPFReq MSHR misses 221011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 700284 # number of HardPFReq MSHR misses 221111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207506 # number of UpgradeReq MSHR misses 221211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 207506 # number of UpgradeReq MSHR misses 221311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 205160 # number of SCUpgradeReq MSHR misses 221411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 205160 # number of SCUpgradeReq MSHR misses 221511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 221611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 221711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229879 # number of ReadExReq MSHR misses 221811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 229879 # number of ReadExReq MSHR misses 221911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 444205 # number of ReadCleanReq MSHR misses 222011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 444205 # number of ReadCleanReq MSHR misses 222111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 894895 # number of ReadSharedReq MSHR misses 222211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 894895 # number of ReadSharedReq MSHR misses 222311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252041 # number of InvalidateReq MSHR misses 222411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 252041 # number of InvalidateReq MSHR misses 222511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18381 # number of demand (read+write) MSHR misses 222611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9249 # number of demand (read+write) MSHR misses 222711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 444205 # number of demand (read+write) MSHR misses 222811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124774 # number of demand (read+write) MSHR misses 222911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1596609 # number of demand (read+write) MSHR misses 223011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18381 # number of overall MSHR misses 223111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9249 # number of overall MSHR misses 223211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 444205 # number of overall MSHR misses 223311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124774 # number of overall MSHR misses 223411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of overall MSHR misses 223511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2296893 # number of overall MSHR misses 223610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 223711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable 223811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17687 # number of ReadReq MSHR uncacheable 223911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable 224011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable 224110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 224211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses 224311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33812 # number of overall MSHR uncacheable misses 224411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of ReadReq MSHR miss cycles 224511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 293982500 # number of ReadReq MSHR miss cycles 224611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 744242500 # number of ReadReq MSHR miss cycles 224711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of HardPFReq MSHR miss cycles 224811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29274832519 # number of HardPFReq MSHR miss cycles 224911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3856981999 # number of UpgradeReq MSHR miss cycles 225011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3856981999 # number of UpgradeReq MSHR miss cycles 225111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3119783996 # number of SCUpgradeReq MSHR miss cycles 225211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3119783996 # number of SCUpgradeReq MSHR miss cycles 225311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1764000 # number of SCUpgradeFailReq MSHR miss cycles 225411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1764000 # number of SCUpgradeFailReq MSHR miss cycles 225511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7964098999 # number of ReadExReq MSHR miss cycles 225611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7964098999 # number of ReadExReq MSHR miss cycles 225711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12231436000 # number of ReadCleanReq MSHR miss cycles 225811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12231436000 # number of ReadCleanReq MSHR miss cycles 225911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24307582500 # number of ReadSharedReq MSHR miss cycles 226011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24307582500 # number of ReadSharedReq MSHR miss cycles 226111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6863337500 # number of InvalidateReq MSHR miss cycles 226211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6863337500 # number of InvalidateReq MSHR miss cycles 226311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of demand (read+write) MSHR miss cycles 226411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 293982500 # number of demand (read+write) MSHR miss cycles 226511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12231436000 # number of demand (read+write) MSHR miss cycles 226611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32271681499 # number of demand (read+write) MSHR miss cycles 226711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 45247359999 # number of demand (read+write) MSHR miss cycles 226811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of overall MSHR miss cycles 226911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 293982500 # number of overall MSHR miss cycles 227011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12231436000 # number of overall MSHR miss cycles 227111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32271681499 # number of overall MSHR miss cycles 227211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of overall MSHR miss cycles 227311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 74522192518 # number of overall MSHR miss cycles 227411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9577000 # number of ReadReq MSHR uncacheable cycles 227511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2837977500 # number of ReadReq MSHR uncacheable cycles 227611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2847554500 # number of ReadReq MSHR uncacheable cycles 227711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9577000 # number of overall MSHR uncacheable cycles 227811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2837977500 # number of overall MSHR uncacheable cycles 227911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2847554500 # number of overall MSHR uncacheable cycles 228011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for ReadReq accesses 228111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for ReadReq accesses 228211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063106 # mshr miss rate for ReadReq accesses 228310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 228410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 228511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 228611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 228711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 228811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 228910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 229010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 229111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.205818 # mshr miss rate for ReadExReq accesses 229211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.205818 # mshr miss rate for ReadExReq accesses 229311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for ReadCleanReq accesses 229411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090722 # mshr miss rate for ReadCleanReq accesses 229511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.239512 # mshr miss rate for ReadSharedReq accesses 229611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239512 # mshr miss rate for ReadSharedReq accesses 229711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.567411 # mshr miss rate for InvalidateReq accesses 229811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.567411 # mshr miss rate for InvalidateReq accesses 229911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses 230011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses 230111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses 230211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses 230311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses 230411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses 230511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses 230611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses 230711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses 230810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 230911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses 231011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency 231111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency 231211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency 231311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency 231411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency 231511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency 231611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency 231711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency 231811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency 231911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency 232011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency 232111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency 232211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency 232311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency 232411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency 232511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency 232611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency 232711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency 232811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency 232911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency 233011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency 233111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency 233211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency 233311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency 233411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency 233511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency 233611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency 233711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency 233811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency 233911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency 234011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency 234111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency 234211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency 234311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency 234411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency 234511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency 234611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter. 234711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data. 234811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 234911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter. 235011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 235111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 235211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 235311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution 235411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution 235511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution 235611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution 235711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution 235811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution 235911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution 236011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution 236111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution 236211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution 236311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution 236411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution 236511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 236611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution 236711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution 236811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution 236911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution 237011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution 237111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution 237211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes) 237311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes) 237411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes) 237511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes) 237611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes) 237711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes) 237811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes) 237911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes) 238011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes) 238111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes) 238211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 4601099 # Total snoops (count) 238311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes) 238411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram 238511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram 238611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram 238710535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 238811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram 238911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram 239011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 239110535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 239211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 239311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 239411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram 239511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks) 239610535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 239711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks) 239810535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 239911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks) 240010535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 240111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks) 240210535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 240311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks) 240410535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 240511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks) 240610535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 240711606Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 240811606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 40399 # Transaction distribution 240911606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 40399 # Transaction distribution 241011606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteReq 136980 # Transaction distribution 241111606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteResp 136980 # Transaction distribution 241211606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes) 241310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 241411245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 241510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 241610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 241710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 241810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 241910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 242010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 242110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 242210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 242311606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 242410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 242511606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes) 242611606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes) 242711606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes) 242810535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 242910535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 243011606Sandreas.sandberg@arm.comsystem.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes) 243111606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes) 243210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 243311245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 243410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 243510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 243610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 243710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 243810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 243910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 244110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244211606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 244310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 244411606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes) 244511606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes) 244611606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes) 244710535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 244810535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 244911606Sandreas.sandberg@arm.comsystem.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes) 245011606Sandreas.sandberg@arm.comsystem.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks) 245110535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 245211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 245310535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 245411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) 245510535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 245611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 245710535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 245811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) 245911245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 246010535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 246110535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 246211353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 246310535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 246411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 246510535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 246611201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 246710535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 246811502SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 246910535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 247011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 247110535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 247211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks) 247310535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 247411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) 247510535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 247611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks) 247710535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 247811606Sandreas.sandberg@arm.comsystem.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks) 247910535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 248011606Sandreas.sandberg@arm.comsystem.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks) 248110535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 248210892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 248310535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 248411606Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 248511606Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 115853 # number of replacements 248611606Sandreas.sandberg@arm.comsystem.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use 248711336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 248811606Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks. 248911336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 249011606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit. 249111606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor 249211606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor 249311606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy 249411606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy 249511606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy 249610535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 249710535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 249810535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 249911606Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 1043178 # Number of tag accesses 250011606Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 1043178 # Number of data accesses 250111606Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 250210535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 250311606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses 250411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 8922 # number of ReadReq misses 250510535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 250610535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 250711606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 250811606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 250910535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 251011606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses 251111606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 115909 # number of demand (read+write) misses 251210535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 251311606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::realview.ide 115869 # number of overall misses 251411606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 115909 # number of overall misses 251511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles 251611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles 251711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles 251810726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 251910726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 252011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles 252111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles 252211606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles 252311606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles 252411606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles 252511606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles 252611606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles 252711606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles 252810535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 252911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses) 253011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses) 253110535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 253210535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 253311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 253411606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 253510535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 253611606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses 253711606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses 253810535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 253911606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses 254011606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses 254110535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 254210535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 254310535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 254410535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 254510535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 254611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 254711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 254810535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 254910535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 255010535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 255110535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 255210535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 255310535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 255411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency 255511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency 255611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency 255710726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 255810726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 255911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency 256011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency 256111606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency 256211606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency 256311606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency 256411606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency 256511606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency 256611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency 256711606Sandreas.sandberg@arm.comsystem.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked 256810535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 256911606Sandreas.sandberg@arm.comsystem.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked 257010535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 257111606Sandreas.sandberg@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked 257210535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257311606Sandreas.sandberg@arm.comsystem.iocache.writebacks::writebacks 106953 # number of writebacks 257411606Sandreas.sandberg@arm.comsystem.iocache.writebacks::total 106953 # number of writebacks 257510535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 257611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8885 # number of ReadReq MSHR misses 257711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 8922 # number of ReadReq MSHR misses 257810535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 257910535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 258011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 258111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 258210535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 258311606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115869 # number of demand (read+write) MSHR misses 258411606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 115909 # number of demand (read+write) MSHR misses 258510535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 258611606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115869 # number of overall MSHR misses 258711606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 115909 # number of overall MSHR misses 258811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3428000 # number of ReadReq MSHR miss cycles 258911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1189343087 # number of ReadReq MSHR miss cycles 259011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1192771087 # number of ReadReq MSHR miss cycles 259110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 259210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 259311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles 259411606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles 259511606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles 259611606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles 259711606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles 259811606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # number of overall MSHR miss cycles 259911606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8742531886 # number of overall MSHR miss cycles 260011606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::total 8746178886 # number of overall MSHR miss cycles 260110535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 260210535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 260310535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 260410535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 260510535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 260611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 260711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 260810535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 260910535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 261010535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 261110535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 261210535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 261310535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 261411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency 261511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency 261611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency 261710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 261810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 261911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698 # average WriteLineReq mshr miss latency 262011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698 # average WriteLineReq mshr miss latency 262111606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency 262211606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency 262311606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency 262411606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency 262511606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency 262611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency 262711606Sandreas.sandberg@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 262811606Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 1378015 # number of replacements 262911606Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 64998.786153 # Cycle average of tags in use 263011606Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 6107230 # Total number of references to valid blocks. 263111606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks. 263211606Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks. 263311606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit. 263411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor 263511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor 263611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor 263711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor 263811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor 263911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor 264011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor 264111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor 264211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor 264311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor 264411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor 264511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy 264611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy 264711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy 264811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy 264911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy 265011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy 265111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy 265211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy 265311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy 265411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy 265511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy 265611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy 265711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id 265811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id 265911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id 266011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id 266111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id 266211606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id 266311606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id 266411606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id 266511606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 266611606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 266711606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id 266811606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 266911606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 267011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id 267111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id 267211606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id 267311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id 267411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id 267511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id 267611606Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 69629880 # Number of tag accesses 267711606Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 69629880 # Number of data accesses 267811606Sandreas.sandberg@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 267911606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2641101 # number of WritebackDirty hits 268011606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 2641101 # number of WritebackDirty hits 268111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 213424 # number of UpgradeReq hits 268211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 155298 # number of UpgradeReq hits 268311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 368722 # number of UpgradeReq hits 268411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 50511 # number of SCUpgradeReq hits 268511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 50527 # number of SCUpgradeReq hits 268611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 101038 # number of SCUpgradeReq hits 268711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 63650 # number of ReadExReq hits 268811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 48993 # number of ReadExReq hits 268911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 112643 # number of ReadExReq hits 269011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 10681 # number of ReadSharedReq hits 269111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5935 # number of ReadSharedReq hits 269211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 422841 # number of ReadSharedReq hits 269311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 567260 # number of ReadSharedReq hits 269411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276728 # number of ReadSharedReq hits 269511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 9775 # number of ReadSharedReq hits 269611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4116 # number of ReadSharedReq hits 269711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 406188 # number of ReadSharedReq hits 269811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits 269911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits 270011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits 270111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits 270211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits 270311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits 270411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits 270511606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits 270611606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits 270711606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits 270811606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits 270911606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits 271011606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4116 # number of demand (read+write) hits 271111606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.inst 406188 # number of demand (read+write) hits 271211606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 561391 # number of demand (read+write) hits 271311606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 278781 # number of demand (read+write) hits 271411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 2607346 # number of demand (read+write) hits 271511606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 10681 # number of overall hits 271611606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5935 # number of overall hits 271711606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.inst 422841 # number of overall hits 271811606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 630910 # number of overall hits 271911606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 276728 # number of overall hits 272011606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 9775 # number of overall hits 272111606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4116 # number of overall hits 272211606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.inst 406188 # number of overall hits 272311606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 561391 # number of overall hits 272411606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 278781 # number of overall hits 272511606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 2607346 # number of overall hits 272611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 24497 # number of UpgradeReq misses 272711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 25507 # number of UpgradeReq misses 272811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 50004 # number of UpgradeReq misses 272911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 796 # number of SCUpgradeReq misses 273011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 825 # number of SCUpgradeReq misses 273111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1621 # number of SCUpgradeReq misses 273211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 72583 # number of ReadExReq misses 273311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 52296 # number of ReadExReq misses 273411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 124879 # number of ReadExReq misses 273511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq misses 273611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1611 # number of ReadSharedReq misses 273711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 56236 # number of ReadSharedReq misses 273811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 130395 # number of ReadSharedReq misses 273911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq misses 274011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq misses 274111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1829 # number of ReadSharedReq misses 274211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 38017 # number of ReadSharedReq misses 274311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 107679 # number of ReadSharedReq misses 274411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq misses 274511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 750998 # number of ReadSharedReq misses 274611606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 430773 # number of InvalidateReq misses 274711606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 119101 # number of InvalidateReq misses 274811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::total 549874 # number of InvalidateReq misses 274911606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1676 # number of demand (read+write) misses 275011606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1611 # number of demand (read+write) misses 275111606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.inst 56236 # number of demand (read+write) misses 275211606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 202978 # number of demand (read+write) misses 275311606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) misses 275411606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1750 # number of demand (read+write) misses 275511606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1829 # number of demand (read+write) misses 275611606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.inst 38017 # number of demand (read+write) misses 275711606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 159975 # number of demand (read+write) misses 275811606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 200910 # number of demand (read+write) misses 275911606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 875877 # number of demand (read+write) misses 276011606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1676 # number of overall misses 276111606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1611 # number of overall misses 276211606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.inst 56236 # number of overall misses 276311606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 202978 # number of overall misses 276411606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 210895 # number of overall misses 276511606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1750 # number of overall misses 276611606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1829 # number of overall misses 276711606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.inst 38017 # number of overall misses 276811606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 159975 # number of overall misses 276911606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 200910 # number of overall misses 277011606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 875877 # number of overall misses 277111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 177641500 # number of UpgradeReq miss cycles 277211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 151031500 # number of UpgradeReq miss cycles 277311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::total 328673000 # number of UpgradeReq miss cycles 277411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 8353500 # number of SCUpgradeReq miss cycles 277511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 8021500 # number of SCUpgradeReq miss cycles 277611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 16375000 # number of SCUpgradeReq miss cycles 277711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 6466021500 # number of ReadExReq miss cycles 277811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4532203999 # number of ReadExReq miss cycles 277911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::total 10998225499 # number of ReadExReq miss cycles 278011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 151916500 # number of ReadSharedReq miss cycles 278111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149670500 # number of ReadSharedReq miss cycles 278211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 4848581000 # number of ReadSharedReq miss cycles 278311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 11828995999 # number of ReadSharedReq miss cycles 278411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of ReadSharedReq miss cycles 278511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157377000 # number of ReadSharedReq miss cycles 278611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 162435000 # number of ReadSharedReq miss cycles 278711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 3283945500 # number of ReadSharedReq miss cycles 278811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 9698473500 # number of ReadSharedReq miss cycles 278911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of ReadSharedReq miss cycles 279011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 80853175921 # number of ReadSharedReq miss cycles 279111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 43381500 # number of InvalidateReq miss cycles 279211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 30876500 # number of InvalidateReq miss cycles 279311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::total 74258000 # number of InvalidateReq miss cycles 279411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 151916500 # number of demand (read+write) miss cycles 279511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 149670500 # number of demand (read+write) miss cycles 279611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 4848581000 # number of demand (read+write) miss cycles 279711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.data 18295017499 # number of demand (read+write) miss cycles 279811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of demand (read+write) miss cycles 279911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 157377000 # number of demand (read+write) miss cycles 280011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 162435000 # number of demand (read+write) miss cycles 280111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 3283945500 # number of demand (read+write) miss cycles 280211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.data 14230677499 # number of demand (read+write) miss cycles 280311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of demand (read+write) miss cycles 280411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::total 91851401420 # number of demand (read+write) miss cycles 280511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 151916500 # number of overall miss cycles 280611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 149670500 # number of overall miss cycles 280711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 4848581000 # number of overall miss cycles 280811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.data 18295017499 # number of overall miss cycles 280911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of overall miss cycles 281011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 157377000 # number of overall miss cycles 281111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 162435000 # number of overall miss cycles 281211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 3283945500 # number of overall miss cycles 281311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.data 14230677499 # number of overall miss cycles 281411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of overall miss cycles 281511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::total 91851401420 # number of overall miss cycles 281611606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2641101 # number of WritebackDirty accesses(hits+misses) 281711606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 2641101 # number of WritebackDirty accesses(hits+misses) 281811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 237921 # number of UpgradeReq accesses(hits+misses) 281911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 180805 # number of UpgradeReq accesses(hits+misses) 282011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 418726 # number of UpgradeReq accesses(hits+misses) 282111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 51307 # number of SCUpgradeReq accesses(hits+misses) 282211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 51352 # number of SCUpgradeReq accesses(hits+misses) 282311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 102659 # number of SCUpgradeReq accesses(hits+misses) 282411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 136233 # number of ReadExReq accesses(hits+misses) 282511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 101289 # number of ReadExReq accesses(hits+misses) 282611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 237522 # number of ReadExReq accesses(hits+misses) 282711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 12357 # number of ReadSharedReq accesses(hits+misses) 282811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7546 # number of ReadSharedReq accesses(hits+misses) 282911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 479077 # number of ReadSharedReq accesses(hits+misses) 283011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 697655 # number of ReadSharedReq accesses(hits+misses) 283111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 487623 # number of ReadSharedReq accesses(hits+misses) 283211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 11525 # number of ReadSharedReq accesses(hits+misses) 283311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5945 # number of ReadSharedReq accesses(hits+misses) 283411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 444205 # number of ReadSharedReq accesses(hits+misses) 283511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 620077 # number of ReadSharedReq accesses(hits+misses) 283611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 479691 # number of ReadSharedReq accesses(hits+misses) 283711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 3245701 # number of ReadSharedReq accesses(hits+misses) 283811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 567330 # number of InvalidateReq accesses(hits+misses) 283911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 239426 # number of InvalidateReq accesses(hits+misses) 284011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::total 806756 # number of InvalidateReq accesses(hits+misses) 284111606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 12357 # number of demand (read+write) accesses 284211606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7546 # number of demand (read+write) accesses 284311606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.inst 479077 # number of demand (read+write) accesses 284411606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 833888 # number of demand (read+write) accesses 284511606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 487623 # number of demand (read+write) accesses 284611606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 11525 # number of demand (read+write) accesses 284711606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5945 # number of demand (read+write) accesses 284811606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.inst 444205 # number of demand (read+write) accesses 284911606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 721366 # number of demand (read+write) accesses 285011606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 479691 # number of demand (read+write) accesses 285111606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 3483223 # number of demand (read+write) accesses 285211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 12357 # number of overall (read+write) accesses 285311606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7546 # number of overall (read+write) accesses 285411606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.inst 479077 # number of overall (read+write) accesses 285511606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 833888 # number of overall (read+write) accesses 285611606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 487623 # number of overall (read+write) accesses 285711606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 11525 # number of overall (read+write) accesses 285811606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5945 # number of overall (read+write) accesses 285911606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.inst 444205 # number of overall (read+write) accesses 286011606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 721366 # number of overall (read+write) accesses 286111606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 479691 # number of overall (read+write) accesses 286211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 3483223 # number of overall (read+write) accesses 286311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.102963 # miss rate for UpgradeReq accesses 286411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.141075 # miss rate for UpgradeReq accesses 286511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.119419 # miss rate for UpgradeReq accesses 286611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.015514 # miss rate for SCUpgradeReq accesses 286711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016066 # miss rate for SCUpgradeReq accesses 286811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.015790 # miss rate for SCUpgradeReq accesses 286911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.532786 # miss rate for ReadExReq accesses 287011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.516305 # miss rate for ReadExReq accesses 287111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.525758 # miss rate for ReadExReq accesses 287211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for ReadSharedReq accesses 287311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.213491 # miss rate for ReadSharedReq accesses 287411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117384 # miss rate for ReadSharedReq accesses 287511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.186905 # miss rate for ReadSharedReq accesses 287611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for ReadSharedReq accesses 287711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for ReadSharedReq accesses 287811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.307653 # miss rate for ReadSharedReq accesses 287911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085584 # miss rate for ReadSharedReq accesses 288011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173654 # miss rate for ReadSharedReq accesses 288111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for ReadSharedReq accesses 288211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.231382 # miss rate for ReadSharedReq accesses 288311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.759299 # miss rate for InvalidateReq accesses 288411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.497444 # miss rate for InvalidateReq accesses 288511606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.681587 # miss rate for InvalidateReq accesses 288611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for demand accesses 288711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.213491 # miss rate for demand accesses 288811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.117384 # miss rate for demand accesses 288911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.243412 # miss rate for demand accesses 289011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for demand accesses 289111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for demand accesses 289211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.307653 # miss rate for demand accesses 289311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.085584 # miss rate for demand accesses 289411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.221767 # miss rate for demand accesses 289511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for demand accesses 289611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.251456 # miss rate for demand accesses 289711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for overall accesses 289811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.213491 # miss rate for overall accesses 289911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.117384 # miss rate for overall accesses 290011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.243412 # miss rate for overall accesses 290111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for overall accesses 290211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for overall accesses 290311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.307653 # miss rate for overall accesses 290411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.085584 # miss rate for overall accesses 290511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.221767 # miss rate for overall accesses 290611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for overall accesses 290711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.251456 # miss rate for overall accesses 290811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7251.561416 # average UpgradeReq miss latency 290911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5921.178500 # average UpgradeReq miss latency 291011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6572.934165 # average UpgradeReq miss latency 291111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10494.346734 # average SCUpgradeReq miss latency 291211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9723.030303 # average SCUpgradeReq miss latency 291311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 10101.789019 # average SCUpgradeReq miss latency 291411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 89084.517036 # average ReadExReq miss latency 291511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 86664.448505 # average ReadExReq miss latency 291611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 88071.056775 # average ReadExReq miss latency 291711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average ReadSharedReq miss latency 291811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92905.338299 # average ReadSharedReq miss latency 291911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86218.454371 # average ReadSharedReq miss latency 292011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90716.637900 # average ReadSharedReq miss latency 292111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average ReadSharedReq miss latency 292211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average ReadSharedReq miss latency 292311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88810.825588 # average ReadSharedReq miss latency 292411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86380.974301 # average ReadSharedReq miss latency 292511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90068.383807 # average ReadSharedReq miss latency 292611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average ReadSharedReq miss latency 292711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 107660.973692 # average ReadSharedReq miss latency 292811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 100.706172 # average InvalidateReq miss latency 292911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 259.246354 # average InvalidateReq miss latency 293011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 135.045483 # average InvalidateReq miss latency 293111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average overall miss latency 293211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 92905.338299 # average overall miss latency 293311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 86218.454371 # average overall miss latency 293411606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 90133.007020 # average overall miss latency 293511606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average overall miss latency 293611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency 293711606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency 293811606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency 293911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency 294011606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency 294111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::total 104867.922574 # average overall miss latency 294211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average overall miss latency 294311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 92905.338299 # average overall miss latency 294411606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 86218.454371 # average overall miss latency 294511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 90133.007020 # average overall miss latency 294611606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average overall miss latency 294711606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency 294811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency 294911606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency 295011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency 295111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency 295211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::total 104867.922574 # average overall miss latency 295311606Sandreas.sandberg@arm.comsystem.l2c.blocked_cycles::no_mshrs 424 # number of cycles access was blocked 295410515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 295511606Sandreas.sandberg@arm.comsystem.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 295610515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 295711606Sandreas.sandberg@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 84.800000 # average number of cycles each access was blocked 295810515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 295911606Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 1062304 # number of writebacks 296011606Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 1062304 # number of writebacks 296111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 133 # number of ReadSharedReq MSHR hits 296211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 64 # number of ReadSharedReq MSHR hits 296311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 89 # number of ReadSharedReq MSHR hits 296411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 16 # number of ReadSharedReq MSHR hits 296511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 302 # number of ReadSharedReq MSHR hits 296611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 133 # number of demand (read+write) MSHR hits 296711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 64 # number of demand (read+write) MSHR hits 296811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 89 # number of demand (read+write) MSHR hits 296911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits 297011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits 297111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 133 # number of overall MSHR hits 297211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 64 # number of overall MSHR hits 297311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 89 # number of overall MSHR hits 297411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits 297511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::total 302 # number of overall MSHR hits 297611606Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 54771 # number of CleanEvict MSHR misses 297711606Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::total 54771 # number of CleanEvict MSHR misses 297811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 24497 # number of UpgradeReq MSHR misses 297911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 25507 # number of UpgradeReq MSHR misses 298011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 50004 # number of UpgradeReq MSHR misses 298111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 796 # number of SCUpgradeReq MSHR misses 298211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 825 # number of SCUpgradeReq MSHR misses 298311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1621 # number of SCUpgradeReq MSHR misses 298411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 72583 # number of ReadExReq MSHR misses 298511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 52296 # number of ReadExReq MSHR misses 298611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::total 124879 # number of ReadExReq MSHR misses 298711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq MSHR misses 298811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1611 # number of ReadSharedReq MSHR misses 298911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 56103 # number of ReadSharedReq MSHR misses 299011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 130331 # number of ReadSharedReq MSHR misses 299111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq MSHR misses 299211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq MSHR misses 299311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1829 # number of ReadSharedReq MSHR misses 299411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 37928 # number of ReadSharedReq MSHR misses 299511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 107663 # number of ReadSharedReq MSHR misses 299611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq MSHR misses 299711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 750696 # number of ReadSharedReq MSHR misses 299811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 430773 # number of InvalidateReq MSHR misses 299911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 119101 # number of InvalidateReq MSHR misses 300011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 549874 # number of InvalidateReq MSHR misses 300111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1676 # number of demand (read+write) MSHR misses 300211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1611 # number of demand (read+write) MSHR misses 300311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 56103 # number of demand (read+write) MSHR misses 300411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 202914 # number of demand (read+write) MSHR misses 300511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) MSHR misses 300611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1750 # number of demand (read+write) MSHR misses 300711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1829 # number of demand (read+write) MSHR misses 300811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 37928 # number of demand (read+write) MSHR misses 300911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 159959 # number of demand (read+write) MSHR misses 301011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 200910 # number of demand (read+write) MSHR misses 301111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::total 875575 # number of demand (read+write) MSHR misses 301211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1676 # number of overall MSHR misses 301311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1611 # number of overall MSHR misses 301411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 56103 # number of overall MSHR misses 301511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 202914 # number of overall MSHR misses 301611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of overall MSHR misses 301711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1750 # number of overall MSHR misses 301811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1829 # number of overall MSHR misses 301911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 37928 # 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number of overall MSHR uncacheable cycles 309011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 8691129005 # number of overall MSHR uncacheable cycles 309110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 309210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 309311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.102963 # mshr miss rate for UpgradeReq accesses 309411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.141075 # mshr miss rate for UpgradeReq accesses 309511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.119419 # mshr miss rate for UpgradeReq accesses 309611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.015514 # mshr miss rate for SCUpgradeReq accesses 309711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016066 # mshr miss rate for SCUpgradeReq accesses 309811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015790 # mshr miss rate for SCUpgradeReq accesses 309911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.532786 # mshr miss rate for ReadExReq accesses 310011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.516305 # mshr miss rate for ReadExReq accesses 310111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.525758 # mshr miss rate for ReadExReq accesses 310211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for ReadSharedReq accesses 310311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for ReadSharedReq accesses 310411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for ReadSharedReq accesses 310511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186813 # mshr miss rate for ReadSharedReq accesses 310611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for ReadSharedReq accesses 310711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for ReadSharedReq accesses 310811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for ReadSharedReq accesses 310911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for ReadSharedReq accesses 311011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173628 # mshr miss rate for ReadSharedReq accesses 311111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for ReadSharedReq accesses 311211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.231289 # mshr miss rate for ReadSharedReq accesses 311311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.759299 # mshr miss rate for InvalidateReq accesses 311411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.497444 # mshr miss rate for InvalidateReq accesses 311511606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.681587 # mshr miss rate for InvalidateReq accesses 311611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for demand accesses 311711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for demand accesses 311811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for demand accesses 311911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for demand accesses 312011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for demand accesses 312111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for demand accesses 312211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for demand accesses 312311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for demand accesses 312411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for demand accesses 312511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for demand accesses 312611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.251369 # mshr miss rate for demand accesses 312711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for overall accesses 312811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for overall accesses 312911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for overall accesses 313011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for overall accesses 313111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for overall accesses 313211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for overall accesses 313311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for overall accesses 313411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for overall accesses 313511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for overall accesses 313611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # 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average ReadExReq mshr miss latency 314511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097 # average ReadExReq mshr miss latency 314611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency 314711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency 314811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency 314911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency 315011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency 315111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency 315211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency 315311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency 315411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency 315511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency 315611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency 315711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency 315811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency 315911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency 316011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency 316111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency 316211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency 316311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency 316411606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency 316511606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency 316611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency 316711606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency 316811606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency 316911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency 317011606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency 317111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency 317211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency 317311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency 317411606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency 317511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency 317611606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency 317711606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency 317811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency 317911606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency 318011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency 318111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency 318211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency 318311502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency 318411606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency 318511606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency 318611606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency 318711606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency 318811502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency 318911606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency 319011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency 319111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency 319211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency 319311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter. 319411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data. 319511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 319611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 319711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 319811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 319911606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 320011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 81835 # Transaction distribution 320111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 841453 # Transaction distribution 320211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 38513 # Transaction distribution 320311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 38513 # Transaction distribution 320411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution 320511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 224172 # Transaction distribution 320611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 330190 # Transaction distribution 320711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution 320811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 21 # Transaction distribution 320911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 321011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 142313 # Transaction distribution 321111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 124217 # Transaction distribution 321211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution 321311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateReq 654423 # Transaction distribution 321411606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes) 321510535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 321611606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes) 321711606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes) 321811606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes) 321911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes) 322011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes) 322111606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes) 322211606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes) 322310535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 322411606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes) 322511606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes) 322611606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes) 322711606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes) 322811606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes) 322911606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes) 323011606Sandreas.sandberg@arm.comsystem.membus.snoops 603280 # Total snoops (count) 323111606Sandreas.sandberg@arm.comsystem.membus.snoopTraffic 185472 # Total snoop traffic (bytes) 323211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 2313692 # Request fanout histogram 323311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.013382 # Request fanout histogram 323411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram 323510535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 323611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram 323711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram 323810535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 323910535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 324011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 324110535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 324211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 2313692 # Request fanout histogram 324311606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks) 324410535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 324511138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 324610535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 324711606Sandreas.sandberg@arm.comsystem.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks) 324810535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324911606Sandreas.sandberg@arm.comsystem.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks) 325010535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 325111606Sandreas.sandberg@arm.comsystem.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks) 325210535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 325311606Sandreas.sandberg@arm.comsystem.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks) 325410535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 325511606Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 325611606Sandreas.sandberg@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 325711606Sandreas.sandberg@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 325811606Sandreas.sandberg@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 325911606Sandreas.sandberg@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 326011606Sandreas.sandberg@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 326111606Sandreas.sandberg@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 326211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 326311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 326411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 326511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 326611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 326711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 326811606Sandreas.sandberg@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 326911606Sandreas.sandberg@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 327010515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 327110515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 327210515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 327310515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 327410515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 327510515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 327610515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 327710515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 327810515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 327911374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 328010515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 328110515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 328210515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 328311374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 328410515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 328510515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 328610515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 328710515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 328810515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 328910515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 329010515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 329110515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 329210515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 329310515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 329410515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 329510515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 329610515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 329710515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 329810515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 329910515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 330010515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 330110515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 330210515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 330310515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 330410515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 330510515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 330610515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 330710515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 330810515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 330910515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 331010515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 331110515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 331211606Sandreas.sandberg@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331311606Sandreas.sandberg@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331411606Sandreas.sandberg@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331511606Sandreas.sandberg@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331611606Sandreas.sandberg@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331711606Sandreas.sandberg@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331811606Sandreas.sandberg@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 331911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 332011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 332111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 332211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 332311606Sandreas.sandberg@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332411606Sandreas.sandberg@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332511606Sandreas.sandberg@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332611606Sandreas.sandberg@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332711606Sandreas.sandberg@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332811606Sandreas.sandberg@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 332911606Sandreas.sandberg@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333011606Sandreas.sandberg@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333111606Sandreas.sandberg@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333211606Sandreas.sandberg@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333311606Sandreas.sandberg@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333411606Sandreas.sandberg@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 333511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter. 333611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data. 333711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 333811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter. 333911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 334011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 334111606Sandreas.sandberg@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states 334211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution 334311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution 334411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution 334511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution 334611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution 334711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution 334811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution 334911606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution 335011606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution 335111606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution 335211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 335311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution 335411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution 335511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution 335611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution 335711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution 335811606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes) 335911606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes) 336011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes) 336111606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes) 336211606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes) 336311606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes) 336411606Sandreas.sandberg@arm.comsystem.toL2Bus.snoops 2839573 # Total snoops (count) 336511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes) 336611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram 336711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram 336811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram 336910515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 337011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram 337111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram 337211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram 337310515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 337411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 337510515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 337611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram 337711606Sandreas.sandberg@arm.comsystem.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks) 337810515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 337911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks) 338010515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 338111606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks) 338210515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 338311606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks) 338410515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 338510515SN/A 338610515SN/A---------- End Simulation Statistics ---------- 3387