stats.txt revision 11570
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 47.403575 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 47403574916500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 473223 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 556671 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 25492174892 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 749540 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 1859.53 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 879974755 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 1035148021 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory 2611570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory 2711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory 2811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 56576516 # Number of bytes read from this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory 3011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory 3111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory 3211570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 75204968 # Number of bytes written to this memory 3611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory 3711570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory 3811570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory 3911570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory 4011570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory 4111570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory 4211570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory 4311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory 4411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory 4511570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory 4611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory 4711570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 924529 # Number of read requests responded to by this memory 4811570SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111570SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory 5211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s) 5311570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s) 5411570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s) 5511570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s) 5611570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s) 5711570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s) 5811570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s) 5911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s) 6011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s) 6111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s) 6211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s) 6311570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s) 6411570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s) 6511570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s) 6611570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s) 6711570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s) 7111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s) 7211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s) 7311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s) 7411570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s) 7511570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s) 7611570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s) 7711570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s) 7811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s) 7911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s) 8011570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s) 8111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s) 8211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s) 8311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s) 8411570SCurtis.Dunham@arm.comsystem.physmem.readReqs 924529 # Number of read requests accepted 8511570SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1177330 # Number of write requests accepted 8611570SCurtis.Dunham@arm.comsystem.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue 8711570SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue 8811570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM 8911570SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue 9011570SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM 9111570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side 9211570SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side 9311570SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue 9411570SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 51848 # Per bank write bursts 9711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 60547 # Per bank write bursts 9811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 52943 # Per bank write bursts 9911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 59873 # Per bank write bursts 10011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 53995 # Per bank write bursts 10111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 59394 # Per bank write bursts 10211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 55656 # Per bank write bursts 10311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 56350 # Per bank write bursts 10411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 47470 # Per bank write bursts 10511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 98045 # Per bank write bursts 10611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 51346 # Per bank write bursts 10711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 58216 # Per bank write bursts 10811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 52575 # Per bank write bursts 10911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 60842 # Per bank write bursts 11011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 50185 # Per bank write bursts 11111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 54822 # Per bank write bursts 11211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 69717 # Per bank write bursts 11311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 76530 # Per bank write bursts 11411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 71410 # Per bank write bursts 11511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 77292 # Per bank write bursts 11611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 71372 # Per bank write bursts 11711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 75019 # Per bank write bursts 11811570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 75211 # Per bank write bursts 11911570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 75617 # Per bank write bursts 12011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 67898 # Per bank write bursts 12111570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 76939 # Per bank write bursts 12211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 70016 # Per bank write bursts 12311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 75357 # Per bank write bursts 12411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 71664 # Per bank write bursts 12511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 78615 # Per bank write bursts 12611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 70257 # Per bank write bursts 12711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 72133 # Per bank write bursts 12810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911570SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 33 # Number of times write queue was full causing retry 13011570SCurtis.Dunham@arm.comsystem.physmem.totGap 47403571626000 # Total gap between requests 13110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 881304 # Read request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411570SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1174756 # Write request sizes (log2) 14511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see 14611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see 14711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see 14811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see 14911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see 15011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see 15111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see 15211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see 15311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see 15411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see 15511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see 15611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see 15711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see 15811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see 15911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see 16011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see 16111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see 16211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see 16311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see 16411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see 16511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 16611502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see 19311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see 19411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see 19511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see 19611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see 19711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see 19811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see 19911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see 20011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see 20111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see 20211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see 20311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see 20411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see 20511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see 20611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see 20711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see 20811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see 20911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see 21011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see 21111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see 21211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see 21311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see 21411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see 21511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see 21611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see 21711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see 21811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see 21911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see 22011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see 22111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see 22211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see 22311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see 22411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see 22511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see 22611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see 22711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see 22811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see 22911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see 23011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see 23111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see 23211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see 23311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see 23411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see 23511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see 23611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see 23711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see 23811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see 23911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see 24011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see 24111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation 24211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation 24311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation 24411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation 24511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation 24611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation 24711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation 24811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation 24911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation 25011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation 25111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation 25211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation 25311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation 25411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation 25511570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes 25611570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes 25711570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes 25811570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes 25911374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26211570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes 26311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads 26411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads 26511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads 26611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads 26711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads 26811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads 26911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads 27011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads 27111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads 27211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads 27311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads 27411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads 27511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads 27611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads 27711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads 27811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads 27911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads 28011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads 28111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads 28211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads 28311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads 28411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads 28511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads 28611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads 28711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads 28811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads 28911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads 29011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads 29111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads 29211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 29311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads 29411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads 29511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads 29611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads 29711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads 29811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 29911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads 30011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads 30111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 30211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 30311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads 30411570SCurtis.Dunham@arm.comsystem.physmem.totQLat 29056215697 # Total ticks spent queuing 30511570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM 30611570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers 30711570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst 30810515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30911570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst 31011502SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 31111570SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s 31211502SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s 31311570SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s 31410515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31511374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 31611201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31710892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31811570SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 31911570SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing 32011570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 688543 # Number of row buffer hits during reads 32111570SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 439987 # Number of row buffer hits during writes 32211570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads 32311570SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes 32411570SCurtis.Dunham@arm.comsystem.physmem.avgGap 22553164.43 # Average gap between requests 32511570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined 32611570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ) 32711570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ) 32811570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ) 32911570SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ) 33011570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) 33111570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ) 33211570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ) 33311570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ) 33411570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 668.669411 # Core power per rank (mW) 33511570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states 33611570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states 33710628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33811570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states 33910628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34011570SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ) 34111570SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ) 34211570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ) 34311570SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ) 34411570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) 34511570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ) 34611570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ) 34711570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ) 34811570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 668.683580 # Core power per rank (mW) 34911570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states 35011570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states 35110628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35211570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states 35310628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35411570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 35510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 36010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 36110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 36210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 36310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 38111570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 38211570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 38311570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 38410535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38510535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38610535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38711353Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38811353Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38911353Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 39010515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 39111570SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 39210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 42211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 114038 # Table walker walks requested 42311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors 42411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate 42511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate 42611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting 42711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency 42811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency 42911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency 43011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency 43111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency 43311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency 43411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency 43511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency 43611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency 43711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency 43811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency 43911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency 44011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency 44111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency 44211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency 44311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency 44411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency 44511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency 44611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency 44711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 44811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 44911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 45011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency 45311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution 45411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution 45511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution 45611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution 45711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution 45811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated 45911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated 46011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated 46111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst 46210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst 46411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst 46510628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst 46711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst 46810535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46910535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 86092375 # DTB read hits 47111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 87013 # DTB read misses 47211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 77928513 # DTB write hits 47311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 27025 # DTB write misses 47410535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 47510535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID 47711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 47811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB 47910535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 48011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch 48110535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions 48311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 86179388 # DTB read accesses 48411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 77955538 # DTB write accesses 48510535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 164020888 # DTB hits 48711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 114038 # DTB misses 48811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 164134926 # DTB accesses 48911570SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 49010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 50810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 51610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 51810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 52011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 57747 # Table walker walks requested 52111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors 52211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate 52311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate 52411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency 52511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency 52611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency 52711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency 52811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency 52911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency 53011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency 53111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency 53211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency 53311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency 53411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency 53511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency 53611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency 53711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency 53811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency 53911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency 54011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency 54111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency 54211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency 54311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 54411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 54511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 54611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 54711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency 54811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution 54911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution 55011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution 55111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated 55211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated 55311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated 55410628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst 55611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst 55710628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 55811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst 55911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst 56011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst 56111570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 458544228 # ITB inst hits 56211570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 57747 # ITB inst misses 56310535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 56410535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 56510535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 56610535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 56710535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 56810535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56911570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID 57011502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 57111570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB 57210535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57310535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57410535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57510535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57610535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 57710535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 57811570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 458601975 # ITB inst accesses 57911570SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 458544228 # DTB hits 58011570SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 57747 # DTB misses 58111570SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 458601975 # DTB accesses 58211570SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 27516 # Number of power state transitions 58311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state 58411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state 58511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state 58611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state 58711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state 58811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state 58911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 59011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 59111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state 59211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state 59311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state 59411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 59511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state 59611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state 59711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states 59811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states 59911570SCurtis.Dunham@arm.comsystem.cpu0.numCycles 94807149833 # number of cpu cycles simulated 60010535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 60110535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 60211167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 60311570SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed 60411570SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 458270897 # Number of instructions committed 60511570SCurtis.Dunham@arm.comsystem.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed 60611570SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses 60711570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses 60811570SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 27507374 # number of times a function call or return occured 60911570SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls 61011570SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 494447989 # number of integer instructions 61111570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 420942 # number of float instructions 61211570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read 61311570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written 61411570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read 61511570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written 61611570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read 61711570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written 61811570SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 164010919 # number of memory refs 61911570SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 86087147 # Number of load instructions 62011570SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 77923772 # Number of store instructions 62111570SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles 62211570SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles 62311570SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles 62411570SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.988082 # Percentage of idle cycles 62511570SCurtis.Dunham@arm.comsystem.cpu0.Branches 102213618 # Number of branches fetched 62611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 62711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction 62811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction 62911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction 63011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction 63111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction 63211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction 63311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction 63411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction 63511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction 63611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction 63711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction 63811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction 63911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction 64011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction 64111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction 64211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction 64311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction 64411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction 64511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction 64611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction 64711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction 64811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction 64911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction 65011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction 65111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction 65211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction 65311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction 65411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction 65511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction 65611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction 65711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction 65810535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 65910535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 66011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 538410126 # Class of executed instruction 66111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 66211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 5755741 # number of replacements 66311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use 66411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks. 66511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks. 66611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks. 66711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 66811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor 66911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy 67011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy 67111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 67211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 67311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id 67411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id 67511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 67611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 67711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses 67811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses 67911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 68011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits 68111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits 68211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits 68311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits 68411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits 68511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits 68611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits 68711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits 68811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits 68911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits 69011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits 69111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits 69211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits 69311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits 69411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits 69511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 153968410 # number of overall hits 69611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses 69711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses 69811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses 69911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses 70011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses 70111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses 70211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses 70311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses 70411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses 70511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses 70611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses 70711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses 70811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses 70911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses 71011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses 71111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 5993812 # number of overall misses 71211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles 71311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles 71411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles 71511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles 71611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles 71711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles 71811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles 71911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles 72011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles 72111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles 72211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles 72311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles 72411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles 72511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles 72611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles 72711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles 72811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses) 72911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses) 73011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses) 73111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses) 73211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses) 73311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses) 73411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses) 73511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses) 73611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses) 73711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses) 73811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses) 73911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses) 74011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses 74111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses 74211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses 74311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses 74411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses 74511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses 74611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses 74711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses 74811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses 74911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses 75011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses 75111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses 75211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses 75311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses 75411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses 75511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses 75611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses 75711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses 75811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses 75911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses 76011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency 76111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency 76211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency 76311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency 76411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency 76511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency 76611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency 76711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency 76811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency 76911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency 77010535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77110535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency 77311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency 77411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency 77511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency 77610535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77710535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77810535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 77910535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78010535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78110535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks 78311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 5755741 # number of writebacks 78411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits 78511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits 78611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits 78711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits 78811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits 78911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits 79011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits 79111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits 79211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits 79311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits 79411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses 79511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses 79611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses 79711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses 79811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses 79911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses 80011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses 80111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses 80211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses 80311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses 80411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses 80511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses 80611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses 80711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses 80811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses 80911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses 81011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable 81111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable 81211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable 81311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable 81411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses 81511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses 81611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles 81711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles 81811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles 81911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles 82011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles 82111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles 82211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles 82311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles 82411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles 82511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles 82611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles 82711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles 82811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles 82911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles 83011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles 83111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles 83211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles 83311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles 83411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles 83511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles 83611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles 83711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles 83811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses 83911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses 84011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses 84111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses 84211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses 84311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses 84411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses 84511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses 84611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses 84711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses 84811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses 84911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses 85011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses 85111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses 85211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses 85311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses 85411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency 85511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency 85611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency 85711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency 85811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency 85911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency 86011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency 86111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency 86211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency 86311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency 86411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency 86511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency 86610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 86710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 86811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency 86911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency 87011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency 87111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency 87211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency 87311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency 87411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency 87511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency 87611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 87711570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 4916262 # number of replacements 87811570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use 87911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks. 88011570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks. 88111570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks. 88211502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. 88311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor 88411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy 88511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy 88610535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88711570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 88811570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 88911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 89011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 89110535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89211570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses 89311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses 89411570SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 89511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits 89611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits 89711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits 89811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits 89911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits 90011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 453627454 # number of overall hits 90111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses 90211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses 90311570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses 90411570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses 90511570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses 90611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 4916774 # number of overall misses 90711570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles 90811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles 90911570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles 91011570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles 91111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles 91211570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles 91311570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses) 91411570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses) 91511570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses 91611570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses 91711570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses 91811570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses 91911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # miss rate for ReadReq accesses 92011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010723 # miss rate for ReadReq accesses 92111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010723 # miss rate for demand accesses 92211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.010723 # miss rate for demand accesses 92311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010723 # miss rate for overall accesses 92411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.010723 # miss rate for overall accesses 92511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807 # average ReadReq miss latency 92611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency 92711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency 92811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency 92911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency 93011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # average overall miss latency 93110535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93210535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93310535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 93410535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 93510535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 93610535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 93711570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 4916262 # number of writebacks 93811570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 4916262 # number of writebacks 93911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4916774 # number of ReadReq MSHR misses 94011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4916774 # number of ReadReq MSHR misses 94111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4916774 # number of demand (read+write) MSHR misses 94211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4916774 # number of demand (read+write) MSHR misses 94311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4916774 # number of overall MSHR misses 94411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4916774 # number of overall MSHR misses 94510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 94610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 94710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 94810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 94911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 49818272500 # number of ReadReq MSHR miss cycles 95011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 49818272500 # number of ReadReq MSHR miss cycles 95111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 49818272500 # number of demand (read+write) MSHR miss cycles 95211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 49818272500 # number of demand (read+write) MSHR miss cycles 95311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 49818272500 # number of overall MSHR miss cycles 95411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 49818272500 # number of overall MSHR miss cycles 95511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles 95611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles 95711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles 95811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles 95911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for ReadReq accesses 96011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010723 # mshr miss rate for ReadReq accesses 96111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for demand accesses 96211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010723 # mshr miss rate for demand accesses 96311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for overall accesses 96411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010723 # mshr miss rate for overall accesses 96511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average ReadReq mshr miss latency 96611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807 # average ReadReq mshr miss latency 96711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency 96811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency 96911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency 97011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency 97111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 97211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 97311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 97411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency 97511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 97611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7829609 # number of hwpf issued 97711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7829625 # number of prefetch candidates identified 97811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 97910628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98010628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1043159 # number of prefetches not generated due to page crossing 98211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 98311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2362641 # number of replacements 98411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16162.227513 # Cycle average of tags in use 98511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 14986861 # Total number of references to valid blocks. 98611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2378231 # Sample count of references to valid blocks. 98711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.301684 # Average number of references to valid blocks. 98811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 98911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557 # Average occupied blocks per requestor 99011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.599278 # Average occupied blocks per requestor 99111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 80.860024 # Average occupied blocks per requestor 99211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 896.591654 # Average occupied blocks per requestor 99311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.923412 # Average percentage of cache occupancy 99411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003394 # Average percentage of cache occupancy 99511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004935 # Average percentage of cache occupancy 99611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054724 # Average percentage of cache occupancy 99711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986464 # Average percentage of cache occupancy 99811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1593 # Occupied blocks per task id 99911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 100011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13925 # Occupied blocks per task id 100111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 258 # Occupied blocks per task id 100211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 732 # Occupied blocks per task id 100311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 603 # Occupied blocks per task id 100411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 100511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id 100611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 100711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 100811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 100911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2612 # Occupied blocks per task id 101011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5888 # Occupied blocks per task id 101111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5210 # Occupied blocks per task id 101211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097229 # Percentage of cache occupancy per task id 101311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 101411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.849915 # Percentage of cache occupancy per task id 101511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 362405390 # Number of tag accesses 101611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 362405390 # Number of data accesses 101711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 101811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 268274 # number of ReadReq hits 101911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147126 # number of ReadReq hits 102011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 415400 # number of ReadReq hits 102111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3821588 # number of WritebackDirty hits 102211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3821588 # number of WritebackDirty hits 102311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6849535 # number of WritebackClean hits 102411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6849535 # number of WritebackClean hits 102511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 548 # number of UpgradeReq hits 102611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 548 # number of UpgradeReq hits 102711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 933451 # number of ReadExReq hits 102811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 933451 # number of ReadExReq hits 102911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4462897 # number of ReadCleanReq hits 103011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4462897 # number of ReadCleanReq hits 103111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2959469 # number of ReadSharedReq hits 103211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2959469 # number of ReadSharedReq hits 103311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 207284 # number of InvalidateReq hits 103411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 207284 # number of InvalidateReq hits 103511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 268274 # number of demand (read+write) hits 103611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 147126 # number of demand (read+write) hits 103711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4462897 # number of demand (read+write) hits 103811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3892920 # number of demand (read+write) hits 103911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 8771217 # number of demand (read+write) hits 104011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 268274 # number of overall hits 104111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 147126 # number of overall hits 104211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4462897 # number of overall hits 104311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3892920 # number of overall hits 104411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 8771217 # number of overall hits 104511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10042 # number of ReadReq misses 104611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8210 # number of ReadReq misses 104711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 18252 # number of ReadReq misses 104811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 241773 # number of UpgradeReq misses 104911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 241773 # number of UpgradeReq misses 105011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190127 # number of SCUpgradeReq misses 105111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 190127 # number of SCUpgradeReq misses 105211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 105311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 105411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 253021 # number of ReadExReq misses 105511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 253021 # number of ReadExReq misses 105611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 453877 # number of ReadCleanReq misses 105711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 453877 # number of ReadCleanReq misses 105811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 922445 # number of ReadSharedReq misses 105911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 922445 # number of ReadSharedReq misses 106011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 574180 # number of InvalidateReq misses 106111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 574180 # number of InvalidateReq misses 106211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10042 # number of demand (read+write) misses 106311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8210 # number of demand (read+write) misses 106411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 453877 # number of demand (read+write) misses 106511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1175466 # number of demand (read+write) misses 106611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 1647595 # number of demand (read+write) misses 106711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10042 # number of overall misses 106811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8210 # number of overall misses 106911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 453877 # number of overall misses 107011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1175466 # number of overall misses 107111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 1647595 # number of overall misses 107211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 376993500 # number of ReadReq miss cycles 107311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 339890500 # number of ReadReq miss cycles 107411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 716884000 # number of ReadReq miss cycles 107511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 1915432500 # number of UpgradeReq miss cycles 107611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 1915432500 # number of UpgradeReq miss cycles 107711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1581298000 # number of SCUpgradeReq miss cycles 107811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1581298000 # number of SCUpgradeReq miss cycles 107911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2680500 # number of SCUpgradeFailReq miss cycles 108011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2680500 # number of SCUpgradeFailReq miss cycles 108111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12742251999 # number of ReadExReq miss cycles 108211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12742251999 # number of ReadExReq miss cycles 108311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15633345500 # number of ReadCleanReq miss cycles 108411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 15633345500 # number of ReadCleanReq miss cycles 108511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 32366023500 # number of ReadSharedReq miss cycles 108611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 32366023500 # number of ReadSharedReq miss cycles 108711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 286150500 # number of InvalidateReq miss cycles 108811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 286150500 # number of InvalidateReq miss cycles 108911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 376993500 # number of demand (read+write) miss cycles 109011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 339890500 # number of demand (read+write) miss cycles 109111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 15633345500 # number of demand (read+write) miss cycles 109211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 45108275499 # number of demand (read+write) miss cycles 109311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 61458504999 # number of demand (read+write) miss cycles 109411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 376993500 # number of overall miss cycles 109511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 339890500 # number of overall miss cycles 109611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 15633345500 # number of overall miss cycles 109711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 45108275499 # number of overall miss cycles 109811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 61458504999 # number of overall miss cycles 109911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278316 # number of ReadReq accesses(hits+misses) 110011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155336 # number of ReadReq accesses(hits+misses) 110111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 433652 # number of ReadReq accesses(hits+misses) 110211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3821588 # number of WritebackDirty accesses(hits+misses) 110311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3821588 # number of WritebackDirty accesses(hits+misses) 110411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6849535 # number of WritebackClean accesses(hits+misses) 110511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6849535 # number of WritebackClean accesses(hits+misses) 110611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242321 # number of UpgradeReq accesses(hits+misses) 110711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 242321 # number of UpgradeReq accesses(hits+misses) 110811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190127 # number of SCUpgradeReq accesses(hits+misses) 110911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 190127 # number of SCUpgradeReq accesses(hits+misses) 111011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 111111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 111211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1186472 # number of ReadExReq accesses(hits+misses) 111311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1186472 # number of ReadExReq accesses(hits+misses) 111411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4916774 # number of ReadCleanReq accesses(hits+misses) 111511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4916774 # number of ReadCleanReq accesses(hits+misses) 111611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3881914 # number of ReadSharedReq accesses(hits+misses) 111711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3881914 # number of ReadSharedReq accesses(hits+misses) 111811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 781464 # number of InvalidateReq accesses(hits+misses) 111911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 781464 # number of InvalidateReq accesses(hits+misses) 112011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278316 # number of demand (read+write) accesses 112111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155336 # number of demand (read+write) accesses 112211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4916774 # number of demand (read+write) accesses 112311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5068386 # number of demand (read+write) accesses 112411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 10418812 # number of demand (read+write) accesses 112511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278316 # number of overall (read+write) accesses 112611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155336 # number of overall (read+write) accesses 112711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4916774 # number of overall (read+write) accesses 112811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5068386 # number of overall (read+write) accesses 112911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 10418812 # number of overall (read+write) accesses 113011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for ReadReq accesses 113111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052853 # miss rate for ReadReq accesses 113211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.042089 # miss rate for ReadReq accesses 113311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997739 # miss rate for UpgradeReq accesses 113411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997739 # miss rate for UpgradeReq accesses 113511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 113611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 113710535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 113810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 113911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213255 # miss rate for ReadExReq accesses 114011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.213255 # miss rate for ReadExReq accesses 114111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092312 # miss rate for ReadCleanReq accesses 114211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092312 # miss rate for ReadCleanReq accesses 114311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.237626 # miss rate for ReadSharedReq accesses 114411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.237626 # miss rate for ReadSharedReq accesses 114511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734749 # miss rate for InvalidateReq accesses 114611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734749 # miss rate for InvalidateReq accesses 114711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for demand accesses 114811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052853 # miss rate for demand accesses 114911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092312 # miss rate for demand accesses 115011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.231921 # miss rate for demand accesses 115111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.158137 # miss rate for demand accesses 115211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for overall accesses 115311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052853 # miss rate for overall accesses 115411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092312 # miss rate for overall accesses 115511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.231921 # miss rate for overall accesses 115611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.158137 # miss rate for overall accesses 115711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average ReadReq miss latency 115811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41399.573691 # average ReadReq miss latency 115911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 39277.010739 # average ReadReq miss latency 116011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7922.441712 # average UpgradeReq miss latency 116111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7922.441712 # average UpgradeReq miss latency 116211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 8317.061753 # average SCUpgradeReq miss latency 116311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 8317.061753 # average SCUpgradeReq miss latency 116411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 382928.571429 # average SCUpgradeFailReq miss latency 116511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382928.571429 # average SCUpgradeFailReq miss latency 116611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50360.452291 # average ReadExReq miss latency 116711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50360.452291 # average ReadExReq miss latency 116811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34444.013466 # average ReadCleanReq miss latency 116911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34444.013466 # average ReadCleanReq miss latency 117011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35087.212246 # average ReadSharedReq miss latency 117111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35087.212246 # average ReadSharedReq miss latency 117211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 498.363754 # average InvalidateReq miss latency 117311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 498.363754 # average InvalidateReq miss latency 117411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency 117511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency 117611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency 117711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency 117811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 37301.949204 # average overall miss latency 117911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency 118011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency 118111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency 118211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency 118311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 37301.949204 # average overall miss latency 118410628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118510535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118610628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 118710535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 118810628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118910535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.unused_prefetches 39736 # number of HardPF blocks evicted w/o reference 119111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1527732 # number of writebacks 119211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1527732 # number of writebacks 119311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5839 # number of ReadExReq MSHR hits 119411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5839 # number of ReadExReq MSHR hits 119511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 307 # number of ReadSharedReq MSHR hits 119611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 307 # number of ReadSharedReq MSHR hits 119711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 6146 # number of demand (read+write) MSHR hits 119811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 6146 # number of demand (read+write) MSHR hits 119911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 6146 # number of overall MSHR hits 120011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 6146 # number of overall MSHR hits 120111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10042 # number of ReadReq MSHR misses 120211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8210 # number of ReadReq MSHR misses 120311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 18252 # number of ReadReq MSHR misses 120411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 748015 # number of HardPFReq MSHR misses 120511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 748015 # number of HardPFReq MSHR misses 120611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 241773 # number of UpgradeReq MSHR misses 120711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 241773 # number of UpgradeReq MSHR misses 120811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190127 # number of SCUpgradeReq MSHR misses 120911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190127 # number of SCUpgradeReq MSHR misses 121011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 121111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 121211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247182 # number of ReadExReq MSHR misses 121311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 247182 # number of ReadExReq MSHR misses 121411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 453877 # number of ReadCleanReq MSHR misses 121511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 453877 # number of ReadCleanReq MSHR misses 121611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 922138 # number of ReadSharedReq MSHR misses 121711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 922138 # number of ReadSharedReq MSHR misses 121811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 574180 # number of InvalidateReq MSHR misses 121911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 574180 # number of InvalidateReq MSHR misses 122011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10042 # number of demand (read+write) MSHR misses 122111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8210 # number of demand (read+write) MSHR misses 122211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 453877 # number of demand (read+write) MSHR misses 122311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1169320 # number of demand (read+write) MSHR misses 122411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1641449 # number of demand (read+write) MSHR misses 122511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10042 # number of overall MSHR misses 122611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8210 # number of overall MSHR misses 122711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 453877 # number of overall MSHR misses 122811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1169320 # number of overall MSHR misses 122911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 748015 # number of overall MSHR misses 123011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2389464 # number of overall MSHR misses 123110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 123211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable 123311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70700 # number of ReadReq MSHR uncacheable 123411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable 123511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable 123610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 123711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses 123811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97240 # number of overall MSHR uncacheable misses 123911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of ReadReq MSHR miss cycles 124011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290630500 # number of ReadReq MSHR miss cycles 124111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 607372000 # number of ReadReq MSHR miss cycles 124211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33693542276 # number of HardPFReq MSHR miss cycles 124311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33693542276 # number of HardPFReq MSHR miss cycles 124411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5018820000 # number of UpgradeReq MSHR miss cycles 124511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5018820000 # number of UpgradeReq MSHR miss cycles 124611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3123659500 # number of SCUpgradeReq MSHR miss cycles 124711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3123659500 # number of SCUpgradeReq MSHR miss cycles 124811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2368500 # number of SCUpgradeFailReq MSHR miss cycles 124911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2368500 # number of SCUpgradeFailReq MSHR miss cycles 125011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10716539999 # number of ReadExReq MSHR miss cycles 125111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10716539999 # number of ReadExReq MSHR miss cycles 125211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 12910083500 # number of ReadCleanReq MSHR miss cycles 125311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 12910083500 # number of ReadCleanReq MSHR miss cycles 125411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 26808700000 # number of ReadSharedReq MSHR miss cycles 125511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 26808700000 # number of ReadSharedReq MSHR miss cycles 125611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18844533500 # number of InvalidateReq MSHR miss cycles 125711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18844533500 # number of InvalidateReq MSHR miss cycles 125811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of demand (read+write) MSHR miss cycles 125911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290630500 # number of demand (read+write) MSHR miss cycles 126011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12910083500 # number of demand (read+write) MSHR miss cycles 126111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37525239999 # number of demand (read+write) MSHR miss cycles 126211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 51042695499 # number of demand (read+write) MSHR miss cycles 126311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of overall MSHR miss cycles 126411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290630500 # number of overall MSHR miss cycles 126511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12910083500 # number of overall MSHR miss cycles 126611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37525239999 # number of overall MSHR miss cycles 126711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33693542276 # number of overall MSHR miss cycles 126811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 84736237775 # number of overall MSHR miss cycles 126911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles 127011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850748500 # number of ReadReq MSHR uncacheable cycles 127111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles 127211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles 127311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles 127411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles 127511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses 127611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses 127711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses 127810535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 127910535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 128011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses 128111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses 128211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 128311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 128410535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 128510535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 128611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses 128711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses 128811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses 128911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses 129011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses 129111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses 129211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses 129311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses 129411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses 129511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses 129611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses 129711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses 129811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses 129911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses 130011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses 130111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses 130211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses 130310535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 130411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses 130511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency 130611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency 130711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency 130811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency 130911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency 131011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency 131111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency 131211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency 131311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency 131411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency 131511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency 131611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency 131711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency 131811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency 131911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency 132011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency 132111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency 132211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency 132311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency 132411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency 132511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency 132611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency 132711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency 132811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency 132911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency 133011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency 133111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency 133211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency 133311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency 133411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency 133511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency 133611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency 133711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency 133811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency 133911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency 134011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency 134111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter. 134211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data. 134311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 134411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter. 134511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 134611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 134711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 134811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution 134911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution 135011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 135111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution 135211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution 135311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution 135411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution 135511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution 135611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution 135711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution 135811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution 135911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution 136011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution 136111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution 136211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution 136311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution 136411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution 136511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution 136611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution 136711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution 136811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes) 136911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes) 137011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes) 137111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes) 137211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes) 137311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes) 137411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes) 137511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes) 137611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes) 137711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes) 137811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 6259200 # Total snoops (count) 137911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes) 138011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram 138111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram 138211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram 138310535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 138411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram 138511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram 138611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram 138710535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 138910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 139011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram 139111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks) 139210535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 139311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks) 139410535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 139511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks) 139610535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 139711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks) 139810535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 139911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks) 140010535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 140111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks) 140210535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 140311570SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 140410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 140510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 140610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 140710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 140810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 140910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 141110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 141310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 141410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 141510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 141610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 141710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 141810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 141910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 142110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 142210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 142310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 142410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 142510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 142610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 142710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 142810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 142910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 143010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 143110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 143210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 143311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 143411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 102344 # Table walker walks requested 143511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors 143611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate 143711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate 143811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting 143911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency 144011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency 144111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency 144211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency 144311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 144411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency 144511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency 144611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency 144711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency 144811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency 144911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency 145011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency 145111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency 145211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency 145311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency 145411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 145511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 145611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 145711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency 145811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution 145911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution 146011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution 146111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution 146211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution 146311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution 146411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated 146511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated 146611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated 146711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst 146810628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst 147011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst 147110628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst 147311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst 147410535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 147510535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 147611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 79660508 # DTB read hits 147711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 74735 # DTB read misses 147811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 72705787 # DTB write hits 147911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 27609 # DTB write misses 148010535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 148110535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID 148311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 148411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB 148510535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 148611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch 148710535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 148811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions 148911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 79735243 # DTB read accesses 149011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 72733396 # DTB write accesses 149110535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 149211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 152366295 # DTB hits 149311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 102344 # DTB misses 149411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 152468639 # DTB accesses 149511570SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 149610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 149710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 149810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 149910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 150010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 150210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 150310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 150410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 150510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 150610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 150710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 150810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 150910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 151010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 151110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 151310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 151510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 151610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 151710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 151810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 151910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 152010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 152110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 152210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 152310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 152410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 152511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 152611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 58593 # Table walker walks requested 152711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors 152811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate 152911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate 153011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency 153111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency 153211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency 153311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency 153411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency 153511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency 153611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency 153711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency 153811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency 153911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency 154011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency 154111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency 154211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency 154311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency 154411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency 154511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency 154611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency 154711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 154811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 154911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 155011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 155111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 155211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency 155311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution 155411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution 155511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution 155611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated 155711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated 155811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated 155910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 156011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst 156111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst 156210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 156311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst 156411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst 156511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst 156611570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 421982441 # ITB inst hits 156711570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 58593 # ITB inst misses 156810535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 156910535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 157010535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 157110535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 157210535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 157310535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 157411570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID 157511502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 157611570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB 157710535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 157810535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 157910535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 158010535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 158110535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 158210535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 158311570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 422041034 # ITB inst accesses 158411570SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 421982441 # DTB hits 158511570SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 58593 # DTB misses 158611570SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 422041034 # DTB accesses 158711570SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 9904 # Number of power state transitions 158811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state 158911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state 159011570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state 159111570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state 159211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state 159311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state 159411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state 159511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state 159611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state 159711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state 159811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state 159911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state 160011570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state 160111570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state 160211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 160311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state 160411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state 160511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states 160611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states 160711570SCurtis.Dunham@arm.comsystem.cpu1.numCycles 94807149833 # number of cpu cycles simulated 160810535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 160910535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 161011167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 161111570SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed 161211570SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 421703858 # Number of instructions committed 161311570SCurtis.Dunham@arm.comsystem.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed 161411570SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses 161511570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses 161611570SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 25188507 # number of times a function call or return occured 161711570SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls 161811570SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 456781482 # number of integer instructions 161911570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 475663 # number of float instructions 162011570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read 162111570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written 162211570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read 162311570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written 162411570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read 162511570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written 162611570SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 152358964 # number of memory refs 162711570SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 79658830 # Number of load instructions 162811570SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 72700134 # Number of store instructions 162911570SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles 163011570SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles 163111570SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles 163211570SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.989420 # Percentage of idle cycles 163311570SCurtis.Dunham@arm.comsystem.cpu1.Branches 94064671 # Number of branches fetched 163411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 163511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction 163611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction 163711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction 163811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction 163911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction 164011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction 164111570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction 164211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction 164311570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction 164411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction 164511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction 164611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction 164711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction 164811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction 164911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction 165011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction 165111570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction 165211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction 165311570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction 165411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction 165511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction 165611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction 165711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction 165811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction 165911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction 166011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction 166111570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction 166211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction 166311570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction 166411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction 166511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction 166610535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 166710535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 166811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 497333042 # Class of executed instruction 166911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 167011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 5003393 # number of replacements 167111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use 167211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks. 167311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks. 167411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks. 167511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit. 167611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor 167711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy 167811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy 167911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 168011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 168111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id 168211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 168311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 168411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses 168511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses 168611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 168711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits 168811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits 168911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits 169011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits 169111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits 169211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits 169311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits 169411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits 169511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits 169611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits 169711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits 169811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits 169911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits 170011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits 170111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits 170211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 143489600 # number of overall hits 170311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses 170411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses 170511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses 170611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses 170711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses 170811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses 170911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses 171011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses 171111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses 171211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses 171311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses 171411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses 171511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses 171611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses 171711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses 171811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 5199606 # number of overall misses 171911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles 172011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles 172111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles 172211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles 172311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles 172411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles 172511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles 172611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles 172711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles 172811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles 172911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles 173011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles 173111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles 173211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles 173311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles 173411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles 173511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses) 173611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses) 173711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses) 173811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses) 173911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses) 174011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses) 174111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses) 174211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses) 174311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses) 174411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses) 174511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses) 174611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses) 174711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses 174811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses 174911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses 175011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses 175111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses 175211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses 175311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses 175411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses 175511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses 175611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses 175711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses 175811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses 175911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses 176011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses 176111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses 176211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses 176311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses 176411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses 176511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses 176611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses 176711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency 176811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency 176911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency 177011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency 177111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency 177211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency 177311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency 177411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency 177511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency 177611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency 177710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 177810535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 177911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency 178011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency 178111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency 178211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency 178310535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178410535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178510535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178610535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 178710535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178810535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 178911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks 179011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 5003393 # number of writebacks 179111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits 179211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits 179311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits 179411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits 179511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits 179611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits 179711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits 179811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits 179911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits 180011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits 180111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses 180211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses 180311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses 180411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses 180511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses 180611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses 180711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses 180811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses 180911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses 181011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses 181111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses 181211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses 181311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses 181411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses 181511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses 181611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses 181711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable 181811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable 181911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable 182011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable 182111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses 182211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses 182311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles 182411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles 182511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles 182611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles 182711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles 182811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles 182911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles 183011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles 183111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles 183211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles 183311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles 183411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles 183511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles 183611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles 183711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles 183811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles 183911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles 184011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles 184111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles 184211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles 184311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles 184411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles 184511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses 184611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses 184711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses 184811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses 184911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses 185011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses 185111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses 185211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses 185311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses 185411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses 185511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses 185611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses 185711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses 185811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses 185911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses 186011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses 186111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency 186211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency 186311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency 186411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency 186511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency 186611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency 186711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency 186811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency 186911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency 187011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency 187111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency 187211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency 187310535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 187410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 187511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency 187611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency 187711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency 187811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency 187911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency 188011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency 188111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency 188211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency 188311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 188411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 5018955 # number of replacements 188511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use 188611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks. 188711570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks. 188811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks. 188911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit. 189011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor 189111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy 189211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy 189310535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 189411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 189511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 189611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 189710535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 189811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses 189911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses 190011570SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 190111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits 190211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits 190311570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits 190411570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits 190511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits 190611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 416962969 # number of overall hits 190711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # number of ReadReq misses 190811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 5019472 # number of ReadReq misses 190911570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5019472 # number of demand (read+write) misses 191011570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 5019472 # number of demand (read+write) misses 191111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5019472 # number of overall misses 191211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 5019472 # number of overall misses 191311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53186343000 # number of ReadReq miss cycles 191411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 53186343000 # number of ReadReq miss cycles 191511570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 53186343000 # number of demand (read+write) miss cycles 191611570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 53186343000 # number of demand (read+write) miss cycles 191711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 53186343000 # number of overall miss cycles 191811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 53186343000 # number of overall miss cycles 191911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 421982441 # number of ReadReq accesses(hits+misses) 192011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 421982441 # number of ReadReq accesses(hits+misses) 192111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 421982441 # number of demand (read+write) accesses 192211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 421982441 # number of demand (read+write) accesses 192311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 421982441 # number of overall (read+write) accesses 192411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 421982441 # number of overall (read+write) accesses 192511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011895 # miss rate for ReadReq accesses 192611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011895 # miss rate for ReadReq accesses 192711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011895 # miss rate for demand accesses 192811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011895 # miss rate for demand accesses 192911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011895 # miss rate for overall accesses 193011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011895 # miss rate for overall accesses 193111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524 # average ReadReq miss latency 193211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524 # average ReadReq miss latency 193311570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency 193411570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10596.003524 # average overall miss latency 193511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency 193611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency 193710535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193810535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 193910535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194010535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 194110535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 194210535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194311570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks 194411570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 5018955 # number of writebacks 194511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses 194611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses 194711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses 194811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses 194911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses 195011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses 195110827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 195210827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 195310827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 195410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 195511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles 195611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles 195711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles 195811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles 195911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles 196011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles 196111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles 196211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles 196311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles 196411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles 196511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses 196611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses 196711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses 196811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses 196911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses 197011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses 197111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency 197211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency 197311570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency 197411570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency 197511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency 197611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency 197711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency 197811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency 197911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency 198011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency 198111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 198211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued 198311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified 198411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 198510628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 198610628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 198711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 855832 # number of prefetches not generated due to page crossing 198811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 198911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 1952199 # number of replacements 199011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13310.052713 # Cycle average of tags in use 199111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 14647404 # Total number of references to valid blocks. 199211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1968271 # Sample count of references to valid blocks. 199311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.441762 # Average number of references to valid blocks. 199411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9691338413500 # Cycle when the warmup percentage was hit. 199511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537 # Average occupied blocks per requestor 199611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.710351 # Average occupied blocks per requestor 199711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 42.105943 # Average occupied blocks per requestor 199811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 846.327882 # Average occupied blocks per requestor 199911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.755304 # Average percentage of cache occupancy 200011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002851 # Average percentage of cache occupancy 200111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002570 # Average percentage of cache occupancy 200211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051656 # Average percentage of cache occupancy 200311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.812381 # Average percentage of cache occupancy 200411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1315 # Occupied blocks per task id 200511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 200611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id 200711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 28 # Occupied blocks per task id 200811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 206 # Occupied blocks per task id 200911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 560 # Occupied blocks per task id 201011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id 201111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id 201211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id 201311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 201411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 201511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id 201611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id 201711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id 201811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id 201911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id 202011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 202111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id 202211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 339868675 # Number of tag accesses 202311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 339868675 # Number of data accesses 202411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 202511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236019 # number of ReadReq hits 202611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150274 # number of ReadReq hits 202711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 386293 # number of ReadReq hits 202811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3171050 # number of WritebackDirty hits 202911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3171050 # number of WritebackDirty hits 203011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6850339 # number of WritebackClean hits 203111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6850339 # number of WritebackClean hits 203211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 404 # number of UpgradeReq hits 203311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 404 # number of UpgradeReq hits 203411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 839001 # number of ReadExReq hits 203511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 839001 # number of ReadExReq hits 203611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4555671 # number of ReadCleanReq hits 203711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4555671 # number of ReadCleanReq hits 203811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2665864 # number of ReadSharedReq hits 203911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2665864 # number of ReadSharedReq hits 204011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201941 # number of InvalidateReq hits 204111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 201941 # number of InvalidateReq hits 204211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236019 # number of demand (read+write) hits 204311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 150274 # number of demand (read+write) hits 204411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4555671 # number of demand (read+write) hits 204511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3504865 # number of demand (read+write) hits 204611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 8446829 # number of demand (read+write) hits 204711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236019 # number of overall hits 204811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 150274 # number of overall hits 204911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4555671 # number of overall hits 205011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3504865 # number of overall hits 205111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 8446829 # number of overall hits 205211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10494 # number of ReadReq misses 205311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9148 # number of ReadReq misses 205411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 19642 # number of ReadReq misses 205511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207236 # number of UpgradeReq misses 205611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 207236 # number of UpgradeReq misses 205711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 191347 # number of SCUpgradeReq misses 205811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 191347 # number of SCUpgradeReq misses 205911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 206011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 206111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 252464 # number of ReadExReq misses 206211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 252464 # number of ReadExReq misses 206311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463801 # number of ReadCleanReq misses 206411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 463801 # number of ReadCleanReq misses 206511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 876385 # number of ReadSharedReq misses 206611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 876385 # number of ReadSharedReq misses 206711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256334 # number of InvalidateReq misses 206811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 256334 # number of InvalidateReq misses 206911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10494 # number of demand (read+write) misses 207011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9148 # number of demand (read+write) misses 207111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 463801 # number of demand (read+write) misses 207211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1128849 # number of demand (read+write) misses 207311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 1612292 # number of demand (read+write) misses 207411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10494 # number of overall misses 207511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9148 # number of overall misses 207611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 463801 # number of overall misses 207711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1128849 # number of overall misses 207811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 1612292 # number of overall misses 207911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 383427500 # number of ReadReq miss cycles 208011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 341472000 # number of ReadReq miss cycles 208111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 724899500 # number of ReadReq miss cycles 208211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1893664000 # number of UpgradeReq miss cycles 208311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 1893664000 # number of UpgradeReq miss cycles 208411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1540982500 # number of SCUpgradeReq miss cycles 208511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1540982500 # number of SCUpgradeReq miss cycles 208611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2848499 # number of SCUpgradeFailReq miss cycles 208711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2848499 # number of SCUpgradeFailReq miss cycles 208811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10062122499 # number of ReadExReq miss cycles 208911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 10062122499 # number of ReadExReq miss cycles 209011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15777836000 # number of ReadCleanReq miss cycles 209111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 15777836000 # number of ReadCleanReq miss cycles 209211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28794953500 # number of ReadSharedReq miss cycles 209311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 28794953500 # number of ReadSharedReq miss cycles 209411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 441282000 # number of InvalidateReq miss cycles 209511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 441282000 # number of InvalidateReq miss cycles 209611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 383427500 # number of demand (read+write) miss cycles 209711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 341472000 # number of demand (read+write) miss cycles 209811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 15777836000 # number of demand (read+write) miss cycles 209911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 38857075999 # number of demand (read+write) miss cycles 210011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 55359811499 # number of demand (read+write) miss cycles 210111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 383427500 # number of overall miss cycles 210211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 341472000 # number of overall miss cycles 210311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 15777836000 # number of overall miss cycles 210411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 38857075999 # number of overall miss cycles 210511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 55359811499 # number of overall miss cycles 210611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 246513 # number of ReadReq accesses(hits+misses) 210711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159422 # number of ReadReq accesses(hits+misses) 210811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 405935 # number of ReadReq accesses(hits+misses) 210911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3171050 # number of WritebackDirty accesses(hits+misses) 211011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3171050 # number of WritebackDirty accesses(hits+misses) 211111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6850339 # number of WritebackClean accesses(hits+misses) 211211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6850339 # number of WritebackClean accesses(hits+misses) 211311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207640 # number of UpgradeReq accesses(hits+misses) 211411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 207640 # number of UpgradeReq accesses(hits+misses) 211511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 191347 # number of SCUpgradeReq accesses(hits+misses) 211611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 191347 # number of SCUpgradeReq accesses(hits+misses) 211711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 211811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 211911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1091465 # number of ReadExReq accesses(hits+misses) 212011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1091465 # number of ReadExReq accesses(hits+misses) 212111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5019472 # number of ReadCleanReq accesses(hits+misses) 212211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5019472 # number of ReadCleanReq accesses(hits+misses) 212311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3542249 # number of ReadSharedReq accesses(hits+misses) 212411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3542249 # number of ReadSharedReq accesses(hits+misses) 212511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458275 # number of InvalidateReq accesses(hits+misses) 212611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 458275 # number of InvalidateReq accesses(hits+misses) 212711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 246513 # number of demand (read+write) accesses 212811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159422 # number of demand (read+write) accesses 212911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5019472 # number of demand (read+write) accesses 213011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4633714 # number of demand (read+write) accesses 213111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 10059121 # number of demand (read+write) accesses 213211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 246513 # number of overall (read+write) accesses 213311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159422 # number of overall (read+write) accesses 213411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5019472 # number of overall (read+write) accesses 213511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4633714 # number of overall (read+write) accesses 213611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 10059121 # number of overall (read+write) accesses 213711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for ReadReq accesses 213811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057382 # miss rate for ReadReq accesses 213911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.048387 # miss rate for ReadReq accesses 214011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998054 # miss rate for UpgradeReq accesses 214111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998054 # miss rate for UpgradeReq accesses 214211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 214311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 214410535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 214510535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 214611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231307 # miss rate for ReadExReq accesses 214711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.231307 # miss rate for ReadExReq accesses 214811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092400 # miss rate for ReadCleanReq accesses 214911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092400 # miss rate for ReadCleanReq accesses 215011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.247409 # miss rate for ReadSharedReq accesses 215111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.247409 # miss rate for ReadSharedReq accesses 215211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.559345 # miss rate for InvalidateReq accesses 215311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.559345 # miss rate for InvalidateReq accesses 215411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for demand accesses 215511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057382 # miss rate for demand accesses 215611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092400 # miss rate for demand accesses 215711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243616 # miss rate for demand accesses 215811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.160282 # miss rate for demand accesses 215911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for overall accesses 216011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057382 # miss rate for overall accesses 216111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092400 # miss rate for overall accesses 216211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243616 # miss rate for overall accesses 216311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.160282 # miss rate for overall accesses 216411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average ReadReq miss latency 216511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37327.503279 # average ReadReq miss latency 216611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 36905.584971 # average ReadReq miss latency 216711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9137.717385 # average UpgradeReq miss latency 216811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9137.717385 # average UpgradeReq miss latency 216911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 8053.340267 # average SCUpgradeReq miss latency 217011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 8053.340267 # average SCUpgradeReq miss latency 217111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 406928.428571 # average SCUpgradeFailReq miss latency 217211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 406928.428571 # average SCUpgradeFailReq miss latency 217311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39855.672488 # average ReadExReq miss latency 217411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39855.672488 # average ReadExReq miss latency 217511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34018.546747 # average ReadCleanReq miss latency 217611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34018.546747 # average ReadCleanReq miss latency 217711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32856.511122 # average ReadSharedReq miss latency 217811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32856.511122 # average ReadSharedReq miss latency 217911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1721.511778 # average InvalidateReq miss latency 218011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1721.511778 # average InvalidateReq miss latency 218111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency 218211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency 218311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency 218411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency 218511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 34336.095136 # average overall miss latency 218611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency 218711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency 218811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency 218911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency 219011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 34336.095136 # average overall miss latency 219110628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219210535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 219310628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 219410535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 219510628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 219610535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 219711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.unused_prefetches 40910 # number of HardPF blocks evicted w/o reference 219811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1077285 # number of writebacks 219911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1077285 # number of writebacks 220011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4355 # number of ReadExReq MSHR hits 220111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4355 # number of ReadExReq MSHR hits 220211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 371 # number of ReadSharedReq MSHR hits 220311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 371 # number of ReadSharedReq MSHR hits 220411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4726 # number of demand (read+write) MSHR hits 220511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4726 # number of demand (read+write) MSHR hits 220611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4726 # number of overall MSHR hits 220711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4726 # number of overall MSHR hits 220811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10494 # number of ReadReq MSHR misses 220911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9148 # number of ReadReq MSHR misses 221011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 19642 # number of ReadReq MSHR misses 221111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of HardPFReq MSHR misses 221211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 670250 # number of HardPFReq MSHR misses 221311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207236 # number of UpgradeReq MSHR misses 221411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 207236 # number of UpgradeReq MSHR misses 221511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 191347 # number of SCUpgradeReq MSHR misses 221611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 191347 # number of SCUpgradeReq MSHR misses 221711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 221811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 221911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248109 # number of ReadExReq MSHR misses 222011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 248109 # number of ReadExReq MSHR misses 222111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463801 # number of ReadCleanReq MSHR misses 222211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463801 # number of ReadCleanReq MSHR misses 222311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 876014 # number of ReadSharedReq MSHR misses 222411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 876014 # number of ReadSharedReq MSHR misses 222511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256334 # number of InvalidateReq MSHR misses 222611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 256334 # number of InvalidateReq MSHR misses 222711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10494 # number of demand (read+write) MSHR misses 222811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9148 # number of demand (read+write) MSHR misses 222911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463801 # number of demand (read+write) MSHR misses 223011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124123 # number of demand (read+write) MSHR misses 223111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1607566 # number of demand (read+write) MSHR misses 223211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10494 # number of overall MSHR misses 223311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9148 # number of overall MSHR misses 223411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463801 # number of overall MSHR misses 223511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124123 # number of overall MSHR misses 223611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of overall MSHR misses 223711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2277816 # number of overall MSHR misses 223810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 223911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable 224011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11131 # number of ReadReq MSHR uncacheable 224111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable 224211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable 224310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 224411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses 224511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23055 # number of overall MSHR uncacheable misses 224611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of ReadReq MSHR miss cycles 224711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286584000 # number of ReadReq MSHR miss cycles 224811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 607047500 # number of ReadReq MSHR miss cycles 224911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of HardPFReq MSHR miss cycles 225011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26432385766 # number of HardPFReq MSHR miss cycles 225111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4355093500 # number of UpgradeReq MSHR miss cycles 225211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4355093500 # number of UpgradeReq MSHR miss cycles 225311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3151504000 # number of SCUpgradeReq MSHR miss cycles 225411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3151504000 # number of SCUpgradeReq MSHR miss cycles 225511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2506499 # number of SCUpgradeFailReq MSHR miss cycles 225611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2506499 # number of SCUpgradeFailReq MSHR miss cycles 225711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8136910999 # number of ReadExReq MSHR miss cycles 225811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8136910999 # number of ReadExReq MSHR miss cycles 225911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12995030000 # number of ReadCleanReq MSHR miss cycles 226011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12995030000 # number of ReadCleanReq MSHR miss cycles 226111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23494652500 # number of ReadSharedReq MSHR miss cycles 226211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23494652500 # number of ReadSharedReq MSHR miss cycles 226311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6984949000 # number of InvalidateReq MSHR miss cycles 226411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6984949000 # number of InvalidateReq MSHR miss cycles 226511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of demand (read+write) MSHR miss cycles 226611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286584000 # number of demand (read+write) MSHR miss cycles 226711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12995030000 # number of demand (read+write) MSHR miss cycles 226811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31631563499 # number of demand (read+write) MSHR miss cycles 226911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 45233640999 # number of demand (read+write) MSHR miss cycles 227011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of overall MSHR miss cycles 227111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286584000 # number of overall MSHR miss cycles 227211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12995030000 # number of overall MSHR miss cycles 227311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31631563499 # number of overall MSHR miss cycles 227411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of overall MSHR miss cycles 227511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 71666026765 # number of overall MSHR miss cycles 227611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401000 # number of ReadReq MSHR uncacheable cycles 227711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1799706000 # number of ReadReq MSHR uncacheable cycles 227811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1809107000 # number of ReadReq MSHR uncacheable cycles 227911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401000 # number of overall MSHR uncacheable cycles 228011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1799706000 # number of overall MSHR uncacheable cycles 228111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1809107000 # number of overall MSHR uncacheable cycles 228211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for ReadReq accesses 228311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for ReadReq accesses 228411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048387 # mshr miss rate for ReadReq accesses 228510535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 228610535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 228711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998054 # mshr miss rate for UpgradeReq accesses 228811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998054 # mshr miss rate for UpgradeReq accesses 228911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 229011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 229110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 229210535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 229311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.227317 # mshr miss rate for ReadExReq accesses 229411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.227317 # mshr miss rate for ReadExReq accesses 229511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for ReadCleanReq accesses 229611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092400 # mshr miss rate for ReadCleanReq accesses 229711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247304 # mshr miss rate for ReadSharedReq accesses 229811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247304 # mshr miss rate for ReadSharedReq accesses 229911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.559345 # mshr miss rate for InvalidateReq accesses 230011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.559345 # mshr miss rate for InvalidateReq accesses 230111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for demand accesses 230211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for demand accesses 230311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for demand accesses 230411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for demand accesses 230511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.159812 # mshr miss rate for demand accesses 230611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for overall accesses 230711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for overall accesses 230811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for overall accesses 230911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for overall accesses 231010535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 231111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses 231211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency 231311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency 231411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency 231511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency 231611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency 231711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency 231811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency 231911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency 232011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency 232111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency 232211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency 232311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency 232411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency 232511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency 232611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency 232711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency 232811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency 232911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency 233011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency 233111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency 233211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency 233311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency 233411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency 233511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency 233611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency 233711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency 233811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency 233911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency 234011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency 234111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency 234211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency 234311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency 234411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency 234511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency 234611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency 234711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency 234811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter. 234911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data. 235011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 235111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter. 235211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 235311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 235411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 235511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution 235611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution 235711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 235811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution 235911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution 236011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution 236111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution 236211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution 236311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution 236411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution 236511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution 236611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution 236711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution 236811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution 236911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution 237011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution 237111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution 237211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution 237311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution 237411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution 237511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes) 237611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes) 237711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes) 237811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes) 237911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes) 238011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes) 238111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes) 238211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes) 238311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes) 238411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes) 238511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 5663025 # Total snoops (count) 238611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes) 238711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram 238811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram 238911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram 239010535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram 239211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram 239311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram 239410535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 239511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 239610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 239711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram 239811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks) 239910535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 240011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks) 240110535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 240211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks) 240310535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 240411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks) 240510535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 240611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks) 240710535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 240811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks) 240910535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 241011570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 241111502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40346 # Transaction distribution 241211502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40346 # Transaction distribution 241311570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 136621 # Transaction distribution 241411570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 136621 # Transaction distribution 241511570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) 241610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 241711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 241810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 241910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 242010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 242110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 242210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 242310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 242410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 242510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 242611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 242710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 242811570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) 242911570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes) 243011570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes) 243110535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 243210535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 243311570SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes) 243411570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) 243510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 243611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 243710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 243810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 243910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 244010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 244410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244511374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 244610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 244711570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) 244811570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes) 244911570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes) 245010535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 245110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 245211570SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes) 245311570SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks) 245410535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 245511502SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 245610535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 245711570SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) 245810535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 245911201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 246010535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 246111570SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) 246211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 246310535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 246410535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 246511353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 246610535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 246711502SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 246810535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 246911201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 247010535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 247111502SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 247210535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 247311570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 247410535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 247511570SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks) 247610535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 247711570SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) 247810535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 247911570SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks) 248010535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 248111570SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) 248210535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 248311570SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks) 248410535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 248510892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 248610535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 248711570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 248811570SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115616 # number of replacements 248911570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use 249011336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 249111570SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks. 249211336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 249311570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit. 249411570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor 249511570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor 249611570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy 249711570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy 249811570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy 249910535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 250010535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 250110535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 250211570SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040928 # Number of tag accesses 250311570SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040928 # Number of data accesses 250411570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 250510535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 250611570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses 250711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8928 # number of ReadReq misses 250810535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 250910535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 251011353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 251111353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 251210535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 251311570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses 251411570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115659 # number of demand (read+write) misses 251510535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 251611570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115619 # number of overall misses 251711570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115659 # number of overall misses 251811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 251911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles 252011570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles 252110726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 252210726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 252311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles 252411570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles 252511570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 252611570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles 252711570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles 252811570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 252911570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles 253011570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles 253110535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 253211570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses) 253311570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses) 253410535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 253510535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 253611353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 253711353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 253810535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 253911570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses 254011570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses 254110535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 254211570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses 254311570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses 254410535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 254510535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 254610535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 254710535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 254810535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 254911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 255011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 255110535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 255210535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 255310535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 255410535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 255510535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 255610535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 255711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 255811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency 255911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency 256010726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 256110726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 256211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency 256311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency 256411570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 256511570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency 256611570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency 256711570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 256811570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency 256911570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency 257011570SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked 257110535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257211570SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked 257310535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 257411570SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked 257510535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257611502SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106695 # number of writebacks 257711502SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106695 # number of writebacks 257810535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 257911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses 258011570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses 258110535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 258210535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 258311353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 258411353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 258510535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 258611570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses 258711570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses 258810535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 258911570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses 259011570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses 259111570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 259211570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles 259311570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles 259410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 259510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 259611570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles 259711570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles 259811570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 259911570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles 260011570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles 260111570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 260211570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles 260311570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles 260410535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 260510535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 260610535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 260710535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 260810535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 260911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 261011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 261110535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 261210535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 261310535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 261410535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 261510535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 261610535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 261711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 261811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency 261911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency 262010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 262110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 262211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency 262311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency 262411570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 262511570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency 262611570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency 262711570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 262811570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency 262911570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency 263011570SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 263111570SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1334376 # number of replacements 263211570SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use 263311570SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 5390543 # Total number of references to valid blocks. 263411570SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks. 263511570SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks. 263611502SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. 263711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 22223.163606 # Average occupied blocks per requestor 263811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 261.500257 # Average occupied blocks per requestor 263911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 456.360455 # Average occupied blocks per requestor 264011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3501.846073 # Average occupied blocks per requestor 264111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 10429.068271 # Average occupied blocks per requestor 264211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383 # Average occupied blocks per requestor 264311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 41.820782 # Average occupied blocks per requestor 264411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 49.581814 # Average occupied blocks per requestor 264511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3191.520948 # Average occupied blocks per requestor 264611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 3798.713740 # Average occupied blocks per requestor 264711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor 264811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy 264911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy 265011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy 265111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy 265211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy 265311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy 265411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy 265511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy 265611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy 265711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy 265811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy 265911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy 266011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id 266111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id 266211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id 266311570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 266411570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id 266511570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id 266611570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id 266711570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id 266811570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 266911570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 267011570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id 267111570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id 267211570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id 267311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id 267411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id 267511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id 267611570SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 69824789 # Number of tag accesses 267711570SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 69824789 # Number of data accesses 267811570SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 267911570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits 268011570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits 268111570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits 268211570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 131498 # number of UpgradeReq hits 268311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 288738 # number of UpgradeReq hits 268411570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 36551 # number of SCUpgradeReq hits 268511570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 35663 # number of SCUpgradeReq hits 268611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 72214 # number of SCUpgradeReq hits 268711570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 46670 # number of ReadExReq hits 268811570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 57995 # number of ReadExReq hits 268911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 104665 # number of ReadExReq hits 269011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4832 # number of ReadSharedReq hits 269111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3674 # number of ReadSharedReq hits 269211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 408343 # number of ReadSharedReq hits 269311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 539971 # number of ReadSharedReq hits 269411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 281420 # number of ReadSharedReq hits 269511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5997 # number of ReadSharedReq hits 269611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5496 # number of ReadSharedReq hits 269711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 419901 # number of ReadSharedReq hits 269811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 530515 # number of ReadSharedReq hits 269911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 275271 # number of ReadSharedReq hits 270011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 2475420 # number of ReadSharedReq hits 270111570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 117433 # number of InvalidateReq hits 270211570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 122622 # number of InvalidateReq hits 270311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 240055 # number of InvalidateReq hits 270411570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 4832 # number of demand (read+write) hits 270511570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3674 # number of demand (read+write) hits 270611570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 408343 # number of demand (read+write) hits 270711570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 586641 # number of demand (read+write) hits 270811570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 281420 # number of demand (read+write) hits 270911570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits 271011570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits 271111570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits 271211570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits 271311570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits 271411570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2580085 # number of demand (read+write) hits 271511570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits 271611570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits 271711570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 408343 # number of overall hits 271811570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 586641 # number of overall hits 271911570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits 272011570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits 272111570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5496 # number of overall hits 272211570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 419901 # number of overall hits 272311570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 588510 # number of overall hits 272411570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 275271 # number of overall hits 272511570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2580085 # number of overall hits 272611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 61532 # number of UpgradeReq misses 272711570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 60685 # number of UpgradeReq misses 272811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 122217 # number of UpgradeReq misses 272911570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 12602 # number of SCUpgradeReq misses 273011570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 13049 # number of SCUpgradeReq misses 273111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 25651 # number of SCUpgradeReq misses 273211570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 81623 # number of ReadExReq misses 273311570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 50736 # number of ReadExReq misses 273411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 132359 # number of ReadExReq misses 273511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq misses 273611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1980 # number of ReadSharedReq misses 273711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 45534 # number of ReadSharedReq misses 273811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 135010 # number of ReadSharedReq misses 273911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq misses 274011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq misses 274111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1646 # number of ReadSharedReq misses 274211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 43900 # number of ReadSharedReq misses 274311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 98157 # number of ReadSharedReq misses 274411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq misses 274511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 747537 # number of ReadSharedReq misses 274611570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 445868 # number of InvalidateReq misses 274711570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 117477 # number of InvalidateReq misses 274811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 563345 # number of InvalidateReq misses 274911570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1903 # number of demand (read+write) misses 275011570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1980 # number of demand (read+write) misses 275111570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 45534 # number of demand (read+write) misses 275211570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 216633 # number of demand (read+write) misses 275311570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) misses 275411570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1748 # number of demand (read+write) misses 275511570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1646 # number of demand (read+write) misses 275611570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 43900 # number of demand (read+write) misses 275711570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 148893 # number of demand (read+write) misses 275811570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) misses 275911570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 879896 # number of demand (read+write) misses 276011570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1903 # number of overall misses 276111570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1980 # number of overall misses 276211570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 45534 # number of overall misses 276311570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 216633 # number of overall misses 276411570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 240877 # number of overall misses 276511570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1748 # number of overall misses 276611570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1646 # number of overall misses 276711570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 43900 # number of overall misses 276811570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 148893 # number of overall misses 276911570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 176782 # number of overall misses 277011570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 879896 # number of overall misses 277111570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 390440000 # number of UpgradeReq miss cycles 277211570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 373608000 # number of UpgradeReq miss cycles 277311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 764048000 # number of UpgradeReq miss cycles 277411570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 65654000 # number of SCUpgradeReq miss cycles 277511570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 76676500 # number of SCUpgradeReq miss cycles 277611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 142330500 # number of SCUpgradeReq miss cycles 277711570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7135565500 # number of ReadExReq miss cycles 277811570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4240679000 # number of ReadExReq miss cycles 277911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 11376244500 # number of ReadExReq miss cycles 278011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 166331500 # number of ReadSharedReq miss cycles 278111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 176995000 # number of ReadSharedReq miss cycles 278211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 3903055500 # number of ReadSharedReq miss cycles 278311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 11953058500 # number of ReadSharedReq miss cycles 278411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of ReadSharedReq miss cycles 278511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157717000 # number of ReadSharedReq miss cycles 278611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151093000 # number of ReadSharedReq miss cycles 278711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 3757434500 # number of ReadSharedReq miss cycles 278811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 9007178500 # number of ReadSharedReq miss cycles 278911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of ReadSharedReq miss cycles 279011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 79243121431 # number of ReadSharedReq miss cycles 279111570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 55722000 # number of InvalidateReq miss cycles 279211570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 43983500 # number of InvalidateReq miss cycles 279311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::total 99705500 # number of InvalidateReq miss cycles 279411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 166331500 # number of demand (read+write) miss cycles 279511570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 176995000 # number of demand (read+write) miss cycles 279611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 3903055500 # number of demand (read+write) miss cycles 279711570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 19088624000 # number of demand (read+write) miss cycles 279811570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of demand (read+write) miss cycles 279911570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 157717000 # number of demand (read+write) miss cycles 280011570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 151093000 # number of demand (read+write) miss cycles 280111570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 3757434500 # number of demand (read+write) miss cycles 280211570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 13247857500 # number of demand (read+write) miss cycles 280311570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of demand (read+write) miss cycles 280411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 90619365931 # number of demand (read+write) miss cycles 280511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 166331500 # number of overall miss cycles 280611570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 176995000 # number of overall miss cycles 280711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 3903055500 # number of overall miss cycles 280811570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 19088624000 # number of overall miss cycles 280911570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of overall miss cycles 281011570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 157717000 # number of overall miss cycles 281111570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 151093000 # number of overall miss cycles 281211570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 3757434500 # number of overall miss cycles 281311570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 13247857500 # number of overall miss cycles 281411570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of overall miss cycles 281511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 90619365931 # number of overall miss cycles 281611570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2605015 # number of WritebackDirty accesses(hits+misses) 281711570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2605015 # number of WritebackDirty accesses(hits+misses) 281811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 218772 # number of UpgradeReq accesses(hits+misses) 281911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 192183 # number of UpgradeReq accesses(hits+misses) 282011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 410955 # number of UpgradeReq accesses(hits+misses) 282111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 49153 # number of SCUpgradeReq accesses(hits+misses) 282211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 48712 # number of SCUpgradeReq accesses(hits+misses) 282311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 97865 # number of SCUpgradeReq accesses(hits+misses) 282411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 128293 # number of ReadExReq accesses(hits+misses) 282511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 108731 # number of ReadExReq accesses(hits+misses) 282611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 237024 # number of ReadExReq accesses(hits+misses) 282711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6735 # number of ReadSharedReq accesses(hits+misses) 282811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5654 # number of ReadSharedReq accesses(hits+misses) 282911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 453877 # number of ReadSharedReq accesses(hits+misses) 283011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 674981 # number of ReadSharedReq accesses(hits+misses) 283111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 522297 # number of ReadSharedReq accesses(hits+misses) 283211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7745 # number of ReadSharedReq accesses(hits+misses) 283311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7142 # number of ReadSharedReq accesses(hits+misses) 283411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 463801 # number of ReadSharedReq accesses(hits+misses) 283511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 628672 # number of ReadSharedReq accesses(hits+misses) 283611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 452053 # number of ReadSharedReq accesses(hits+misses) 283711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 3222957 # number of ReadSharedReq accesses(hits+misses) 283811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 563301 # number of InvalidateReq accesses(hits+misses) 283911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 240099 # number of InvalidateReq accesses(hits+misses) 284011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 803400 # number of InvalidateReq accesses(hits+misses) 284111570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 6735 # number of demand (read+write) accesses 284211570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses 284311570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 453877 # number of demand (read+write) accesses 284411570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 803274 # number of demand (read+write) accesses 284511570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 522297 # number of demand (read+write) accesses 284611570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 7745 # number of demand (read+write) accesses 284711570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7142 # number of demand (read+write) accesses 284811570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 463801 # number of demand (read+write) accesses 284911570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 737403 # number of demand (read+write) accesses 285011570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 452053 # number of demand (read+write) accesses 285111570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 3459981 # number of demand (read+write) accesses 285211570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 6735 # number of overall (read+write) accesses 285311570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses 285411570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 453877 # number of overall (read+write) accesses 285511570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 803274 # number of overall (read+write) accesses 285611570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 522297 # number of overall (read+write) accesses 285711570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 7745 # number of overall (read+write) accesses 285811570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7142 # number of overall (read+write) accesses 285911570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 463801 # number of overall (read+write) accesses 286011570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 737403 # number of overall (read+write) accesses 286111570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 452053 # number of overall (read+write) accesses 286211570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 3459981 # number of overall (read+write) accesses 286311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.281261 # miss rate for UpgradeReq accesses 286411570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.315767 # miss rate for UpgradeReq accesses 286511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.297398 # miss rate for UpgradeReq accesses 286611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.256383 # miss rate for SCUpgradeReq accesses 286711570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.267881 # miss rate for SCUpgradeReq accesses 286811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.262106 # miss rate for SCUpgradeReq accesses 286911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.636223 # miss rate for ReadExReq accesses 287011570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.466619 # miss rate for ReadExReq accesses 287111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.558420 # miss rate for ReadExReq accesses 287211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for ReadSharedReq accesses 287311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.350195 # miss rate for ReadSharedReq accesses 287411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100322 # miss rate for ReadSharedReq accesses 287511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200020 # miss rate for ReadSharedReq accesses 287611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for ReadSharedReq accesses 287711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for ReadSharedReq accesses 287811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230468 # miss rate for ReadSharedReq accesses 287911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.094653 # miss rate for ReadSharedReq accesses 288011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.156134 # miss rate for ReadSharedReq accesses 288111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for ReadSharedReq accesses 288211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.231941 # miss rate for ReadSharedReq accesses 288311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.791527 # miss rate for InvalidateReq accesses 288411570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.489286 # miss rate for InvalidateReq accesses 288511570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.701201 # miss rate for InvalidateReq accesses 288611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for demand accesses 288711570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.350195 # miss rate for demand accesses 288811570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.100322 # miss rate for demand accesses 288911570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.269688 # miss rate for demand accesses 289011570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for demand accesses 289111570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for demand accesses 289211570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.230468 # miss rate for demand accesses 289311570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.094653 # miss rate for demand accesses 289411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.201915 # miss rate for demand accesses 289511570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for demand accesses 289611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.254307 # miss rate for demand accesses 289711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for overall accesses 289811570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.350195 # miss rate for overall accesses 289911570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.100322 # miss rate for overall accesses 290011570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.269688 # miss rate for overall accesses 290111570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for overall accesses 290211570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for overall accesses 290311570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.230468 # miss rate for overall accesses 290411570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.094653 # miss rate for overall accesses 290511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.201915 # miss rate for overall accesses 290611570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for overall accesses 290711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.254307 # miss rate for overall accesses 290811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6345.316258 # average UpgradeReq miss latency 290911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6156.513142 # average UpgradeReq miss latency 291011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6251.568931 # average UpgradeReq miss latency 291111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5209.807967 # average SCUpgradeReq miss latency 291211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5876.044141 # average SCUpgradeReq miss latency 291311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 5548.731044 # average SCUpgradeReq miss latency 291411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 87421.014910 # average ReadExReq miss latency 291511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 83583.234784 # average ReadExReq miss latency 291611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 85949.912737 # average ReadExReq miss latency 291711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average ReadSharedReq miss latency 291811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89391.414141 # average ReadSharedReq miss latency 291911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85717.387008 # average ReadSharedReq miss latency 292011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88534.615954 # average ReadSharedReq miss latency 292111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average ReadSharedReq miss latency 292211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average ReadSharedReq miss latency 292311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 91794.046173 # average ReadSharedReq miss latency 292411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85590.763098 # average ReadSharedReq miss latency 292511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91762.976660 # average ReadSharedReq miss latency 292611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average ReadSharedReq miss latency 292711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 106005.617690 # average ReadSharedReq miss latency 292811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 124.974208 # average InvalidateReq miss latency 292911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 374.400947 # average InvalidateReq miss latency 293011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 176.988346 # average InvalidateReq miss latency 293111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency 293211570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency 293311570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency 293411570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency 293511570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency 293611570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency 293711570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency 293811570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency 293911570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency 294011570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency 294111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 102988.723589 # average overall miss latency 294211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency 294311570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency 294411570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency 294511570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency 294611570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency 294711570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency 294811570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency 294911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency 295011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency 295111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency 295211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 102988.723589 # average overall miss latency 295311570SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 494 # number of cycles access was blocked 295410515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 295511570SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 9 # number of cycles access was blocked 295610515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 295711570SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 54.888889 # average number of cycles each access was blocked 295810515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 295911570SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1068061 # number of writebacks 296011570SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1068061 # number of writebacks 296111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 54 # number of ReadSharedReq MSHR hits 296211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits 296311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 49 # number of ReadSharedReq MSHR hits 296411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 43 # number of ReadSharedReq MSHR hits 296511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 165 # number of ReadSharedReq MSHR hits 296611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 54 # number of demand (read+write) MSHR hits 296711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits 296811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 49 # number of demand (read+write) MSHR hits 296911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 43 # number of demand (read+write) MSHR hits 297011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 297111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 54 # number of overall MSHR hits 297211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits 297311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 49 # number of overall MSHR hits 297411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 43 # number of overall MSHR hits 297511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 165 # number of overall MSHR hits 297611570SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 48108 # number of CleanEvict MSHR misses 297711570SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 48108 # number of CleanEvict MSHR misses 297811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 61532 # number of UpgradeReq MSHR misses 297911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 60685 # number of UpgradeReq MSHR misses 298011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 122217 # number of UpgradeReq MSHR misses 298111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12602 # number of SCUpgradeReq MSHR misses 298211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 13049 # number of SCUpgradeReq MSHR misses 298311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 25651 # number of SCUpgradeReq MSHR misses 298411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 81623 # number of ReadExReq MSHR misses 298511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 50736 # number of ReadExReq MSHR misses 298611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 132359 # number of ReadExReq MSHR misses 298711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq MSHR misses 298811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1980 # number of ReadSharedReq MSHR misses 298911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45480 # number of ReadSharedReq MSHR misses 299011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 134991 # number of ReadSharedReq MSHR misses 299111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq MSHR misses 299211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq MSHR misses 299311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1646 # number of ReadSharedReq MSHR misses 299411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 43851 # number of ReadSharedReq MSHR misses 299511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 98114 # number of ReadSharedReq MSHR misses 299611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq MSHR misses 299711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 747372 # number of ReadSharedReq MSHR misses 299811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 445868 # number of InvalidateReq MSHR misses 299911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 117477 # number of InvalidateReq MSHR misses 300011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 563345 # number of InvalidateReq MSHR misses 300111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1903 # number of demand (read+write) MSHR misses 300211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1980 # number of demand (read+write) MSHR misses 300311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 45480 # number of demand (read+write) MSHR misses 300411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 216614 # number of demand (read+write) MSHR misses 300511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) MSHR misses 300611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1748 # number of demand (read+write) MSHR misses 300711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1646 # number of demand (read+write) MSHR misses 300811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 43851 # number of demand (read+write) MSHR misses 300911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 148850 # number of demand (read+write) MSHR misses 301011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) MSHR misses 301111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 879731 # number of demand (read+write) MSHR misses 301211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1903 # number of overall MSHR misses 301311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1980 # number of overall MSHR misses 301411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 45480 # number of overall MSHR misses 301511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 216614 # number of overall MSHR misses 301611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of overall MSHR misses 301711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1748 # number of overall MSHR misses 301811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1646 # number of overall MSHR misses 301911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 43851 # number of overall MSHR misses 302011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 148850 # number of overall MSHR misses 302111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of overall MSHR misses 302211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 879731 # number of overall MSHR misses 302310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 302411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable 302510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 302611570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 11019 # number of ReadReq MSHR uncacheable 302711570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81829 # number of ReadReq MSHR uncacheable 302811570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable 302911570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable 303011570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38464 # number of WriteReq MSHR uncacheable 303110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 303211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses 303310827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 303411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 22943 # number of overall MSHR uncacheable misses 303511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 120293 # number of overall MSHR uncacheable misses 303611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1338948000 # number of UpgradeReq MSHR miss cycles 303711570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1324584000 # number of UpgradeReq MSHR miss cycles 303811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 2663532000 # number of UpgradeReq MSHR miss cycles 303911570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 312012000 # number of SCUpgradeReq MSHR miss cycles 304011570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 323877000 # number of SCUpgradeReq MSHR miss cycles 304111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 635889000 # number of SCUpgradeReq MSHR miss cycles 304211570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6319298576 # number of ReadExReq MSHR miss cycles 304311570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3733266108 # number of ReadExReq MSHR miss cycles 304411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 10052564684 # number of ReadExReq MSHR miss cycles 304511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of ReadSharedReq MSHR miss cycles 304611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 157194002 # number of ReadSharedReq MSHR miss cycles 304711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3443824526 # number of ReadSharedReq MSHR miss cycles 304811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10601706692 # number of ReadSharedReq MSHR miss cycles 304911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of ReadSharedReq MSHR miss cycles 305011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of ReadSharedReq MSHR miss cycles 305111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 134631004 # number of ReadSharedReq MSHR miss cycles 305211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3315499572 # number of ReadSharedReq MSHR miss cycles 305311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8022481292 # number of ReadSharedReq MSHR miss cycles 305411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of ReadSharedReq MSHR miss cycles 305511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 71756096476 # number of ReadSharedReq MSHR miss cycles 305611570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8904054000 # number of InvalidateReq MSHR miss cycles 305711570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2392104000 # number of InvalidateReq MSHR miss cycles 305811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 11296158000 # number of InvalidateReq MSHR miss cycles 305911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of demand (read+write) MSHR miss cycles 306011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 157194002 # number of demand (read+write) MSHR miss cycles 306111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 3443824526 # number of demand (read+write) MSHR miss cycles 306211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 16921005268 # number of demand (read+write) MSHR miss cycles 306311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of demand (read+write) MSHR miss cycles 306411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of demand (read+write) MSHR miss cycles 306511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 134631004 # number of demand (read+write) MSHR miss cycles 306611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 3315499572 # number of demand (read+write) MSHR miss cycles 306711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 11755747400 # number of demand (read+write) MSHR miss cycles 306811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of demand (read+write) MSHR miss cycles 306911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 81808661160 # number of demand (read+write) MSHR miss cycles 307011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of overall MSHR miss cycles 307111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 157194002 # number of overall MSHR miss cycles 307211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 3443824526 # number of overall MSHR miss cycles 307311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 16921005268 # number of overall MSHR miss cycles 307411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of overall MSHR miss cycles 307511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of overall MSHR miss cycles 307611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 134631004 # number of overall MSHR miss cycles 307711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 3315499572 # number of overall MSHR miss cycles 307811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 11755747400 # number of overall MSHR miss cycles 307911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of overall MSHR miss cycles 308011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 81808661160 # number of overall MSHR miss cycles 308111502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles 308211570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4354335503 # number of ReadReq MSHR uncacheable cycles 308311570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7420500 # number of ReadReq MSHR uncacheable cycles 308411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1601314002 # number of ReadReq MSHR uncacheable cycles 308511570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8682852005 # number of ReadReq MSHR uncacheable cycles 308611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles 308711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 4354335503 # number of overall MSHR uncacheable cycles 308811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7420500 # number of overall MSHR uncacheable cycles 308911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 1601314002 # number of overall MSHR uncacheable cycles 309011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 8682852005 # number of overall MSHR uncacheable cycles 309110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 309210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 309311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.281261 # mshr miss rate for UpgradeReq accesses 309411570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315767 # mshr miss rate for UpgradeReq accesses 309511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.297398 # mshr miss rate for UpgradeReq accesses 309611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.256383 # mshr miss rate for SCUpgradeReq accesses 309711570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.267881 # mshr miss rate for SCUpgradeReq accesses 309811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.262106 # mshr miss rate for SCUpgradeReq accesses 309911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.636223 # mshr miss rate for ReadExReq accesses 310011570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466619 # mshr miss rate for ReadExReq accesses 310111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.558420 # mshr miss rate for ReadExReq accesses 310211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for ReadSharedReq accesses 310311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for ReadSharedReq accesses 310411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for ReadSharedReq accesses 310511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199992 # mshr miss rate for ReadSharedReq accesses 310611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for ReadSharedReq accesses 310711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for ReadSharedReq accesses 310811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for ReadSharedReq accesses 310911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for ReadSharedReq accesses 311011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.156065 # mshr miss rate for ReadSharedReq accesses 311111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for ReadSharedReq accesses 311211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.231890 # mshr miss rate for ReadSharedReq accesses 311311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.791527 # mshr miss rate for InvalidateReq accesses 311411570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489286 # mshr miss rate for InvalidateReq accesses 311511570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.701201 # mshr miss rate for InvalidateReq accesses 311611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for demand accesses 311711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for demand accesses 311811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for demand accesses 311911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for demand accesses 312011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for demand accesses 312111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for demand accesses 312211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for demand accesses 312311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for demand accesses 312411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for demand accesses 312511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for demand accesses 312611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.254259 # mshr miss rate for demand accesses 312711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for overall accesses 312811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for overall accesses 312911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for overall accesses 313011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for overall accesses 313111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for overall accesses 313211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for overall accesses 313311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for overall accesses 313411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for overall accesses 313511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for overall accesses 313611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for overall accesses 313711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.254259 # mshr miss rate for overall accesses 313811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820 # average UpgradeReq mshr miss latency 313911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064 # average UpgradeReq mshr miss latency 314011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721 # average UpgradeReq mshr miss latency 314111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154 # average SCUpgradeReq mshr miss latency 314211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840 # average SCUpgradeReq mshr miss latency 314311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679 # average SCUpgradeReq mshr miss latency 314411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538 # average ReadExReq mshr miss latency 314511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289 # average ReadExReq mshr miss latency 314611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159 # average ReadExReq mshr miss latency 314711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average ReadSharedReq mshr miss latency 314811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average ReadSharedReq mshr miss latency 314911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average ReadSharedReq mshr miss latency 315011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441 # average ReadSharedReq mshr miss latency 315111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average ReadSharedReq mshr miss latency 315211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average ReadSharedReq mshr miss latency 315311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average ReadSharedReq mshr miss latency 315411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average ReadSharedReq mshr miss latency 315511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359 # average ReadSharedReq mshr miss latency 315611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average ReadSharedReq mshr miss latency 315711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611 # average ReadSharedReq mshr miss latency 315811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087 # average InvalidateReq mshr miss latency 315911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730 # average InvalidateReq mshr miss latency 316011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203 # average InvalidateReq mshr miss latency 316111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency 316211570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency 316311570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency 316411570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency 316511570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency 316611570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency 316711570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency 316811570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency 316911570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency 317011570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency 317111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency 317211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency 317311570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency 317411570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency 317511570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency 317611570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency 317711570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency 317811570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency 317911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency 318011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency 318111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency 318211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency 318311502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency 318411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency 318511570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency 318611570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency 318711570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency 318811502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency 318911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency 319011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency 319111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency 319211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency 319311570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter. 319411570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data. 319511570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 319611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 319711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 319811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 319911570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 320011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 81829 # Transaction distribution 320111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 838129 # Transaction distribution 320211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38464 # Transaction distribution 320311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38464 # Transaction distribution 320411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution 320511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 216961 # Transaction distribution 320611570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 398327 # Transaction distribution 320711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution 320811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 22 # Transaction distribution 320911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 321011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 145872 # Transaction distribution 321111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 127949 # Transaction distribution 321211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution 321311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 666856 # Transaction distribution 321411570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) 321510535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 321611570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes) 321711570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes) 321811570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes) 321911570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes) 322011570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes) 322111570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes) 322211570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) 322310535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 322411570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes) 322511570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes) 322611570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes) 322711570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) 322811570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) 322911570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes) 323011570SCurtis.Dunham@arm.comsystem.membus.snoops 572885 # Total snoops (count) 323111570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 188480 # Total snoop traffic (bytes) 323211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2396814 # Request fanout histogram 323311570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.013654 # Request fanout histogram 323411570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram 323510535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 323611570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram 323711570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram 323810535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 323910535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 324011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 324110535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 324211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2396814 # Request fanout histogram 324311570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks) 324410535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 324511138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 324610535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 324711570SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks) 324810535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324911570SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks) 325010535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 325111570SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks) 325210535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 325311570SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks) 325410535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 325511570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 325611570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 325711570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 325811570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 325911570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 326011570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 326111570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 326211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 326311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 326411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 326511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 326611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 326711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 326811570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 326911570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 327010515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 327110515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 327210515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 327310515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 327410515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 327510515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 327610515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 327710515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 327810515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 327911374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 328010515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 328110515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 328210515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 328311374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 328410515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 328510515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 328610515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 328710515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 328810515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 328910515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 329010515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 329110515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 329210515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 329310515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 329410515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 329510515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 329610515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 329710515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 329810515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 329910515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 330010515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 330110515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 330210515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 330310515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 330410515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 330510515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 330610515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 330710515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 330810515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 330910515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 331010515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 331110515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 331211570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331311570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331411570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331511570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331611570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331711570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331811570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 331911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 332011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 332111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 332211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 332311570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332411570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332511570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332611570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332711570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332811570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 332911570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333011570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333111570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333211570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333311570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333411570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 333511570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter. 333611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data. 333711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 333811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter. 333911570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 334011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 334111570SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states 334211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution 334311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution 334411570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution 334511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution 334611570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution 334711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution 334811570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution 334911570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution 335011570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution 335111570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution 335211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution 335311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution 335411570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution 335511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution 335611570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution 335711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution 335811570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes) 335911570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes) 336011570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes) 336111570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes) 336211570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes) 336311570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes) 336411570SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 2716758 # Total snoops (count) 336511570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes) 336611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram 336711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram 336811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram 336910515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 337011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram 337111570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram 337211570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram 337310515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 337411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 337510515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 337611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram 337711570SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks) 337810515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 337911570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks) 338010515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 338111570SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks) 338210515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 338311570SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks) 338410515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 338510515SN/A 338610515SN/A---------- End Simulation Statistics ---------- 3387