xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.522770                       # Number of seconds simulated
sim_ticks                                47522770414500                       # Number of ticks simulated
final_tick                               47522770414500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 771698                       # Simulator instruction rate (inst/s)
host_op_rate                                   907739                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            41601502224                       # Simulator tick rate (ticks/s)
host_mem_usage                                 746908                       # Number of bytes of host memory used
host_seconds                                  1142.33                       # Real time elapsed on the host
sim_insts                                   881535802                       # Number of instructions simulated
sim_ops                                    1036940641                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        93760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        96448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3323828                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13811400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     14713664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       137344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       135424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2499960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9313680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     12080896                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        425472                       # Number of bytes read from this memory
system.physmem.bytes_read::total             56631876                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3323828                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2499960                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5823788                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75221696                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75242280                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1465                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1507                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             92342                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            215816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       229901                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2146                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2116                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             39150                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            145539                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       188764                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6648                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                925394                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1175339                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1177913                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2030                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               69942                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              290627                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       309613                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2890                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2850                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52606                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              195984                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       254213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8953                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1191679                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          69942                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52606                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             122547                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1582856                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1583289                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1582856                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2030                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              69942                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             291060                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       309613                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2890                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2850                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52606                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             195984                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       254213                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8953                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2774968                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        925394                       # Number of read requests accepted
system.physmem.writeReqs                      1177913                       # Number of write requests accepted
system.physmem.readBursts                      925394                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1177913                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59200512                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     24704                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  75241664                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  56631876                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               75242280                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      386                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               52385                       # Per bank write bursts
system.physmem.perBankRdBursts::1               62471                       # Per bank write bursts
system.physmem.perBankRdBursts::2               52469                       # Per bank write bursts
system.physmem.perBankRdBursts::3               57006                       # Per bank write bursts
system.physmem.perBankRdBursts::4               52192                       # Per bank write bursts
system.physmem.perBankRdBursts::5               61065                       # Per bank write bursts
system.physmem.perBankRdBursts::6               52770                       # Per bank write bursts
system.physmem.perBankRdBursts::7               53841                       # Per bank write bursts
system.physmem.perBankRdBursts::8               49119                       # Per bank write bursts
system.physmem.perBankRdBursts::9               95933                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50791                       # Per bank write bursts
system.physmem.perBankRdBursts::11              57135                       # Per bank write bursts
system.physmem.perBankRdBursts::12              57588                       # Per bank write bursts
system.physmem.perBankRdBursts::13              62036                       # Per bank write bursts
system.physmem.perBankRdBursts::14              54549                       # Per bank write bursts
system.physmem.perBankRdBursts::15              53658                       # Per bank write bursts
system.physmem.perBankWrBursts::0               70290                       # Per bank write bursts
system.physmem.perBankWrBursts::1               77699                       # Per bank write bursts
system.physmem.perBankWrBursts::2               70837                       # Per bank write bursts
system.physmem.perBankWrBursts::3               75524                       # Per bank write bursts
system.physmem.perBankWrBursts::4               70767                       # Per bank write bursts
system.physmem.perBankWrBursts::5               75365                       # Per bank write bursts
system.physmem.perBankWrBursts::6               70544                       # Per bank write bursts
system.physmem.perBankWrBursts::7               72537                       # Per bank write bursts
system.physmem.perBankWrBursts::8               71114                       # Per bank write bursts
system.physmem.perBankWrBursts::9               74364                       # Per bank write bursts
system.physmem.perBankWrBursts::10              70757                       # Per bank write bursts
system.physmem.perBankWrBursts::11              75591                       # Per bank write bursts
system.physmem.perBankWrBursts::12              74466                       # Per bank write bursts
system.physmem.perBankWrBursts::13              78806                       # Per bank write bursts
system.physmem.perBankWrBursts::14              73579                       # Per bank write bursts
system.physmem.perBankWrBursts::15              73411                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
system.physmem.totGap                    47522767065000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  882169                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1175339                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    655692                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     79783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     38713                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     33532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     28749                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     25275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     22122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     17971                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15915                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2679                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1375                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      894                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      696                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      480                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      203                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       82                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    31337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    50193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    64392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    67139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    68853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    71615                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    75238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    77530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    73364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    73677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    78266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    71127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    65923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    63783                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      960                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      126                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       971842                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      138.337154                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      95.235739                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     185.809364                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         667325     68.67%     68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       188611     19.41%     88.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        42123      4.33%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        19056      1.96%     94.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13469      1.39%     95.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         8562      0.88%     96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6056      0.62%     97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5131      0.53%     97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21509      2.21%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         971842                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         61007                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.162244                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      130.580515                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          61004    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           61007                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         61007                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.270756                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.528593                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.773323                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49057     80.41%     80.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            4844      7.94%     88.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            2913      4.77%     93.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1752      2.87%     96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             961      1.58%     97.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             299      0.49%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             177      0.29%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             148      0.24%     98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              74      0.12%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              52      0.09%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              27      0.04%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              55      0.09%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             405      0.66%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              51      0.08%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              50      0.08%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              40      0.07%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              25      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               4      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             8      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             7      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             8      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           61007                       # Writes before turning the bus around for reads
system.physmem.totQLat                    29196891613                       # Total ticks spent queuing
system.physmem.totMemAccLat               46540791613                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4625040000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       31563.93                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  50313.93                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.93                       # Average write queue length when enqueuing
system.physmem.readRowHits                     690198                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    438618                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.31                       # Row buffer hit rate for writes
system.physmem.avgGap                     22594308.42                       # Average gap between requests
system.physmem.pageHitRate                      53.74                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3631876920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1981678875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3464752200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3781488240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3103956292320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1186873055955                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27472545160500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31776234305010                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.652826                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45702691627494                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1586889720000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    233188460006                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3715248600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2027169375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3750271200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3836730240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3103956292320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1194406095015                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27465937231500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31777629038250                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.682174                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45691606890492                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1586889720000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    244273354008                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   111522                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               111522                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12043                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84023                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           24                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       111498                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.224219                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    74.869765                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       111497    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       111498                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        96090                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        91679     95.41%     95.41% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3478      3.62%     99.03% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303          141      0.15%     99.18% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071          658      0.68%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839           17      0.02%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607           14      0.01%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375           32      0.03%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143           16      0.02%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911           20      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        96090                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   2194735056                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.089935                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -197382796     -8.99%     -8.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     2392117852    108.99%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   2194735056                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        84024     87.46%     87.46% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        12043     12.54%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        96067                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       111522                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       111522                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        96067                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        96067                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       207589                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    86856517                       # DTB read hits
system.cpu0.dtb.read_misses                     84644                       # DTB read misses
system.cpu0.dtb.write_hits                   78666499                       # DTB write hits
system.cpu0.dtb.write_misses                    26878                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41069                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   37476                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4693                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9143                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                86941161                       # DTB read accesses
system.cpu0.dtb.write_accesses               78693377                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        165523016                       # DTB hits
system.cpu0.dtb.misses                         111522                       # DTB misses
system.cpu0.dtb.accesses                    165634538                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    57441                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                57441                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          633                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51280                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        57441                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          57441    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        57441                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        51913                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        50947     98.14%     98.14% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          829      1.60%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           33      0.06%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           47      0.09%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           45      0.09%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        51913                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -282313796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -282313796    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -282313796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        51280     98.78%     98.78% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          633      1.22%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        51913                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57441                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57441                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        51913                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        51913                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       109354                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   461199865                       # ITB inst hits
system.cpu0.itb.inst_misses                     57441                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41069                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26626                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               461257306                       # ITB inst accesses
system.cpu0.itb.hits                        461199865                       # DTB hits
system.cpu0.itb.misses                          57441                       # DTB misses
system.cpu0.itb.accesses                    461257306                       # DTB accesses
system.cpu0.numCycles                     95045540829                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13927                       # number of quiesce instructions executed
system.cpu0.committedInsts                  460929213                       # Number of instructions committed
system.cpu0.committedOps                    541179982                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            497492129                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                434558                       # Number of float alu accesses
system.cpu0.num_func_calls                   27781850                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     69589132                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   497492129                       # number of integer instructions
system.cpu0.num_fp_insts                       434558                       # number of float instructions
system.cpu0.num_int_register_reads          719293830                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         394367415                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              718787                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             331792                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           119457726                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          119087316                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    165514046                       # number of memory refs
system.cpu0.num_load_insts                   86852092                       # Number of load instructions
system.cpu0.num_store_insts                  78661954                       # Number of store instructions
system.cpu0.num_idle_cycles              93905101360.384018                       # Number of idle cycles
system.cpu0.num_busy_cycles              1140439468.615976                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011999                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988001                       # Percentage of idle cycles
system.cpu0.Branches                        102755128                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                374676211     69.19%     69.19% # Class of executed instruction
system.cpu0.op_class::IntMult                 1194745      0.22%     69.41% # Class of executed instruction
system.cpu0.op_class::IntDiv                    63344      0.01%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             45411      0.01%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::MemRead                86852092     16.04%     85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite               78661954     14.53%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 541493758                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          5689621                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          508.423656                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          159582136                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5690133                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.045414                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       4031081000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.423656                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993015                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.993015                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        336711039                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       336711039                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80892970                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80892970                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     74279623                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      74279623                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199389                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       199389                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       162229                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       162229                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1824290                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1824290                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1791894                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1791894                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    155334822                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       155334822                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    155534211                       # number of overall hits
system.cpu0.dcache.overall_hits::total      155534211                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3104051                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3104051                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1401631                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1401631                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       634089                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       634089                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       792659                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       792659                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       174131                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       174131                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       205146                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       205146                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5298341                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5298341                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5932430                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5932430                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46355544000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  46355544000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29179707500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  29179707500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25804948000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25804948000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2634324500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2634324500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5093103500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5093103500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3129500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3129500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 101340199500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 101340199500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83997021                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83997021                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     75681254                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     75681254                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       833478                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       833478                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       954888                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       954888                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1998421                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1998421                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1997040                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1997040                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    160633163                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    160633163                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    161466641                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    161466641                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036954                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036954                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018520                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018520                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.760775                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760775                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.830107                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.830107                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.087134                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.087134                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.102725                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.102725                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032984                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.032984                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036741                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.036741                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5689621                       # number of writebacks
system.cpu0.dcache.writebacks::total          5689621                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25484                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25484                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21272                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21272                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45280                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45280                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        46756                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        46756                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        46756                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        46756                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3078567                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3078567                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1380359                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1380359                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       632927                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       632927                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792659                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       792659                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128851                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128851                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       205146                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       205146                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5251585                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5251585                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5884512                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5884512                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        27617                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        27617                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26565                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26565                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        54182                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        54182                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42188847000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42188847000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27459987000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27459987000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13648405000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13648405000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25012289000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  25012289000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1718421000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1718421000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4888014500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4888014500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3072500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3072500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  94661123000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  94661123000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5072174500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5072174500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5072174500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5072174500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036651                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036651                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018239                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018239                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759381                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759381                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.830107                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.830107                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064476                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064476                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.102725                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.102725                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032693                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.032693                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036444                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.036444                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          5142905                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.908178                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          456056448                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5143417                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.667990                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      29905343000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.908178                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999821                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999821                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          134                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        927543147                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       927543147                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    456056448                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      456056448                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    456056448                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       456056448                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    456056448                       # number of overall hits
system.cpu0.icache.overall_hits::total      456056448                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5143417                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5143417                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5143417                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5143417                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5143417                       # number of overall misses
system.cpu0.icache.overall_misses::total      5143417                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  54463305000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  54463305000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  54463305000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  54463305000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  54463305000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  54463305000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    461199865                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    461199865                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    461199865                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    461199865                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    461199865                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    461199865                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011152                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011152                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011152                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011152                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011152                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011152                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10588.934360                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10588.934360                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      5142905                       # number of writebacks
system.cpu0.icache.writebacks::total          5142905                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5143417                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5143417                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5143417                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5143417                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5143417                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5143417                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  51891596500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  51891596500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  51891596500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  51891596500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  51891596500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  51891596500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3819470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3819470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011152                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011152                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011152                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011152                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011152                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011152                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10088.934360                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10088.934360                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7619798                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7619814                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1013066                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2348165                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16134.688776                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          15333996                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2364235                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.485817                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5100393500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.858641                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.489283                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   784.884937                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.928250                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003776                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004852                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.047906                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.984783                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1310                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           52                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14708                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          179                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          589                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          529                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           22                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           19                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          970                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4517                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5300                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3841                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.079956                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003174                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.897705                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       367708056                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      367708056                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       263860                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       148030                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        411890                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3764500                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3764500                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7067152                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7067152                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          393                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          393                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       904509                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       904509                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4682717                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4682717                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2902504                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2902504                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       213097                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       213097                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       263860                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       148030                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4682717                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3807013                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8901620                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       263860                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       148030                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4682717                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3807013                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8901620                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9421                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7390                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        16811                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       243749                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       243749                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       205138                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       205138                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       251209                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       251209                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       460700                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       460700                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       937841                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       937841                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       577609                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       577609                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         9421                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7390                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       460700                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1189050                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1666561                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9421                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7390                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       460700                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1189050                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1666561                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    332469500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    285177500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    617647000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   1968962500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   1968962500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1588151500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1588151500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2987000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2987000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12588187000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  12588187000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  16045103500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  16045103500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  32885800500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  32885800500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    322469500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    322469500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    332469500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    285177500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  16045103500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  45473987500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  62136738000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    332469500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    285177500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  16045103500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  45473987500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  62136738000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       273281                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155420                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       428701                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3764500                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3764500                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7067152                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7067152                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       244142                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       244142                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       205138                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       205138                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1155718                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1155718                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5143417                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5143417                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3840345                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3840345                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790706                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       790706                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       273281                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155420                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5143417                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4996063                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10568181                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       273281                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155420                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5143417                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4996063                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10568181                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.034474                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.047549                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.039214                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998390                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998390                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.217362                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.217362                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.089571                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.089571                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.244207                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.244207                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.730498                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.730498                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.034474                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.047549                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.089571                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.237997                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.157696                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.034474                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.047549                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.089571                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.237997                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.157696                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35290.255811                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38589.648173                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36740.646006                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  8077.828012                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  8077.828012                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  7741.868888                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  7741.868888                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       373375                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       373375                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50110.414038                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50110.414038                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34827.661168                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34827.661168                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35065.432733                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35065.432733                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   558.283372                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   558.283372                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35290.255811                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38589.648173                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34827.661168                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38243.965771                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 37284.406631                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35290.255811                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38589.648173                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34827.661168                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38243.965771                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 37284.406631                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           37568                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1506522                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1506522                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5548                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5548                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          408                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          408                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5956                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5956                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5956                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5956                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         9421                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7390                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        16811                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       719381                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       719381                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       243749                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       243749                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       205138                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       205138                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       245661                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       245661                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       460700                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       460700                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       937433                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       937433                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       577609                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       577609                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         9421                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7390                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       460700                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1183094                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1660605                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         9421                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7390                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       460700                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1183094                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       719381                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2379986                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        27617                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        70742                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26565                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26565                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        54182                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        97307                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    275943500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    240837500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    516781000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  32427966574                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  32427966574                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5063458500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5063458500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3348331499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3348331499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2645000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2645000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10596762500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10596762500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  13280903500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  13280903500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27229516500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27229516500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18926305000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18926305000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    275943500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    240837500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  13280903500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  37826279000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  51623963500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    275943500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    240837500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  13280903500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37826279000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  32427966574                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  84051930074                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4850886500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8346919000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4850886500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8346919000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.034474                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.047549                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.039214                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998390                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998390                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.212561                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.212561                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.089571                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.089571                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.244101                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.244101                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.730498                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.730498                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.034474                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.047549                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.089571                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.236805                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157133                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.034474                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.047549                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.089571                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.236805                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.225203                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       330625                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       330625                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     22441141                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11511110                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          870                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1820685                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1820422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          263                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        564136                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9642625                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        26565                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26565                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5274768                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7068022                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2298392                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       883953                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       441648                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       374962                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       517397                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           66                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1188175                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1165072                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5143417                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4741538                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       839102                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       790706                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15515989                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18442402                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       326965                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       595128                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         34880484                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    658497108                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    690726071                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1243360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2186248                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1352652787                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6279047                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     18012222                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.113865                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.317693                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          15961520     88.61%     88.61% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2050439     11.38%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               263      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      18012222                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   22247152499                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    190413774                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7758250500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8155256101                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    171545000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    321847000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   105013                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               105013                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10670                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        79078                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       105006                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.076186                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    24.687831                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511       105005    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       105006                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        89755                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        88364     98.45%     98.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1205      1.34%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           34      0.04%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           69      0.08%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           59      0.07%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        89755                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -3159480544                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.804201                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.396815                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -618623648     19.58%     19.58% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -2540856896     80.42%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -3159480544                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        79078     88.11%     88.11% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10670     11.89%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        89748                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       105013                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       105013                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        89748                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        89748                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       194761                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    79229823                       # DTB read hits
system.cpu1.dtb.read_misses                     76992                       # DTB read misses
system.cpu1.dtb.write_hits                   72255246                       # DTB write hits
system.cpu1.dtb.write_misses                    28021                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41069                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   37178                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4820                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10425                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                79306815                       # DTB read accesses
system.cpu1.dtb.write_accesses               72283267                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        151485069                       # DTB hits
system.cpu1.dtb.misses                         105013                       # DTB misses
system.cpu1.dtb.accesses                    151590082                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    58945                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                58945                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          561                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        53052                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        58945                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          58945    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        58945                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        53613                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        48130     89.77%     89.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         4065      7.58%     97.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303           53      0.10%     97.45% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071         1140      2.13%     99.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           30      0.06%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           18      0.03%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           57      0.11%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           51      0.10%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679           22      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447           16      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        53613                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1503172148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1503172148    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1503172148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        53052     98.95%     98.95% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          561      1.05%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        53613                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        58945                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        58945                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53613                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53613                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       112558                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   420888418                       # ITB inst hits
system.cpu1.itb.inst_misses                     58945                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41069                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25875                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               420947363                       # ITB inst accesses
system.cpu1.itb.hits                        420888418                       # DTB hits
system.cpu1.itb.misses                          58945                       # DTB misses
system.cpu1.itb.accesses                    420947363                       # DTB accesses
system.cpu1.numCycles                     95045540824                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4988                       # number of quiesce instructions executed
system.cpu1.committedInsts                  420606589                       # Number of instructions committed
system.cpu1.committedOps                    495760659                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            455422102                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                465343                       # Number of float alu accesses
system.cpu1.num_func_calls                   25050170                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     64233743                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   455422102                       # number of integer instructions
system.cpu1.num_fp_insts                       465343                       # number of float instructions
system.cpu1.num_int_register_reads          665130045                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         361560137                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              742394                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             410584                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           110025684                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          109785328                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    151477231                       # number of memory refs
system.cpu1.num_load_insts                   79227868                       # Number of load instructions
system.cpu1.num_store_insts                  72249363                       # Number of store instructions
system.cpu1.num_idle_cycles              94048242615.068481                       # Number of idle cycles
system.cpu1.num_busy_cycles              997298208.931515                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010493                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989507                       # Percentage of idle cycles
system.cpu1.Branches                         93889993                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                343412693     69.23%     69.23% # Class of executed instruction
system.cpu1.op_class::IntMult                 1029907      0.21%     69.44% # Class of executed instruction
system.cpu1.op_class::IntDiv                    56328      0.01%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             66396      0.01%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::MemRead                79227868     15.97%     85.43% # Class of executed instruction
system.cpu1.op_class::MemWrite               72249363     14.57%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 496042597                       # Class of executed instruction
system.cpu1.dcache.tags.replacements          5018466                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          434.493139                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          146277741                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5018977                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.144932                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8378732349000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   434.493139                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.848619                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.848619                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        308017993                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       308017993                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     73753622                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       73753622                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     68485479                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      68485479                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       174561                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       174561                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       162110                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       162110                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1665176                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1665176                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1621987                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1621987                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    142401211                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       142401211                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    142575772                       # number of overall hits
system.cpu1.dcache.overall_hits::total      142575772                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2838030                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2838030                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1310627                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1310627                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       624714                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       624714                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       447850                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       447850                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       162703                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       162703                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       204676                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       204676                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4596507                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4596507                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5221221                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5221221                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  40862074000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  40862074000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  24688918000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  24688918000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10778682000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  10778682000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2442456000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2442456000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5069864000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5069864000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3108000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3108000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  76329674000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  76329674000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  76329674000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  76329674000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     76591652                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     76591652                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69796106                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69796106                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       799275                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       799275                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       609960                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       609960                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1827879                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1827879                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1826663                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1826663                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    146997718                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    146997718                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    147796993                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    147796993                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037054                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037054                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018778                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018778                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.781601                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.781601                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.734228                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.734228                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.089012                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.089012                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112049                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112049                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031269                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031269                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035327                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035327                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5018466                       # number of writebacks
system.cpu1.dcache.writebacks::total          5018466                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16365                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        16365                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          405                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          405                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        42163                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        42163                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        16770                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        16770                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        16770                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        16770                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2821665                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2821665                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1310222                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1310222                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       624714                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       624714                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       447850                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       447850                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120540                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120540                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       204676                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       204676                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4579737                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4579737                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5204451                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5204451                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        11035                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        11035                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11949                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11949                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        22984                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        22984                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  37160053500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  37160053500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23356658000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23356658000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12967475000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12967475000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10330832000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10330832000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1654542500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1654542500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4865246000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4865246000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3050000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3050000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  70847543500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  70847543500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  83815018500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  83815018500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1894238000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1894238000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1894238000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1894238000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036840                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036840                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018772                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018772                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.781601                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.781601                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.734228                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.734228                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065945                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065945                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112049                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112049                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031155                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031155                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035214                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035214                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements          4797887                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.259979                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          416090013                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4798399                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            86.714342                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8378704245000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.259979                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969258                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969258                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          277                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          180                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        846575240                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       846575240                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    416090013                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      416090013                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    416090013                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       416090013                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    416090013                       # number of overall hits
system.cpu1.icache.overall_hits::total      416090013                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4798405                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4798405                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4798405                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4798405                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4798405                       # number of overall misses
system.cpu1.icache.overall_misses::total      4798405                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  50998473000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  50998473000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  50998473000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  50998473000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  50998473000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  50998473000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    420888418                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    420888418                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    420888418                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    420888418                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    420888418                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    420888418                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011401                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011401                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011401                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011401                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011401                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011401                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10628.213542                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10628.213542                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10628.213542                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10628.213542                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10628.213542                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      4797887                       # number of writebacks
system.cpu1.icache.writebacks::total          4797887                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4798405                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4798405                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4798405                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4798405                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4798405                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4798405                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  48599271000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  48599271000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  48599271000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  48599271000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  48599271000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  48599271000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10226500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10226500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10226500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10226500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011401                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011401                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011401                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6995617                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6995617                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       854583                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         1970256                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13301.448664                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          14231615                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         1985806                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.166669                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10058718427000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    44.190300                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    64.411311                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   905.409563                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.749966                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002697                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003931                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055262                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.811856                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1582                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13889                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          228                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          690                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          664                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2519                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5802                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5375                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.096558                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.847717                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       333785497                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      333785497                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       241732                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       150683                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        392415                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3174179                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3174179                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6641283                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6641283                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          549                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          549                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       848093                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       848093                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4339488                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4339488                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2669176                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2669176                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       193952                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       193952                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       241732                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       150683                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4339488                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3517269                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8249172                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       241732                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       150683                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4339488                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3517269                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8249172                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10752                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9335                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        20087                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       209731                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       209731                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       204666                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       204666                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           10                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       253892                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       253892                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       458917                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       458917                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       897743                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       897743                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252003                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       252003                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10752                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9335                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       458917                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1151635                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1630639                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10752                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9335                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       458917                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1151635                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1630639                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    421263500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    385353500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    806617000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   1909199500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   1909199500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1509536500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1509536500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2962499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2962499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10235182000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10235182000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  15333921500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  15333921500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29041295500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29041295500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    413814500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    413814500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    421263500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    385353500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  15333921500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  39276477500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  55417016000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    421263500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    385353500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  15333921500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  39276477500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  55417016000                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       252484                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       160018                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       412502                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3174179                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3174179                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6641283                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6641283                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       210280                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       210280                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       204666                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       204666                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1101985                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1101985                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4798405                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4798405                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3566919                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3566919                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       445955                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       445955                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       252484                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       160018                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4798405                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4668904                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      9879811                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       252484                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       160018                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4798405                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4668904                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      9879811                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.042585                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.048696                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997389                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997389                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.230395                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.230395                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.095639                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.095639                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.251686                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.251686                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.565086                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.565086                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.042585                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.095639                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246661                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.165048                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.042585                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.095639                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246661                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.165048                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39180.013021                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41280.503482                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 40156.170658                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  9103.086811                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  9103.086811                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  7375.609530                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  7375.609530                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 296249.900000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 296249.900000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40313.133143                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40313.133143                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33413.278436                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33413.278436                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32349.230793                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32349.230793                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1642.101483                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1642.101483                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39180.013021                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41280.503482                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33413.278436                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34104.970325                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 33984.846431                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39180.013021                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41280.503482                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33413.278436                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34104.970325                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 33984.846431                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           39843                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1100180                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1100180                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4729                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         4729                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          266                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          266                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4995                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4995                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4995                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4995                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10752                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9335                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        20087                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       687556                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       687556                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       209731                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       209731                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       204666                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       204666                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       249163                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       249163                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       458917                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       458917                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       897477                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       897477                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252001                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252001                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10752                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9335                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       458917                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1146640                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1625644                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10752                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9335                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       458917                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1146640                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       687556                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2313200                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        11035                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        11145                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11949                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11949                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        22984                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        23094                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    356751500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    329343500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    686095000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27876431726                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27876431726                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4396610500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4396610500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3329007000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3329007000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2614499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2614499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8260901500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8260901500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12580419500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12580419500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23624853500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23624853500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6839135500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6839135500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    356751500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    329343500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12580419500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31885755000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  45152269500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    356751500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    329343500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12580419500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31885755000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27876431726                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  73028701226                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9401500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1805437500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1814839000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9401500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1805437500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1814839000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.042585                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.058337                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.048696                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997389                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997389                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.226104                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.226104                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.095639                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.095639                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.251611                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251611                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.565082                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.565082                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.042585                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.058337                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.095639                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245591                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.164542                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.042585                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.058337                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.095639                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245591                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.234134                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     20384822                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10471744                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          887                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1760623                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1760449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          174                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        491097                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      8950741                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11949                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11949                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4279928                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6642170                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2284917                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       836860                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       390891                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       375101                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       483493                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           67                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1131381                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1109621                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4798405                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4426002                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       496716                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       445955                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14394916                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16294669                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       336160                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       556294                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         31582039                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    614163064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    626579614                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1280144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2019872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1244042694                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5755928                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     16349135                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.122449                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.327837                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          14347367     87.76%     87.76% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2001594     12.24%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               174      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      16349135                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   20146131499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    187574309                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7197716000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7451139989                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    176142000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    303810499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136634                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136634                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122674                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231206                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231206                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47760                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155781                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338840                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338840                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496707                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36949503                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               319500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26494000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37417500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569020926                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92771000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147902000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115585                       # number of replacements
system.iocache.tags.tagsinuse               11.243817                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115601                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9095565849000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.827817                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.416000                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239239                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.463500                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.702739                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040784                       # Number of tag accesses
system.iocache.tags.data_accesses             1040784                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8875                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8912                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115603                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115643                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115603                       # number of overall misses
system.iocache.overall_misses::total           115643                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1623231612                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1628431112                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12905416814                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12905416814                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14528648426                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14534216926                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14528648426                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14534216926                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8875                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8912                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115603                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115643                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115603                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115643                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182723.419210                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125677.088190                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125681.769982                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125677.088190                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125681.769982                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         31595                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3437                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.192610                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106695                       # number of writebacks
system.iocache.writebacks::total               106695                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8875                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8912                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115603                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115643                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115603                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115643                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1179481612                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1182831112                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7559977711                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7559977711                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8739459323                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8743027823                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8739459323                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8743027823                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75603.606124                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75603.606124                       # average overall mshr miss latency
system.l2c.tags.replacements                  1336257                       # number of replacements
system.l2c.tags.tagsinuse                63239.486009                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5390392                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1394864                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.864457                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               9808893500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   23096.089917                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   135.068224                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   220.083460                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4065.866850                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     8220.853874                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  8325.282047                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   163.986041                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   269.420690                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2932.882407                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     5116.369986                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.352418                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002061                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003358                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.062040                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.125440                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.127034                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002502                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004111                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.044752                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.078070                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.163171                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.964958                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10513                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          227                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        47867                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          208                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          519                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9786                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1623                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5220                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        40883                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.160416                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003464                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.730392                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 69855982                       # Number of tag accesses
system.l2c.tags.data_accesses                69855982                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2606701                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2606701                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          157949                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          130434                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              288383                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         36828                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         37034                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             73862                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            45889                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            57251                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               103140                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4670                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3337                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       411404                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       536957                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       268808                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6004                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5313                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       419752                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       541221                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       283166                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2480632                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       118921                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       122409                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           241330                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4670                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3337                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              411404                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              582846                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       268808                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6004                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5313                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              419752                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              598472                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       283166                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2583772                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4670                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3337                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             411404                       # number of overall hits
system.l2c.overall_hits::cpu0.data             582846                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       268808                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6004                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5313                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             419752                       # number of overall hits
system.l2c.overall_hits::cpu1.data             598472                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       283166                       # number of overall hits
system.l2c.overall_hits::total                2583772                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         61222                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         59774                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            120996                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        13056                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        12621                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           25677                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          80578                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          52729                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133307                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1465                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1507                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        49296                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       137179                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       229932                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2146                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2116                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        39165                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        95585                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       188965                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         747356                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       446352                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       114497                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         560849                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1465                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1507                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             49296                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            217757                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       229932                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2146                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2116                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            148314                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       188965                       # number of demand (read+write) misses
system.l2c.demand_misses::total                880663                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1465                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1507                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            49296                       # number of overall misses
system.l2c.overall_misses::cpu0.data           217757                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       229932                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2146                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2116                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39165                       # number of overall misses
system.l2c.overall_misses::cpu1.data           148314                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       188965                       # number of overall misses
system.l2c.overall_misses::total               880663                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    367859500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    359764000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    727623500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     70353500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     71619000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    141972500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7055893500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4403905000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11459798500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    131430500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    136636000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   4206937000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  12205051500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  27523923010                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    192694000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    194855000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3362110000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   8709641000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  22702984983                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  79366262993                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     47144000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     45361000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total     92505000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    131430500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    136636000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   4206937000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19260945000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  27523923010                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    192694000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    194855000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3362110000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  13113546000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  22702984983                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     90826061493                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    131430500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    136636000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   4206937000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19260945000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  27523923010                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    192694000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    194855000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3362110000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  13113546000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  22702984983                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    90826061493                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2606701                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2606701                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       219171                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       190208                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          409379                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        49884                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        49655                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         99539                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       126467                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       109980                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           236447                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6135                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4844                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       460700                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       674136                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       498740                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8150                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7429                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       458917                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       636806                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       472131                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3227988                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       565273                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       236906                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       802179                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6135                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4844                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          460700                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          800603                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       498740                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8150                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          458917                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          746786                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       472131                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3464435                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6135                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4844                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         460700                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         800603                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       498740                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8150                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         458917                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         746786                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       472131                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3464435                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.279334                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.314256                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.295560                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.261727                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.254174                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.257959                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.637146                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.479442                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.563792                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.238794                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.311107                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.107002                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.203489                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.263313                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.284830                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.085342                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.150101                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.231524                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.789622                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.483301                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.699157                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.238794                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.311107                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.107002                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.271991                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.263313                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.284830                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.085342                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.198603                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.254201                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.238794                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.311107                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.107002                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.271991                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.263313                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.284830                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.085342                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.198603                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.254201                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6008.616184                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6018.737244                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6013.616153                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5388.595282                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5674.589969                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5529.170074                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87566.004368                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83519.600220                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85965.466930                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89713.651877                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90667.551427                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85340.331873                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88971.719432                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89792.171482                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92086.483932                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85844.759351                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91119.328346                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 106196.060503                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   105.620676                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   396.176319                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   164.937443                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89713.651877                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90667.551427                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85340.331873                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 88451.553796                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89792.171482                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92086.483932                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85844.759351                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 88417.452162                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 103133.731624                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89713.651877                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90667.551427                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85340.331873                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 88451.553796                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89792.171482                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92086.483932                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85844.759351                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 88417.452162                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 103133.731624                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               237                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           237                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1068644                       # number of writebacks
system.l2c.writebacks::total                  1068644                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           42                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          109                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           24                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          182                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             42                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            109                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                182                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            42                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           109                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               182                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        46836                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        46836                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        61222                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        59774                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       120996                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13056                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12621                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        25677                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        80578                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        52729                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133307                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1465                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1507                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        49254                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       137172                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       229932                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2146                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2116                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39056                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        95561                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       188965                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       747174                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       446352                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       114497                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       560849                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1465                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1507                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        49254                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       217750                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       229932                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2146                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2116                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        39056                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       148290                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       188965                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           880481                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1465                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1507                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        49254                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       217750                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       229932                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2146                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2116                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        39056                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       148290                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       188965                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          880481                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        27617                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        11033                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81885                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26565                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11949                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38514                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        54182                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        22982                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       120399                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1334926500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1302438000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2637364500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    323030000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    313272000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    636302000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6250073584                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3876565100                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10126638684                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    116780001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    121565002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3711112036                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10832879176                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  25224418397                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    171229509                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    173694002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   2962814058                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   7752148763                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  20813061565                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  71879702509                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8910827500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2333318000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  11244145500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    116780001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    121565002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3711112036                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  17082952760                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  25224418397                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    171229509                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    173694002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2962814058                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  11628713863                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  20813061565                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  82006341193                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    116780001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    121565002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3711112036                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  17082952760                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25224418397                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    171229509                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    173694002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2962814058                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  11628713863                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  20813061565                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  82006341193                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4353667507                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7421000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1606781004                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8687651511                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4353667507                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7421000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1606781004                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8687651511                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.279334                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.314256                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.295560                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.261727                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.254174                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.257959                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.637146                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.479442                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.563792                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.238794                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.311107                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.106911                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.203478                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.263313                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.284830                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085105                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.150063                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.231467                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.789622                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.483301                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.699157                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.238794                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.311107                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.106911                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.271982                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.263313                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.284830                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085105                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.198571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.254149                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.238794                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.311107                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.106911                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.271982                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461026                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.263313                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.284830                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085105                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.198571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.400238                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.254149                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 93138.115636                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 93138.115636                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       3697678                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2246661                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3188                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq               81885                       # Transaction distribution
system.membus.trans_dist::ReadResp             837971                       # Transaction distribution
system.membus.trans_dist::WriteReq              38514                       # Transaction distribution
system.membus.trans_dist::WriteResp             38514                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1175339                       # Transaction distribution
system.membus.trans_dist::CleanEvict           216465                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           402269                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         335845                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            147056                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129063                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        756086                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        664574                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122674                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26434                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4433526                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4582726                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237876                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237876                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4820602                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155781                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52868                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124620204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    124829057                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7253952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               132083009                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           605187                       # Total snoops (count)
system.membus.snoop_fanout::samples           2426230                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013777                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.116566                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2392803     98.62%     98.62% # Request fanout histogram
system.membus.snoop_fanout::1                   33427      1.38%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2426230                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101268497                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21861496                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8209418227                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4835085635                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45398182                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     10840157                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5896724                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1754214                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         132701                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       121224                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11477                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              81887                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4082535                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38514                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38514                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3675345                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2314292                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          683405                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        409707                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1093112                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          115                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           292338                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          292338                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4001459                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       832376                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       802179                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8623692                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7234411                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15858103                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    210145531                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    178915910                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              389061441                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2781791                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          7676067                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.360389                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.483218                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4921172     64.11%     64.11% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2743418     35.74%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11477      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            7676067                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8520913919                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2554437                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3920667694                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3580148330                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------