stats.txt revision 11374
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311374Ssteve.reinhardt@amd.comsim_seconds 47.460623 # Number of seconds simulated 411374Ssteve.reinhardt@amd.comsim_ticks 47460623015500 # Number of ticks simulated 511374Ssteve.reinhardt@amd.comfinal_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711374Ssteve.reinhardt@amd.comhost_inst_rate 557401 # Simulator instruction rate (inst/s) 811374Ssteve.reinhardt@amd.comhost_op_rate 655644 # Simulator op (including micro ops) rate (op/s) 911374Ssteve.reinhardt@amd.comhost_tick_rate 30226773681 # Simulator tick rate (ticks/s) 1011374Ssteve.reinhardt@amd.comhost_mem_usage 730476 # Number of bytes of host memory used 1111374Ssteve.reinhardt@amd.comhost_seconds 1570.15 # Real time elapsed on the host 1211374Ssteve.reinhardt@amd.comsim_insts 875204273 # Number of instructions simulated 1311374Ssteve.reinhardt@amd.comsim_ops 1029460892 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory 1711374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory 1811374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory 1911374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory 2011374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 12415040 # Number of bytes read from this memory 2111374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.dtb.walker 115712 # Number of bytes read from this memory 2211374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.itb.walker 117120 # Number of bytes read from this memory 2311374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.inst 2511992 # Number of bytes read from this memory 2411374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.data 9752208 # Number of bytes read from this memory 2511374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 13330752 # Number of bytes read from this memory 2611374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::realview.ide 455552 # Number of bytes read from this memory 2711374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::total 53916868 # Number of bytes read from this memory 2811374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::cpu0.inst 3183732 # Number of instructions bytes read from this memory 2911374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::cpu1.inst 2511992 # Number of instructions bytes read from this memory 3011374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::total 5695724 # Number of instructions bytes read from this memory 3111374Ssteve.reinhardt@amd.comsystem.physmem.bytes_written::writebacks 73320768 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411374Ssteve.reinhardt@amd.comsystem.physmem.bytes_written::total 73341352 # Number of bytes written to this memory 3511374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.dtb.walker 1280 # Number of read requests responded to by this memory 3611374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.itb.walker 1221 # Number of read requests responded to by this memory 3711374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.inst 90153 # Number of read requests responded to by this memory 3811374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.data 185555 # Number of read requests responded to by this memory 3911374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 193985 # Number of read requests responded to by this memory 4011374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.dtb.walker 1808 # Number of read requests responded to by this memory 4111374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.itb.walker 1830 # Number of read requests responded to by this memory 4211374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.inst 39338 # Number of read requests responded to by this memory 4311374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.data 152391 # Number of read requests responded to by this memory 4411374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 208293 # Number of read requests responded to by this memory 4511374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::realview.ide 7118 # Number of read requests responded to by this memory 4611374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::total 882972 # Number of read requests responded to by this memory 4711374Ssteve.reinhardt@amd.comsystem.physmem.num_writes::writebacks 1145637 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011374Ssteve.reinhardt@amd.comsystem.physmem.num_writes::total 1148211 # Number of write requests responded to by this memory 5111374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s) 5211374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.itb.walker 1647 # Total read bandwidth from this memory (bytes/s) 5311374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.inst 67082 # Total read bandwidth from this memory (bytes/s) 5411374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.data 250201 # Total read bandwidth from this memory (bytes/s) 5511374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 261586 # Total read bandwidth from this memory (bytes/s) 5611374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.dtb.walker 2438 # Total read bandwidth from this memory (bytes/s) 5711374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.itb.walker 2468 # Total read bandwidth from this memory (bytes/s) 5811374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.inst 52928 # Total read bandwidth from this memory (bytes/s) 5911374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.data 205480 # Total read bandwidth from this memory (bytes/s) 6011374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 280880 # Total read bandwidth from this memory (bytes/s) 6111374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::realview.ide 9599 # Total read bandwidth from this memory (bytes/s) 6211374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::total 1136034 # Total read bandwidth from this memory (bytes/s) 6311374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu0.inst 67082 # Instruction read bandwidth from this memory (bytes/s) 6411374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu1.inst 52928 # Instruction read bandwidth from this memory (bytes/s) 6511374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::total 120009 # Instruction read bandwidth from this memory (bytes/s) 6611374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::writebacks 1544876 # Write bandwidth from this memory (bytes/s) 6711374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::total 1545310 # Write bandwidth from this memory (bytes/s) 7011374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::writebacks 1544876 # Total bandwidth to/from this memory (bytes/s) 7111374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s) 7211374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.itb.walker 1647 # Total bandwidth to/from this memory (bytes/s) 7311374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.inst 67082 # Total bandwidth to/from this memory (bytes/s) 7411374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.data 250635 # Total bandwidth to/from this memory (bytes/s) 7511374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 261586 # Total bandwidth to/from this memory (bytes/s) 7611374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.dtb.walker 2438 # Total bandwidth to/from this memory (bytes/s) 7711374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.itb.walker 2468 # Total bandwidth to/from this memory (bytes/s) 7811374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.inst 52928 # Total bandwidth to/from this memory (bytes/s) 7911374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.data 205480 # Total bandwidth to/from this memory (bytes/s) 8011374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 280880 # Total bandwidth to/from this memory (bytes/s) 8111374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::realview.ide 9599 # Total bandwidth to/from this memory (bytes/s) 8211374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::total 2681343 # Total bandwidth to/from this memory (bytes/s) 8311374Ssteve.reinhardt@amd.comsystem.physmem.readReqs 882972 # Number of read requests accepted 8411374Ssteve.reinhardt@amd.comsystem.physmem.writeReqs 1148211 # Number of write requests accepted 8511374Ssteve.reinhardt@amd.comsystem.physmem.readBursts 882972 # Number of DRAM read bursts, including those serviced by the write queue 8611374Ssteve.reinhardt@amd.comsystem.physmem.writeBursts 1148211 # Number of DRAM write bursts, including those merged in the write queue 8711374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadDRAM 56486656 # Total number of bytes read from DRAM 8811374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue 8911374Ssteve.reinhardt@amd.comsystem.physmem.bytesWritten 73339968 # Total number of bytes written to DRAM 9011374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadSys 53916868 # Total read bytes from the system interface side 9111374Ssteve.reinhardt@amd.comsystem.physmem.bytesWrittenSys 73341352 # Total written bytes from the system interface side 9211374Ssteve.reinhardt@amd.comsystem.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue 9311374Ssteve.reinhardt@amd.comsystem.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one 9411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9511374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::0 53897 # Per bank write bursts 9611374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::1 57581 # Per bank write bursts 9711374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::2 50596 # Per bank write bursts 9811374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::3 56941 # Per bank write bursts 9911374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::4 52224 # Per bank write bursts 10011374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::5 57867 # Per bank write bursts 10111374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::6 48622 # Per bank write bursts 10211374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::7 53589 # Per bank write bursts 10311374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::8 50057 # Per bank write bursts 10411374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 95322 # Per bank write bursts 10511374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::10 46946 # Per bank write bursts 10611374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::11 52908 # Per bank write bursts 10711374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::12 47194 # Per bank write bursts 10811374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::13 52526 # Per bank write bursts 10911374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::14 52237 # Per bank write bursts 11011374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 54097 # Per bank write bursts 11111374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::0 68696 # Per bank write bursts 11211374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::1 73430 # Per bank write bursts 11311374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::2 69832 # Per bank write bursts 11411374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::3 74009 # Per bank write bursts 11511374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::4 72053 # Per bank write bursts 11611374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::5 74820 # Per bank write bursts 11711374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::6 69700 # Per bank write bursts 11811374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::7 72497 # Per bank write bursts 11911374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::8 69824 # Per bank write bursts 12011374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::9 74930 # Per bank write bursts 12111374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::10 66965 # Per bank write bursts 12211374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::11 71787 # Per bank write bursts 12311374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::12 69900 # Per bank write bursts 12411374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::13 73092 # Per bank write bursts 12511374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::14 71437 # Per bank write bursts 12611374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::15 72965 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811374Ssteve.reinhardt@amd.comsystem.physmem.numWrRetry 49 # Number of times write queue was full causing retry 12911374Ssteve.reinhardt@amd.comsystem.physmem.totGap 47460619650000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611374Ssteve.reinhardt@amd.comsystem.physmem.readPktSize::6 839747 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311374Ssteve.reinhardt@amd.comsystem.physmem.writePktSize::6 1145637 # Write request sizes (log2) 14411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::0 632223 # What read queue length does an incoming req see 14511374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::1 71339 # What read queue length does an incoming req see 14611374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::2 35282 # What read queue length does an incoming req see 14711374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::3 31150 # What read queue length does an incoming req see 14811374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::4 27029 # What read queue length does an incoming req see 14911374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::5 24072 # What read queue length does an incoming req see 15011374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::6 21057 # What read queue length does an incoming req see 15111374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::7 18521 # What read queue length does an incoming req see 15211374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::8 14779 # What read queue length does an incoming req see 15311374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::9 2467 # What read queue length does an incoming req see 15411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::10 1357 # What read queue length does an incoming req see 15511374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::11 874 # What read queue length does an incoming req see 15611374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::12 674 # What read queue length does an incoming req see 15711374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::13 507 # What read queue length does an incoming req see 15811374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::14 376 # What read queue length does an incoming req see 15911374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::15 293 # What read queue length does an incoming req see 16011374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 16111374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see 16211374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 16311374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see 16411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::15 33201 # What write queue length does an incoming req see 19211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::16 39474 # What write queue length does an incoming req see 19311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::17 49559 # What write queue length does an incoming req see 19411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::18 52179 # What write queue length does an incoming req see 19511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::19 57658 # What write queue length does an incoming req see 19611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::20 60584 # What write queue length does an incoming req see 19711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::21 63950 # What write queue length does an incoming req see 19811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::22 67460 # What write queue length does an incoming req see 19911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::23 69091 # What write queue length does an incoming req see 20011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::24 68874 # What write queue length does an incoming req see 20111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::25 71191 # What write queue length does an incoming req see 20211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::26 73992 # What write queue length does an incoming req see 20311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::27 71007 # What write queue length does an incoming req see 20411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::28 71950 # What write queue length does an incoming req see 20511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::29 78189 # What write queue length does an incoming req see 20611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::30 71162 # What write queue length does an incoming req see 20711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::31 66652 # What write queue length does an incoming req see 20811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::32 64454 # What write queue length does an incoming req see 20911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::33 3233 # What write queue length does an incoming req see 21011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::34 1565 # What write queue length does an incoming req see 21111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::35 1104 # What write queue length does an incoming req see 21211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::36 916 # What write queue length does an incoming req see 21311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::37 789 # What write queue length does an incoming req see 21411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::38 640 # What write queue length does an incoming req see 21511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::39 509 # What write queue length does an incoming req see 21611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::40 414 # What write queue length does an incoming req see 21711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::41 499 # What write queue length does an incoming req see 21811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::42 407 # What write queue length does an incoming req see 21911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see 22011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::44 378 # What write queue length does an incoming req see 22111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::45 363 # What write queue length does an incoming req see 22211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::46 334 # What write queue length does an incoming req see 22311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::47 316 # What write queue length does an incoming req see 22411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see 22511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see 22611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::50 377 # What write queue length does an incoming req see 22711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see 22811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::52 282 # What write queue length does an incoming req see 22911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see 23011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see 23111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::55 182 # What write queue length does an incoming req see 23211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see 23311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see 23411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see 23511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see 23611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see 23711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::61 166 # What write queue length does an incoming req see 23811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see 23911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::63 141 # What write queue length does an incoming req see 24011374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::samples 939668 # Bytes accessed per row activation 24111374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::mean 138.161751 # Bytes accessed per row activation 24211374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::gmean 95.082106 # Bytes accessed per row activation 24311374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::stdev 185.728908 # Bytes accessed per row activation 24411374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::0-127 647019 68.86% 68.86% # Bytes accessed per row activation 24511374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::128-255 180648 19.22% 88.08% # Bytes accessed per row activation 24611374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::256-383 40379 4.30% 92.38% # Bytes accessed per row activation 24711374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::384-511 17830 1.90% 94.28% # Bytes accessed per row activation 24811374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::512-639 14299 1.52% 95.80% # Bytes accessed per row activation 24911374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::640-767 8441 0.90% 96.70% # Bytes accessed per row activation 25011374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::768-895 5223 0.56% 97.25% # Bytes accessed per row activation 25111374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::896-1023 4905 0.52% 97.77% # Bytes accessed per row activation 25211374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::1024-1151 20924 2.23% 100.00% # Bytes accessed per row activation 25311374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::total 939668 # Bytes accessed per row activation 25411374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::samples 60779 # Reads before turning the bus around for writes 25511374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::mean 14.521496 # Reads before turning the bus around for writes 25611374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::stdev 130.920998 # Reads before turning the bus around for writes 25711374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::0-1023 60776 100.00% 100.00% # Reads before turning the bus around for writes 25811374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26111374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::total 60779 # Reads before turning the bus around for writes 26211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::samples 60779 # Writes before turning the bus around for reads 26311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::mean 18.854160 # Writes before turning the bus around for reads 26411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::gmean 18.212866 # Writes before turning the bus around for reads 26511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::stdev 7.632019 # Writes before turning the bus around for reads 26611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::16-19 48749 80.21% 80.21% # Writes before turning the bus around for reads 26711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::20-23 9610 15.81% 96.02% # Writes before turning the bus around for reads 26811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::24-27 589 0.97% 96.99% # Writes before turning the bus around for reads 26911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::28-31 189 0.31% 97.30% # Writes before turning the bus around for reads 27011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::32-35 137 0.23% 97.52% # Writes before turning the bus around for reads 27111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::36-39 124 0.20% 97.73% # Writes before turning the bus around for reads 27211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::40-43 218 0.36% 98.09% # Writes before turning the bus around for reads 27311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::44-47 91 0.15% 98.24% # Writes before turning the bus around for reads 27411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::48-51 270 0.44% 98.68% # Writes before turning the bus around for reads 27511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::52-55 61 0.10% 98.78% # Writes before turning the bus around for reads 27611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::56-59 30 0.05% 98.83% # Writes before turning the bus around for reads 27711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::60-63 50 0.08% 98.91% # Writes before turning the bus around for reads 27811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::64-67 255 0.42% 99.33% # Writes before turning the bus around for reads 27911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::68-71 52 0.09% 99.42% # Writes before turning the bus around for reads 28011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::72-75 24 0.04% 99.46% # Writes before turning the bus around for reads 28111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::76-79 99 0.16% 99.62% # Writes before turning the bus around for reads 28211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::80-83 170 0.28% 99.90% # Writes before turning the bus around for reads 28311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.90% # Writes before turning the bus around for reads 28411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 28511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 28611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 28711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads 28811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::112-115 3 0.00% 99.92% # Writes before turning the bus around for reads 28911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 29011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::128-131 22 0.04% 99.96% # Writes before turning the bus around for reads 29111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 29211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 29311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 29411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads 29511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 29611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 29711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads 29811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 29911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::total 60779 # Writes before turning the bus around for reads 30011374Ssteve.reinhardt@amd.comsystem.physmem.totQLat 27990688881 # Total ticks spent queuing 30111374Ssteve.reinhardt@amd.comsystem.physmem.totMemAccLat 44539513881 # Total ticks spent from burst creation until serviced by the DRAM 30211374Ssteve.reinhardt@amd.comsystem.physmem.totBusLat 4413020000 # Total ticks spent in databus transfers 30311374Ssteve.reinhardt@amd.comsystem.physmem.avgQLat 31713.76 # Average queueing delay per DRAM burst 30410515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30511374Ssteve.reinhardt@amd.comsystem.physmem.avgMemAccLat 50463.76 # Average memory access latency per DRAM burst 30611374Ssteve.reinhardt@amd.comsystem.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s 30711374Ssteve.reinhardt@amd.comsystem.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s 30811374Ssteve.reinhardt@amd.comsystem.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s 30911374Ssteve.reinhardt@amd.comsystem.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s 31010515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31111374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 31211201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31310892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31411374Ssteve.reinhardt@amd.comsystem.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing 31511374Ssteve.reinhardt@amd.comsystem.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 31611374Ssteve.reinhardt@amd.comsystem.physmem.readRowHits 659544 # Number of row buffer hits during reads 31711374Ssteve.reinhardt@amd.comsystem.physmem.writeRowHits 429323 # Number of row buffer hits during writes 31811374Ssteve.reinhardt@amd.comsystem.physmem.readRowHitRate 74.73 # Row buffer hit rate for reads 31911374Ssteve.reinhardt@amd.comsystem.physmem.writeRowHitRate 37.46 # Row buffer hit rate for writes 32011374Ssteve.reinhardt@amd.comsystem.physmem.avgGap 23365998.85 # Average gap between requests 32111374Ssteve.reinhardt@amd.comsystem.physmem.pageHitRate 53.68 # Row buffer hit rate, read and write combined 32211374Ssteve.reinhardt@amd.comsystem.physmem_0.actEnergy 3575759040 # Energy for activate commands per rank (pJ) 32311374Ssteve.reinhardt@amd.comsystem.physmem_0.preEnergy 1951059000 # Energy for precharge commands per rank (pJ) 32411374Ssteve.reinhardt@amd.comsystem.physmem_0.readEnergy 3364272600 # Energy for read commands per rank (pJ) 32511374Ssteve.reinhardt@amd.comsystem.physmem_0.writeEnergy 3726194400 # Energy for write commands per rank (pJ) 32611374Ssteve.reinhardt@amd.comsystem.physmem_0.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) 32711374Ssteve.reinhardt@amd.comsystem.physmem_0.actBackEnergy 1199863250505 # Energy for active background per rank (pJ) 32811374Ssteve.reinhardt@amd.comsystem.physmem_0.preBackEnergy 27423860344500 # Energy for precharge background per rank (pJ) 32911374Ssteve.reinhardt@amd.comsystem.physmem_0.totalEnergy 31736237846445 # Total energy per rank (pJ) 33011374Ssteve.reinhardt@amd.comsystem.physmem_0.averagePower 668.685699 # Core power per rank (mW) 33111374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::IDLE 45621402632571 # Time in different power states 33211374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::REF 1584814400000 # Time in different power states 33310628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33411374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::ACT 254405603429 # Time in different power states 33510628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33611374Ssteve.reinhardt@amd.comsystem.physmem_1.actEnergy 3528047880 # Energy for activate commands per rank (pJ) 33711374Ssteve.reinhardt@amd.comsystem.physmem_1.preEnergy 1925026125 # Energy for precharge commands per rank (pJ) 33811374Ssteve.reinhardt@amd.comsystem.physmem_1.readEnergy 3519999600 # Energy for read commands per rank (pJ) 33911374Ssteve.reinhardt@amd.comsystem.physmem_1.writeEnergy 3699373680 # Energy for write commands per rank (pJ) 34011374Ssteve.reinhardt@amd.comsystem.physmem_1.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) 34111374Ssteve.reinhardt@amd.comsystem.physmem_1.actBackEnergy 1198418138910 # Energy for active background per rank (pJ) 34211374Ssteve.reinhardt@amd.comsystem.physmem_1.preBackEnergy 27425127986250 # Energy for precharge background per rank (pJ) 34311374Ssteve.reinhardt@amd.comsystem.physmem_1.totalEnergy 31736115538845 # Total energy per rank (pJ) 34411374Ssteve.reinhardt@amd.comsystem.physmem_1.averagePower 668.683122 # Core power per rank (mW) 34511374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::IDLE 45623502554973 # Time in different power states 34611374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::REF 1584814400000 # Time in different power states 34710628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34811374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::ACT 252305273527 # Time in different power states 34910628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35010515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35110515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35210515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35310515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 35810515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 35910515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36010515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36110515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36210515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36310515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36410515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36510515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36610515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37610535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37710535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37810535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37911353Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38011353Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38111353Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38210515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walks 102194 # Table walker walks requested 41311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLong 102194 # Table walker walks initiated with long descriptors 41411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9208 # Level at which table walker walks with long descriptors terminate 41511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76624 # Level at which table walker walks with long descriptors terminate 41611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 41711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::samples 102185 # Table walker wait (enqueue to first request) latency 41811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.254440 # Table walker wait (enqueue to first request) latency 41911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 81.335431 # Table walker wait (enqueue to first request) latency 42011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 102184 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::total 102185 # Table walker wait (enqueue to first request) latency 42311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 85841 # Table walker service (enqueue to completion) latency 42411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800 # Table walker service (enqueue to completion) latency 42511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936 # Table walker service (enqueue to completion) latency 42611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669 # Table walker service (enqueue to completion) latency 42711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 85046 99.07% 99.07% # Table walker service (enqueue to completion) latency 42811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 170 0.20% 99.27% # Table walker service (enqueue to completion) latency 42911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 522 0.61% 99.88% # Table walker service (enqueue to completion) latency 43011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 25 0.03% 99.91% # Table walker service (enqueue to completion) latency 43111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.94% # Table walker service (enqueue to completion) latency 43211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency 43311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 28 0.03% 99.99% # Table walker service (enqueue to completion) latency 43411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 43511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 43611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 43711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::total 85841 # Table walker service (enqueue to completion) latency 43811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::samples 4536625496 # Table walker pending requests distribution 43911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::mean 0.282786 # Table walker pending requests distribution 44011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::stdev 0.450353 # Table walker pending requests distribution 44111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::0 3253731032 71.72% 71.72% # Table walker pending requests distribution 44211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::1 1282894464 28.28% 100.00% # Table walker pending requests distribution 44311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksPending::total 4536625496 # Table walker pending requests distribution 44411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::4K 76625 89.27% 89.27% # Table walker page sizes translated 44511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9208 10.73% 100.00% # Table walker page sizes translated 44611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::total 85833 # Table walker page sizes translated 44711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 102194 # Table walker requests started/completed, data/inst 44810628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 102194 # Table walker requests started/completed, data/inst 45011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85833 # Table walker requests started/completed, data/inst 45110628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85833 # Table walker requests started/completed, data/inst 45311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 188027 # Table walker requests started/completed, data/inst 45410535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45510535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_hits 85563003 # DTB read hits 45711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_misses 75756 # DTB read misses 45811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_hits 77475573 # DTB write hits 45911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_misses 26438 # DTB write misses 46010535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46110535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 46311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 46411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_entries 34001 # Number of entries that have been flushed from TLB 46510535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 46611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.prefetch_faults 4044 # Number of TLB faults due to prefetch 46710535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.perms_faults 8915 # Number of TLB faults due to permissions restrictions 46911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_accesses 85638759 # DTB read accesses 47011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_accesses 77502011 # DTB write accesses 47110535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.hits 163038576 # DTB hits 47311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.misses 102194 # DTB misses 47411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.accesses 163140770 # DTB accesses 47510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walks 56381 # Table walker walks requested 50511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLong 56381 # Table walker walks initiated with long descriptors 50611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 642 # Level at which table walker walks with long descriptors terminate 50711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 50009 # Level at which table walker walks with long descriptors terminate 50811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::samples 56381 # Table walker wait (enqueue to first request) latency 50911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::0 56381 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::total 56381 # Table walker wait (enqueue to first request) latency 51111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::samples 50651 # Table walker service (enqueue to completion) latency 51211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25304.495469 # Table walker service (enqueue to completion) latency 51311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990 # Table walker service (enqueue to completion) latency 51411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846 # Table walker service (enqueue to completion) latency 51511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 49913 98.54% 98.54% # Table walker service (enqueue to completion) latency 51611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 55 0.11% 98.65% # Table walker service (enqueue to completion) latency 51711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 593 1.17% 99.82% # Table walker service (enqueue to completion) latency 51811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.84% # Table walker service (enqueue to completion) latency 51911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.06% 99.90% # Table walker service (enqueue to completion) latency 52011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.92% # Table walker service (enqueue to completion) latency 52111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 34 0.07% 99.99% # Table walker service (enqueue to completion) latency 52211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 52311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::total 50651 # Table walker service (enqueue to completion) latency 52511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 52611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 52711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 52811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::4K 50009 98.73% 98.73% # Table walker page sizes translated 52911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::2M 642 1.27% 100.00% # Table walker page sizes translated 53011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::total 50651 # Table walker page sizes translated 53110628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56381 # Table walker requests started/completed, data/inst 53311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 56381 # Table walker requests started/completed, data/inst 53410628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50651 # Table walker requests started/completed, data/inst 53611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 50651 # Table walker requests started/completed, data/inst 53711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin::total 107032 # Table walker requests started/completed, data/inst 53811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_hits 455204971 # ITB inst hits 53911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_misses 56381 # ITB inst misses 54010535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54110535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 54210535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 54310535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 54410535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 54510535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 54711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 54811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_entries 24108 # Number of entries that have been flushed from TLB 54910535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55010535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55110535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55210535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 55310535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 55410535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 55511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_accesses 455261352 # ITB inst accesses 55611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.hits 455204971 # DTB hits 55711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.misses 56381 # DTB misses 55811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.accesses 455261352 # DTB accesses 55911374Ssteve.reinhardt@amd.comsystem.cpu0.numCycles 94921246031 # number of cpu cycles simulated 56010535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56110535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56211167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 56311374Ssteve.reinhardt@amd.comsystem.cpu0.kern.inst.quiesce 13214 # number of quiesce instructions executed 56411374Ssteve.reinhardt@amd.comsystem.cpu0.committedInsts 454926589 # Number of instructions committed 56511374Ssteve.reinhardt@amd.comsystem.cpu0.committedOps 534313943 # Number of ops (including micro ops) committed 56611374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_alu_accesses 491049300 # Number of integer alu accesses 56711374Ssteve.reinhardt@amd.comsystem.cpu0.num_fp_alu_accesses 395385 # Number of float alu accesses 56811374Ssteve.reinhardt@amd.comsystem.cpu0.num_func_calls 27308099 # number of times a function call or return occured 56911374Ssteve.reinhardt@amd.comsystem.cpu0.num_conditional_control_insts 68959046 # number of instructions that are conditional controls 57011374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_insts 491049300 # number of integer instructions 57111374Ssteve.reinhardt@amd.comsystem.cpu0.num_fp_insts 395385 # number of float instructions 57211374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_register_reads 709557386 # number of times the integer registers were read 57311374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_register_writes 389375063 # number of times the integer registers were written 57411374Ssteve.reinhardt@amd.comsystem.cpu0.num_fp_register_reads 654866 # number of times the floating registers were read 57511374Ssteve.reinhardt@amd.comsystem.cpu0.num_fp_register_writes 293356 # number of times the floating registers were written 57611374Ssteve.reinhardt@amd.comsystem.cpu0.num_cc_register_reads 117980325 # number of times the CC registers were read 57711374Ssteve.reinhardt@amd.comsystem.cpu0.num_cc_register_writes 117652107 # number of times the CC registers were written 57811374Ssteve.reinhardt@amd.comsystem.cpu0.num_mem_refs 163029477 # number of memory refs 57911374Ssteve.reinhardt@amd.comsystem.cpu0.num_load_insts 85557806 # Number of load instructions 58011374Ssteve.reinhardt@amd.comsystem.cpu0.num_store_insts 77471671 # Number of store instructions 58111374Ssteve.reinhardt@amd.comsystem.cpu0.num_idle_cycles 93727706914.782028 # Number of idle cycles 58211374Ssteve.reinhardt@amd.comsystem.cpu0.num_busy_cycles 1193539116.217975 # Number of busy cycles 58311374Ssteve.reinhardt@amd.comsystem.cpu0.not_idle_fraction 0.012574 # Percentage of non-idle cycles 58411374Ssteve.reinhardt@amd.comsystem.cpu0.idle_fraction 0.987426 # Percentage of idle cycles 58511374Ssteve.reinhardt@amd.comsystem.cpu0.Branches 101606994 # Number of branches fetched 58611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 58711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntAlu 370328410 69.27% 69.27% # Class of executed instruction 58811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntMult 1177627 0.22% 69.49% # Class of executed instruction 58911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntDiv 60510 0.01% 69.50% # Class of executed instruction 59011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 59111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 59211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 59311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 59411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 59511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 59611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 59711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 59811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 59911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 60011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 60111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 60211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 60311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 60411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 60511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 60611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 60711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.50% # Class of executed instruction 60811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 60911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.50% # Class of executed instruction 61011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.50% # Class of executed instruction 61111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 61211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMisc 39424 0.01% 69.51% # Class of executed instruction 61311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 61411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 61511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 61611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::MemRead 85557806 16.00% 85.51% # Class of executed instruction 61711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::MemWrite 77471671 14.49% 100.00% # Class of executed instruction 61810535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 61910535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::total 534635449 # Class of executed instruction 62111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.replacements 5459134 # number of replacements 62211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.tagsinuse 479.881862 # Cycle average of tags in use 62311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.total_refs 157334556 # Total number of references to valid blocks. 62411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.sampled_refs 5459646 # Sample count of references to valid blocks. 62511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.avg_refs 28.817721 # Average number of references to valid blocks. 62611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 62711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 479.881862 # Average occupied blocks per requestor 62811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy 62911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_percent::total 0.937269 # Average percentage of cache occupancy 63011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 63211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id 63311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 63411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.tag_accesses 331496751 # Number of tag accesses 63611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.data_accesses 331496751 # Number of data accesses 63711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 79723477 # number of ReadReq hits 63811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_hits::total 79723477 # number of ReadReq hits 63911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 73152105 # number of WriteReq hits 64011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_hits::total 73152105 # number of WriteReq hits 64111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits 64211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits 64311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits 64411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits 64511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits 64611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits 64711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits 64811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits 64911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits 65011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits 65111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits 65211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_hits::total 153075138 # number of overall hits 65311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses 65411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses 65511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses 65611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_misses::total 1350734 # number of WriteReq misses 65711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 619590 # number of SoftPFReq misses 65811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_misses::total 619590 # number of SoftPFReq misses 65911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 750130 # number of WriteLineReq misses 66011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_misses::total 750130 # number of WriteLineReq misses 66111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632 # number of LoadLockedReq misses 66211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses 66311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses 66411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses 66511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses 66611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses 66711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses 66811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_misses::total 4954267 # number of overall misses 66911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles 67011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles 67111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles 67211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles 67311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles 67411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles 67511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles 67611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles 67711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles 67811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles 67911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles 68011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles 68111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles 68211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles 68311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles 68411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles 68511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) 68611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) 68711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) 68811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) 68911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) 69011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) 69111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) 69211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) 69311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) 69411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) 69511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) 69611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) 69711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses 69811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses 69911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses 70011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses 70111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses 70211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses 70311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses 70411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses 70511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses 70611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses 70711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses 70811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses 70911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses 71011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses 71111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses 71211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses 71311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses 71411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses 71511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses 71611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses 71711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency 71811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency 71911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency 72011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency 72111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency 72211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency 72311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency 72411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency 72511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency 72611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency 72710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 72810535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 72911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency 73011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency 73111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency 73211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency 73310535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73410535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73510535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 73610535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 73710535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73810535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73910585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 74010535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 74111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks 74211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.writebacks::total 5459134 # number of writebacks 74311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits 74411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits 74511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21402 # number of WriteReq MSHR hits 74611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21402 # number of WriteReq MSHR hits 74711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43300 # number of LoadLockedReq MSHR hits 74811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits 74911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 45637 # number of demand (read+write) MSHR hits 75011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_hits::total 45637 # number of demand (read+write) MSHR hits 75111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 45637 # number of overall MSHR hits 75211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_hits::total 45637 # number of overall MSHR hits 75311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2959708 # number of ReadReq MSHR misses 75411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2959708 # number of ReadReq MSHR misses 75511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1329332 # number of WriteReq MSHR misses 75611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1329332 # number of WriteReq MSHR misses 75711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses 75811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses 75911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses 76011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses 76111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses 76211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses 76311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses 76411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses 76511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses 76611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses 76711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses 76811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses 76911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 77011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable 77111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 77211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 77311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 77411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses 77511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles 77611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles 77711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33090463000 # number of WriteReq MSHR miss cycles 77811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 33090463000 # number of WriteReq MSHR miss cycles 77911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14878889500 # number of SoftPFReq MSHR miss cycles 78011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14878889500 # number of SoftPFReq MSHR miss cycles 78111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles 78211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles 78311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles 78411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles 78511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles 78611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles 78711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles 78811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles 78911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles 79011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles 79111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles 79211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles 79311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles 79411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles 79511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles 79611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles 79711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles 79811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles 79911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses 80011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses 80111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses 80211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses 80311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses 80411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses 80511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses 80611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses 80711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses 80811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses 80911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses 81011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses 81111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses 81211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses 81311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses 81411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses 81511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency 81611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency 81711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency 81811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency 81911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency 82011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency 82111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency 82211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency 82311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency 82411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency 82511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency 82611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency 82710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 82810535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 82911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency 83011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency 83111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency 83211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency 83311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency 83411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency 83511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency 83611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency 83711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency 83811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency 83910535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.replacements 5000286 # number of replacements 84111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use 84211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. 84311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. 84411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. 84511353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. 84611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor 84711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy 84811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.occ_percent::total 0.999714 # Average percentage of cache occupancy 84910535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 85111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 85211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id 85310535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.tag_accesses 915410741 # Number of tag accesses 85511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.data_accesses 915410741 # Number of data accesses 85611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 450204172 # number of ReadReq hits 85711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_hits::total 450204172 # number of ReadReq hits 85811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_hits::cpu0.inst 450204172 # number of demand (read+write) hits 85911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_hits::total 450204172 # number of demand (read+write) hits 86011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_hits::cpu0.inst 450204172 # number of overall hits 86111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_hits::total 450204172 # number of overall hits 86211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5000799 # number of ReadReq misses 86311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_misses::total 5000799 # number of ReadReq misses 86411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_misses::cpu0.inst 5000799 # number of demand (read+write) misses 86511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_misses::total 5000799 # number of demand (read+write) misses 86611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_misses::cpu0.inst 5000799 # number of overall misses 86711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_misses::total 5000799 # number of overall misses 86811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55488072500 # number of ReadReq miss cycles 86911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_latency::total 55488072500 # number of ReadReq miss cycles 87011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 55488072500 # number of demand (read+write) miss cycles 87111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_latency::total 55488072500 # number of demand (read+write) miss cycles 87211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 55488072500 # number of overall miss cycles 87311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_latency::total 55488072500 # number of overall miss cycles 87411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 455204971 # number of ReadReq accesses(hits+misses) 87511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_accesses::total 455204971 # number of ReadReq accesses(hits+misses) 87611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_accesses::cpu0.inst 455204971 # number of demand (read+write) accesses 87711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_accesses::total 455204971 # number of demand (read+write) accesses 87811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_accesses::cpu0.inst 455204971 # number of overall (read+write) accesses 87911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_accesses::total 455204971 # number of overall (read+write) accesses 88011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010986 # miss rate for ReadReq accesses 88111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010986 # miss rate for ReadReq accesses 88211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010986 # miss rate for demand accesses 88311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_rate::total 0.010986 # miss rate for demand accesses 88411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010986 # miss rate for overall accesses 88511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_rate::total 0.010986 # miss rate for overall accesses 88611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11095.841385 # average ReadReq miss latency 88711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11095.841385 # average ReadReq miss latency 88811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 88911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_miss_latency::total 11095.841385 # average overall miss latency 89011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 89111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_miss_latency::total 11095.841385 # average overall miss latency 89210535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89310535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89410535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89510535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 89610535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89710535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89810535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 89910535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 90011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks 90111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.writebacks::total 5000286 # number of writebacks 90211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses 90311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_misses::total 5000799 # number of ReadReq MSHR misses 90411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 5000799 # number of demand (read+write) MSHR misses 90511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_misses::total 5000799 # number of demand (read+write) MSHR misses 90611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 5000799 # number of overall MSHR misses 90711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_misses::total 5000799 # number of overall MSHR misses 90810827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 90910827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 91010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 91110827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 91211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 52987673000 # number of ReadReq MSHR miss cycles 91311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 52987673000 # number of ReadReq MSHR miss cycles 91411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 52987673000 # number of demand (read+write) MSHR miss cycles 91511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_latency::total 52987673000 # number of demand (read+write) MSHR miss cycles 91611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 52987673000 # number of overall MSHR miss cycles 91711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_latency::total 52987673000 # number of overall MSHR miss cycles 91811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 91911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 92011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 92111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 92211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for ReadReq accesses 92311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010986 # mshr miss rate for ReadReq accesses 92411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for demand accesses 92511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010986 # mshr miss rate for demand accesses 92611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for overall accesses 92711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010986 # mshr miss rate for overall accesses 92811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average ReadReq mshr miss latency 92911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10595.841385 # average ReadReq mshr miss latency 93011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 93111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 93211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 93311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 93411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 93511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 93611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 93711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 93810535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 93911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued 94011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified 94111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue 94210628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94310628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 974782 # number of prefetches not generated due to page crossing 94511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.replacements 2298690 # number of replacements 94611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.tagsinuse 16186.717586 # Cycle average of tags in use 94711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.total_refs 14759696 # Total number of references to valid blocks. 94811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.sampled_refs 2314768 # Sample count of references to valid blocks. 94911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.avg_refs 6.376318 # Average number of references to valid blocks. 95011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit. 95111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15157.672211 # Average occupied blocks per requestor 95211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.142846 # Average occupied blocks per requestor 95311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.415973 # Average occupied blocks per requestor 95411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.486557 # Average occupied blocks per requestor 95511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.925151 # Average percentage of cache occupancy 95611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003244 # Average percentage of cache occupancy 95711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004664 # Average percentage of cache occupancy 95811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054900 # Average percentage of cache occupancy 95911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::total 0.987959 # Average percentage of cache occupancy 96011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1325 # Occupied blocks per task id 96111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 96211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14699 # Occupied blocks per task id 96311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id 96411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 96511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 683 # Occupied blocks per task id 96611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 429 # Occupied blocks per task id 96711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 96811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 96911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 97011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 97111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1043 # Occupied blocks per task id 97211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4210 # Occupied blocks per task id 97311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6256 # Occupied blocks per task id 97411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id 97511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080872 # Percentage of cache occupancy per task id 97611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id 97711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897156 # Percentage of cache occupancy per task id 97811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.tag_accesses 354680611 # Number of tag accesses 97911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.data_accesses 354680611 # Number of data accesses 98011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 235924 # number of ReadReq hits 98111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143301 # number of ReadReq hits 98211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::total 379225 # number of ReadReq hits 98311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3602563 # number of WritebackDirty hits 98411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3602563 # number of WritebackDirty hits 98511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6855894 # number of WritebackClean hits 98611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_hits::total 6855894 # number of WritebackClean hits 98711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 389 # number of UpgradeReq hits 98811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_hits::total 389 # number of UpgradeReq hits 98911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 855344 # number of ReadExReq hits 99011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_hits::total 855344 # number of ReadExReq hits 99111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4541852 # number of ReadCleanReq hits 99211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4541852 # number of ReadCleanReq hits 99311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2786021 # number of ReadSharedReq hits 99411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2786021 # number of ReadSharedReq hits 99511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 182713 # number of InvalidateReq hits 99611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_hits::total 182713 # number of InvalidateReq hits 99711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 235924 # number of demand (read+write) hits 99811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 143301 # number of demand (read+write) hits 99911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4541852 # number of demand (read+write) hits 100011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3641365 # number of demand (read+write) hits 100111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::total 8562442 # number of demand (read+write) hits 100211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 235924 # number of overall hits 100311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 143301 # number of overall hits 100411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4541852 # number of overall hits 100511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3641365 # number of overall hits 100611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::total 8562442 # number of overall hits 100711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9735 # number of ReadReq misses 100811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7677 # number of ReadReq misses 100911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::total 17412 # number of ReadReq misses 101011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 241880 # number of UpgradeReq misses 101111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_misses::total 241880 # number of UpgradeReq misses 101211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190989 # number of SCUpgradeReq misses 101311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 190989 # number of SCUpgradeReq misses 101411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 17 # number of SCUpgradeFailReq misses 101511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 17 # number of SCUpgradeFailReq misses 101611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 251163 # number of ReadExReq misses 101711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_misses::total 251163 # number of ReadExReq misses 101811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 458947 # number of ReadCleanReq misses 101911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 458947 # number of ReadCleanReq misses 102011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 908465 # number of ReadSharedReq misses 102111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 908465 # number of ReadSharedReq misses 102211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 565429 # number of InvalidateReq misses 102311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_misses::total 565429 # number of InvalidateReq misses 102411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9735 # number of demand (read+write) misses 102511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 7677 # number of demand (read+write) misses 102611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 458947 # number of demand (read+write) misses 102711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1159628 # number of demand (read+write) misses 102811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::total 1635987 # number of demand (read+write) misses 102911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9735 # number of overall misses 103011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 7677 # number of overall misses 103111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 458947 # number of overall misses 103211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1159628 # number of overall misses 103311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::total 1635987 # number of overall misses 103411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 390278500 # number of ReadReq miss cycles 103511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 327424000 # number of ReadReq miss cycles 103611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 717702500 # number of ReadReq miss cycles 103711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3214093500 # number of UpgradeReq miss cycles 103811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3214093500 # number of UpgradeReq miss cycles 103911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1890945000 # number of SCUpgradeReq miss cycles 104011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1890945000 # number of SCUpgradeReq miss cycles 104111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5616997 # number of SCUpgradeFailReq miss cycles 104211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5616997 # number of SCUpgradeFailReq miss cycles 104311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16356012499 # number of ReadExReq miss cycles 104411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 16356012499 # number of ReadExReq miss cycles 104511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18207706500 # number of ReadCleanReq miss cycles 104611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 18207706500 # number of ReadCleanReq miss cycles 104711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36093910000 # number of ReadSharedReq miss cycles 104811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 36093910000 # number of ReadSharedReq miss cycles 104911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 390401000 # number of InvalidateReq miss cycles 105011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 390401000 # number of InvalidateReq miss cycles 105111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 390278500 # number of demand (read+write) miss cycles 105211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 327424000 # number of demand (read+write) miss cycles 105311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 18207706500 # number of demand (read+write) miss cycles 105411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 52449922499 # number of demand (read+write) miss cycles 105511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::total 71375331499 # number of demand (read+write) miss cycles 105611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 390278500 # number of overall miss cycles 105711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 327424000 # number of overall miss cycles 105811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 18207706500 # number of overall miss cycles 105911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 52449922499 # number of overall miss cycles 106011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::total 71375331499 # number of overall miss cycles 106111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 245659 # number of ReadReq accesses(hits+misses) 106211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150978 # number of ReadReq accesses(hits+misses) 106311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::total 396637 # number of ReadReq accesses(hits+misses) 106411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3602563 # number of WritebackDirty accesses(hits+misses) 106511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3602563 # number of WritebackDirty accesses(hits+misses) 106611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6855894 # number of WritebackClean accesses(hits+misses) 106711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6855894 # number of WritebackClean accesses(hits+misses) 106811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242269 # number of UpgradeReq accesses(hits+misses) 106911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 242269 # number of UpgradeReq accesses(hits+misses) 107011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190989 # number of SCUpgradeReq accesses(hits+misses) 107111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 190989 # number of SCUpgradeReq accesses(hits+misses) 107211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 17 # number of SCUpgradeFailReq accesses(hits+misses) 107311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 17 # number of SCUpgradeFailReq accesses(hits+misses) 107411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1106507 # number of ReadExReq accesses(hits+misses) 107511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1106507 # number of ReadExReq accesses(hits+misses) 107611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5000799 # number of ReadCleanReq accesses(hits+misses) 107711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5000799 # number of ReadCleanReq accesses(hits+misses) 107811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3694486 # number of ReadSharedReq accesses(hits+misses) 107911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3694486 # number of ReadSharedReq accesses(hits+misses) 108011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 748142 # number of InvalidateReq accesses(hits+misses) 108111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 748142 # number of InvalidateReq accesses(hits+misses) 108211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 245659 # number of demand (read+write) accesses 108311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150978 # number of demand (read+write) accesses 108411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5000799 # number of demand (read+write) accesses 108511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4800993 # number of demand (read+write) accesses 108611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::total 10198429 # number of demand (read+write) accesses 108711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 245659 # number of overall (read+write) accesses 108811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150978 # number of overall (read+write) accesses 108911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5000799 # number of overall (read+write) accesses 109011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4800993 # number of overall (read+write) accesses 109111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::total 10198429 # number of overall (read+write) accesses 109211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for ReadReq accesses 109311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050848 # miss rate for ReadReq accesses 109411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.043899 # miss rate for ReadReq accesses 109511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998394 # miss rate for UpgradeReq accesses 109611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998394 # miss rate for UpgradeReq accesses 109711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 109811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 109910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110010535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 110111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.226987 # miss rate for ReadExReq accesses 110211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.226987 # miss rate for ReadExReq accesses 110311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091775 # miss rate for ReadCleanReq accesses 110411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091775 # miss rate for ReadCleanReq accesses 110511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.245898 # miss rate for ReadSharedReq accesses 110611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.245898 # miss rate for ReadSharedReq accesses 110711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755778 # miss rate for InvalidateReq accesses 110811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755778 # miss rate for InvalidateReq accesses 110911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for demand accesses 111011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050848 # miss rate for demand accesses 111111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091775 # miss rate for demand accesses 111211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241539 # miss rate for demand accesses 111311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::total 0.160416 # miss rate for demand accesses 111411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039628 # miss rate for overall accesses 111511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050848 # miss rate for overall accesses 111611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091775 # miss rate for overall accesses 111711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241539 # miss rate for overall accesses 111811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::total 0.160416 # miss rate for overall accesses 111911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average ReadReq miss latency 112011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42649.993487 # average ReadReq miss latency 112111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 41218.843326 # average ReadReq miss latency 112211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13287.967174 # average UpgradeReq miss latency 112311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13287.967174 # average UpgradeReq miss latency 112411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9900.805806 # average SCUpgradeReq miss latency 112511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9900.805806 # average SCUpgradeReq miss latency 112611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 330411.588235 # average SCUpgradeFailReq miss latency 112711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 330411.588235 # average SCUpgradeFailReq miss latency 112811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65121.106608 # average ReadExReq miss latency 112911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65121.106608 # average ReadExReq miss latency 113011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39672.786836 # average ReadCleanReq miss latency 113111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39672.786836 # average ReadCleanReq miss latency 113211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39730.655556 # average ReadSharedReq miss latency 113311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39730.655556 # average ReadSharedReq miss latency 113411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 690.450967 # average InvalidateReq miss latency 113511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 690.450967 # average InvalidateReq miss latency 113611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average overall miss latency 113711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42649.993487 # average overall miss latency 113811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39672.786836 # average overall miss latency 113911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 114011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 43628.299919 # average overall miss latency 114111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40090.241397 # average overall miss latency 114211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42649.993487 # average overall miss latency 114311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39672.786836 # average overall miss latency 114411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 114511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 43628.299919 # average overall miss latency 114610628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114710535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114810628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 114910535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 115010628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 115110535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 115210535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 115310535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 115411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks 115511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.writebacks::total 1473434 # number of writebacks 115611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits 115711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5831 # number of ReadExReq MSHR hits 115811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 658 # number of ReadSharedReq MSHR hits 115911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 658 # number of ReadSharedReq MSHR hits 116011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 6489 # number of demand (read+write) MSHR hits 116111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_hits::total 6489 # number of demand (read+write) MSHR hits 116211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 6489 # number of overall MSHR hits 116311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_hits::total 6489 # number of overall MSHR hits 116411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9735 # number of ReadReq MSHR misses 116511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7677 # number of ReadReq MSHR misses 116611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 17412 # number of ReadReq MSHR misses 116711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 676944 # number of HardPFReq MSHR misses 116811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 676944 # number of HardPFReq MSHR misses 116911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 241880 # number of UpgradeReq MSHR misses 117011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 241880 # number of UpgradeReq MSHR misses 117111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190989 # number of SCUpgradeReq MSHR misses 117211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190989 # number of SCUpgradeReq MSHR misses 117311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 17 # number of SCUpgradeFailReq MSHR misses 117411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 17 # number of SCUpgradeFailReq MSHR misses 117511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 245332 # number of ReadExReq MSHR misses 117611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 245332 # number of ReadExReq MSHR misses 117711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 458947 # number of ReadCleanReq MSHR misses 117811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 458947 # number of ReadCleanReq MSHR misses 117911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 907807 # number of ReadSharedReq MSHR misses 118011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 907807 # number of ReadSharedReq MSHR misses 118111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 565429 # number of InvalidateReq MSHR misses 118211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 565429 # number of InvalidateReq MSHR misses 118311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9735 # number of demand (read+write) MSHR misses 118411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7677 # number of demand (read+write) MSHR misses 118511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 458947 # number of demand (read+write) MSHR misses 118611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1153139 # number of demand (read+write) MSHR misses 118711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::total 1629498 # number of demand (read+write) MSHR misses 118811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9735 # number of overall MSHR misses 118911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7677 # number of overall MSHR misses 119011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 458947 # number of overall MSHR misses 119111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1153139 # number of overall MSHR misses 119211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 676944 # number of overall MSHR misses 119311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::total 2306442 # number of overall MSHR misses 119410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 119511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 119611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72575 # number of ReadReq MSHR uncacheable 119711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 119811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 119910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 120011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 120111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 101499 # number of overall MSHR uncacheable misses 120211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of ReadReq MSHR miss cycles 120311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 281362000 # number of ReadReq MSHR miss cycles 120411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 613230500 # number of ReadReq MSHR miss cycles 120511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of HardPFReq MSHR miss cycles 120611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37650647602 # number of HardPFReq MSHR miss cycles 120711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7335732000 # number of UpgradeReq MSHR miss cycles 120811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7335732000 # number of UpgradeReq MSHR miss cycles 120911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3705379500 # number of SCUpgradeReq MSHR miss cycles 121011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3705379500 # number of SCUpgradeReq MSHR miss cycles 121111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5238997 # number of SCUpgradeFailReq MSHR miss cycles 121211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5238997 # number of SCUpgradeFailReq MSHR miss cycles 121311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14201538999 # number of ReadExReq MSHR miss cycles 121411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14201538999 # number of ReadExReq MSHR miss cycles 121511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15454024500 # number of ReadCleanReq MSHR miss cycles 121611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15454024500 # number of ReadCleanReq MSHR miss cycles 121711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30580591000 # number of ReadSharedReq MSHR miss cycles 121811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30580591000 # number of ReadSharedReq MSHR miss cycles 121911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39622342000 # number of InvalidateReq MSHR miss cycles 122011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39622342000 # number of InvalidateReq MSHR miss cycles 122111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of demand (read+write) MSHR miss cycles 122211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 281362000 # number of demand (read+write) MSHR miss cycles 122311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15454024500 # number of demand (read+write) MSHR miss cycles 122411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44782129999 # number of demand (read+write) MSHR miss cycles 122511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 60849384999 # number of demand (read+write) MSHR miss cycles 122611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 331868500 # number of overall MSHR miss cycles 122711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 281362000 # number of overall MSHR miss cycles 122811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15454024500 # number of overall MSHR miss cycles 122911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44782129999 # number of overall MSHR miss cycles 123011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of overall MSHR miss cycles 123111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 98500032601 # number of overall MSHR miss cycles 123211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 123311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5203415000 # number of ReadReq MSHR uncacheable cycles 123411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10834186500 # number of ReadReq MSHR uncacheable cycles 123511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles 123611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles 123711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 123811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles 123911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles 124011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for ReadReq accesses 124111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for ReadReq accesses 124211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043899 # mshr miss rate for ReadReq accesses 124310535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 124410535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 124511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses 124611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses 124711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 124811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 124910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 125010535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 125111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221718 # mshr miss rate for ReadExReq accesses 125211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221718 # mshr miss rate for ReadExReq accesses 125311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for ReadCleanReq accesses 125411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091775 # mshr miss rate for ReadCleanReq accesses 125511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245719 # mshr miss rate for ReadSharedReq accesses 125611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245719 # mshr miss rate for ReadSharedReq accesses 125711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755778 # mshr miss rate for InvalidateReq accesses 125811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755778 # mshr miss rate for InvalidateReq accesses 125911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for demand accesses 126011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for demand accesses 126111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for demand accesses 126211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for demand accesses 126311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.159779 # mshr miss rate for demand accesses 126411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for overall accesses 126511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for overall accesses 126611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for overall accesses 126711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for overall accesses 126810535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 126911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.226157 # mshr miss rate for overall accesses 127011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average ReadReq mshr miss latency 127111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average ReadReq mshr miss latency 127211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326 # average ReadReq mshr miss latency 127311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average HardPFReq mshr miss latency 127411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748 # average HardPFReq mshr miss latency 127511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817 # average UpgradeReq mshr miss latency 127611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817 # average UpgradeReq mshr miss latency 127711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006 # average SCUpgradeReq mshr miss latency 127811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006 # average SCUpgradeReq mshr miss latency 127911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118 # average SCUpgradeFailReq mshr miss latency 128011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118 # average SCUpgradeFailReq mshr miss latency 128111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480 # average ReadExReq mshr miss latency 128211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480 # average ReadExReq mshr miss latency 128311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average ReadCleanReq mshr miss latency 128411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836 # average ReadCleanReq mshr miss latency 128511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156 # average ReadSharedReq mshr miss latency 128611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156 # average ReadSharedReq mshr miss latency 128711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676 # average InvalidateReq mshr miss latency 128811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676 # average InvalidateReq mshr miss latency 128911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency 129011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 129111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 129211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 129311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589 # average overall mshr miss latency 129411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency 129511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 129611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 129711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 129811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency 129911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency 130011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 130111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency 130211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency 130311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency 130411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency 130511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 130611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency 130711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency 130810535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 130911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. 131011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. 131111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 131211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. 131311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 131411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 131511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution 131611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution 131711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28925 # Transaction distribution 131811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28924 # Transaction distribution 131911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5081322 # Transaction distribution 132011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6856856 # Transaction distribution 132111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2248329 # Transaction distribution 132211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 834929 # Transaction distribution 132311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 132411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 427184 # Transaction distribution 132511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348871 # Transaction distribution 132611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 496915 # Transaction distribution 132711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution 132811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 132911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1135852 # Transaction distribution 133011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1114697 # Transaction distribution 133111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5000799 # Transaction distribution 133211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4556956 # Transaction distribution 133311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 799366 # Transaction distribution 133411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 748142 # Transaction distribution 133511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15088134 # Packet count per connected master and slave (bytes) 133611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17701155 # Packet count per connected master and slave (bytes) 133711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 319339 # Packet count per connected master and slave (bytes) 133811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542421 # Packet count per connected master and slave (bytes) 133911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count::total 33651049 # Packet count per connected master and slave (bytes) 134011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 640241940 # Cumulative packet size per connected master and slave (bytes) 134111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663021135 # Cumulative packet size per connected master and slave (bytes) 134211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1207824 # Cumulative packet size per connected master and slave (bytes) 134311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1965272 # Cumulative packet size per connected master and slave (bytes) 134411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size::total 1306436171 # Cumulative packet size per connected master and slave (bytes) 134511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoops 6076867 # Total snoops (count) 134611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::samples 17397758 # Request fanout histogram 134711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.114750 # Request fanout histogram 134811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.318774 # Request fanout histogram 134910535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::0 15401663 88.53% 88.53% # Request fanout histogram 135111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::1 1995797 11.47% 100.00% # Request fanout histogram 135211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram 135310535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 135411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 135510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 135611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::total 17397758 # Request fanout histogram 135711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 21478508994 # Layer occupancy (ticks) 135810535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 135911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 177190009 # Layer occupancy (ticks) 136010535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7544323500 # Layer occupancy (ticks) 136210535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 136311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7836374127 # Layer occupancy (ticks) 136410535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 136511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer2.occupancy 168361000 # Layer occupancy (ticks) 136610535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 136711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer3.occupancy 296762000 # Layer occupancy (ticks) 136810535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 136910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 137010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 137110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 137210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 137610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 137710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 137810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 137910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 138010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 138110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 138210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 138310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 138410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 139010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 139110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 139310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 139510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 139610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 139710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walks 108457 # Table walker walks requested 139911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLong 108457 # Table walker walks initiated with long descriptors 140011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9827 # Level at which table walker walks with long descriptors terminate 140111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84631 # Level at which table walker walks with long descriptors terminate 140211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 140311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::samples 108435 # Table walker wait (enqueue to first request) latency 140411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.073777 # Table walker wait (enqueue to first request) latency 140511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 24.294348 # Table walker wait (enqueue to first request) latency 140611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 108434 100.00% 100.00% # Table walker wait (enqueue to first request) latency 140711353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 140811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::total 108435 # Table walker wait (enqueue to first request) latency 140911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 94480 # Table walker service (enqueue to completion) latency 141011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930 # Table walker service (enqueue to completion) latency 141111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554 # Table walker service (enqueue to completion) latency 141211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287 # Table walker service (enqueue to completion) latency 141311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 93351 98.81% 98.81% # Table walker service (enqueue to completion) latency 141411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 176 0.19% 98.99% # Table walker service (enqueue to completion) latency 141511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 798 0.84% 99.84% # Table walker service (enqueue to completion) latency 141611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.04% 99.88% # Table walker service (enqueue to completion) latency 141711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.93% # Table walker service (enqueue to completion) latency 141811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.03% 99.95% # Table walker service (enqueue to completion) latency 141911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.03% 99.98% # Table walker service (enqueue to completion) latency 142011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 142111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 142211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 142311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::total 94480 # Table walker service (enqueue to completion) latency 142511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksPending::samples 3353012192 # Table walker pending requests distribution 142611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksPending::mean 1.550742 # Table walker pending requests distribution 142711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksPending::0 -1846644332 -55.07% -55.07% # Table walker pending requests distribution 142811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksPending::1 5199656524 155.07% 100.00% # Table walker pending requests distribution 142911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksPending::total 3353012192 # Table walker pending requests distribution 143011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::4K 84631 89.60% 89.60% # Table walker page sizes translated 143111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9827 10.40% 100.00% # Table walker page sizes translated 143211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::total 94458 # Table walker page sizes translated 143311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108457 # Table walker requests started/completed, data/inst 143410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108457 # Table walker requests started/completed, data/inst 143611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 94458 # Table walker requests started/completed, data/inst 143710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 94458 # Table walker requests started/completed, data/inst 143911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 202915 # Table walker requests started/completed, data/inst 144010535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 144110535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 144211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_hits 79507348 # DTB read hits 144311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_misses 80723 # DTB read misses 144411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_hits 72319570 # DTB write hits 144511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_misses 27734 # DTB write misses 144610535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 144710535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 144911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 145011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_entries 39844 # Number of entries that have been flushed from TLB 145110535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 145211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.prefetch_faults 4607 # Number of TLB faults due to prefetch 145310535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.perms_faults 10580 # Number of TLB faults due to permissions restrictions 145511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_accesses 79588071 # DTB read accesses 145611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_accesses 72347304 # DTB write accesses 145710535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 145811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.hits 151826918 # DTB hits 145911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.misses 108457 # DTB misses 146011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.accesses 151935375 # DTB accesses 146110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 146310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 146510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 146710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 146810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 146910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 147010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 147110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 147210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 147310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 147410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 147510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 147610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 147810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 148210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 148310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 148410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 148510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 148610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 148710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 148810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 148910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 149011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walks 59789 # Table walker walks requested 149111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLong 59789 # Table walker walks initiated with long descriptors 149211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 555 # Level at which table walker walks with long descriptors terminate 149311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 54230 # Level at which table walker walks with long descriptors terminate 149411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::samples 59789 # Table walker wait (enqueue to first request) latency 149511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::0 59789 100.00% 100.00% # Table walker wait (enqueue to first request) latency 149611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::total 59789 # Table walker wait (enqueue to first request) latency 149711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::samples 54785 # Table walker service (enqueue to completion) latency 149811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26806.178699 # Table walker service (enqueue to completion) latency 149911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376 # Table walker service (enqueue to completion) latency 150011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406 # Table walker service (enqueue to completion) latency 150111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 53612 97.86% 97.86% # Table walker service (enqueue to completion) latency 150211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 36 0.07% 97.92% # Table walker service (enqueue to completion) latency 150311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 992 1.81% 99.74% # Table walker service (enqueue to completion) latency 150411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.79% # Table walker service (enqueue to completion) latency 150511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 57 0.10% 99.89% # Table walker service (enqueue to completion) latency 150611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.91% # Table walker service (enqueue to completion) latency 150711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 37 0.07% 99.98% # Table walker service (enqueue to completion) latency 150811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.98% # Table walker service (enqueue to completion) latency 150911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 151011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 151111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 151211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::total 54785 # Table walker service (enqueue to completion) latency 151311353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution 151411353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution 151511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution 151611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::4K 54230 98.99% 98.99% # Table walker page sizes translated 151711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::2M 555 1.01% 100.00% # Table walker page sizes translated 151811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::total 54785 # Table walker page sizes translated 151910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59789 # Table walker requests started/completed, data/inst 152111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 59789 # Table walker requests started/completed, data/inst 152210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 152311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54785 # Table walker requests started/completed, data/inst 152411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54785 # Table walker requests started/completed, data/inst 152511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin::total 114574 # Table walker requests started/completed, data/inst 152611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_hits 420546617 # ITB inst hits 152711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_misses 59789 # ITB inst misses 152810535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 152910535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 153010535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 153110535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 153210535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 153310535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 153411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID 153511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID 153611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_entries 27682 # Number of entries that have been flushed from TLB 153710535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153810535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153910535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154010535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154110535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 154210535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 154311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_accesses 420606406 # ITB inst accesses 154411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.hits 420546617 # DTB hits 154511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.misses 59789 # DTB misses 154611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.accesses 420606406 # DTB accesses 154711374Ssteve.reinhardt@amd.comsystem.cpu1.numCycles 94920662633 # number of cpu cycles simulated 154810535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 154910535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 155011167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 155111374Ssteve.reinhardt@amd.comsystem.cpu1.kern.inst.quiesce 5531 # number of quiesce instructions executed 155211374Ssteve.reinhardt@amd.comsystem.cpu1.committedInsts 420277684 # Number of instructions committed 155311374Ssteve.reinhardt@amd.comsystem.cpu1.committedOps 495146949 # Number of ops (including micro ops) committed 155411374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_alu_accesses 454880180 # Number of integer alu accesses 155511374Ssteve.reinhardt@amd.comsystem.cpu1.num_fp_alu_accesses 506575 # Number of float alu accesses 155611374Ssteve.reinhardt@amd.comsystem.cpu1.num_func_calls 25039229 # number of times a function call or return occured 155711374Ssteve.reinhardt@amd.comsystem.cpu1.num_conditional_control_insts 63957319 # number of instructions that are conditional controls 155811374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_insts 454880180 # number of integer instructions 155911374Ssteve.reinhardt@amd.comsystem.cpu1.num_fp_insts 506575 # number of float instructions 156011374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_register_reads 664278142 # number of times the integer registers were read 156111374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_register_writes 361063382 # number of times the integer registers were written 156211374Ssteve.reinhardt@amd.comsystem.cpu1.num_fp_register_reads 809640 # number of times the floating registers were read 156311374Ssteve.reinhardt@amd.comsystem.cpu1.num_fp_register_writes 450820 # number of times the floating registers were written 156411374Ssteve.reinhardt@amd.comsystem.cpu1.num_cc_register_reads 110083158 # number of times the CC registers were read 156511374Ssteve.reinhardt@amd.comsystem.cpu1.num_cc_register_writes 109779727 # number of times the CC registers were written 156611374Ssteve.reinhardt@amd.comsystem.cpu1.num_mem_refs 151817768 # number of memory refs 156711374Ssteve.reinhardt@amd.comsystem.cpu1.num_load_insts 79504880 # Number of load instructions 156811374Ssteve.reinhardt@amd.comsystem.cpu1.num_store_insts 72312888 # Number of store instructions 156911374Ssteve.reinhardt@amd.comsystem.cpu1.num_idle_cycles 93883487625.302155 # Number of idle cycles 157011374Ssteve.reinhardt@amd.comsystem.cpu1.num_busy_cycles 1037175007.697842 # Number of busy cycles 157111374Ssteve.reinhardt@amd.comsystem.cpu1.not_idle_fraction 0.010927 # Percentage of non-idle cycles 157211374Ssteve.reinhardt@amd.comsystem.cpu1.idle_fraction 0.989073 # Percentage of idle cycles 157311374Ssteve.reinhardt@amd.comsystem.cpu1.Branches 93646526 # Number of branches fetched 157411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 157511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntAlu 342430715 69.12% 69.12% # Class of executed instruction 157611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntMult 1035788 0.21% 69.33% # Class of executed instruction 157711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntDiv 58966 0.01% 69.34% # Class of executed instruction 157811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.34% # Class of executed instruction 157911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.34% # Class of executed instruction 158011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.34% # Class of executed instruction 158111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.34% # Class of executed instruction 158211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.34% # Class of executed instruction 158311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.34% # Class of executed instruction 158411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.34% # Class of executed instruction 158511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.34% # Class of executed instruction 158611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.34% # Class of executed instruction 158711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.34% # Class of executed instruction 158811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.34% # Class of executed instruction 158911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.34% # Class of executed instruction 159011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.34% # Class of executed instruction 159111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.34% # Class of executed instruction 159211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.34% # Class of executed instruction 159311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.34% # Class of executed instruction 159411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.34% # Class of executed instruction 159511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.34% # Class of executed instruction 159611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.34% # Class of executed instruction 159711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.34% # Class of executed instruction 159811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.34% # Class of executed instruction 159911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.34% # Class of executed instruction 160011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMisc 72713 0.01% 69.36% # Class of executed instruction 160111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction 160211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction 160311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction 160411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::MemRead 79504880 16.05% 85.40% # Class of executed instruction 160511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::MemWrite 72312888 14.60% 100.00% # Class of executed instruction 160610535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 160710535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 160811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::total 495415992 # Class of executed instruction 160911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.replacements 5111729 # number of replacements 161011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.tagsinuse 453.815972 # Cycle average of tags in use 161111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.total_refs 146515734 # Total number of references to valid blocks. 161211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.sampled_refs 5112105 # Sample count of references to valid blocks. 161311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.avg_refs 28.660549 # Average number of references to valid blocks. 161411353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. 161511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 453.815972 # Average occupied blocks per requestor 161611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.886359 # Average percentage of cache occupancy 161711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_percent::total 0.886359 # Average percentage of cache occupancy 161811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id 161911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 373 # Occupied blocks per task id 162011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 162111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 162211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.tag_accesses 308802786 # Number of tag accesses 162311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.data_accesses 308802786 # Number of data accesses 162411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 74029008 # number of ReadReq hits 162511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_hits::total 74029008 # number of ReadReq hits 162611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68561672 # number of WriteReq hits 162711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_hits::total 68561672 # number of WriteReq hits 162811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits 162911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits 163011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits 163111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits 163211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits 163311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits 163411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits 163511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits 163611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits 163711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits 163811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits 163911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_hits::total 142761779 # number of overall hits 164011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses 164111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses 164211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses 164311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses 164411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses 164511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses 164611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses 164711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses 164811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses 164911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses 165011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses 165111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses 165211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses 165311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses 165411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses 165511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_misses::total 4814576 # number of overall misses 165611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles 165711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles 165811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles 165911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_latency::total 30099423000 # number of WriteReq miss cycles 166011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18095848000 # number of WriteLineReq miss cycles 166111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 18095848000 # number of WriteLineReq miss cycles 166211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2729020500 # number of LoadLockedReq miss cycles 166311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles 166411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles 166511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles 166611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles 166711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles 166811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles 166911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles 167011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles 167111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles 167211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) 167311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) 167411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) 167511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) 167611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) 167711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) 167811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) 167911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) 168011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) 168111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) 168211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) 168311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) 168411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses 168511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses 168611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses 168711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses 168811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses 168911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses 169011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses 169111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses 169211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses 169311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses 169411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses 169511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses 169611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses 169711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses 169811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses 169911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses 170011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses 170111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses 170211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses 170311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses 170411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency 170511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency 170611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency 170711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency 170811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency 170911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency 171011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency 171111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency 171211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency 171311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency 171410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 171510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 171611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency 171711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency 171811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency 171911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency 172010535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172110535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172210535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172310535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 172410535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172510535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172610585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 172710535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 172811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks 172911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.writebacks::total 5111729 # number of writebacks 173011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits 173111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 16692 # number of ReadReq MSHR hits 173211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 173311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 173411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44979 # number of LoadLockedReq MSHR hits 173511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44979 # number of LoadLockedReq MSHR hits 173611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 17094 # number of demand (read+write) MSHR hits 173711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_hits::total 17094 # number of demand (read+write) MSHR hits 173811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 17094 # number of overall MSHR hits 173911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_hits::total 17094 # number of overall MSHR hits 174011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858353 # number of ReadReq MSHR misses 174111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2858353 # number of ReadReq MSHR misses 174211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1312828 # number of WriteReq MSHR misses 174311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1312828 # number of WriteReq MSHR misses 174411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses 174511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses 174611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses 174711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses 174811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 174911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 175011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses 175111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses 175211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses 175311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses 175411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses 175511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses 175611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 175711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable 175811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 175911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 176011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 176111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses 176211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles 176311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles 176411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28757951500 # number of WriteReq MSHR miss cycles 176511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 28757951500 # number of WriteReq MSHR miss cycles 176611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14279978500 # number of SoftPFReq MSHR miss cycles 176711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14279978500 # number of SoftPFReq MSHR miss cycles 176811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles 176911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles 177011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles 177111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles 177211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles 177311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles 177411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles 177511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles 177611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles 177711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles 177811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles 177911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles 178011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles 178111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles 178211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles 178311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles 178411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles 178511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles 178611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses 178711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses 178811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses 178911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses 179011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses 179111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses 179211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses 179311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses 179411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses 179511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses 179611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses 179711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses 179811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses 179911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses 180011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses 180111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses 180211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency 180311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency 180411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency 180511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency 180611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency 180711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency 180811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency 180911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency 181011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency 181111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency 181211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency 181311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency 181410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 181510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 181611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency 181711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency 181811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency 181911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency 182011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency 182111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency 182211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency 182311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency 182411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency 182511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency 182610535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 182711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.replacements 4920276 # number of replacements 182811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use 182911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. 183011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. 183111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. 183211353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. 183311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor 183411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy 183511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_percent::total 0.968867 # Average percentage of cache occupancy 183610535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 183711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id 183811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id 183910535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 184011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.tag_accesses 846014027 # Number of tag accesses 184111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.data_accesses 846014027 # Number of data accesses 184211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 415625824 # number of ReadReq hits 184311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_hits::total 415625824 # number of ReadReq hits 184411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_hits::cpu1.inst 415625824 # number of demand (read+write) hits 184511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_hits::total 415625824 # number of demand (read+write) hits 184611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_hits::cpu1.inst 415625824 # number of overall hits 184711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_hits::total 415625824 # number of overall hits 184811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4920793 # number of ReadReq misses 184911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_misses::total 4920793 # number of ReadReq misses 185011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_misses::cpu1.inst 4920793 # number of demand (read+write) misses 185111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_misses::total 4920793 # number of demand (read+write) misses 185211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_misses::cpu1.inst 4920793 # number of overall misses 185311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_misses::total 4920793 # number of overall misses 185411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53750624000 # number of ReadReq miss cycles 185511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_latency::total 53750624000 # number of ReadReq miss cycles 185611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 53750624000 # number of demand (read+write) miss cycles 185711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_latency::total 53750624000 # number of demand (read+write) miss cycles 185811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 53750624000 # number of overall miss cycles 185911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_latency::total 53750624000 # number of overall miss cycles 186011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 420546617 # number of ReadReq accesses(hits+misses) 186111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_accesses::total 420546617 # number of ReadReq accesses(hits+misses) 186211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_accesses::cpu1.inst 420546617 # number of demand (read+write) accesses 186311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_accesses::total 420546617 # number of demand (read+write) accesses 186411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_accesses::cpu1.inst 420546617 # number of overall (read+write) accesses 186511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_accesses::total 420546617 # number of overall (read+write) accesses 186611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011701 # miss rate for ReadReq accesses 186711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011701 # miss rate for ReadReq accesses 186811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011701 # miss rate for demand accesses 186911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_rate::total 0.011701 # miss rate for demand accesses 187011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011701 # miss rate for overall accesses 187111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_rate::total 0.011701 # miss rate for overall accesses 187211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10923.162994 # average ReadReq miss latency 187311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10923.162994 # average ReadReq miss latency 187411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 187511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_miss_latency::total 10923.162994 # average overall miss latency 187611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 187711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency 187810535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187910535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188010535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188110535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 188210535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 188310535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188410535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 188510535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 188611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks 188711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.writebacks::total 4920276 # number of writebacks 188811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # number of ReadReq MSHR misses 188911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4920793 # number of ReadReq MSHR misses 189011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4920793 # number of demand (read+write) MSHR misses 189111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_misses::total 4920793 # number of demand (read+write) MSHR misses 189211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4920793 # number of overall MSHR misses 189311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_misses::total 4920793 # number of overall MSHR misses 189410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 189510827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 189610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 189710827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 189811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51290227500 # number of ReadReq MSHR miss cycles 189911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 51290227500 # number of ReadReq MSHR miss cycles 190011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51290227500 # number of demand (read+write) MSHR miss cycles 190111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_latency::total 51290227500 # number of demand (read+write) MSHR miss cycles 190211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51290227500 # number of overall MSHR miss cycles 190311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_latency::total 51290227500 # number of overall MSHR miss cycles 190411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14763500 # number of ReadReq MSHR uncacheable cycles 190511353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14763500 # number of ReadReq MSHR uncacheable cycles 190611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14763500 # number of overall MSHR uncacheable cycles 190711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 14763500 # number of overall MSHR uncacheable cycles 190811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for ReadReq accesses 190911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011701 # mshr miss rate for ReadReq accesses 191011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for demand accesses 191111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011701 # mshr miss rate for demand accesses 191211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for overall accesses 191311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011701 # mshr miss rate for overall accesses 191411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average ReadReq mshr miss latency 191511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10423.162994 # average ReadReq mshr miss latency 191611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 191711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 191811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 191911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 192011353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency 192111353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency 192211353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency 192311353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency 192410535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 192511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued 192611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified 192711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue 192810628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 192910628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 193011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 877146 # number of prefetches not generated due to page crossing 193111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.replacements 1947890 # number of replacements 193211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.tagsinuse 13258.686630 # Cycle average of tags in use 193311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.total_refs 14658232 # Total number of references to valid blocks. 193411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.sampled_refs 1963173 # Sample count of references to valid blocks. 193511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.avg_refs 7.466602 # Average number of references to valid blocks. 193611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.warmup_cycle 10431898029000 # Cycle when the warmup percentage was hit. 193711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12337.010876 # Average occupied blocks per requestor 193811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.483445 # Average occupied blocks per requestor 193911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.799198 # Average occupied blocks per requestor 194011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 783.393111 # Average occupied blocks per requestor 194111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.752991 # Average percentage of cache occupancy 194211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003936 # Average percentage of cache occupancy 194311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004504 # Average percentage of cache occupancy 194411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.047815 # Average percentage of cache occupancy 194511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::total 0.809246 # Average percentage of cache occupancy 194611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1528 # Occupied blocks per task id 194711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 194811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 13687 # Occupied blocks per task id 194911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 43 # Occupied blocks per task id 195011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 698 # Occupied blocks per task id 195111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 787 # Occupied blocks per task id 195211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id 195311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 29 # Occupied blocks per task id 195411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 680 # Occupied blocks per task id 195511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6525 # Occupied blocks per task id 195611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6482 # Occupied blocks per task id 195711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.093262 # Percentage of cache occupancy per task id 195811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 195911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.835388 # Percentage of cache occupancy per task id 196011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.tag_accesses 340572805 # Number of tag accesses 196111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.data_accesses 340572805 # Number of data accesses 196211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 256581 # number of ReadReq hits 196311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155471 # number of ReadReq hits 196411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::total 412052 # number of ReadReq hits 196511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3259472 # number of WritebackDirty hits 196611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3259472 # number of WritebackDirty hits 196711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6771640 # number of WritebackClean hits 196811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_hits::total 6771640 # number of WritebackClean hits 196911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 476 # number of UpgradeReq hits 197011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_hits::total 476 # number of UpgradeReq hits 197111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 874528 # number of ReadExReq hits 197211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_hits::total 874528 # number of ReadExReq hits 197311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4470558 # number of ReadCleanReq hits 197411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4470558 # number of ReadCleanReq hits 197511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2746836 # number of ReadSharedReq hits 197611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2746836 # number of ReadSharedReq hits 197711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 216255 # number of InvalidateReq hits 197811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_hits::total 216255 # number of InvalidateReq hits 197911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 256581 # number of demand (read+write) hits 198011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155471 # number of demand (read+write) hits 198111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4470558 # number of demand (read+write) hits 198211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3621364 # number of demand (read+write) hits 198311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::total 8503974 # number of demand (read+write) hits 198411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 256581 # number of overall hits 198511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155471 # number of overall hits 198611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4470558 # number of overall hits 198711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3621364 # number of overall hits 198811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::total 8503974 # number of overall hits 198911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9634 # number of ReadReq misses 199011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8009 # number of ReadReq misses 199111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::total 17643 # number of ReadReq misses 199211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 195149 # number of UpgradeReq misses 199311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_misses::total 195149 # number of UpgradeReq misses 199411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193373 # number of SCUpgradeReq misses 199511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 193373 # number of SCUpgradeReq misses 199611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 14 # number of SCUpgradeFailReq misses 199711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 14 # number of SCUpgradeFailReq misses 199811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 244689 # number of ReadExReq misses 199911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_misses::total 244689 # number of ReadExReq misses 200011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 450235 # number of ReadCleanReq misses 200111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 450235 # number of ReadCleanReq misses 200211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 858358 # number of ReadSharedReq misses 200311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 858358 # number of ReadSharedReq misses 200411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265386 # number of InvalidateReq misses 200511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_misses::total 265386 # number of InvalidateReq misses 200611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9634 # number of demand (read+write) misses 200711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8009 # number of demand (read+write) misses 200811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 450235 # number of demand (read+write) misses 200911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1103047 # number of demand (read+write) misses 201011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::total 1570925 # number of demand (read+write) misses 201111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9634 # number of overall misses 201211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8009 # number of overall misses 201311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 450235 # number of overall misses 201411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1103047 # number of overall misses 201511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::total 1570925 # number of overall misses 201611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 459999000 # number of ReadReq miss cycles 201711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 417305500 # number of ReadReq miss cycles 201811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 877304500 # number of ReadReq miss cycles 201911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3163875000 # number of UpgradeReq miss cycles 202011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3163875000 # number of UpgradeReq miss cycles 202111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2039332500 # number of SCUpgradeReq miss cycles 202211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2039332500 # number of SCUpgradeReq miss cycles 202311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6154498 # number of SCUpgradeFailReq miss cycles 202411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6154498 # number of SCUpgradeFailReq miss cycles 202511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13641270998 # number of ReadExReq miss cycles 202611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 13641270998 # number of ReadExReq miss cycles 202711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17048494000 # number of ReadCleanReq miss cycles 202811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 17048494000 # number of ReadCleanReq miss cycles 202911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33667115000 # number of ReadSharedReq miss cycles 203011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 33667115000 # number of ReadSharedReq miss cycles 203111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 534332000 # number of InvalidateReq miss cycles 203211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 534332000 # number of InvalidateReq miss cycles 203311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 459999000 # number of demand (read+write) miss cycles 203411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 417305500 # number of demand (read+write) miss cycles 203511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 17048494000 # number of demand (read+write) miss cycles 203611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 47308385998 # number of demand (read+write) miss cycles 203711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::total 65234184498 # number of demand (read+write) miss cycles 203811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 459999000 # number of overall miss cycles 203911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 417305500 # number of overall miss cycles 204011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 17048494000 # number of overall miss cycles 204111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 47308385998 # number of overall miss cycles 204211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::total 65234184498 # number of overall miss cycles 204311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 266215 # number of ReadReq accesses(hits+misses) 204411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163480 # number of ReadReq accesses(hits+misses) 204511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::total 429695 # number of ReadReq accesses(hits+misses) 204611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3259472 # number of WritebackDirty accesses(hits+misses) 204711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3259472 # number of WritebackDirty accesses(hits+misses) 204811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6771640 # number of WritebackClean accesses(hits+misses) 204911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6771640 # number of WritebackClean accesses(hits+misses) 205011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 195625 # number of UpgradeReq accesses(hits+misses) 205111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 195625 # number of UpgradeReq accesses(hits+misses) 205211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193373 # number of SCUpgradeReq accesses(hits+misses) 205311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 193373 # number of SCUpgradeReq accesses(hits+misses) 205411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 14 # number of SCUpgradeFailReq accesses(hits+misses) 205511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 14 # number of SCUpgradeFailReq accesses(hits+misses) 205611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119217 # number of ReadExReq accesses(hits+misses) 205711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1119217 # number of ReadExReq accesses(hits+misses) 205811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4920793 # number of ReadCleanReq accesses(hits+misses) 205911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4920793 # number of ReadCleanReq accesses(hits+misses) 206011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3605194 # number of ReadSharedReq accesses(hits+misses) 206111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3605194 # number of ReadSharedReq accesses(hits+misses) 206211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 481641 # number of InvalidateReq accesses(hits+misses) 206311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 481641 # number of InvalidateReq accesses(hits+misses) 206411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 266215 # number of demand (read+write) accesses 206511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163480 # number of demand (read+write) accesses 206611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4920793 # number of demand (read+write) accesses 206711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4724411 # number of demand (read+write) accesses 206811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::total 10074899 # number of demand (read+write) accesses 206911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 266215 # number of overall (read+write) accesses 207011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163480 # number of overall (read+write) accesses 207111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4920793 # number of overall (read+write) accesses 207211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4724411 # number of overall (read+write) accesses 207311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::total 10074899 # number of overall (read+write) accesses 207411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for ReadReq accesses 207511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048991 # miss rate for ReadReq accesses 207611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.041059 # miss rate for ReadReq accesses 207711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997567 # miss rate for UpgradeReq accesses 207811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997567 # miss rate for UpgradeReq accesses 207911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 208011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 208110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 208210535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 208311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.218625 # miss rate for ReadExReq accesses 208411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.218625 # miss rate for ReadExReq accesses 208511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091496 # miss rate for ReadCleanReq accesses 208611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091496 # miss rate for ReadCleanReq accesses 208711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.238089 # miss rate for ReadSharedReq accesses 208811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.238089 # miss rate for ReadSharedReq accesses 208911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.551004 # miss rate for InvalidateReq accesses 209011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.551004 # miss rate for InvalidateReq accesses 209111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for demand accesses 209211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048991 # miss rate for demand accesses 209311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091496 # miss rate for demand accesses 209411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.233478 # miss rate for demand accesses 209511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::total 0.155925 # miss rate for demand accesses 209611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036189 # miss rate for overall accesses 209711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048991 # miss rate for overall accesses 209811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091496 # miss rate for overall accesses 209911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.233478 # miss rate for overall accesses 210011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::total 0.155925 # miss rate for overall accesses 210111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average ReadReq miss latency 210211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 52104.569859 # average ReadReq miss latency 210311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 49725.358499 # average ReadReq miss latency 210411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16212.611902 # average UpgradeReq miss latency 210511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16212.611902 # average UpgradeReq miss latency 210611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10546.107781 # average SCUpgradeReq miss latency 210711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10546.107781 # average SCUpgradeReq miss latency 210811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 439607 # average SCUpgradeFailReq miss latency 210911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 439607 # average SCUpgradeFailReq miss latency 211011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55749.424772 # average ReadExReq miss latency 211111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55749.424772 # average ReadExReq miss latency 211211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37865.767877 # average ReadCleanReq miss latency 211311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37865.767877 # average ReadCleanReq miss latency 211411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39222.696124 # average ReadSharedReq miss latency 211511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39222.696124 # average ReadSharedReq miss latency 211611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2013.414423 # average InvalidateReq miss latency 211711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2013.414423 # average InvalidateReq miss latency 211811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average overall miss latency 211911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 52104.569859 # average overall miss latency 212011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37865.767877 # average overall miss latency 212111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 212211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 41525.970048 # average overall miss latency 212311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47747.456923 # average overall miss latency 212411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 52104.569859 # average overall miss latency 212511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37865.767877 # average overall miss latency 212611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 212711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 41525.970048 # average overall miss latency 212810628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212910535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213010628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 213110535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 213210628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 213310535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213410535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 213510535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 213611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks 213711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.writebacks::total 1103180 # number of writebacks 213811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits 213911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 6962 # number of ReadExReq MSHR hits 214011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 454 # number of ReadSharedReq MSHR hits 214111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 454 # number of ReadSharedReq MSHR hits 214211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 214311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 214411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 7416 # number of demand (read+write) MSHR hits 214511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_hits::total 7416 # number of demand (read+write) MSHR hits 214611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 7416 # number of overall MSHR hits 214711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_hits::total 7416 # number of overall MSHR hits 214811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9634 # number of ReadReq MSHR misses 214911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8009 # number of ReadReq MSHR misses 215011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 17643 # number of ReadReq MSHR misses 215111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688811 # number of HardPFReq MSHR misses 215211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 688811 # number of HardPFReq MSHR misses 215311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 195149 # number of UpgradeReq MSHR misses 215411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 195149 # number of UpgradeReq MSHR misses 215511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193373 # number of SCUpgradeReq MSHR misses 215611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193373 # number of SCUpgradeReq MSHR misses 215711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 14 # number of SCUpgradeFailReq MSHR misses 215811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 14 # number of SCUpgradeFailReq MSHR misses 215911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237727 # number of ReadExReq MSHR misses 216011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 237727 # number of ReadExReq MSHR misses 216111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 450235 # number of ReadCleanReq MSHR misses 216211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 450235 # number of ReadCleanReq MSHR misses 216311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 857904 # number of ReadSharedReq MSHR misses 216411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 857904 # number of ReadSharedReq MSHR misses 216511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 265385 # number of InvalidateReq MSHR misses 216611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 265385 # number of InvalidateReq MSHR misses 216711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9634 # number of demand (read+write) MSHR misses 216811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8009 # number of demand (read+write) MSHR misses 216911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 450235 # number of demand (read+write) MSHR misses 217011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1095631 # number of demand (read+write) MSHR misses 217111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::total 1563509 # number of demand (read+write) MSHR misses 217211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9634 # number of overall MSHR misses 217311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8009 # number of overall MSHR misses 217411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 450235 # number of overall MSHR misses 217511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1095631 # number of overall MSHR misses 217611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688811 # number of overall MSHR misses 217711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::total 2252320 # number of overall MSHR misses 217810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 217911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 218011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8821 # number of ReadReq MSHR uncacheable 218111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 218211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 218310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 218411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 218511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17914 # number of overall MSHR uncacheable misses 218611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of ReadReq MSHR miss cycles 218711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369251500 # number of ReadReq MSHR miss cycles 218811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 771446500 # number of ReadReq MSHR miss cycles 218911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of HardPFReq MSHR miss cycles 219011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40532964082 # number of HardPFReq MSHR miss cycles 219111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6306578500 # number of UpgradeReq MSHR miss cycles 219211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6306578500 # number of UpgradeReq MSHR miss cycles 219311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3905504500 # number of SCUpgradeReq MSHR miss cycles 219411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3905504500 # number of SCUpgradeReq MSHR miss cycles 219511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5728498 # number of SCUpgradeFailReq MSHR miss cycles 219611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5728498 # number of SCUpgradeFailReq MSHR miss cycles 219711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11332534498 # number of ReadExReq MSHR miss cycles 219811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11332534498 # number of ReadExReq MSHR miss cycles 219911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14347084000 # number of ReadCleanReq MSHR miss cycles 220011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14347084000 # number of ReadCleanReq MSHR miss cycles 220111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28473868000 # number of ReadSharedReq MSHR miss cycles 220211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28473868000 # number of ReadSharedReq MSHR miss cycles 220311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13840214500 # number of InvalidateReq MSHR miss cycles 220411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13840214500 # number of InvalidateReq MSHR miss cycles 220511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of demand (read+write) MSHR miss cycles 220611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369251500 # number of demand (read+write) MSHR miss cycles 220711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14347084000 # number of demand (read+write) MSHR miss cycles 220811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39806402498 # number of demand (read+write) MSHR miss cycles 220911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 54924932998 # number of demand (read+write) MSHR miss cycles 221011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 402195000 # number of overall MSHR miss cycles 221111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369251500 # number of overall MSHR miss cycles 221211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14347084000 # number of overall MSHR miss cycles 221311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39806402498 # number of overall MSHR miss cycles 221411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of overall MSHR miss cycles 221511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 95457897080 # number of overall MSHR miss cycles 221611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles 221711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1390451500 # number of ReadReq MSHR uncacheable cycles 221811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1404390000 # number of ReadReq MSHR uncacheable cycles 221911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles 222011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles 222111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles 222211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles 222311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles 222411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses 222511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses 222611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses 222710535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 222810535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 222911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses 223011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses 223111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 223211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 223310535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 223410535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 223511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212405 # mshr miss rate for ReadExReq accesses 223611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212405 # mshr miss rate for ReadExReq accesses 223711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for ReadCleanReq accesses 223811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091496 # mshr miss rate for ReadCleanReq accesses 223911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.237963 # mshr miss rate for ReadSharedReq accesses 224011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237963 # mshr miss rate for ReadSharedReq accesses 224111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.551002 # mshr miss rate for InvalidateReq accesses 224211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.551002 # mshr miss rate for InvalidateReq accesses 224311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for demand accesses 224411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for demand accesses 224511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for demand accesses 224611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for demand accesses 224711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.155189 # mshr miss rate for demand accesses 224811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for overall accesses 224911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for overall accesses 225011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for overall accesses 225111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for overall accesses 225210535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 225311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.223558 # mshr miss rate for overall accesses 225411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average ReadReq mshr miss latency 225511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average ReadReq mshr miss latency 225611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 43725.358499 # average ReadReq mshr miss latency 225711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average HardPFReq mshr miss latency 225811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58844.826929 # average HardPFReq mshr miss latency 225911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32316.734905 # average UpgradeReq mshr miss latency 226011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905 # average UpgradeReq mshr miss latency 226111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531 # average SCUpgradeReq mshr miss latency 226211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531 # average SCUpgradeReq mshr miss latency 226311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571 # average SCUpgradeFailReq mshr miss latency 226411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571 # average SCUpgradeFailReq mshr miss latency 226511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889 # average ReadExReq mshr miss latency 226611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889 # average ReadExReq mshr miss latency 226711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average ReadCleanReq mshr miss latency 226811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877 # average ReadCleanReq mshr miss latency 226911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911 # average ReadSharedReq mshr miss latency 227011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911 # average ReadSharedReq mshr miss latency 227111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317 # average InvalidateReq mshr miss latency 227211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317 # average InvalidateReq mshr miss latency 227311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency 227411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 227511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 227611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 227711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040 # average overall mshr miss latency 227811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency 227911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 228011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 228111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 228211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency 228311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency 228411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency 228511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency 228611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency 228711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency 228811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency 228911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency 229011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency 229111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency 229210535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 229311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. 229411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 229511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 229611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. 229711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 229811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 229911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution 230011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution 230111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 9093 # Transaction distribution 230211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 9093 # Transaction distribution 230311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4367100 # Transaction distribution 230411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6772532 # Transaction distribution 230511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2206652 # Transaction distribution 230611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 838220 # Transaction distribution 230711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 373270 # Transaction distribution 230811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 349428 # Transaction distribution 230911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 455882 # Transaction distribution 231011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 231111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 231211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1149239 # Transaction distribution 231311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1127446 # Transaction distribution 231411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4920793 # Transaction distribution 231511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4454860 # Transaction distribution 231611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 528061 # Transaction distribution 231711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 481641 # Transaction distribution 231811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14762082 # Packet count per connected master and slave (bytes) 231911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16505656 # Packet count per connected master and slave (bytes) 232011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 342155 # Packet count per connected master and slave (bytes) 232111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 581136 # Packet count per connected master and slave (bytes) 232211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count::total 32191029 # Packet count per connected master and slave (bytes) 232311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 629828856 # Cumulative packet size per connected master and slave (bytes) 232411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 636046096 # Cumulative packet size per connected master and slave (bytes) 232511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1307840 # Cumulative packet size per connected master and slave (bytes) 232611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2129720 # Cumulative packet size per connected master and slave (bytes) 232711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size::total 1269312512 # Cumulative packet size per connected master and slave (bytes) 232811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoops 5644464 # Total snoops (count) 232911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::samples 16439738 # Request fanout histogram 233011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.118176 # Request fanout histogram 233111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.322847 # Request fanout histogram 233210535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 233311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::0 14497112 88.18% 88.18% # Request fanout histogram 233411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::1 1942467 11.82% 100.00% # Request fanout histogram 233511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::2 159 0.00% 100.00% # Request fanout histogram 233610535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 233711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 233810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 233911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::total 16439738 # Request fanout histogram 234011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 20566237996 # Layer occupancy (ticks) 234110535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 234211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 185505924 # Layer occupancy (ticks) 234310535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 234411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7381299500 # Layer occupancy (ticks) 234510535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 234611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7535601373 # Layer occupancy (ticks) 234710535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 234811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer2.occupancy 178675000 # Layer occupancy (ticks) 234910535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 235011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer3.occupancy 314921000 # Layer occupancy (ticks) 235110535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 235211374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadReq 40334 # Transaction distribution 235311374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadResp 40334 # Transaction distribution 235411374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::WriteReq 136621 # Transaction distribution 235511374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::WriteResp 136621 # Transaction distribution 235611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) 235710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 235811245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 235910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 236010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 236110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 236210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 236310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 236410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 236510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 236610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 236711374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 236810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 236911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) 237011374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) 237111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) 237210535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 237310535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 237411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count::total 353910 # Packet count per connected master and slave (bytes) 237511374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 237711245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 237810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 237910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 238010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 238110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 238510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 238710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 238811374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) 238911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) 239011374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) 239110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 239210535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 239311374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size::total 7496681 # Cumulative packet size per connected master and slave (bytes) 239411374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer0.occupancy 36912500 # Layer occupancy (ticks) 239510535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 239611353Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 239710535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 239811374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) 239910535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 240011201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 240110535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 240211336Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 240311245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 240410535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 240510535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 240611353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 240710535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 240811201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 240910535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 241011201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 241110535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 241211201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 241310535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 241411353Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 241510535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 241611374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer23.occupancy 26561500 # Layer occupancy (ticks) 241710535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 241811374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer24.occupancy 37416000 # Layer occupancy (ticks) 241910535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 242011374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer25.occupancy 567387857 # Layer occupancy (ticks) 242110535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 242211374Ssteve.reinhardt@amd.comsystem.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) 242310535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 242411374Ssteve.reinhardt@amd.comsystem.iobus.respLayer3.occupancy 147910000 # Layer occupancy (ticks) 242510535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 242610892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 242710535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 242811374Ssteve.reinhardt@amd.comsystem.iocache.tags.replacements 115602 # number of replacements 242911374Ssteve.reinhardt@amd.comsystem.iocache.tags.tagsinuse 11.206206 # Cycle average of tags in use 243011336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 243111374Ssteve.reinhardt@amd.comsystem.iocache.tags.sampled_refs 115618 # Sample count of references to valid blocks. 243211336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 243311374Ssteve.reinhardt@amd.comsystem.iocache.tags.warmup_cycle 9192082489000 # Cycle when the warmup percentage was hit. 243411374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.403530 # Average occupied blocks per requestor 243511374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_blocks::realview.ide 3.802676 # Average occupied blocks per requestor 243611374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::realview.ethernet 0.462721 # Average percentage of cache occupancy 243711374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::realview.ide 0.237667 # Average percentage of cache occupancy 243811374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::total 0.700388 # Average percentage of cache occupancy 243910535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 244010535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 244110535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 244211374Ssteve.reinhardt@amd.comsystem.iocache.tags.tag_accesses 1040820 # Number of tag accesses 244311374Ssteve.reinhardt@amd.comsystem.iocache.tags.data_accesses 1040820 # Number of data accesses 244410535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 244511374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses 244611374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_misses::total 8916 # number of ReadReq misses 244710535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 244810535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 244911353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 245011353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 245110535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 245211374Ssteve.reinhardt@amd.comsystem.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses 245311374Ssteve.reinhardt@amd.comsystem.iocache.demand_misses::total 8919 # number of demand (read+write) misses 245410535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 245511374Ssteve.reinhardt@amd.comsystem.iocache.overall_misses::realview.ide 8879 # number of overall misses 245611374Ssteve.reinhardt@amd.comsystem.iocache.overall_misses::total 8919 # number of overall misses 245711374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 245811374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles 245911374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles 246010726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 246110726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 246211374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles 246311374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles 246411374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 246511374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles 246611374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles 246711374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 246811374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles 246911374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles 247010535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 247111374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) 247211374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) 247310535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 247410535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 247511353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 247611353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 247710535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 247811374Ssteve.reinhardt@amd.comsystem.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses 247911374Ssteve.reinhardt@amd.comsystem.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses 248010535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 248111374Ssteve.reinhardt@amd.comsystem.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses 248211374Ssteve.reinhardt@amd.comsystem.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses 248310535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 248410535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 248510535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 248610535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 248710535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 248911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 249010535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 249110535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 249210535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 249310535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 249410535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 249510535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 249611374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 249711374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency 249811374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency 249910726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 250010726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 250111374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency 250211374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency 250311374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 250411374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 250511374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency 250611374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 250711374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 250811374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency 250911374Ssteve.reinhardt@amd.comsystem.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked 251010535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 251111374Ssteve.reinhardt@amd.comsystem.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked 251210535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 251311374Ssteve.reinhardt@amd.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked 251410535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251510585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 251610535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 251711374Ssteve.reinhardt@amd.comsystem.iocache.writebacks::writebacks 106693 # number of writebacks 251811374Ssteve.reinhardt@amd.comsystem.iocache.writebacks::total 106693 # number of writebacks 251910535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 252011374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses 252111374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses 252210535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 252310535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 252411353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 252511353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 252610535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 252711374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses 252811374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses 252910535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 253011374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses 253111374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses 253211374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 253311374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles 253411374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles 253510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 253610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 253711374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles 253811374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles 253911374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 254011374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles 254111374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles 254211374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 254311374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles 254411374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles 254510535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 254610535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 254710535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 254810535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 254910535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 255011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 255111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 255210535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 255310535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 255410535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 255510535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 255610535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 255710535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 255811374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 255911374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787 # average ReadReq mshr miss latency 256011374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237 # average ReadReq mshr miss latency 256110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 256210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 256311374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency 256411374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency 256511374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 256611374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 256711374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency 256811374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 256911374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 257011374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency 257110535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 257211374Ssteve.reinhardt@amd.comsystem.l2c.tags.replacements 1288575 # number of replacements 257311374Ssteve.reinhardt@amd.comsystem.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use 257411374Ssteve.reinhardt@amd.comsystem.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. 257511374Ssteve.reinhardt@amd.comsystem.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. 257611374Ssteve.reinhardt@amd.comsystem.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. 257711353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. 257811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::writebacks 24026.415823 # Average occupied blocks per requestor 257911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 182.847205 # Average occupied blocks per requestor 258011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 272.174490 # Average occupied blocks per requestor 258111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.inst 3917.360352 # Average occupied blocks per requestor 258211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.data 7074.037074 # Average occupied blocks per requestor 258311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11678.333096 # Average occupied blocks per requestor 258411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 109.068959 # Average occupied blocks per requestor 258511374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 171.850259 # Average occupied blocks per requestor 258611374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.inst 3448.642027 # Average occupied blocks per requestor 258711374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.data 6022.848319 # Average occupied blocks per requestor 258811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6430.905066 # Average occupied blocks per requestor 258911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::writebacks 0.366614 # Average percentage of cache occupancy 259011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002790 # Average percentage of cache occupancy 259111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.004153 # Average percentage of cache occupancy 259211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.inst 0.059774 # Average percentage of cache occupancy 259311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.data 0.107941 # Average percentage of cache occupancy 259411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.178197 # Average percentage of cache occupancy 259511374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy 259611374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.002622 # Average percentage of cache occupancy 259711374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.inst 0.052622 # Average percentage of cache occupancy 259811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.data 0.091901 # Average percentage of cache occupancy 259911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.098128 # Average percentage of cache occupancy 260011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::total 0.966408 # Average percentage of cache occupancy 260111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1022 9960 # Occupied blocks per task id 260211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1023 230 # Occupied blocks per task id 260311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id 260411374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id 260511374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::3 303 # Occupied blocks per task id 260611374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::4 9611 # Occupied blocks per task id 260711374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1023::4 230 # Occupied blocks per task id 260811374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 260911374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id 261011374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::2 1722 # Occupied blocks per task id 261111374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::3 5705 # Occupied blocks per task id 261211374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::4 40867 # Occupied blocks per task id 261311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1022 0.151978 # Percentage of cache occupancy per task id 261411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1023 0.003510 # Percentage of cache occupancy per task id 261511374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 261611374Ssteve.reinhardt@amd.comsystem.l2c.tags.tag_accesses 68640564 # Number of tag accesses 261711374Ssteve.reinhardt@amd.comsystem.l2c.tags.data_accesses 68640564 # Number of data accesses 261811374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_hits::writebacks 2576614 # number of WritebackDirty hits 261911374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_hits::total 2576614 # number of WritebackDirty hits 262011374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::cpu0.data 159474 # number of UpgradeReq hits 262111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::cpu1.data 125945 # number of UpgradeReq hits 262211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::total 285419 # number of UpgradeReq hits 262311374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 36876 # number of SCUpgradeReq hits 262411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 37537 # number of SCUpgradeReq hits 262511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::total 74413 # number of SCUpgradeReq hits 262611374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::cpu0.data 50046 # number of ReadExReq hits 262711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::cpu1.data 51540 # number of ReadExReq hits 262811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::total 101586 # number of ReadExReq hits 262911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5134 # number of ReadSharedReq hits 263011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3916 # number of ReadSharedReq hits 263111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 411784 # number of ReadSharedReq hits 263211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.data 545243 # number of ReadSharedReq hits 263311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276625 # number of ReadSharedReq hits 263411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5262 # number of ReadSharedReq hits 263511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4295 # number of ReadSharedReq hits 263611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 410923 # number of ReadSharedReq hits 263711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.data 516914 # number of ReadSharedReq hits 263811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 270635 # number of ReadSharedReq hits 263911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::total 2450731 # number of ReadSharedReq hits 264011374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::cpu0.data 123087 # number of InvalidateReq hits 264111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::cpu1.data 119603 # number of InvalidateReq hits 264211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::total 242690 # number of InvalidateReq hits 264311374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.dtb.walker 5134 # number of demand (read+write) hits 264411374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.itb.walker 3916 # number of demand (read+write) hits 264511374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.inst 411784 # number of demand (read+write) hits 264611374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.data 595289 # number of demand (read+write) hits 264711374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 276625 # number of demand (read+write) hits 264811374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.dtb.walker 5262 # number of demand (read+write) hits 264911374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.itb.walker 4295 # number of demand (read+write) hits 265011374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.inst 410923 # number of demand (read+write) hits 265111374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.data 568454 # number of demand (read+write) hits 265211374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 270635 # number of demand (read+write) hits 265311374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::total 2552317 # number of demand (read+write) hits 265411374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.dtb.walker 5134 # number of overall hits 265511374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.itb.walker 3916 # number of overall hits 265611374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.inst 411784 # number of overall hits 265711374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.data 595289 # number of overall hits 265811374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 276625 # number of overall hits 265911374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.dtb.walker 5262 # number of overall hits 266011374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.itb.walker 4295 # number of overall hits 266111374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.inst 410923 # number of overall hits 266211374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.data 568454 # number of overall hits 266311374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 270635 # number of overall hits 266411374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::total 2552317 # number of overall hits 266511374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::cpu0.data 60660 # number of UpgradeReq misses 266611374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::cpu1.data 57967 # number of UpgradeReq misses 266711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::total 118627 # number of UpgradeReq misses 266811374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 11966 # number of SCUpgradeReq misses 266911374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 14089 # number of SCUpgradeReq misses 267011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::total 26055 # number of SCUpgradeReq misses 267111374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::cpu0.data 73366 # number of ReadExReq misses 267211374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::cpu1.data 52915 # number of ReadExReq misses 267311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::total 126281 # number of ReadExReq misses 267411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1280 # number of ReadSharedReq misses 267511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1221 # number of ReadSharedReq misses 267611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 47163 # number of ReadSharedReq misses 267711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.data 114217 # number of ReadSharedReq misses 267811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 194151 # number of ReadSharedReq misses 267911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1808 # number of ReadSharedReq misses 268011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1830 # number of ReadSharedReq misses 268111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 39312 # number of ReadSharedReq misses 268211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.data 102014 # number of ReadSharedReq misses 268311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208359 # number of ReadSharedReq misses 268411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::total 711355 # number of ReadSharedReq misses 268511374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::cpu0.data 431001 # number of InvalidateReq misses 268611374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::cpu1.data 129981 # number of InvalidateReq misses 268711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::total 560982 # number of InvalidateReq misses 268811374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.dtb.walker 1280 # number of demand (read+write) misses 268911374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.itb.walker 1221 # number of demand (read+write) misses 269011374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.inst 47163 # number of demand (read+write) misses 269111374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.data 187583 # number of demand (read+write) misses 269211374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 194151 # number of demand (read+write) misses 269311374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.dtb.walker 1808 # number of demand (read+write) misses 269411374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.itb.walker 1830 # number of demand (read+write) misses 269511374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.inst 39312 # number of demand (read+write) misses 269611374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.data 154929 # number of demand (read+write) misses 269711374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 208359 # number of demand (read+write) misses 269811374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::total 837636 # number of demand (read+write) misses 269911374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.dtb.walker 1280 # number of overall misses 270011374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.itb.walker 1221 # number of overall misses 270111374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.inst 47163 # number of overall misses 270211374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.data 187583 # number of overall misses 270311374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 194151 # number of overall misses 270411374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.dtb.walker 1808 # number of overall misses 270511374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.itb.walker 1830 # number of overall misses 270611374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.inst 39312 # number of overall misses 270711374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.data 154929 # number of overall misses 270811374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 208359 # number of overall misses 270911374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::total 837636 # number of overall misses 271011374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 923139500 # number of UpgradeReq miss cycles 271111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 911457500 # number of UpgradeReq miss cycles 271211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::total 1834597000 # number of UpgradeReq miss cycles 271311374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 172867000 # number of SCUpgradeReq miss cycles 271411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 183172000 # number of SCUpgradeReq miss cycles 271511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::total 356039000 # number of SCUpgradeReq miss cycles 271611374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 10023511500 # number of ReadExReq miss cycles 271711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 7102572500 # number of ReadExReq miss cycles 271811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::total 17126084000 # number of ReadExReq miss cycles 271911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 179763500 # number of ReadSharedReq miss cycles 272011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 168992000 # number of ReadSharedReq miss cycles 272111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6377154500 # number of ReadSharedReq miss cycles 272211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15730524500 # number of ReadSharedReq miss cycles 272311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of ReadSharedReq miss cycles 272411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 254502500 # number of ReadSharedReq miss cycles 272511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 255185000 # number of ReadSharedReq miss cycles 272611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5294694000 # number of ReadSharedReq miss cycles 272711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 14274314499 # number of ReadSharedReq miss cycles 272811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of ReadSharedReq miss cycles 272911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::total 110856686244 # number of ReadSharedReq miss cycles 273011374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 147802000 # number of InvalidateReq miss cycles 273111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 150755500 # number of InvalidateReq miss cycles 273211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::total 298557500 # number of InvalidateReq miss cycles 273311374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 179763500 # number of demand (read+write) miss cycles 273411374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 168992000 # number of demand (read+write) miss cycles 273511374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.inst 6377154500 # number of demand (read+write) miss cycles 273611374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.data 25754036000 # number of demand (read+write) miss cycles 273711374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of demand (read+write) miss cycles 273811374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 254502500 # number of demand (read+write) miss cycles 273911374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 255185000 # number of demand (read+write) miss cycles 274011374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.inst 5294694000 # number of demand (read+write) miss cycles 274111374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.data 21376886999 # number of demand (read+write) miss cycles 274211374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of demand (read+write) miss cycles 274311374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::total 127982770244 # number of demand (read+write) miss cycles 274411374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 179763500 # number of overall miss cycles 274511374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 168992000 # number of overall miss cycles 274611374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.inst 6377154500 # number of overall miss cycles 274711374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.data 25754036000 # number of overall miss cycles 274811374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32714560984 # number of overall miss cycles 274911374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 254502500 # number of overall miss cycles 275011374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 255185000 # number of overall miss cycles 275111374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.inst 5294694000 # number of overall miss cycles 275211374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.data 21376886999 # number of overall miss cycles 275311374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35606994761 # number of overall miss cycles 275411374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::total 127982770244 # number of overall miss cycles 275511374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_accesses::writebacks 2576614 # number of WritebackDirty accesses(hits+misses) 275611374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_accesses::total 2576614 # number of WritebackDirty accesses(hits+misses) 275711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::cpu0.data 220134 # number of UpgradeReq accesses(hits+misses) 275811374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::cpu1.data 183912 # number of UpgradeReq accesses(hits+misses) 275911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::total 404046 # number of UpgradeReq accesses(hits+misses) 276011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 48842 # number of SCUpgradeReq accesses(hits+misses) 276111374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 51626 # number of SCUpgradeReq accesses(hits+misses) 276211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::total 100468 # number of SCUpgradeReq accesses(hits+misses) 276311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::cpu0.data 123412 # number of ReadExReq accesses(hits+misses) 276411374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::cpu1.data 104455 # number of ReadExReq accesses(hits+misses) 276511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::total 227867 # number of ReadExReq accesses(hits+misses) 276611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6414 # number of ReadSharedReq accesses(hits+misses) 276711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5137 # number of ReadSharedReq accesses(hits+misses) 276811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 458947 # number of ReadSharedReq accesses(hits+misses) 276911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 659460 # number of ReadSharedReq accesses(hits+misses) 277011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 470776 # number of ReadSharedReq accesses(hits+misses) 277111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7070 # number of ReadSharedReq accesses(hits+misses) 277211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6125 # number of ReadSharedReq accesses(hits+misses) 277311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 450235 # number of ReadSharedReq accesses(hits+misses) 277411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 618928 # number of ReadSharedReq accesses(hits+misses) 277511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 478994 # number of ReadSharedReq accesses(hits+misses) 277611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::total 3162086 # number of ReadSharedReq accesses(hits+misses) 277711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::cpu0.data 554088 # number of InvalidateReq accesses(hits+misses) 277811374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::cpu1.data 249584 # number of InvalidateReq accesses(hits+misses) 277911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::total 803672 # number of InvalidateReq accesses(hits+misses) 278011374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.dtb.walker 6414 # number of demand (read+write) accesses 278111374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.itb.walker 5137 # number of demand (read+write) accesses 278211374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.inst 458947 # number of demand (read+write) accesses 278311374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.data 782872 # number of demand (read+write) accesses 278411374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 470776 # number of demand (read+write) accesses 278511374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.dtb.walker 7070 # number of demand (read+write) accesses 278611374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.itb.walker 6125 # number of demand (read+write) accesses 278711374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.inst 450235 # number of demand (read+write) accesses 278811374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.data 723383 # number of demand (read+write) accesses 278911374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 478994 # number of demand (read+write) accesses 279011374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::total 3389953 # number of demand (read+write) accesses 279111374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.dtb.walker 6414 # number of overall (read+write) accesses 279211374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.itb.walker 5137 # number of overall (read+write) accesses 279311374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.inst 458947 # number of overall (read+write) accesses 279411374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.data 782872 # number of overall (read+write) accesses 279511374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 470776 # number of overall (read+write) accesses 279611374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.dtb.walker 7070 # number of overall (read+write) accesses 279711374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.itb.walker 6125 # number of overall (read+write) accesses 279811374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.inst 450235 # number of overall (read+write) accesses 279911374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.data 723383 # number of overall (read+write) accesses 280011374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 478994 # number of overall (read+write) accesses 280111374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::total 3389953 # number of overall (read+write) accesses 280211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.275559 # miss rate for UpgradeReq accesses 280311374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.315189 # miss rate for UpgradeReq accesses 280411374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::total 0.293598 # miss rate for UpgradeReq accesses 280511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.244994 # miss rate for SCUpgradeReq accesses 280611374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.272905 # miss rate for SCUpgradeReq accesses 280711374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.259336 # miss rate for SCUpgradeReq accesses 280811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.594480 # miss rate for ReadExReq accesses 280911374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.506582 # miss rate for ReadExReq accesses 281011374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::total 0.554187 # miss rate for ReadExReq accesses 281111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for ReadSharedReq accesses 281211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.237687 # miss rate for ReadSharedReq accesses 281311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102763 # miss rate for ReadSharedReq accesses 281411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.173198 # miss rate for ReadSharedReq accesses 281511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for ReadSharedReq accesses 281611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for ReadSharedReq accesses 281711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.298776 # miss rate for ReadSharedReq accesses 281811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087314 # miss rate for ReadSharedReq accesses 281911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164824 # miss rate for ReadSharedReq accesses 282011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for ReadSharedReq accesses 282111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::total 0.224964 # miss rate for ReadSharedReq accesses 282211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.777857 # miss rate for InvalidateReq accesses 282311374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.520791 # miss rate for InvalidateReq accesses 282411374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::total 0.698024 # miss rate for InvalidateReq accesses 282511374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for demand accesses 282611374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.237687 # miss rate for demand accesses 282711374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.inst 0.102763 # miss rate for demand accesses 282811374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.data 0.239609 # miss rate for demand accesses 282911374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for demand accesses 283011374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for demand accesses 283111374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.298776 # miss rate for demand accesses 283211374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.inst 0.087314 # miss rate for demand accesses 283311374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.data 0.214173 # miss rate for demand accesses 283411374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for demand accesses 283511374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::total 0.247094 # miss rate for demand accesses 283611374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.199563 # miss rate for overall accesses 283711374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.237687 # miss rate for overall accesses 283811374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.inst 0.102763 # miss rate for overall accesses 283911374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.data 0.239609 # miss rate for overall accesses 284011374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.412406 # miss rate for overall accesses 284111374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.255728 # miss rate for overall accesses 284211374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.298776 # miss rate for overall accesses 284311374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.inst 0.087314 # miss rate for overall accesses 284411374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.data 0.214173 # miss rate for overall accesses 284511374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.434993 # miss rate for overall accesses 284611374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::total 0.247094 # miss rate for overall accesses 284711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15218.257501 # average UpgradeReq miss latency 284811374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15723.730743 # average UpgradeReq miss latency 284911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::total 15465.256645 # average UpgradeReq miss latency 285011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14446.515126 # average SCUpgradeReq miss latency 285111374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13001.064660 # average SCUpgradeReq miss latency 285211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 13664.901171 # average SCUpgradeReq miss latency 285311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 136623.388218 # average ReadExReq miss latency 285411374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 134226.070112 # average ReadExReq miss latency 285511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::total 135618.850025 # average ReadExReq miss latency 285611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average ReadSharedReq miss latency 285711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138404.586405 # average ReadSharedReq miss latency 285811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135215.200475 # average ReadSharedReq miss latency 285911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137724.896469 # average ReadSharedReq miss latency 286011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average ReadSharedReq miss latency 286111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average ReadSharedReq miss latency 286211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139445.355191 # average ReadSharedReq miss latency 286311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134683.913309 # average ReadSharedReq miss latency 286411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139925.054394 # average ReadSharedReq miss latency 286511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average ReadSharedReq miss latency 286611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 155838.767203 # average ReadSharedReq miss latency 286711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 342.927279 # average InvalidateReq miss latency 286811374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1159.827206 # average InvalidateReq miss latency 286911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::total 532.205133 # average InvalidateReq miss latency 287011374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average overall miss latency 287111374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 138404.586405 # average overall miss latency 287211374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 135215.200475 # average overall miss latency 287311374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.data 137294.083153 # average overall miss latency 287411374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average overall miss latency 287511374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average overall miss latency 287611374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 139445.355191 # average overall miss latency 287711374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 134683.913309 # average overall miss latency 287811374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.data 137978.603096 # average overall miss latency 287911374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 288011374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::total 152790.436710 # average overall miss latency 288111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140440.234375 # average overall miss latency 288211374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 138404.586405 # average overall miss latency 288311374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 135215.200475 # average overall miss latency 288411374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.data 137294.083153 # average overall miss latency 288511374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117 # average overall miss latency 288611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140764.657080 # average overall miss latency 288711374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 139445.355191 # average overall miss latency 288811374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 134683.913309 # average overall miss latency 288911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.data 137978.603096 # average overall miss latency 289011374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 289111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::total 152790.436710 # average overall miss latency 289211374Ssteve.reinhardt@amd.comsystem.l2c.blocked_cycles::no_mshrs 1300 # number of cycles access was blocked 289310515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 289411374Ssteve.reinhardt@amd.comsystem.l2c.blocked::no_mshrs 25 # number of cycles access was blocked 289510515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 289611374Ssteve.reinhardt@amd.comsystem.l2c.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked 289710515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 289810515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 289910515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 290011374Ssteve.reinhardt@amd.comsystem.l2c.writebacks::writebacks 1038944 # number of writebacks 290111374Ssteve.reinhardt@amd.comsystem.l2c.writebacks::total 1038944 # number of writebacks 290211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 98 # number of ReadSharedReq MSHR hits 290311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 290411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 68 # number of ReadSharedReq MSHR hits 290511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 290611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::total 208 # number of ReadSharedReq MSHR hits 290711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.inst 98 # number of demand (read+write) MSHR hits 290811374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 290911374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu1.inst 68 # number of demand (read+write) MSHR hits 291011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 291111374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits 291211374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.inst 98 # number of overall MSHR hits 291311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 291411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu1.inst 68 # number of overall MSHR hits 291511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 291611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::total 208 # number of overall MSHR hits 291711374Ssteve.reinhardt@amd.comsystem.l2c.CleanEvict_mshr_misses::writebacks 42465 # number of CleanEvict MSHR misses 291811374Ssteve.reinhardt@amd.comsystem.l2c.CleanEvict_mshr_misses::total 42465 # number of CleanEvict MSHR misses 291911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 60660 # number of UpgradeReq MSHR misses 292011374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 57967 # number of UpgradeReq MSHR misses 292111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::total 118627 # number of UpgradeReq MSHR misses 292211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11966 # number of SCUpgradeReq MSHR misses 292311374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 14089 # number of SCUpgradeReq MSHR misses 292411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::total 26055 # number of SCUpgradeReq MSHR misses 292511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 73366 # number of ReadExReq MSHR misses 292611374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 52915 # number of ReadExReq MSHR misses 292711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::total 126281 # number of ReadExReq MSHR misses 292811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1280 # number of ReadSharedReq MSHR misses 292911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1221 # number of ReadSharedReq MSHR misses 293011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 47065 # number of ReadSharedReq MSHR misses 293111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 114192 # number of ReadSharedReq MSHR misses 293211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 194151 # number of ReadSharedReq MSHR misses 293311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1808 # number of ReadSharedReq MSHR misses 293411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1830 # number of ReadSharedReq MSHR misses 293511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39244 # number of ReadSharedReq MSHR misses 293611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 101997 # number of ReadSharedReq MSHR misses 293711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 208359 # number of ReadSharedReq MSHR misses 293811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::total 711147 # number of ReadSharedReq MSHR misses 293911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 431001 # number of InvalidateReq MSHR misses 294011374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 129981 # number of InvalidateReq MSHR misses 294111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::total 560982 # number of InvalidateReq MSHR misses 294211374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1280 # number of demand (read+write) MSHR misses 294311374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1221 # number of demand (read+write) MSHR misses 294411374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.inst 47065 # number of demand (read+write) MSHR misses 294511374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.data 187558 # number of demand (read+write) MSHR misses 294611374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 194151 # number of demand (read+write) MSHR misses 294711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1808 # number of demand (read+write) MSHR misses 294811374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1830 # number of demand (read+write) MSHR misses 294911374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu1.inst 39244 # number of demand (read+write) MSHR misses 295011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu1.data 154912 # number of demand (read+write) MSHR misses 295111374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 208359 # number of demand (read+write) MSHR misses 295211374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::total 837428 # number of demand (read+write) MSHR misses 295311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1280 # number of overall MSHR misses 295411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1221 # number of overall MSHR misses 295511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu0.inst 47065 # number of overall MSHR misses 295611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu0.data 187558 # number of overall MSHR misses 295711374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 194151 # number of overall MSHR misses 295811374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1808 # number of overall MSHR misses 295911374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1830 # number of overall MSHR misses 296011374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu1.inst 39244 # number of overall MSHR misses 296111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu1.data 154912 # number of overall MSHR misses 296211374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 208359 # number of overall MSHR misses 296311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_misses::total 837428 # number of overall MSHR misses 296410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 296511374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 296610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 296711374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 8709 # number of ReadReq MSHR uncacheable 296811374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable::total 81394 # number of ReadReq MSHR uncacheable 296911374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 297011374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 297111374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable::total 38017 # number of WriteReq MSHR uncacheable 297210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 297311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 297410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 297511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 17802 # number of overall MSHR uncacheable misses 297611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_misses::total 119411 # number of overall MSHR uncacheable misses 297711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4288394500 # number of UpgradeReq MSHR miss cycles 297811374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4102128000 # number of UpgradeReq MSHR miss cycles 297911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 8390522500 # number of UpgradeReq MSHR miss cycles 298011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 882418000 # number of SCUpgradeReq MSHR miss cycles 298111374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1039410000 # number of SCUpgradeReq MSHR miss cycles 298211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 1921828000 # number of SCUpgradeReq MSHR miss cycles 298311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9289531460 # number of ReadExReq MSHR miss cycles 298411374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6573150768 # number of ReadExReq MSHR miss cycles 298511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_latency::total 15862682228 # number of ReadExReq MSHR miss cycles 298611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 166958510 # number of ReadSharedReq MSHR miss cycles 298711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 156778008 # number of ReadSharedReq MSHR miss cycles 298811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5894891941 # number of ReadSharedReq MSHR miss cycles 298911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14584550481 # number of ReadSharedReq MSHR miss cycles 299011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30771342562 # number of ReadSharedReq MSHR miss cycles 299111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 236409526 # number of ReadSharedReq MSHR miss cycles 299211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 236875020 # number of ReadSharedReq MSHR miss cycles 299311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4895215723 # number of ReadSharedReq MSHR miss cycles 299411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13251631295 # number of ReadSharedReq MSHR miss cycles 299511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of ReadSharedReq MSHR miss cycles 299611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 103716578310 # number of ReadSharedReq MSHR miss cycles 299711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 29736888998 # number of InvalidateReq MSHR miss cycles 299811374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 8990235999 # number of InvalidateReq MSHR miss cycles 299911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 38727124997 # number of InvalidateReq MSHR miss cycles 300011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 166958510 # number of demand (read+write) MSHR miss cycles 300111374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 156778008 # number of demand (read+write) MSHR miss cycles 300211374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5894891941 # number of demand (read+write) MSHR miss cycles 300311374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 23874081941 # number of demand (read+write) MSHR miss cycles 300411374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30771342562 # number of demand (read+write) MSHR miss cycles 300511374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 236409526 # number of demand (read+write) MSHR miss cycles 300611374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 236875020 # number of demand (read+write) MSHR miss cycles 300711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 4895215723 # number of demand (read+write) MSHR miss cycles 300811374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 19824782063 # number of demand (read+write) MSHR miss cycles 300911374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of demand (read+write) MSHR miss cycles 301011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_latency::total 119579260538 # number of demand (read+write) MSHR miss cycles 301111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 166958510 # number of overall MSHR miss cycles 301211374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 156778008 # number of overall MSHR miss cycles 301311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5894891941 # number of overall MSHR miss cycles 301411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 23874081941 # number of overall MSHR miss cycles 301511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30771342562 # number of overall MSHR miss cycles 301611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 236409526 # number of overall MSHR miss cycles 301711374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236875020 # number of overall MSHR miss cycles 301811374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 4895215723 # number of overall MSHR miss cycles 301911374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 19824782063 # number of overall MSHR miss cycles 302011374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of overall MSHR miss cycles 302111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_latency::total 119579260538 # number of overall MSHR miss cycles 302211201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 302311374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4673220523 # number of ReadReq MSHR uncacheable cycles 302411353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles 302511374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1233601518 # number of ReadReq MSHR uncacheable cycles 302611374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 10773300041 # number of ReadReq MSHR uncacheable cycles 302711374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles 302811374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles 302911374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles 303011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 303111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles 303211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles 303311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles 303411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles 303510892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 303610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 303711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses 303811374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315189 # mshr miss rate for UpgradeReq accesses 303911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.293598 # mshr miss rate for UpgradeReq accesses 304011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244994 # mshr miss rate for SCUpgradeReq accesses 304111374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.272905 # mshr miss rate for SCUpgradeReq accesses 304211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259336 # mshr miss rate for SCUpgradeReq accesses 304311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.594480 # mshr miss rate for ReadExReq accesses 304411374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506582 # mshr miss rate for ReadExReq accesses 304511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.554187 # mshr miss rate for ReadExReq accesses 304611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for ReadSharedReq accesses 304711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for ReadSharedReq accesses 304811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for ReadSharedReq accesses 304911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173160 # mshr miss rate for ReadSharedReq accesses 305011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for ReadSharedReq accesses 305111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for ReadSharedReq accesses 305211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for ReadSharedReq accesses 305311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for ReadSharedReq accesses 305411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164796 # mshr miss rate for ReadSharedReq accesses 305511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for ReadSharedReq accesses 305611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.224898 # mshr miss rate for ReadSharedReq accesses 305711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.777857 # mshr miss rate for InvalidateReq accesses 305811374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.520791 # mshr miss rate for InvalidateReq accesses 305911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.698024 # mshr miss rate for InvalidateReq accesses 306011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for demand accesses 306111374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for demand accesses 306211374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for demand accesses 306311374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for demand accesses 306411374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for demand accesses 306511374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for demand accesses 306611374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for demand accesses 306711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for demand accesses 306811374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for demand accesses 306911374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for demand accesses 307011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_miss_rate::total 0.247032 # mshr miss rate for demand accesses 307111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for overall accesses 307211374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for overall accesses 307311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for overall accesses 307411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for overall accesses 307511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for overall accesses 307611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for overall accesses 307711374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for overall accesses 307811374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for overall accesses 307911374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for overall accesses 308011374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for overall accesses 308111374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_miss_rate::total 0.247032 # mshr miss rate for overall accesses 308211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70695.590175 # average UpgradeReq mshr miss latency 308311374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70766.608588 # average UpgradeReq mshr miss latency 308411374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 70730.293272 # average UpgradeReq mshr miss latency 308511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73743.774026 # average SCUpgradeReq mshr miss latency 308611374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73774.575910 # average SCUpgradeReq mshr miss latency 308711374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73760.429860 # average SCUpgradeReq mshr miss latency 308811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 126619.025979 # average ReadExReq mshr miss latency 308911374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124220.934858 # average ReadExReq mshr miss latency 309011374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 125614.163873 # average ReadExReq mshr miss latency 309111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average ReadSharedReq mshr miss latency 309211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average ReadSharedReq mshr miss latency 309311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average ReadSharedReq mshr miss latency 309411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127719.546737 # average ReadSharedReq mshr miss latency 309511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average ReadSharedReq mshr miss latency 309611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average ReadSharedReq mshr miss latency 309711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average ReadSharedReq mshr miss latency 309811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average ReadSharedReq mshr miss latency 309911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129921.775101 # average ReadSharedReq mshr miss latency 310011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average ReadSharedReq mshr miss latency 310111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 145844.077680 # average ReadSharedReq mshr miss latency 310211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68994.942002 # average InvalidateReq mshr miss latency 310311374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69165.770374 # average InvalidateReq mshr miss latency 310411374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 69034.523384 # average InvalidateReq mshr miss latency 310511374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency 310611374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency 310711374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency 310811374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency 310911374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency 311011374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency 311111374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency 311211374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency 311311374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 311411374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 311511374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 311611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency 311711374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency 311811374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency 311911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency 312011374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency 312111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency 312211374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency 312311374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency 312411374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 312511374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 312611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 312711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 312811374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency 312911353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency 313011374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency 313111374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency 313211374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency 313311374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency 313411374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency 313511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 313611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency 313711353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency 313811374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency 313911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency 314010515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 314111374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadReq 81394 # Transaction distribution 314211374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadResp 801457 # Transaction distribution 314311374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WriteReq 38017 # Transaction distribution 314411374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WriteResp 38017 # Transaction distribution 314511374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution 314611374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::CleanEvict 202586 # Transaction distribution 314711374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::UpgradeReq 388021 # Transaction distribution 314811374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution 314911374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::UpgradeResp 24 # Transaction distribution 315011374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 315111374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExReq 139521 # Transaction distribution 315211374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExResp 122200 # Transaction distribution 315311374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadSharedReq 720063 # Transaction distribution 315411374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::InvalidateReq 663960 # Transaction distribution 315511374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) 315610535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 315711374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24516 # Packet count per connected master and slave (bytes) 315811374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4262617 # Packet count per connected master and slave (bytes) 315911374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::total 4409841 # Packet count per connected master and slave (bytes) 316011374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238367 # Packet count per connected master and slave (bytes) 316111374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.iocache.mem_side::total 238367 # Packet count per connected master and slave (bytes) 316211374Ssteve.reinhardt@amd.comsystem.membus.pkt_count::total 4648208 # Packet count per connected master and slave (bytes) 316311374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) 316410535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 316511374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49032 # Cumulative packet size per connected master and slave (bytes) 316611374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 119974316 # Cumulative packet size per connected master and slave (bytes) 316711374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::total 120179275 # Cumulative packet size per connected master and slave (bytes) 316811374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283904 # Cumulative packet size per connected master and slave (bytes) 316911374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.iocache.mem_side::total 7283904 # Cumulative packet size per connected master and slave (bytes) 317011374Ssteve.reinhardt@amd.comsystem.membus.pkt_size::total 127463179 # Cumulative packet size per connected master and slave (bytes) 317111374Ssteve.reinhardt@amd.comsystem.membus.snoops 565217 # Total snoops (count) 317211374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::samples 3689099 # Request fanout histogram 317310535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 317410535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 317510535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 317610535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 317711374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::1 3689099 100.00% 100.00% # Request fanout histogram 317810535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 317910535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 318010535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 318110535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 318211374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::total 3689099 # Request fanout histogram 318311374Ssteve.reinhardt@amd.comsystem.membus.reqLayer0.occupancy 101296000 # Layer occupancy (ticks) 318410535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 318511138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 318610535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 318711374Ssteve.reinhardt@amd.comsystem.membus.reqLayer2.occupancy 20132498 # Layer occupancy (ticks) 318810535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 318911374Ssteve.reinhardt@amd.comsystem.membus.reqLayer5.occupancy 7983633356 # Layer occupancy (ticks) 319010535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 319111374Ssteve.reinhardt@amd.comsystem.membus.respLayer2.occupancy 4606610325 # Layer occupancy (ticks) 319210535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 319311374Ssteve.reinhardt@amd.comsystem.membus.respLayer3.occupancy 45425919 # Layer occupancy (ticks) 319410535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 319511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 319611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 319711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 319811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 319911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 320011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 320110515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 320210515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 320310515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 320410515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 320510515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 320610515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 320710515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 320810515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 320910515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 321011374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 321110515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 321210515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 321310515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 321411374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 321510515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 321610515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 321710515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 321810515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 321910515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 322010515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 322110515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 322210515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 322310515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 322410515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 322510515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 322610515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 322710515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 322810515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 322910515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 323010515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 323110515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 323210515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 323310515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 323410515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 323510515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 323610515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 323710515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 323810515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 323910515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 324010515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 324110515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 324210515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 324311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 324411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 324511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 324611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 324711374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.tot_requests 10607741 # Total number of requests made to the snoop filter. 324811374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_single_requests 5778542 # Number of requests hitting in the snoop filter with a single holder of the requested data. 324911374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1706398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 325011374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.tot_snoops 126357 # Total number of snoops made to the snoop filter. 325111374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_single_snoops 115095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 325211374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 11262 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 325311374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadReq 81396 # Transaction distribution 325411374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadResp 3972795 # Transaction distribution 325511374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WriteReq 38017 # Transaction distribution 325611374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WriteResp 38017 # Transaction distribution 325711374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WritebackDirty 3722299 # Transaction distribution 325811374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::CleanEvict 2264546 # Transaction distribution 325911374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeReq 665609 # Transaction distribution 326011374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::SCUpgradeReq 384259 # Transaction distribution 326111374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeResp 1049868 # Transaction distribution 326211374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution 326311374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution 326411374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadExReq 281631 # Transaction distribution 326511374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadExResp 281631 # Transaction distribution 326611374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadSharedReq 3898638 # Transaction distribution 326711374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::InvalidateReq 910400 # Transaction distribution 326811374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::InvalidateResp 803672 # Transaction distribution 326911374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8440853 # Packet count per connected master and slave (bytes) 327011374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7105433 # Packet count per connected master and slave (bytes) 327111374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count::total 15546286 # Packet count per connected master and slave (bytes) 327211374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 205041299 # Cumulative packet size per connected master and slave (bytes) 327311374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177324920 # Cumulative packet size per connected master and slave (bytes) 327411374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size::total 382366219 # Cumulative packet size per connected master and slave (bytes) 327511374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoops 2848440 # Total snoops (count) 327611374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::samples 7664337 # Request fanout histogram 327711374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::mean 0.347835 # Request fanout histogram 327811374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram 327910515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 328011374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::0 5009678 65.36% 65.36% # Request fanout histogram 328111374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::1 2643397 34.49% 99.85% # Request fanout histogram 328211374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::2 11262 0.15% 100.00% # Request fanout histogram 328310515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 328411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 328510515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 328611374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::total 7664337 # Request fanout histogram 328711374Ssteve.reinhardt@amd.comsystem.toL2Bus.reqLayer0.occupancy 8363064932 # Layer occupancy (ticks) 328810515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 328911374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoopLayer0.occupancy 2585436 # Layer occupancy (ticks) 329010515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 329111374Ssteve.reinhardt@amd.comsystem.toL2Bus.respLayer0.occupancy 3816515270 # Layer occupancy (ticks) 329210515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 329311374Ssteve.reinhardt@amd.comsystem.toL2Bus.respLayer1.occupancy 3482933794 # Layer occupancy (ticks) 329410515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 329510515SN/A 329610515SN/A---------- End Simulation Statistics ---------- 3297