stats.txt revision 11353
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311353Sandreas.hansson@arm.comsim_seconds 47.579919 # Number of seconds simulated 411353Sandreas.hansson@arm.comsim_ticks 47579919171500 # Number of ticks simulated 511353Sandreas.hansson@arm.comfinal_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711353Sandreas.hansson@arm.comhost_inst_rate 994477 # Simulator instruction rate (inst/s) 811353Sandreas.hansson@arm.comhost_op_rate 1169790 # Simulator op (including micro ops) rate (op/s) 911353Sandreas.hansson@arm.comhost_tick_rate 52043300787 # Simulator tick rate (ticks/s) 1011353Sandreas.hansson@arm.comhost_mem_usage 760992 # Number of bytes of host memory used 1111353Sandreas.hansson@arm.comhost_seconds 914.24 # Real time elapsed on the host 1211353Sandreas.hansson@arm.comsim_insts 909188095 # Number of instructions simulated 1311353Sandreas.hansson@arm.comsim_ops 1069465904 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory 1711353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory 1811353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory 1911353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory 2011353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory 2111353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory 2211353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory 2311353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory 2411353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory 2511353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory 2611353Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory 2711353Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 66121412 # Number of bytes read from this memory 2811353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory 2911353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory 3011353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory 3111353Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411353Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 84323880 # Number of bytes written to this memory 3511353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory 3611353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory 3711353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory 3811353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory 3911353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory 4011353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory 4111353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory 4211353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory 4311353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory 4411353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory 4511353Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory 4611353Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory 4711353Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011353Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory 5111353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s) 5211353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s) 5311353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s) 5411353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s) 5511353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s) 5611353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s) 5711353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s) 5811353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s) 5911353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s) 6011353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s) 6111353Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s) 6211353Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s) 6311353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s) 6411353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s) 6511353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s) 6611353Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s) 6711353Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911353Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s) 7011353Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s) 7111353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s) 7211353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s) 7311353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s) 7411353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s) 7511353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s) 7611353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s) 7711353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s) 7811353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s) 7911353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s) 8011353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s) 8111353Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s) 8211353Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s) 8311353Sandreas.hansson@arm.comsystem.physmem.readReqs 1073668 # Number of read requests accepted 8411353Sandreas.hansson@arm.comsystem.physmem.writeReqs 1319813 # Number of write requests accepted 8511353Sandreas.hansson@arm.comsystem.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue 8611353Sandreas.hansson@arm.comsystem.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue 8711353Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM 8811353Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue 8911353Sandreas.hansson@arm.comsystem.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM 9011353Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side 9111353Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side 9211353Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue 9311353Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one 9411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9511353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 64017 # Per bank write bursts 9611353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 68044 # Per bank write bursts 9711353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 61517 # Per bank write bursts 9811353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 65955 # Per bank write bursts 9911353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 65874 # Per bank write bursts 10011353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 75726 # Per bank write bursts 10111353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 64933 # Per bank write bursts 10211353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 65424 # Per bank write bursts 10311353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 62003 # Per bank write bursts 10411353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 113372 # Per bank write bursts 10511353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 63434 # Per bank write bursts 10611353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 64718 # Per bank write bursts 10711353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 56904 # Per bank write bursts 10811353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 64084 # Per bank write bursts 10911353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 56898 # Per bank write bursts 11011353Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 60394 # Per bank write bursts 11111353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 80527 # Per bank write bursts 11211353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 85904 # Per bank write bursts 11311353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 80420 # Per bank write bursts 11411353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 86054 # Per bank write bursts 11511353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 85401 # Per bank write bursts 11611353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 88715 # Per bank write bursts 11711353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 80808 # Per bank write bursts 11811353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 81222 # Per bank write bursts 11911353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 80522 # Per bank write bursts 12011353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 87926 # Per bank write bursts 12111353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 79616 # Per bank write bursts 12211353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 81105 # Per bank write bursts 12311353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 77689 # Per bank write bursts 12411353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 84231 # Per bank write bursts 12511353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 77252 # Per bank write bursts 12611353Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 80134 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811353Sandreas.hansson@arm.comsystem.physmem.numWrRetry 116 # Number of times write queue was full causing retry 12911353Sandreas.hansson@arm.comsystem.physmem.totGap 47579915806000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611353Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1030443 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311353Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1317239 # Write request sizes (log2) 14411353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 761963 # What read queue length does an incoming req see 14511353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 94096 # What read queue length does an incoming req see 14611353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 44762 # What read queue length does an incoming req see 14711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 38689 # What read queue length does an incoming req see 14811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 33193 # What read queue length does an incoming req see 14911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 29336 # What read queue length does an incoming req see 15011353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 25572 # What read queue length does an incoming req see 15111353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 22083 # What read queue length does an incoming req see 15211353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 17610 # What read queue length does an incoming req see 15311353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see 15411353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1054 # What read queue length does an incoming req see 15511353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 617 # What read queue length does an incoming req see 15611353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 470 # What read queue length does an incoming req see 15711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 330 # What read queue length does an incoming req see 15811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 233 # What read queue length does an incoming req see 15911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 201 # What read queue length does an incoming req see 16011353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 153 # What read queue length does an incoming req see 16111353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 138 # What read queue length does an incoming req see 16211353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see 16311353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see 16411353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 35874 # What write queue length does an incoming req see 19211353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 42279 # What write queue length does an incoming req see 19311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 54831 # What write queue length does an incoming req see 19411353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 58608 # What write queue length does an incoming req see 19511353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 65543 # What write queue length does an incoming req see 19611353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 69713 # What write queue length does an incoming req see 19711353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 74423 # What write queue length does an incoming req see 19811353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 78144 # What write queue length does an incoming req see 19911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 80302 # What write queue length does an incoming req see 20011353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 80268 # What write queue length does an incoming req see 20111353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 82803 # What write queue length does an incoming req see 20211353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 85991 # What write queue length does an incoming req see 20311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 82780 # What write queue length does an incoming req see 20411353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 84137 # What write queue length does an incoming req see 20511353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 91440 # What write queue length does an incoming req see 20611353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 82956 # What write queue length does an incoming req see 20711353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 77042 # What write queue length does an incoming req see 20811353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 74792 # What write queue length does an incoming req see 20911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3448 # What write queue length does an incoming req see 21011353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1528 # What write queue length does an incoming req see 21111353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see 21211353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 878 # What write queue length does an incoming req see 21311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 781 # What write queue length does an incoming req see 21411353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 698 # What write queue length does an incoming req see 21511353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 574 # What write queue length does an incoming req see 21611353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 498 # What write queue length does an incoming req see 21711353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 492 # What write queue length does an incoming req see 21811353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 412 # What write queue length does an incoming req see 21911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see 22011353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see 22111353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 374 # What write queue length does an incoming req see 22211353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see 22311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see 22411353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see 22511353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see 22611353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see 22711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see 22811353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see 22911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see 23011353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see 23111353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see 23211353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see 23311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see 23411353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 154 # What write queue length does an incoming req see 23511353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 157 # What write queue length does an incoming req see 23611353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 23711353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see 23811353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 157 # What write queue length does an incoming req see 23911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 302 # What write queue length does an incoming req see 24011353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1107709 # Bytes accessed per row activation 24111353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 138.133954 # Bytes accessed per row activation 24211353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 95.206974 # Bytes accessed per row activation 24311353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 184.490982 # Bytes accessed per row activation 24411353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 762645 68.85% 68.85% # Bytes accessed per row activation 24511353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 210995 19.05% 87.90% # Bytes accessed per row activation 24611353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 48832 4.41% 92.31% # Bytes accessed per row activation 24711353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 22284 2.01% 94.32% # Bytes accessed per row activation 24811353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 16979 1.53% 95.85% # Bytes accessed per row activation 24911353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 10320 0.93% 96.78% # Bytes accessed per row activation 25011353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 6180 0.56% 97.34% # Bytes accessed per row activation 25111353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 5743 0.52% 97.86% # Bytes accessed per row activation 25211353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 23731 2.14% 100.00% # Bytes accessed per row activation 25311353Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1107709 # Bytes accessed per row activation 25411353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 70958 # Reads before turning the bus around for writes 25511353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 15.125666 # Reads before turning the bus around for writes 25611353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 121.252784 # Reads before turning the bus around for writes 25711353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 70954 99.99% 99.99% # Reads before turning the bus around for writes 25811353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 70958 # Reads before turning the bus around for writes 26211353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 70958 # Writes before turning the bus around for reads 26311353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 18.567688 # Writes before turning the bus around for reads 26411353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.991036 # Writes before turning the bus around for reads 26511353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.306981 # Writes before turning the bus around for reads 26611353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 58539 82.50% 82.50% # Writes before turning the bus around for reads 26711353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 9965 14.04% 96.54% # Writes before turning the bus around for reads 26811353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 642 0.90% 97.45% # Writes before turning the bus around for reads 26911353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 182 0.26% 97.70% # Writes before turning the bus around for reads 27011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 135 0.19% 97.89% # Writes before turning the bus around for reads 27111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 121 0.17% 98.06% # Writes before turning the bus around for reads 27211353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 191 0.27% 98.33% # Writes before turning the bus around for reads 27311353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 83 0.12% 98.45% # Writes before turning the bus around for reads 27411353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 286 0.40% 98.85% # Writes before turning the bus around for reads 27511353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 59 0.08% 98.94% # Writes before turning the bus around for reads 27611353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 34 0.05% 98.98% # Writes before turning the bus around for reads 27711353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 42 0.06% 99.04% # Writes before turning the bus around for reads 27811353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 259 0.37% 99.41% # Writes before turning the bus around for reads 27911353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 42 0.06% 99.47% # Writes before turning the bus around for reads 28011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 31 0.04% 99.51% # Writes before turning the bus around for reads 28111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 116 0.16% 99.67% # Writes before turning the bus around for reads 28211353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 167 0.24% 99.91% # Writes before turning the bus around for reads 28311353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads 28411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 28511353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads 28611353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads 28711353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads 28811353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads 28911353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads 29011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 4 0.01% 99.94% # Writes before turning the bus around for reads 29111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads 29211353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 29311353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads 29411353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 8 0.01% 99.98% # Writes before turning the bus around for reads 29511353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 29611353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 29711353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads 29811353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 99.98% # Writes before turning the bus around for reads 29911353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 8 0.01% 99.99% # Writes before turning the bus around for reads 30011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 30111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads 30211353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads 30311353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads 30411353Sandreas.hansson@arm.comsystem.physmem.totQLat 35332291342 # Total ticks spent queuing 30511353Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM 30611353Sandreas.hansson@arm.comsystem.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers 30711353Sandreas.hansson@arm.comsystem.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst 30810515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30911353Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst 31011353Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s 31111353Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s 31211353Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s 31311353Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s 31410515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31510827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31611201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31710892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31811353Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing 31911353Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing 32011353Sandreas.hansson@arm.comsystem.physmem.readRowHits 793862 # Number of row buffer hits during reads 32111353Sandreas.hansson@arm.comsystem.physmem.writeRowHits 489250 # Number of row buffer hits during writes 32211353Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads 32311353Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes 32411353Sandreas.hansson@arm.comsystem.physmem.avgGap 19878961.15 # Average gap between requests 32511353Sandreas.hansson@arm.comsystem.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined 32611353Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ) 32711353Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ) 32811353Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ) 32911353Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ) 33011353Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) 33111353Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ) 33211353Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ) 33311353Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ) 33411353Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.795690 # Core power per rank (mW) 33511353Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states 33611353Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states 33710628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33811353Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states 33910628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34011353Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ) 34111353Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ) 34211353Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ) 34311353Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ) 34411353Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) 34511353Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ) 34611353Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ) 34711353Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ) 34811353Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.771738 # Core power per rank (mW) 34911353Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states 35011353Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states 35110628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35211353Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states 35310628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35410515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35810515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35910515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 36010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 36110515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 36210515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36310515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36410515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36510515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36610515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36710515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37710515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37810515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37910515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 38010535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38110535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38210535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38311353Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38411353Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38511353Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38610515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41611353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 116306 # Table walker walks requested 41711353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors 41811353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate 41911353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate 42011353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 42111353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency 42211353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency 42311353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency 42411353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42611353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency 42711353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency 42811353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency 42911353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency 43011353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency 43111353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency 43211353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency 43311353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency 43411353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency 43511353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency 43611353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency 43711353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency 43811353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 43911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 44011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44111353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44211353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency 44311353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution 44411353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution 44511353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution 44611353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution 44711353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution 44811353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution 44911353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated 45011353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated 45111353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated 45211353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst 45310628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45411353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst 45511353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst 45610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45711353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst 45811353Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst 45910535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46010535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46111353Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 86290817 # DTB read hits 46211353Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 86990 # DTB read misses 46311353Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 77965379 # DTB write hits 46411353Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 29316 # DTB write misses 46510535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46610535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46711353Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID 46811353Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID 46911353Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB 47010535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 47111353Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch 47210535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47311353Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions 47411353Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 86377807 # DTB read accesses 47511353Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 77994695 # DTB write accesses 47610535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47711353Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 164256196 # DTB hits 47811353Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 116306 # DTB misses 47911353Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 164372502 # DTB accesses 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50911353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 53337 # Table walker walks requested 51011353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors 51111353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate 51211353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate 51311353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency 51411353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51511353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency 51611353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency 51711353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency 51811353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency 51911353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency 52011353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency 52111353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency 52211353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency 52311353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency 52411353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency 52511353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency 52611353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency 52711353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 52811353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 52911353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53011353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53111353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53211353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency 53311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 53511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 53611353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated 53711353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated 53811353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated 53910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54011353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst 54111353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst 54210628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54311353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst 54411353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst 54511353Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst 54611353Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 461259285 # ITB inst hits 54711353Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 53337 # ITB inst misses 54810535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54910535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 55010535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 55110535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 55210535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55310535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55411353Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID 55511353Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID 55611353Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB 55710535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55810535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55910535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56010535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56110535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 56210535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 56311353Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 461312622 # ITB inst accesses 56411353Sandreas.hansson@arm.comsystem.cpu0.itb.hits 461259285 # DTB hits 56511353Sandreas.hansson@arm.comsystem.cpu0.itb.misses 53337 # DTB misses 56611353Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 461312622 # DTB accesses 56711353Sandreas.hansson@arm.comsystem.cpu0.numCycles 95159838338 # number of cpu cycles simulated 56810535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56910535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 57011167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 57111353Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed 57211353Sandreas.hansson@arm.comsystem.cpu0.committedInsts 460977499 # Number of instructions committed 57311353Sandreas.hansson@arm.comsystem.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed 57411353Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses 57511353Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses 57611353Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 27096084 # number of times a function call or return occured 57711353Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls 57811353Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 495872658 # number of integer instructions 57911353Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 377758 # number of float instructions 58011353Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read 58111353Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written 58211353Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read 58311353Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written 58411353Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read 58511353Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written 58611353Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 164249297 # number of memory refs 58711353Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 86287437 # Number of load instructions 58811353Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 77961860 # Number of store instructions 58911353Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles 59011353Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles 59111353Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles 59211353Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.987161 # Percentage of idle cycles 59311353Sandreas.hansson@arm.comsystem.cpu0.Branches 102925889 # Number of branches fetched 59411201Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 59511353Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction 59611353Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction 59711353Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction 59811353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction 59911353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction 60011353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction 60111353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction 60211353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction 60311353Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction 60411353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction 60511353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction 60611353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction 60711353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction 60811353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction 60911353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction 61011353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction 61111353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction 61211353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction 61311353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction 61411353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction 61511353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction 61611353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction 61711353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction 61811353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction 61911353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction 62011353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction 62111353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction 62211353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction 62311353Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction 62411353Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction 62511353Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction 62610535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 62710535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62811353Sandreas.hansson@arm.comsystem.cpu0.op_class::total 541013060 # Class of executed instruction 62911353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5729731 # number of replacements 63011353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use 63111353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks. 63211353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks. 63311353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks. 63411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 63511353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor 63611353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy 63711353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy 63811353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 63911353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 64011353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id 64111353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id 64211353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 64311353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 64411353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses 64511353Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses 64611353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits 64711353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits 64811353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits 64911353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits 65011353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits 65111353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits 65211353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits 65311353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits 65411353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits 65511353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits 65611353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits 65711353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits 65811353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits 65911353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits 66011353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits 66111353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 153932821 # number of overall hits 66211353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses 66311353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses 66411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses 66511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses 66611353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses 66711353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses 66811353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses 66911353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses 67011353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses 67111353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses 67211353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses 67311353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses 67411353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses 67511353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses 67611353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses 67711353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5223943 # number of overall misses 67811353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles 67911353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles 68011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles 68111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles 68211353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49559521500 # number of WriteLineReq miss cycles 68311353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 49559521500 # number of WriteLineReq miss cycles 68411353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2516267500 # number of LoadLockedReq miss cycles 68511353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2516267500 # number of LoadLockedReq miss cycles 68611353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5589291500 # number of StoreCondReq miss cycles 68711353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5589291500 # number of StoreCondReq miss cycles 68811353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2738500 # number of StoreCondFailReq miss cycles 68911353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2738500 # number of StoreCondFailReq miss cycles 69011353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 90800968500 # number of demand (read+write) miss cycles 69111353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 90800968500 # number of demand (read+write) miss cycles 69211353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 90800968500 # number of overall miss cycles 69311353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 90800968500 # number of overall miss cycles 69411353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 83324174 # number of ReadReq accesses(hits+misses) 69511353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 83324174 # number of ReadReq accesses(hits+misses) 69611353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74936215 # number of WriteReq accesses(hits+misses) 69711353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 74936215 # number of WriteReq accesses(hits+misses) 69811353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 896375 # number of SoftPFReq accesses(hits+misses) 69911353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 896375 # number of SoftPFReq accesses(hits+misses) 70011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 953537 # number of WriteLineReq accesses(hits+misses) 70111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 953537 # number of WriteLineReq accesses(hits+misses) 70211353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2041774 # number of LoadLockedReq accesses(hits+misses) 70311353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2041774 # number of LoadLockedReq accesses(hits+misses) 70411353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2040330 # number of StoreCondReq accesses(hits+misses) 70511353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2040330 # number of StoreCondReq accesses(hits+misses) 70611353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 158260389 # number of demand (read+write) accesses 70711353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 158260389 # number of demand (read+write) accesses 70811353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 159156764 # number of overall (read+write) accesses 70911353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 159156764 # number of overall (read+write) accesses 71011353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036964 # miss rate for ReadReq accesses 71111353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036964 # miss rate for ReadReq accesses 71211353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019323 # miss rate for WriteReq accesses 71311353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.019323 # miss rate for WriteReq accesses 71411353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.776409 # miss rate for SoftPFReq accesses 71511353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.776409 # miss rate for SoftPFReq accesses 71611353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.806155 # miss rate for WriteLineReq accesses 71711353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.806155 # miss rate for WriteLineReq accesses 71811353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077614 # miss rate for LoadLockedReq accesses 71911353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077614 # miss rate for LoadLockedReq accesses 72011353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097109 # miss rate for StoreCondReq accesses 72111353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.097109 # miss rate for StoreCondReq accesses 72211353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.028611 # miss rate for demand accesses 72311353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.028611 # miss rate for demand accesses 72411353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032823 # miss rate for overall accesses 72511353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032823 # miss rate for overall accesses 72611353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546 # average ReadReq miss latency 72711353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546 # average ReadReq miss latency 72811353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993 # average WriteReq miss latency 72911353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993 # average WriteReq miss latency 73011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407 # average WriteLineReq miss latency 73111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407 # average WriteLineReq miss latency 73211353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128 # average LoadLockedReq miss latency 73311353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128 # average LoadLockedReq miss latency 73411353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568 # average StoreCondReq miss latency 73511353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568 # average StoreCondReq miss latency 73610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 73710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 73811353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141 # average overall miss latency 73911353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20053.266141 # average overall miss latency 74011353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048 # average overall miss latency 74111353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17381.692048 # average overall miss latency 74210535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 74310535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74410535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 74510535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 74610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74710535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74810585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 74910535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 75011353Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5729731 # number of writebacks 75111353Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5729731 # number of writebacks 75211353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28073 # number of ReadReq MSHR hits 75311353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 28073 # number of ReadReq MSHR hits 75411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21239 # number of WriteReq MSHR hits 75511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21239 # number of WriteReq MSHR hits 75611353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41058 # number of LoadLockedReq MSHR hits 75711353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 41058 # number of LoadLockedReq MSHR hits 75811353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 49312 # number of demand (read+write) MSHR hits 75911353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 49312 # number of demand (read+write) MSHR hits 76011353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 49312 # number of overall MSHR hits 76111353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 49312 # number of overall MSHR hits 76211353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3051928 # number of ReadReq MSHR misses 76311353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3051928 # number of ReadReq MSHR misses 76411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1426749 # number of WriteReq MSHR misses 76511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1426749 # number of WriteReq MSHR misses 76611353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694810 # number of SoftPFReq MSHR misses 76711353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 694810 # number of SoftPFReq MSHR misses 76811353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 768699 # number of WriteLineReq MSHR misses 76911353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 768699 # number of WriteLineReq MSHR misses 77011353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117412 # number of LoadLockedReq MSHR misses 77111353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 117412 # number of LoadLockedReq MSHR misses 77211353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198134 # number of StoreCondReq MSHR misses 77311353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 198134 # number of StoreCondReq MSHR misses 77411353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4478677 # number of demand (read+write) MSHR misses 77511353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4478677 # number of demand (read+write) MSHR misses 77611353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5173487 # number of overall MSHR misses 77711353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5173487 # number of overall MSHR misses 77811353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable 77911353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable 78011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable 78111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable 78211353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses 78311353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 56385 # number of overall MSHR uncacheable misses 78411353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47315434500 # number of ReadReq MSHR miss cycles 78511353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 47315434500 # number of ReadReq MSHR miss cycles 78611353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36384996000 # number of WriteReq MSHR miss cycles 78711353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 36384996000 # number of WriteReq MSHR miss cycles 78811353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17003029000 # number of SoftPFReq MSHR miss cycles 78911353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17003029000 # number of SoftPFReq MSHR miss cycles 79011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 48790822500 # number of WriteLineReq MSHR miss cycles 79111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 48790822500 # number of WriteLineReq MSHR miss cycles 79211353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1643233500 # number of LoadLockedReq MSHR miss cycles 79311353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles 79411353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5391195500 # number of StoreCondReq MSHR miss cycles 79511353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5391195500 # number of StoreCondReq MSHR miss cycles 79611353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2700500 # number of StoreCondFailReq MSHR miss cycles 79711353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2700500 # number of StoreCondFailReq MSHR miss cycles 79811353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83700430500 # number of demand (read+write) MSHR miss cycles 79911353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 83700430500 # number of demand (read+write) MSHR miss cycles 80011353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100703459500 # number of overall MSHR miss cycles 80111353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 100703459500 # number of overall MSHR miss cycles 80211353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5280351500 # number of ReadReq MSHR uncacheable cycles 80311353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5280351500 # number of ReadReq MSHR uncacheable cycles 80411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086850000 # number of WriteReq MSHR uncacheable cycles 80511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086850000 # number of WriteReq MSHR uncacheable cycles 80611353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10367201500 # number of overall MSHR uncacheable cycles 80711353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 10367201500 # number of overall MSHR uncacheable cycles 80811353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036627 # mshr miss rate for ReadReq accesses 80911353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036627 # mshr miss rate for ReadReq accesses 81011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019040 # mshr miss rate for WriteReq accesses 81111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019040 # mshr miss rate for WriteReq accesses 81211353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775133 # mshr miss rate for SoftPFReq accesses 81311353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses 81411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses 81511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.806155 # mshr miss rate for WriteLineReq accesses 81611353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses 81711353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses 81811353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097109 # mshr miss rate for StoreCondReq accesses 81911353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097109 # mshr miss rate for StoreCondReq accesses 82011353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028299 # mshr miss rate for demand accesses 82111353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028299 # mshr miss rate for demand accesses 82211353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses 82311353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses 82411353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency 82511353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency 82611353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency 82711353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency 82811353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency 82911353Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency 83011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency 83111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency 83211353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency 83311353Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency 83411353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency 83511353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency 83610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 83710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 83811353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800 # average overall mshr miss latency 83911353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency 84011353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714 # average overall mshr miss latency 84111353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714 # average overall mshr miss latency 84211353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency 84311353Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency 84411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738 # average WriteReq mshr uncacheable latency 84511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738 # average WriteReq mshr uncacheable latency 84611353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573 # average overall mshr uncacheable latency 84711353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency 84810535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84911353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 4741257 # number of replacements 85011353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use 85111353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks. 85211353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 4741769 # Sample count of references to valid blocks. 85311353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 96.275780 # Average number of references to valid blocks. 85411353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. 85511353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.854043 # Average occupied blocks per requestor 85611353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999715 # Average percentage of cache occupancy 85711353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999715 # Average percentage of cache occupancy 85810535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85911353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 86011353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 86111353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 86211353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 86310535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 86411353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 927260344 # Number of tag accesses 86511353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 927260344 # Number of data accesses 86611353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 456517510 # number of ReadReq hits 86711353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 456517510 # number of ReadReq hits 86811353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 456517510 # number of demand (read+write) hits 86911353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 456517510 # number of demand (read+write) hits 87011353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 456517510 # number of overall hits 87111353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 456517510 # number of overall hits 87211353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4741775 # number of ReadReq misses 87311353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 4741775 # number of ReadReq misses 87411353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4741775 # number of demand (read+write) misses 87511353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 4741775 # number of demand (read+write) misses 87611353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4741775 # number of overall misses 87711353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 4741775 # number of overall misses 87811353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53890518500 # number of ReadReq miss cycles 87911353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 53890518500 # number of ReadReq miss cycles 88011353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 53890518500 # number of demand (read+write) miss cycles 88111353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 53890518500 # number of demand (read+write) miss cycles 88211353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 53890518500 # number of overall miss cycles 88311353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 53890518500 # number of overall miss cycles 88411353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 461259285 # number of ReadReq accesses(hits+misses) 88511353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 461259285 # number of ReadReq accesses(hits+misses) 88611353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 461259285 # number of demand (read+write) accesses 88711353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 461259285 # number of demand (read+write) accesses 88811353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 461259285 # number of overall (read+write) accesses 88911353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 461259285 # number of overall (read+write) accesses 89011353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010280 # miss rate for ReadReq accesses 89111353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010280 # miss rate for ReadReq accesses 89211353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010280 # miss rate for demand accesses 89311353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.010280 # miss rate for demand accesses 89411353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010280 # miss rate for overall accesses 89511353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.010280 # miss rate for overall accesses 89611353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11365.051800 # average ReadReq miss latency 89711353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800 # average ReadReq miss latency 89811353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency 89911353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency 90011353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency 90111353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11365.051800 # average overall miss latency 90210535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 90310535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90410535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 90510535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 90610535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90710535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90810535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 90910535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 91011353Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 4741257 # number of writebacks 91111353Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 4741257 # number of writebacks 91211353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4741775 # number of ReadReq MSHR misses 91311353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4741775 # number of ReadReq MSHR misses 91411353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4741775 # number of demand (read+write) MSHR misses 91511353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4741775 # number of demand (read+write) MSHR misses 91611353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4741775 # number of overall MSHR misses 91711353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4741775 # number of overall MSHR misses 91810827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 91910827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 92010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 92110827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 92211353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51519631500 # number of ReadReq MSHR miss cycles 92311353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 51519631500 # number of ReadReq MSHR miss cycles 92411353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51519631500 # number of demand (read+write) MSHR miss cycles 92511353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 51519631500 # number of demand (read+write) MSHR miss cycles 92611353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51519631500 # number of overall MSHR miss cycles 92711353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 51519631500 # number of overall MSHR miss cycles 92811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 92911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 93011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 93111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 93211353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for ReadReq accesses 93311353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010280 # mshr miss rate for ReadReq accesses 93411353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for demand accesses 93511353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010280 # mshr miss rate for demand accesses 93611353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for overall accesses 93711353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010280 # mshr miss rate for overall accesses 93811353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average ReadReq mshr miss latency 93911353Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10865.051906 # average ReadReq mshr miss latency 94011353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency 94111353Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency 94211353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency 94311353Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency 94411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 94511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 94611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 94711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 94810535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8039497 # number of hwpf issued 95011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8039521 # number of prefetch candidates identified 95111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue 95210628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 95310628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 95411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1012143 # number of prefetches not generated due to page crossing 95511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2514209 # number of replacements 95611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16169.325614 # Cycle average of tags in use 95711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 14408578 # Total number of references to valid blocks. 95811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2529817 # Sample count of references to valid blocks. 95911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.695502 # Average number of references to valid blocks. 96011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit. 96111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15164.632353 # Average occupied blocks per requestor 96211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.004325 # Average occupied blocks per requestor 96311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 56.118535 # Average occupied blocks per requestor 96411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 903.570401 # Average occupied blocks per requestor 96511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.925576 # Average percentage of cache occupancy 96611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002747 # Average percentage of cache occupancy 96711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003425 # Average percentage of cache occupancy 96811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.055150 # Average percentage of cache occupancy 96911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986897 # Average percentage of cache occupancy 97011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1599 # Occupied blocks per task id 97111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id 97211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13927 # Occupied blocks per task id 97311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id 97411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 682 # Occupied blocks per task id 97511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id 97611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 97711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 97811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 97911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 98011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id 98111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2528 # Occupied blocks per task id 98211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5951 # Occupied blocks per task id 98311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5308 # Occupied blocks per task id 98411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097595 # Percentage of cache occupancy per task id 98511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id 98611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.850037 # Percentage of cache occupancy per task id 98711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 356318803 # Number of tag accesses 98811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 356318803 # Number of data accesses 98911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 276065 # number of ReadReq hits 99011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 135571 # number of ReadReq hits 99111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 411636 # number of ReadReq hits 99211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3830429 # number of WritebackDirty hits 99311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3830429 # number of WritebackDirty hits 99411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6639546 # number of WritebackClean hits 99511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6639546 # number of WritebackClean hits 99611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 500 # number of UpgradeReq hits 99711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 500 # number of UpgradeReq hits 99811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 929961 # number of ReadExReq hits 99911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 929961 # number of ReadExReq hits 100011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4274266 # number of ReadCleanReq hits 100111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4274266 # number of ReadCleanReq hits 100211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2881532 # number of ReadSharedReq hits 100311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2881532 # number of ReadSharedReq hits 100411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 169886 # number of InvalidateReq hits 100511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 169886 # number of InvalidateReq hits 100611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 276065 # number of demand (read+write) hits 100711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 135571 # number of demand (read+write) hits 100811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4274266 # number of demand (read+write) hits 100911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3811493 # number of demand (read+write) hits 101011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8497395 # number of demand (read+write) hits 101111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 276065 # number of overall hits 101211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 135571 # number of overall hits 101311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4274266 # number of overall hits 101411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3811493 # number of overall hits 101511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8497395 # number of overall hits 101611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10002 # number of ReadReq misses 101711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7458 # number of ReadReq misses 101811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 17460 # number of ReadReq misses 101911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 252814 # number of UpgradeReq misses 102011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 252814 # number of UpgradeReq misses 102111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 198129 # number of SCUpgradeReq misses 102211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 198129 # number of SCUpgradeReq misses 102311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 102411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 102511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 262789 # number of ReadExReq misses 102611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 262789 # number of ReadExReq misses 102711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 467509 # number of ReadCleanReq misses 102811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 467509 # number of ReadCleanReq misses 102911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 982618 # number of ReadSharedReq misses 103011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 982618 # number of ReadSharedReq misses 103111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 596960 # number of InvalidateReq misses 103211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 596960 # number of InvalidateReq misses 103311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10002 # number of demand (read+write) misses 103411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 7458 # number of demand (read+write) misses 103511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 467509 # number of demand (read+write) misses 103611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1245407 # number of demand (read+write) misses 103711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1730376 # number of demand (read+write) misses 103811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10002 # number of overall misses 103911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 7458 # number of overall misses 104011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 467509 # number of overall misses 104111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1245407 # number of overall misses 104211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1730376 # number of overall misses 104311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 427118500 # number of ReadReq miss cycles 104411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 335132000 # number of ReadReq miss cycles 104511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 762250500 # number of ReadReq miss cycles 104611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3305201500 # number of UpgradeReq miss cycles 104711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3305201500 # number of UpgradeReq miss cycles 104811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2087626000 # number of SCUpgradeReq miss cycles 104911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2087626000 # number of SCUpgradeReq miss cycles 105011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2642498 # number of SCUpgradeFailReq miss cycles 105111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2642498 # number of SCUpgradeFailReq miss cycles 105211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18677102500 # number of ReadExReq miss cycles 105311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 18677102500 # number of ReadExReq miss cycles 105411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18746620500 # number of ReadCleanReq miss cycles 105511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 18746620500 # number of ReadCleanReq miss cycles 105611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41394693000 # number of ReadSharedReq miss cycles 105711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 41394693000 # number of ReadSharedReq miss cycles 105811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 415110500 # number of InvalidateReq miss cycles 105911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 415110500 # number of InvalidateReq miss cycles 106011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 427118500 # number of demand (read+write) miss cycles 106111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 335132000 # number of demand (read+write) miss cycles 106211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 18746620500 # number of demand (read+write) miss cycles 106311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 60071795500 # number of demand (read+write) miss cycles 106411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 79580666500 # number of demand (read+write) miss cycles 106511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 427118500 # number of overall miss cycles 106611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 335132000 # number of overall miss cycles 106711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 18746620500 # number of overall miss cycles 106811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 60071795500 # number of overall miss cycles 106911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 79580666500 # number of overall miss cycles 107011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 286067 # number of ReadReq accesses(hits+misses) 107111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 143029 # number of ReadReq accesses(hits+misses) 107211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 429096 # number of ReadReq accesses(hits+misses) 107311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3830429 # number of WritebackDirty accesses(hits+misses) 107411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3830429 # number of WritebackDirty accesses(hits+misses) 107511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6639546 # number of WritebackClean accesses(hits+misses) 107611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6639546 # number of WritebackClean accesses(hits+misses) 107711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 253314 # number of UpgradeReq accesses(hits+misses) 107811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 253314 # number of UpgradeReq accesses(hits+misses) 107911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 198129 # number of SCUpgradeReq accesses(hits+misses) 108011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 198129 # number of SCUpgradeReq accesses(hits+misses) 108111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 108211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 108311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1192750 # number of ReadExReq accesses(hits+misses) 108411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1192750 # number of ReadExReq accesses(hits+misses) 108511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4741775 # number of ReadCleanReq accesses(hits+misses) 108611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4741775 # number of ReadCleanReq accesses(hits+misses) 108711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3864150 # number of ReadSharedReq accesses(hits+misses) 108811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3864150 # number of ReadSharedReq accesses(hits+misses) 108911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 766846 # number of InvalidateReq accesses(hits+misses) 109011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 766846 # number of InvalidateReq accesses(hits+misses) 109111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 286067 # number of demand (read+write) accesses 109211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 143029 # number of demand (read+write) accesses 109311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4741775 # number of demand (read+write) accesses 109411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5056900 # number of demand (read+write) accesses 109511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 10227771 # number of demand (read+write) accesses 109611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 286067 # number of overall (read+write) accesses 109711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 143029 # number of overall (read+write) accesses 109811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4741775 # number of overall (read+write) accesses 109911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5056900 # number of overall (read+write) accesses 110011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 10227771 # number of overall (read+write) accesses 110111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for ReadReq accesses 110211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052143 # miss rate for ReadReq accesses 110311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.040690 # miss rate for ReadReq accesses 110411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998026 # miss rate for UpgradeReq accesses 110511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998026 # miss rate for UpgradeReq accesses 110611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 110711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 111011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.220322 # miss rate for ReadExReq accesses 111111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.220322 # miss rate for ReadExReq accesses 111211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098594 # miss rate for ReadCleanReq accesses 111311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098594 # miss rate for ReadCleanReq accesses 111411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.254291 # miss rate for ReadSharedReq accesses 111511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.254291 # miss rate for ReadSharedReq accesses 111611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.778461 # miss rate for InvalidateReq accesses 111711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.778461 # miss rate for InvalidateReq accesses 111811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for demand accesses 111911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052143 # miss rate for demand accesses 112011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098594 # miss rate for demand accesses 112111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246279 # miss rate for demand accesses 112211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.169184 # miss rate for demand accesses 112311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for overall accesses 112411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052143 # miss rate for overall accesses 112511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098594 # miss rate for overall accesses 112611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246279 # miss rate for overall accesses 112711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.169184 # miss rate for overall accesses 112811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average ReadReq miss latency 112911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44935.907750 # average ReadReq miss latency 113011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 43656.958763 # average ReadReq miss latency 113111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13073.649007 # average UpgradeReq miss latency 113211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13073.649007 # average UpgradeReq miss latency 113311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10536.700836 # average SCUpgradeReq miss latency 113411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10536.700836 # average SCUpgradeReq miss latency 113511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528499.600000 # average SCUpgradeFailReq miss latency 113611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528499.600000 # average SCUpgradeFailReq miss latency 113711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 71072.619097 # average ReadExReq miss latency 113811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 71072.619097 # average ReadExReq miss latency 113911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40098.951036 # average ReadCleanReq miss latency 114011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40098.951036 # average ReadCleanReq miss latency 114111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 42126.943532 # average ReadSharedReq miss latency 114211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 42126.943532 # average ReadSharedReq miss latency 114311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 695.374062 # average InvalidateReq miss latency 114411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 695.374062 # average InvalidateReq miss latency 114511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average overall miss latency 114611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44935.907750 # average overall miss latency 114711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40098.951036 # average overall miss latency 114811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48234.669871 # average overall miss latency 114911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 45990.389661 # average overall miss latency 115011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average overall miss latency 115111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44935.907750 # average overall miss latency 115211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40098.951036 # average overall miss latency 115311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48234.669871 # average overall miss latency 115411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 45990.389661 # average overall miss latency 115510628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 115610535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115710628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 115810535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 115910628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 116010535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 116110535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 116210535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 116311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1647047 # number of writebacks 116411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1647047 # number of writebacks 116511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9683 # number of ReadExReq MSHR hits 116611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9683 # number of ReadExReq MSHR hits 116711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 697 # number of ReadSharedReq MSHR hits 116811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 697 # number of ReadSharedReq MSHR hits 116911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 10380 # number of demand (read+write) MSHR hits 117011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 10380 # number of demand (read+write) MSHR hits 117111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 10380 # number of overall MSHR hits 117211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 10380 # number of overall MSHR hits 117311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10002 # number of ReadReq MSHR misses 117411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7458 # number of ReadReq MSHR misses 117511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 17460 # number of ReadReq MSHR misses 117611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 803286 # number of HardPFReq MSHR misses 117711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 803286 # number of HardPFReq MSHR misses 117811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 252814 # number of UpgradeReq MSHR misses 117911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 252814 # number of UpgradeReq MSHR misses 118011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 198129 # number of SCUpgradeReq MSHR misses 118111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 198129 # number of SCUpgradeReq MSHR misses 118211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 118311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 118411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 253106 # number of ReadExReq MSHR misses 118511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 253106 # number of ReadExReq MSHR misses 118611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 467509 # number of ReadCleanReq MSHR misses 118711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 467509 # number of ReadCleanReq MSHR misses 118811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 981921 # number of ReadSharedReq MSHR misses 118911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 981921 # number of ReadSharedReq MSHR misses 119011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 596960 # number of InvalidateReq MSHR misses 119111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 596960 # number of InvalidateReq MSHR misses 119211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10002 # number of demand (read+write) MSHR misses 119311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7458 # number of demand (read+write) MSHR misses 119411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 467509 # number of demand (read+write) MSHR misses 119511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1235027 # number of demand (read+write) MSHR misses 119611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1719996 # number of demand (read+write) MSHR misses 119711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10002 # number of overall MSHR misses 119811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7458 # number of overall MSHR misses 119911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 467509 # number of overall MSHR misses 120011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1235027 # number of overall MSHR misses 120111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 803286 # number of overall MSHR misses 120211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2523282 # number of overall MSHR misses 120310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 120411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable 120511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71639 # number of ReadReq MSHR uncacheable 120611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable 120711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable 120810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 120911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses 121011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 99510 # number of overall MSHR uncacheable misses 121111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of ReadReq MSHR miss cycles 121211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290384000 # number of ReadReq MSHR miss cycles 121311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 657490500 # number of ReadReq MSHR miss cycles 121411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 55761183140 # number of HardPFReq MSHR miss cycles 121511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 55761183140 # number of HardPFReq MSHR miss cycles 121611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7610950500 # number of UpgradeReq MSHR miss cycles 121711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7610950500 # number of UpgradeReq MSHR miss cycles 121811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3903930000 # number of SCUpgradeReq MSHR miss cycles 121911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3903930000 # number of SCUpgradeReq MSHR miss cycles 122011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2414498 # number of SCUpgradeFailReq MSHR miss cycles 122111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2414498 # number of SCUpgradeFailReq MSHR miss cycles 122211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15925015500 # number of ReadExReq MSHR miss cycles 122311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15925015500 # number of ReadExReq MSHR miss cycles 122411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15941566500 # number of ReadCleanReq MSHR miss cycles 122511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15941566500 # number of ReadCleanReq MSHR miss cycles 122611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 35435763500 # number of ReadSharedReq MSHR miss cycles 122711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 35435763500 # number of ReadSharedReq MSHR miss cycles 122811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 42907731500 # number of InvalidateReq MSHR miss cycles 122911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 42907731500 # number of InvalidateReq MSHR miss cycles 123011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of demand (read+write) MSHR miss cycles 123111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290384000 # number of demand (read+write) MSHR miss cycles 123211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15941566500 # number of demand (read+write) MSHR miss cycles 123311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51360779000 # number of demand (read+write) MSHR miss cycles 123411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 67959836000 # number of demand (read+write) MSHR miss cycles 123511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of overall MSHR miss cycles 123611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290384000 # number of overall MSHR miss cycles 123711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15941566500 # number of overall MSHR miss cycles 123811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51360779000 # number of overall MSHR miss cycles 123911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55761183140 # number of overall MSHR miss cycles 124011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 123721019140 # number of overall MSHR miss cycles 124111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 124211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5051874500 # number of ReadReq MSHR uncacheable cycles 124311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10682646000 # number of ReadReq MSHR uncacheable cycles 124411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4877454000 # number of WriteReq MSHR uncacheable cycles 124511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4877454000 # number of WriteReq MSHR uncacheable cycles 124611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 124711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9929328500 # number of overall MSHR uncacheable cycles 124811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15560100000 # number of overall MSHR uncacheable cycles 124911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for ReadReq accesses 125011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for ReadReq accesses 125111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040690 # mshr miss rate for ReadReq accesses 125210535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 125310535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 125411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998026 # mshr miss rate for UpgradeReq accesses 125511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998026 # mshr miss rate for UpgradeReq accesses 125611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 125711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 125810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 125910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 126011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212204 # mshr miss rate for ReadExReq accesses 126111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212204 # mshr miss rate for ReadExReq accesses 126211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for ReadCleanReq accesses 126311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadCleanReq accesses 126411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254110 # mshr miss rate for ReadSharedReq accesses 126511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254110 # mshr miss rate for ReadSharedReq accesses 126611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.778461 # mshr miss rate for InvalidateReq accesses 126711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.778461 # mshr miss rate for InvalidateReq accesses 126811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for demand accesses 126911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for demand accesses 127011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for demand accesses 127111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for demand accesses 127211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.168169 # mshr miss rate for demand accesses 127311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for overall accesses 127411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for overall accesses 127511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for overall accesses 127611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for overall accesses 127710535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 127811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses 127911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency 128011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency 128111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency 128211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency 128311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency 128411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency 128511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency 128611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency 128711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency 128811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency 128911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency 129011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency 129111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency 129211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency 129311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency 129411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency 129511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency 129611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency 129711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency 129811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency 129911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency 130011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency 130111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency 130211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency 130311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency 130411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency 130511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency 130611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency 130711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency 130811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency 130911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 131011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency 131111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency 131211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency 131311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency 131411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 131511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency 131611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency 131710535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 131811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter. 131911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data. 132011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 132111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter. 132211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 132311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 132411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution 132511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution 132611353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution 132711353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution 132811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution 132911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution 133011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution 133111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution 133211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution 133311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution 133411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution 133511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 133611353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 133711353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution 133811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution 133911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution 134011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution 134111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution 134211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution 134311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes) 134411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes) 134511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes) 134611353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes) 134711353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes) 134811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes) 134911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes) 135011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes) 135111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes) 135211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes) 135311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6577979 # Total snoops (count) 135411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram 135511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram 135611353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram 135710535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram 135911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram 136011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram 136110535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 136211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 136310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 136411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram 136511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks) 136610535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 136711353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks) 136810535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks) 137010535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 137111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks) 137210535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 137311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks) 137410535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 137511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks) 137610535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 137710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 137810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 137910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 138010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 138110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 138410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 139010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 139110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 139210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 139310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 139410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 139510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 139610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 139710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 139810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 139910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 140010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 140110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 140210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 140310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 140410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 140510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 140611353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 108188 # Table walker walks requested 140711353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors 140811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate 140911353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate 141011353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting 141111353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency 141211353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency 141311353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency 141411353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141511353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 141611353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency 141711353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency 141811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency 141911353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency 142011353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency 142111353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency 142211353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency 142311353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency 142411353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency 142511353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency 142611353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency 142711353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency 142811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency 142911353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 143011353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 143111353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 143211353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 143311353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 143411353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency 143511353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution 143611353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution 143711353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution 143811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution 143911353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution 144011353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated 144111353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated 144211353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated 144311353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst 144410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144511353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst 144611353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst 144710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst 144911353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst 145010535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 145110535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 145211353Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 84911532 # DTB read hits 145311353Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 79075 # DTB read misses 145411353Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 77663318 # DTB write hits 145511353Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 29113 # DTB write misses 145610535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 145710535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145811353Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID 145911353Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID 146011353Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB 146110535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 146211353Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch 146310535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 146411353Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions 146511353Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 84990607 # DTB read accesses 146611353Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 77692431 # DTB write accesses 146710535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 146811353Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 162574850 # DTB hits 146911353Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 108188 # DTB misses 147011353Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 162683038 # DTB accesses 147110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 147210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 147410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 147510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 147610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 147810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 148210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 148310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 148410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 148510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 148610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 148910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 149010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 149110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 149210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 149310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 149510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 149610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 149710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 149810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 149910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 150011353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 63937 # Table walker walks requested 150111353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors 150211353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate 150311353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate 150411353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency 150511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency 150611353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency 150711353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency 150811353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency 150911353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency 151011353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency 151111353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency 151211353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency 151311353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency 151411353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency 151511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency 151611353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency 151711353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency 151811353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency 151911353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency 152011353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 152111353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 152211353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 152311336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 152411353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency 152511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution 152611353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution 152711353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution 152811353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated 152911353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated 153011353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated 153110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 153211353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst 153311353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst 153410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 153511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst 153611353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst 153711353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst 153811353Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 448499634 # ITB inst hits 153911353Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 63937 # ITB inst misses 154010535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 154110535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 154210535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 154310535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 154410535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 154510535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 154611353Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID 154711353Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID 154811353Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB 154910535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 155010535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 155110535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155210535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155310535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 155410535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 155511353Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 448563571 # ITB inst accesses 155611353Sandreas.hansson@arm.comsystem.cpu1.itb.hits 448499634 # DTB hits 155711353Sandreas.hansson@arm.comsystem.cpu1.itb.misses 63937 # DTB misses 155811353Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 448563571 # DTB accesses 155911353Sandreas.hansson@arm.comsystem.cpu1.numCycles 95159838343 # number of cpu cycles simulated 156010535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 156110535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 156211167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 156311353Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed 156411353Sandreas.hansson@arm.comsystem.cpu1.committedInsts 448210596 # Number of instructions committed 156511353Sandreas.hansson@arm.comsystem.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed 156611353Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses 156711353Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses 156811353Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 27136019 # number of times a function call or return occured 156911353Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls 157011353Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 486415785 # number of integer instructions 157111353Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 519922 # number of float instructions 157211353Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read 157311353Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written 157411353Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read 157511353Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written 157611353Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read 157711353Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written 157811353Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 162566757 # number of memory refs 157911353Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 84909557 # Number of load instructions 158011353Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 77657200 # Number of store instructions 158111353Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles 158211353Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles 158311353Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles 158411353Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988289 # Percentage of idle cycles 158511353Sandreas.hansson@arm.comsystem.cpu1.Branches 99989008 # Number of branches fetched 158611201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 158711353Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction 158811353Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction 158911353Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction 159011353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction 159111353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction 159211353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction 159311353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction 159411353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction 159511353Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction 159611353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction 159711353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction 159811353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction 159911353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction 160011353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction 160111353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction 160211353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction 160311353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction 160411353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction 160511353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction 160611353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction 160711353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction 160811353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction 160911353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction 161011353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction 161111353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction 161211353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction 161311353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction 161411353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction 161511353Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction 161611353Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction 161711353Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction 161810535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 161910535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 162011353Sandreas.hansson@arm.comsystem.cpu1.op_class::total 529066901 # Class of executed instruction 162111353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5332630 # number of replacements 162211353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use 162311353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks. 162411353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks. 162511353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks. 162611353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. 162711353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor 162811353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy 162911353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy 163011353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 163111353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 163211353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 163311353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id 163411353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 163511353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses 163611353Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses 163711353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits 163811353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits 163911353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits 164011353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits 164111353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits 164211353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits 164311353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits 164411353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits 164511353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits 164611353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits 164711353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits 164811353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits 164911353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits 165011353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits 165111353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits 165211353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 152980241 # number of overall hits 165311353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses 165411353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses 165511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses 165611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses 165711353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses 165811353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses 165911353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses 166011353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses 166111353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses 166211353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses 166311353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses 166411353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses 166511353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses 166611353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses 166711353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses 166811353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5054936 # number of overall misses 166911353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles 167011353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles 167111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles 167211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles 167311353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles 167411353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles 167511353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles 167611353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles 167711353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles 167811353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles 167911353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles 168011353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles 168111353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles 168211353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles 168311353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles 168411353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles 168511353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses) 168611353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses) 168711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses) 168811353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses) 168911353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses) 169011353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses) 169111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses) 169211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses) 169311353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses) 169411353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses) 169511353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses) 169611353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses) 169711353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses 169811353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses 169911353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses 170011353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses 170111353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses 170211353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses 170311353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses 170411353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses 170511353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses 170611353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses 170711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses 170811353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses 170911353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses 171011353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses 171111353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses 171211353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses 171311353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses 171411353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses 171511353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses 171611353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses 171711353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency 171811353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency 171911353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency 172011353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency 172111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency 172211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency 172311353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency 172411353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency 172511353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency 172611353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency 172710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 172810535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 172911353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19053.898740 # average overall miss latency 173011353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 19053.898740 # average overall miss latency 173111353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992 # average overall miss latency 173211353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 16647.799992 # average overall miss latency 173310535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173410535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173510535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173610535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 173710535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173810535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173910585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 174010535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 174111353Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5332630 # number of writebacks 174211353Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5332630 # number of writebacks 174311353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 22206 # number of ReadReq MSHR hits 174411353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 22206 # number of ReadReq MSHR hits 174511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 454 # number of WriteReq MSHR hits 174611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 454 # number of WriteReq MSHR hits 174711353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46550 # number of LoadLockedReq MSHR hits 174811353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 46550 # number of LoadLockedReq MSHR hits 174911353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 22660 # number of demand (read+write) MSHR hits 175011353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 22660 # number of demand (read+write) MSHR hits 175111353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 22660 # number of overall MSHR hits 175211353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 22660 # number of overall MSHR hits 175311353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3028931 # number of ReadReq MSHR misses 175411353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3028931 # number of ReadReq MSHR misses 175511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1365015 # number of WriteReq MSHR misses 175611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1365015 # number of WriteReq MSHR misses 175711353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 638330 # number of SoftPFReq MSHR misses 175811353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 638330 # number of SoftPFReq MSHR misses 175911353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 475836 # number of WriteLineReq MSHR misses 176011353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 475836 # number of WriteLineReq MSHR misses 176111353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 130306 # number of LoadLockedReq MSHR misses 176211353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 130306 # number of LoadLockedReq MSHR misses 176311353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201345 # number of StoreCondReq MSHR misses 176411353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 201345 # number of StoreCondReq MSHR misses 176511353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4393946 # number of demand (read+write) MSHR misses 176611353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4393946 # number of demand (read+write) MSHR misses 176711353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5032276 # number of overall MSHR misses 176811353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5032276 # number of overall MSHR misses 176911353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 10149 # number of ReadReq MSHR uncacheable 177011353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 10149 # number of ReadReq MSHR uncacheable 177111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable 177211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 10618 # number of WriteReq MSHR uncacheable 177311353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 20767 # number of overall MSHR uncacheable misses 177411353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 20767 # number of overall MSHR uncacheable misses 177511353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46920862500 # number of ReadReq MSHR miss cycles 177611353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 46920862500 # number of ReadReq MSHR miss cycles 177711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30832329000 # number of WriteReq MSHR miss cycles 177811353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 30832329000 # number of WriteReq MSHR miss cycles 177911353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15929044000 # number of SoftPFReq MSHR miss cycles 178011353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15929044000 # number of SoftPFReq MSHR miss cycles 178111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16618554000 # number of WriteLineReq MSHR miss cycles 178211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16618554000 # number of WriteLineReq MSHR miss cycles 178311353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1916877000 # number of LoadLockedReq MSHR miss cycles 178411353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1916877000 # number of LoadLockedReq MSHR miss cycles 178511353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5559123500 # number of StoreCondReq MSHR miss cycles 178611353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5559123500 # number of StoreCondReq MSHR miss cycles 178711353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4381500 # number of StoreCondFailReq MSHR miss cycles 178811353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4381500 # number of StoreCondFailReq MSHR miss cycles 178911353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77753191500 # number of demand (read+write) MSHR miss cycles 179011353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 77753191500 # number of demand (read+write) MSHR miss cycles 179111353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93682235500 # number of overall MSHR miss cycles 179211353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 93682235500 # number of overall MSHR miss cycles 179311353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1652437500 # number of ReadReq MSHR uncacheable cycles 179411353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1652437500 # number of ReadReq MSHR uncacheable cycles 179511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1820826500 # number of WriteReq MSHR uncacheable cycles 179611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1820826500 # number of WriteReq MSHR uncacheable cycles 179711353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3473264000 # number of overall MSHR uncacheable cycles 179811353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 3473264000 # number of overall MSHR uncacheable cycles 179911353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036878 # mshr miss rate for ReadReq accesses 180011353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036878 # mshr miss rate for ReadReq accesses 180111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018181 # mshr miss rate for WriteReq accesses 180211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018181 # mshr miss rate for WriteReq accesses 180311353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775939 # mshr miss rate for SoftPFReq accesses 180411353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775939 # mshr miss rate for SoftPFReq accesses 180511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.770176 # mshr miss rate for WriteLineReq accesses 180611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.770176 # mshr miss rate for WriteLineReq accesses 180711353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066969 # mshr miss rate for LoadLockedReq accesses 180811353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066969 # mshr miss rate for LoadLockedReq accesses 180911353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103555 # mshr miss rate for StoreCondReq accesses 181011353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103555 # mshr miss rate for StoreCondReq accesses 181111353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027949 # mshr miss rate for demand accesses 181211353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027949 # mshr miss rate for demand accesses 181311353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031843 # mshr miss rate for overall accesses 181411353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses 181511353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15490.898439 # average ReadReq mshr miss latency 181611353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15490.898439 # average ReadReq mshr miss latency 181711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598 # average WriteReq mshr miss latency 181811353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22587.538598 # average WriteReq mshr miss latency 181911353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24954.246236 # average SoftPFReq mshr miss latency 182011353Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24954.246236 # average SoftPFReq mshr miss latency 182111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541 # average WriteLineReq mshr miss latency 182211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34924.961541 # average WriteLineReq mshr miss latency 182311353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14710.581247 # average LoadLockedReq mshr miss latency 182411353Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247 # average LoadLockedReq mshr miss latency 182511353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27609.940649 # average StoreCondReq mshr miss latency 182611353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649 # average StoreCondReq mshr miss latency 182710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 182810535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 182911353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17695.527323 # average overall mshr miss latency 183011353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323 # average overall mshr miss latency 183111353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18616.275320 # average overall mshr miss latency 183211353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 18616.275320 # average overall mshr miss latency 183311353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162817.765297 # average ReadReq mshr uncacheable latency 183411353Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297 # average ReadReq mshr uncacheable latency 183511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171484.884159 # average WriteReq mshr uncacheable latency 183611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171484.884159 # average WriteReq mshr uncacheable latency 183711353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167249.193432 # average overall mshr uncacheable latency 183811353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432 # average overall mshr uncacheable latency 183910535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 184011353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 5368535 # number of replacements 184111353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.099630 # Cycle average of tags in use 184211353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 443130586 # Total number of references to valid blocks. 184311353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 5369047 # Sample count of references to valid blocks. 184411353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 82.534309 # Average number of references to valid blocks. 184511353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. 184611353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.099630 # Average occupied blocks per requestor 184711353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.968945 # Average percentage of cache occupancy 184811353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.968945 # Average percentage of cache occupancy 184910535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 185011353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 185111353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 185211353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id 185310535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 185411353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 902368316 # Number of tag accesses 185511353Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 902368316 # Number of data accesses 185611353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 443130586 # number of ReadReq hits 185711353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 443130586 # number of ReadReq hits 185811353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 443130586 # number of demand (read+write) hits 185911353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 443130586 # number of demand (read+write) hits 186011353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 443130586 # number of overall hits 186111353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 443130586 # number of overall hits 186211353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5369048 # number of ReadReq misses 186311353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 5369048 # number of ReadReq misses 186411353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5369048 # number of demand (read+write) misses 186511353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 5369048 # number of demand (read+write) misses 186611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5369048 # number of overall misses 186711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 5369048 # number of overall misses 186811353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 58701560000 # number of ReadReq miss cycles 186911353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 58701560000 # number of ReadReq miss cycles 187011353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 58701560000 # number of demand (read+write) miss cycles 187111353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 58701560000 # number of demand (read+write) miss cycles 187211353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 58701560000 # number of overall miss cycles 187311353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 58701560000 # number of overall miss cycles 187411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 448499634 # number of ReadReq accesses(hits+misses) 187511353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 448499634 # number of ReadReq accesses(hits+misses) 187611353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 448499634 # number of demand (read+write) accesses 187711353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 448499634 # number of demand (read+write) accesses 187811353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 448499634 # number of overall (read+write) accesses 187911353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 448499634 # number of overall (read+write) accesses 188011353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011971 # miss rate for ReadReq accesses 188111353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011971 # miss rate for ReadReq accesses 188211353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011971 # miss rate for demand accesses 188311353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011971 # miss rate for demand accesses 188411353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011971 # miss rate for overall accesses 188511353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011971 # miss rate for overall accesses 188611353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10933.327473 # average ReadReq miss latency 188711353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10933.327473 # average ReadReq miss latency 188811353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10933.327473 # average overall miss latency 188911353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10933.327473 # average overall miss latency 189011353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10933.327473 # average overall miss latency 189111353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10933.327473 # average overall miss latency 189210535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 189310535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 189410535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 189510535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 189610535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189710535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 189810535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 189910535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 190011353Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 5368535 # number of writebacks 190111353Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 5368535 # number of writebacks 190211353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5369048 # number of ReadReq MSHR misses 190311353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5369048 # number of ReadReq MSHR misses 190411353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5369048 # number of demand (read+write) MSHR misses 190511353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5369048 # number of demand (read+write) MSHR misses 190611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5369048 # number of overall MSHR misses 190711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5369048 # number of overall MSHR misses 190810827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 190910827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 191010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 191110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 191211353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56017036000 # number of ReadReq MSHR miss cycles 191311353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 56017036000 # number of ReadReq MSHR miss cycles 191411353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56017036000 # number of demand (read+write) MSHR miss cycles 191511353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 56017036000 # number of demand (read+write) MSHR miss cycles 191611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56017036000 # number of overall MSHR miss cycles 191711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 56017036000 # number of overall MSHR miss cycles 191811353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14763500 # number of ReadReq MSHR uncacheable cycles 191911353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14763500 # number of ReadReq MSHR uncacheable cycles 192011353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14763500 # number of overall MSHR uncacheable cycles 192111353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 14763500 # number of overall MSHR uncacheable cycles 192211353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for ReadReq accesses 192311353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011971 # mshr miss rate for ReadReq accesses 192411353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for demand accesses 192511353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011971 # mshr miss rate for demand accesses 192611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for overall accesses 192711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011971 # mshr miss rate for overall accesses 192811353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average ReadReq mshr miss latency 192911353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473 # average ReadReq mshr miss latency 193011353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency 193111353Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency 193211353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency 193311353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency 193411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency 193511353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency 193611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency 193711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency 193810535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 193911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7379094 # number of hwpf issued 194011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7379143 # number of prefetch candidates identified 194111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue 194210628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 194310628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 194411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 880313 # number of prefetches not generated due to page crossing 194511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2062305 # number of replacements 194611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13347.402456 # Cycle average of tags in use 194711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 15756881 # Total number of references to valid blocks. 194811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2078287 # Sample count of references to valid blocks. 194911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.581667 # Average number of references to valid blocks. 195011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10111476094500 # Cycle when the warmup percentage was hit. 195111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12484.773775 # Average occupied blocks per requestor 195211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.991468 # Average occupied blocks per requestor 195311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.953770 # Average occupied blocks per requestor 195411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.683443 # Average occupied blocks per requestor 195511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.762010 # Average percentage of cache occupancy 195611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003173 # Average percentage of cache occupancy 195711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003659 # Average percentage of cache occupancy 195811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy 195911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.814661 # Average percentage of cache occupancy 196011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1312 # Occupied blocks per task id 196111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id 196211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14621 # Occupied blocks per task id 196311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id 196411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 231 # Occupied blocks per task id 196511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 561 # Occupied blocks per task id 196611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id 196711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 196811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id 196911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 197011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 197111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 197211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 989 # Occupied blocks per task id 197311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4575 # Occupied blocks per task id 197411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5108 # Occupied blocks per task id 197511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3891 # Occupied blocks per task id 197611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080078 # Percentage of cache occupancy per task id 197711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id 197811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892395 # Percentage of cache occupancy per task id 197911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 362674413 # Number of tag accesses 198011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 362674413 # Number of data accesses 198111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 250614 # number of ReadReq hits 198211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 164455 # number of ReadReq hits 198311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 415069 # number of ReadReq hits 198411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3362211 # number of WritebackDirty hits 198511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3362211 # number of WritebackDirty hits 198611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 7338042 # number of WritebackClean hits 198711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 7338042 # number of WritebackClean hits 198811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 793 # number of UpgradeReq hits 198911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 793 # number of UpgradeReq hits 199011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 895753 # number of ReadExReq hits 199111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 895753 # number of ReadExReq hits 199211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4900610 # number of ReadCleanReq hits 199311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4900610 # number of ReadCleanReq hits 199411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2870677 # number of ReadSharedReq hits 199511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2870677 # number of ReadSharedReq hits 199611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 215360 # number of InvalidateReq hits 199711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 215360 # number of InvalidateReq hits 199811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 250614 # number of demand (read+write) hits 199911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 164455 # number of demand (read+write) hits 200011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4900610 # number of demand (read+write) hits 200111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3766430 # number of demand (read+write) hits 200211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 9082109 # number of demand (read+write) hits 200311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 250614 # number of overall hits 200411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 164455 # number of overall hits 200511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4900610 # number of overall hits 200611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3766430 # number of overall hits 200711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 9082109 # number of overall hits 200811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11669 # number of ReadReq misses 200911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10135 # number of ReadReq misses 201011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 21804 # number of ReadReq misses 201111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207192 # number of UpgradeReq misses 201211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 207192 # number of UpgradeReq misses 201311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201338 # number of SCUpgradeReq misses 201411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 201338 # number of SCUpgradeReq misses 201511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 201611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 201711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 263735 # number of ReadExReq misses 201811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 263735 # number of ReadExReq misses 201911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 468438 # number of ReadCleanReq misses 202011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 468438 # number of ReadCleanReq misses 202111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 926890 # number of ReadSharedReq misses 202211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 926890 # number of ReadSharedReq misses 202311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258258 # number of InvalidateReq misses 202411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 258258 # number of InvalidateReq misses 202511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11669 # number of demand (read+write) misses 202611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10135 # number of demand (read+write) misses 202711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 468438 # number of demand (read+write) misses 202811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1190625 # number of demand (read+write) misses 202911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1680867 # number of demand (read+write) misses 203011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11669 # number of overall misses 203111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10135 # number of overall misses 203211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 468438 # number of overall misses 203311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1190625 # number of overall misses 203411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1680867 # number of overall misses 203511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 716522000 # number of ReadReq miss cycles 203611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 701084000 # number of ReadReq miss cycles 203711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1417606000 # number of ReadReq miss cycles 203811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3305334500 # number of UpgradeReq miss cycles 203911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3305334500 # number of UpgradeReq miss cycles 204011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2142938000 # number of SCUpgradeReq miss cycles 204111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2142938000 # number of SCUpgradeReq miss cycles 204211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4308999 # number of SCUpgradeFailReq miss cycles 204311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4308999 # number of SCUpgradeFailReq miss cycles 204411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 15026168500 # number of ReadExReq miss cycles 204511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 15026168500 # number of ReadExReq miss cycles 204611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18507593500 # number of ReadCleanReq miss cycles 204711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 18507593500 # number of ReadCleanReq miss cycles 204811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 40367140999 # number of ReadSharedReq miss cycles 204911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 40367140999 # number of ReadSharedReq miss cycles 205011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 516760500 # number of InvalidateReq miss cycles 205111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 516760500 # number of InvalidateReq miss cycles 205211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 716522000 # number of demand (read+write) miss cycles 205311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 701084000 # number of demand (read+write) miss cycles 205411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 18507593500 # number of demand (read+write) miss cycles 205511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 55393309499 # number of demand (read+write) miss cycles 205611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 75318508999 # number of demand (read+write) miss cycles 205711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 716522000 # number of overall miss cycles 205811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 701084000 # number of overall miss cycles 205911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 18507593500 # number of overall miss cycles 206011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 55393309499 # number of overall miss cycles 206111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 75318508999 # number of overall miss cycles 206211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 262283 # number of ReadReq accesses(hits+misses) 206311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174590 # number of ReadReq accesses(hits+misses) 206411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 436873 # number of ReadReq accesses(hits+misses) 206511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3362211 # number of WritebackDirty accesses(hits+misses) 206611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3362211 # number of WritebackDirty accesses(hits+misses) 206711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 7338042 # number of WritebackClean accesses(hits+misses) 206811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 7338042 # number of WritebackClean accesses(hits+misses) 206911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207985 # number of UpgradeReq accesses(hits+misses) 207011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 207985 # number of UpgradeReq accesses(hits+misses) 207111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201338 # number of SCUpgradeReq accesses(hits+misses) 207211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 201338 # number of SCUpgradeReq accesses(hits+misses) 207311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 207411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 207511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1159488 # number of ReadExReq accesses(hits+misses) 207611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1159488 # number of ReadExReq accesses(hits+misses) 207711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5369048 # number of ReadCleanReq accesses(hits+misses) 207811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5369048 # number of ReadCleanReq accesses(hits+misses) 207911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3797567 # number of ReadSharedReq accesses(hits+misses) 208011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3797567 # number of ReadSharedReq accesses(hits+misses) 208111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 473618 # number of InvalidateReq accesses(hits+misses) 208211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 473618 # number of InvalidateReq accesses(hits+misses) 208311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 262283 # number of demand (read+write) accesses 208411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174590 # number of demand (read+write) accesses 208511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5369048 # number of demand (read+write) accesses 208611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4957055 # number of demand (read+write) accesses 208711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10762976 # number of demand (read+write) accesses 208811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 262283 # number of overall (read+write) accesses 208911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174590 # number of overall (read+write) accesses 209011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5369048 # number of overall (read+write) accesses 209111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4957055 # number of overall (read+write) accesses 209211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10762976 # number of overall (read+write) accesses 209311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for ReadReq accesses 209411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058050 # miss rate for ReadReq accesses 209511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.049909 # miss rate for ReadReq accesses 209611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996187 # miss rate for UpgradeReq accesses 209711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996187 # miss rate for UpgradeReq accesses 209811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 209911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 210010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 210110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 210211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227458 # miss rate for ReadExReq accesses 210311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.227458 # miss rate for ReadExReq accesses 210411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087248 # miss rate for ReadCleanReq accesses 210511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087248 # miss rate for ReadCleanReq accesses 210611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244075 # miss rate for ReadSharedReq accesses 210711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244075 # miss rate for ReadSharedReq accesses 210811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.545288 # miss rate for InvalidateReq accesses 210911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.545288 # miss rate for InvalidateReq accesses 211011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for demand accesses 211111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058050 # miss rate for demand accesses 211211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087248 # miss rate for demand accesses 211311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240188 # miss rate for demand accesses 211411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.156171 # miss rate for demand accesses 211511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for overall accesses 211611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058050 # miss rate for overall accesses 211711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087248 # miss rate for overall accesses 211811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240188 # miss rate for overall accesses 211911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.156171 # miss rate for overall accesses 212011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average ReadReq miss latency 212111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 69174.543661 # average ReadReq miss latency 212211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 65015.868648 # average ReadReq miss latency 212311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15953.002529 # average UpgradeReq miss latency 212411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15953.002529 # average UpgradeReq miss latency 212511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10643.485085 # average SCUpgradeReq miss latency 212611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10643.485085 # average SCUpgradeReq miss latency 212711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 615571.285714 # average SCUpgradeFailReq miss latency 212811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 615571.285714 # average SCUpgradeFailReq miss latency 212911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56974.495232 # average ReadExReq miss latency 213011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56974.495232 # average ReadExReq miss latency 213111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39509.163433 # average ReadCleanReq miss latency 213211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39509.163433 # average ReadCleanReq miss latency 213311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43551.166804 # average ReadSharedReq miss latency 213411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43551.166804 # average ReadSharedReq miss latency 213511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2000.946728 # average InvalidateReq miss latency 213611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2000.946728 # average InvalidateReq miss latency 213711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average overall miss latency 213811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 69174.543661 # average overall miss latency 213911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39509.163433 # average overall miss latency 214011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46524.564409 # average overall miss latency 214111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 44809.321022 # average overall miss latency 214211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average overall miss latency 214311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 69174.543661 # average overall miss latency 214411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39509.163433 # average overall miss latency 214511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46524.564409 # average overall miss latency 214611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 44809.321022 # average overall miss latency 214710628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 214810535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214910628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 215010535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 215110628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 215210535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 215310535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 215410535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 215511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1141854 # number of writebacks 215611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1141854 # number of writebacks 215711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5992 # number of ReadExReq MSHR hits 215811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 5992 # number of ReadExReq MSHR hits 215911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 581 # number of ReadSharedReq MSHR hits 216011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 581 # number of ReadSharedReq MSHR hits 216111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 6573 # number of demand (read+write) MSHR hits 216211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 6573 # number of demand (read+write) MSHR hits 216311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 6573 # number of overall MSHR hits 216411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 6573 # number of overall MSHR hits 216511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11669 # number of ReadReq MSHR misses 216611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10135 # number of ReadReq MSHR misses 216711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 21804 # number of ReadReq MSHR misses 216811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 737355 # number of HardPFReq MSHR misses 216911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 737355 # number of HardPFReq MSHR misses 217011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207192 # number of UpgradeReq MSHR misses 217111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 207192 # number of UpgradeReq MSHR misses 217211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201338 # number of SCUpgradeReq MSHR misses 217311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201338 # number of SCUpgradeReq MSHR misses 217411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 217511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 217611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257743 # number of ReadExReq MSHR misses 217711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 257743 # number of ReadExReq MSHR misses 217811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 468438 # number of ReadCleanReq MSHR misses 217911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 468438 # number of ReadCleanReq MSHR misses 218011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 926309 # number of ReadSharedReq MSHR misses 218111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 926309 # number of ReadSharedReq MSHR misses 218211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258258 # number of InvalidateReq MSHR misses 218311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 258258 # number of InvalidateReq MSHR misses 218411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11669 # number of demand (read+write) MSHR misses 218511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10135 # number of demand (read+write) MSHR misses 218611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 468438 # number of demand (read+write) MSHR misses 218711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1184052 # number of demand (read+write) MSHR misses 218811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1674294 # number of demand (read+write) MSHR misses 218911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11669 # number of overall MSHR misses 219011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10135 # number of overall MSHR misses 219111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 468438 # number of overall MSHR misses 219211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1184052 # number of overall MSHR misses 219311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 737355 # number of overall MSHR misses 219411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2411649 # number of overall MSHR misses 219510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 219611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 10149 # number of ReadReq MSHR uncacheable 219711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 10259 # number of ReadReq MSHR uncacheable 219811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable 219911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 10618 # number of WriteReq MSHR uncacheable 220010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 220111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 20767 # number of overall MSHR uncacheable misses 220211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 20877 # number of overall MSHR uncacheable misses 220311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of ReadReq MSHR miss cycles 220411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 640274000 # number of ReadReq MSHR miss cycles 220511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1286782000 # number of ReadReq MSHR miss cycles 220611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39407007921 # number of HardPFReq MSHR miss cycles 220711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 39407007921 # number of HardPFReq MSHR miss cycles 220811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6717201500 # number of UpgradeReq MSHR miss cycles 220911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6717201500 # number of UpgradeReq MSHR miss cycles 221011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 4047781500 # number of SCUpgradeReq MSHR miss cycles 221111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 4047781500 # number of SCUpgradeReq MSHR miss cycles 221211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4020999 # number of SCUpgradeFailReq MSHR miss cycles 221311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4020999 # number of SCUpgradeFailReq MSHR miss cycles 221411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12743172000 # number of ReadExReq MSHR miss cycles 221511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12743172000 # number of ReadExReq MSHR miss cycles 221611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15696965500 # number of ReadCleanReq MSHR miss cycles 221711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15696965500 # number of ReadCleanReq MSHR miss cycles 221811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 34752380999 # number of ReadSharedReq MSHR miss cycles 221911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 34752380999 # number of ReadSharedReq MSHR miss cycles 222011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12891073000 # number of InvalidateReq MSHR miss cycles 222111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12891073000 # number of InvalidateReq MSHR miss cycles 222211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of demand (read+write) MSHR miss cycles 222311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 640274000 # number of demand (read+write) MSHR miss cycles 222411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15696965500 # number of demand (read+write) MSHR miss cycles 222511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 47495552999 # number of demand (read+write) MSHR miss cycles 222611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 64479300499 # number of demand (read+write) MSHR miss cycles 222711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of overall MSHR miss cycles 222811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 640274000 # number of overall MSHR miss cycles 222911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15696965500 # number of overall MSHR miss cycles 223011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 47495552999 # number of overall MSHR miss cycles 223111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39407007921 # number of overall MSHR miss cycles 223211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 103886308420 # number of overall MSHR miss cycles 223311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles 223411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1570752500 # number of ReadReq MSHR uncacheable cycles 223511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1584691000 # number of ReadReq MSHR uncacheable cycles 223611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1740638000 # number of WriteReq MSHR uncacheable cycles 223711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1740638000 # number of WriteReq MSHR uncacheable cycles 223811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles 223911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3311390500 # number of overall MSHR uncacheable cycles 224011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3325329000 # number of overall MSHR uncacheable cycles 224111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for ReadReq accesses 224211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for ReadReq accesses 224311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.049909 # mshr miss rate for ReadReq accesses 224410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 224510535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 224611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996187 # mshr miss rate for UpgradeReq accesses 224711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996187 # mshr miss rate for UpgradeReq accesses 224811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 224911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 225010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 225110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 225211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222290 # mshr miss rate for ReadExReq accesses 225311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222290 # mshr miss rate for ReadExReq accesses 225411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses 225511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses 225611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243922 # mshr miss rate for ReadSharedReq accesses 225711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243922 # mshr miss rate for ReadSharedReq accesses 225811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.545288 # mshr miss rate for InvalidateReq accesses 225911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.545288 # mshr miss rate for InvalidateReq accesses 226011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for demand accesses 226111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for demand accesses 226211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses 226311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for demand accesses 226411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.155561 # mshr miss rate for demand accesses 226511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for overall accesses 226611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for overall accesses 226711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses 226811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for overall accesses 226910535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 227011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.224069 # mshr miss rate for overall accesses 227111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average ReadReq mshr miss latency 227211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average ReadReq mshr miss latency 227311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 59015.868648 # average ReadReq mshr miss latency 227411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average HardPFReq mshr miss latency 227511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53443.738662 # average HardPFReq mshr miss latency 227611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32420.177903 # average UpgradeReq mshr miss latency 227711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32420.177903 # average UpgradeReq mshr miss latency 227811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20104.409004 # average SCUpgradeReq mshr miss latency 227911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004 # average SCUpgradeReq mshr miss latency 228011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571 # average SCUpgradeFailReq mshr miss latency 228111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571 # average SCUpgradeFailReq mshr miss latency 228211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291 # average ReadExReq mshr miss latency 228311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291 # average ReadExReq mshr miss latency 228411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average ReadCleanReq mshr miss latency 228511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433 # average ReadCleanReq mshr miss latency 228611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925 # average ReadSharedReq mshr miss latency 228711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925 # average ReadSharedReq mshr miss latency 228811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741 # average InvalidateReq mshr miss latency 228911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741 # average InvalidateReq mshr miss latency 229011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency 229111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency 229211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency 229311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency 229411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017 # average overall mshr miss latency 229511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency 229611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency 229711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency 229811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency 229911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average overall mshr miss latency 230011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448 # average overall mshr miss latency 230111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency 230211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency 230311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency 230411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency 230511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency 230611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency 230711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency 230811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency 230910535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 231011353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter. 231111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data. 231211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 231311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter. 231411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 231511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 231611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution 231711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution 231811353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution 231911353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution 232011353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution 232111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution 232211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution 232311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution 232411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution 232511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution 232611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution 232711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 232811353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 232911353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution 233011353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution 233111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution 233211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution 233311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution 233411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution 233511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes) 233611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes) 233711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes) 233811353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes) 233911353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes) 234011353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes) 234111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes) 234211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes) 234311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes) 234411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes) 234511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5987251 # Total snoops (count) 234611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram 234711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram 234811353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram 234910535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 235011353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram 235111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram 235211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram 235310535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 235411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 235510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 235611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram 235711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks) 235810535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 235911353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks) 236010535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 236111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks) 236210535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 236311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks) 236410535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 236511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks) 236610535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 236711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks) 236810535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 236911353Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40370 # Transaction distribution 237011353Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40370 # Transaction distribution 237111353Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136628 # Transaction distribution 237211353Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136628 # Transaction distribution 237311353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 237410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 237511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 237710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 237810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 237910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 238010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 238110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 238210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 238310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 238411353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 238510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 238611353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) 238711353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes) 238811353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes) 238910535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 239010535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 239111353Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes) 239211353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 239310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 239411245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 239510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 239610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 239710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 239810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 240210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240311353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 240410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 240511353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) 240611353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339024 # Cumulative packet size per connected master and slave (bytes) 240711353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7339024 # Cumulative packet size per connected master and slave (bytes) 240810535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 240910535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 241011353Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496904 # Cumulative packet size per connected master and slave (bytes) 241111353Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 37005501 # Layer occupancy (ticks) 241210535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 241311353Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 241410535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 241511353Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 324001 # Layer occupancy (ticks) 241610535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 241711201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 241810535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 241911336Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 242011245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 242110535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 242210535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 242311353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 242410535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 242511201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 242610535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 242711201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 242810535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 242911201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 243010535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 243111353Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 243210535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 243311353Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 26468500 # Layer occupancy (ticks) 243410535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 243511353Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 37415000 # Layer occupancy (ticks) 243610535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 243711353Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 567277400 # Layer occupancy (ticks) 243810535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 243911353Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) 244010535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 244111353Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147948000 # Layer occupancy (ticks) 244210535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 244310892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 244410535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 244511353Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115622 # number of replacements 244611353Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.298154 # Cycle average of tags in use 244711336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 244811353Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115638 # Sample count of references to valid blocks. 244911336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 245011353Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9192209246000 # Cycle when the warmup percentage was hit. 245111353Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.385038 # Average occupied blocks per requestor 245211353Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.913116 # Average occupied blocks per requestor 245311353Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.461565 # Average percentage of cache occupancy 245411353Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.244570 # Average percentage of cache occupancy 245511353Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy 245610535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 245710535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 245810535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 245911353Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040991 # Number of tag accesses 246011353Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040991 # Number of data accesses 246110535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 246211353Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses 246311353Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8935 # number of ReadReq misses 246410535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 246510535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 246611353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 246711353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 246810535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 246911353Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses 247011353Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8938 # number of demand (read+write) misses 247110535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 247211353Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8898 # number of overall misses 247311353Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8938 # number of overall misses 247411353Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 247511353Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1672896003 # number of ReadReq miss cycles 247611353Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1678095503 # number of ReadReq miss cycles 247710726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 247810726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 247911353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13552714897 # number of WriteLineReq miss cycles 248011353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13552714897 # number of WriteLineReq miss cycles 248111353Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 248211353Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1672896003 # number of demand (read+write) miss cycles 248311353Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1678464503 # number of demand (read+write) miss cycles 248411353Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 248511353Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1672896003 # number of overall miss cycles 248611353Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1678464503 # number of overall miss cycles 248710535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 248811353Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) 248911353Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) 249010535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 249110535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 249211353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 249311353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 249410535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 249511353Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses 249611353Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses 249710535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 249811353Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses 249911353Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses 250010535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 250110535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 250210535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 250310535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 250410535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 250511336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 250611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 250710535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 250810535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 250910535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 251010535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 251110535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 251210535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 251311353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 251411353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 188008.092043 # average ReadReq miss latency 251511353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 187811.472076 # average ReadReq miss latency 251610726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 251710726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 251811353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 126983.686540 # average WriteLineReq miss latency 251911353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126983.686540 # average WriteLineReq miss latency 252011353Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 252111353Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency 252211353Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 187789.718393 # average overall miss latency 252311353Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 252411353Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency 252511353Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 187789.718393 # average overall miss latency 252611353Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 33965 # number of cycles access was blocked 252710535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252811353Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3500 # number of cycles access was blocked 252910535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 253011353Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.704286 # average number of cycles each access was blocked 253110535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253210585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 253310535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 253411353Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 253511353Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 253610535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 253711353Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses 253811353Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses 253910535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 254010535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 254111353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 254211353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 254310535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 254411353Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses 254511353Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses 254610535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 254711353Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses 254811353Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses 254911353Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 255011353Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1227996003 # number of ReadReq MSHR miss cycles 255111353Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1231345503 # number of ReadReq MSHR miss cycles 255210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 255310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 255411353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8209903918 # number of WriteLineReq MSHR miss cycles 255511353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8209903918 # number of WriteLineReq MSHR miss cycles 255611353Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 255711353Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1227996003 # number of demand (read+write) MSHR miss cycles 255811353Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1231564503 # number of demand (read+write) MSHR miss cycles 255911353Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 256011353Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1227996003 # number of overall MSHR miss cycles 256111353Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1231564503 # number of overall MSHR miss cycles 256210535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 256310535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 256410535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 256510535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 256610535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 256711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 256811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 256910535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 257010535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 257110535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 257210535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 257310535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 257410535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 257511353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 257611353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138008.092043 # average ReadReq mshr miss latency 257711353Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 137811.472076 # average ReadReq mshr miss latency 257810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 257910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 258011353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76923.618151 # average WriteLineReq mshr miss latency 258111353Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76923.618151 # average WriteLineReq mshr miss latency 258211353Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 258311353Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency 258411353Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency 258511353Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 258611353Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency 258711353Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency 258810535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 258911353Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1521682 # number of replacements 259011353Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63275.480852 # Cycle average of tags in use 259111353Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5639856 # Total number of references to valid blocks. 259211353Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1580939 # Sample count of references to valid blocks. 259311353Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.567409 # Average number of references to valid blocks. 259411353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. 259511353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 23300.510768 # Average occupied blocks per requestor 259611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 120.316787 # Average occupied blocks per requestor 259711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 198.572474 # Average occupied blocks per requestor 259811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3006.389178 # Average occupied blocks per requestor 259911353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 5620.523219 # Average occupied blocks per requestor 260011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9896.072880 # Average occupied blocks per requestor 260111353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 161.524171 # Average occupied blocks per requestor 260211353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 257.856403 # Average occupied blocks per requestor 260311353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3567.908148 # Average occupied blocks per requestor 260411353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 7366.209685 # Average occupied blocks per requestor 260511353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9779.597138 # Average occupied blocks per requestor 260611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.355538 # Average percentage of cache occupancy 260711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001836 # Average percentage of cache occupancy 260811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003030 # Average percentage of cache occupancy 260911353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.045874 # Average percentage of cache occupancy 261011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.085762 # Average percentage of cache occupancy 261111353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.151002 # Average percentage of cache occupancy 261211353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002465 # Average percentage of cache occupancy 261311353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.003935 # Average percentage of cache occupancy 261411353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.054442 # Average percentage of cache occupancy 261511353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.112399 # Average percentage of cache occupancy 261611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.149225 # Average percentage of cache occupancy 261711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.965507 # Average percentage of cache occupancy 261811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10707 # Occupied blocks per task id 261911353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id 262011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48305 # Occupied blocks per task id 262111353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id 262211353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 740 # Occupied blocks per task id 262311353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9837 # Occupied blocks per task id 262411353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id 262511353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 262611353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id 262711353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id 262811353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5150 # Occupied blocks per task id 262911353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 41466 # Occupied blocks per task id 263011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.163376 # Percentage of cache occupancy per task id 263111353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id 263211353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.737076 # Percentage of cache occupancy per task id 263311353Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 74056413 # Number of tag accesses 263411353Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 74056413 # Number of data accesses 263511353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2788899 # number of WritebackDirty hits 263611353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2788899 # number of WritebackDirty hits 263711353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 164206 # number of UpgradeReq hits 263811353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 131282 # number of UpgradeReq hits 263911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 295488 # number of UpgradeReq hits 264011353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 38310 # number of SCUpgradeReq hits 264111353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 41053 # number of SCUpgradeReq hits 264211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 79363 # number of SCUpgradeReq hits 264311353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 46553 # number of ReadExReq hits 264411353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 57229 # number of ReadExReq hits 264511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 103782 # number of ReadExReq hits 264611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5034 # number of ReadSharedReq hits 264711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3536 # number of ReadSharedReq hits 264811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 418413 # number of ReadSharedReq hits 264911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 580330 # number of ReadSharedReq hits 265011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 274635 # number of ReadSharedReq hits 265111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits 265211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4587 # number of ReadSharedReq hits 265311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 421326 # number of ReadSharedReq hits 265411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 539744 # number of ReadSharedReq hits 265511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292866 # number of ReadSharedReq hits 265611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2546044 # number of ReadSharedReq hits 265711353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 113687 # number of InvalidateReq hits 265811353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 125274 # number of InvalidateReq hits 265911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 238961 # number of InvalidateReq hits 266011353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5034 # number of demand (read+write) hits 266111353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3536 # number of demand (read+write) hits 266211353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 418413 # number of demand (read+write) hits 266311353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 626883 # number of demand (read+write) hits 266411353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 274635 # number of demand (read+write) hits 266511353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits 266611353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4587 # number of demand (read+write) hits 266711353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 421326 # number of demand (read+write) hits 266811353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 596973 # number of demand (read+write) hits 266911353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 292866 # number of demand (read+write) hits 267011353Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2649826 # number of demand (read+write) hits 267111353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5034 # number of overall hits 267211353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3536 # number of overall hits 267311353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 418413 # number of overall hits 267411353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 626883 # number of overall hits 267511353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 274635 # number of overall hits 267611353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits 267711353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4587 # number of overall hits 267811353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 421326 # number of overall hits 267911353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 596973 # number of overall hits 268011353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 292866 # number of overall hits 268111353Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2649826 # number of overall hits 268211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 62081 # number of UpgradeReq misses 268311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 62914 # number of UpgradeReq misses 268411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 124995 # number of UpgradeReq misses 268511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 13155 # number of SCUpgradeReq misses 268611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 14316 # number of SCUpgradeReq misses 268711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 27471 # number of SCUpgradeReq misses 268811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 85397 # number of ReadExReq misses 268911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 60501 # number of ReadExReq misses 269011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 145898 # number of ReadExReq misses 269111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1497 # number of ReadSharedReq misses 269211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1290 # number of ReadSharedReq misses 269311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 49096 # number of ReadSharedReq misses 269411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 140382 # number of ReadSharedReq misses 269511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 293392 # number of ReadSharedReq misses 269611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3412 # number of ReadSharedReq misses 269711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3601 # number of ReadSharedReq misses 269811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 47112 # number of ReadSharedReq misses 269911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 140231 # number of ReadSharedReq misses 270011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 203866 # number of ReadSharedReq misses 270111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 883879 # number of ReadSharedReq misses 270211353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 471175 # number of InvalidateReq misses 270311353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 117804 # number of InvalidateReq misses 270411353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 588979 # number of InvalidateReq misses 270511353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1497 # number of demand (read+write) misses 270611353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1290 # number of demand (read+write) misses 270711336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 49096 # number of demand (read+write) misses 270811353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 225779 # number of demand (read+write) misses 270911353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 293392 # number of demand (read+write) misses 271011353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3412 # number of demand (read+write) misses 271111353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3601 # number of demand (read+write) misses 271211353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 47112 # number of demand (read+write) misses 271311353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 200732 # number of demand (read+write) misses 271411353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 203866 # number of demand (read+write) misses 271511353Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1029777 # number of demand (read+write) misses 271611353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1497 # number of overall misses 271711353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1290 # number of overall misses 271811336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 49096 # number of overall misses 271911353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 225779 # number of overall misses 272011353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 293392 # number of overall misses 272111353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3412 # number of overall misses 272211353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3601 # number of overall misses 272311353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 47112 # number of overall misses 272411353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 200732 # number of overall misses 272511353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 203866 # number of overall misses 272611353Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1029777 # number of overall misses 272711353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 990526500 # number of UpgradeReq miss cycles 272811353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1021428000 # number of UpgradeReq miss cycles 272911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 2011954500 # number of UpgradeReq miss cycles 273011353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 200664500 # number of SCUpgradeReq miss cycles 273111353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 227119000 # number of SCUpgradeReq miss cycles 273211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 427783500 # number of SCUpgradeReq miss cycles 273311353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 11753356499 # number of ReadExReq miss cycles 273411353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 8113476500 # number of ReadExReq miss cycles 273511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 19866832999 # number of ReadExReq miss cycles 273611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 212874000 # number of ReadSharedReq miss cycles 273711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 183032000 # number of ReadSharedReq miss cycles 273811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6661915000 # number of ReadSharedReq miss cycles 273911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 19580832500 # number of ReadSharedReq miss cycles 274011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 50706713994 # number of ReadSharedReq miss cycles 274111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 480314000 # number of ReadSharedReq miss cycles 274211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 507652000 # number of ReadSharedReq miss cycles 274311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6389557500 # number of ReadSharedReq miss cycles 274411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 19780122000 # number of ReadSharedReq miss cycles 274511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 34128825244 # number of ReadSharedReq miss cycles 274611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 138631838238 # number of ReadSharedReq miss cycles 274711353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 137833000 # number of InvalidateReq miss cycles 274811353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 159862500 # number of InvalidateReq miss cycles 274911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_latency::total 297695500 # number of InvalidateReq miss cycles 275011353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 212874000 # number of demand (read+write) miss cycles 275111353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 183032000 # number of demand (read+write) miss cycles 275211353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6661915000 # number of demand (read+write) miss cycles 275311353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 31334188999 # number of demand (read+write) miss cycles 275411353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 50706713994 # number of demand (read+write) miss cycles 275511353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 480314000 # number of demand (read+write) miss cycles 275611353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 507652000 # number of demand (read+write) miss cycles 275711353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6389557500 # number of demand (read+write) miss cycles 275811353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 27893598500 # number of demand (read+write) miss cycles 275911353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 34128825244 # number of demand (read+write) miss cycles 276011353Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 158498671237 # number of demand (read+write) miss cycles 276111353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 212874000 # number of overall miss cycles 276211353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 183032000 # number of overall miss cycles 276311353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6661915000 # number of overall miss cycles 276411353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 31334188999 # number of overall miss cycles 276511353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 50706713994 # number of overall miss cycles 276611353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 480314000 # number of overall miss cycles 276711353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 507652000 # number of overall miss cycles 276811353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6389557500 # number of overall miss cycles 276911353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 27893598500 # number of overall miss cycles 277011353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 34128825244 # number of overall miss cycles 277111353Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 158498671237 # number of overall miss cycles 277211353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2788899 # number of WritebackDirty accesses(hits+misses) 277311353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2788899 # number of WritebackDirty accesses(hits+misses) 277411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 226287 # number of UpgradeReq accesses(hits+misses) 277511353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 194196 # number of UpgradeReq accesses(hits+misses) 277611353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 420483 # number of UpgradeReq accesses(hits+misses) 277711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 51465 # number of SCUpgradeReq accesses(hits+misses) 277811353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 55369 # number of SCUpgradeReq accesses(hits+misses) 277911353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 106834 # number of SCUpgradeReq accesses(hits+misses) 278011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 131950 # number of ReadExReq accesses(hits+misses) 278111353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 117730 # number of ReadExReq accesses(hits+misses) 278211353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 249680 # number of ReadExReq accesses(hits+misses) 278311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6531 # number of ReadSharedReq accesses(hits+misses) 278411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4826 # number of ReadSharedReq accesses(hits+misses) 278511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 467509 # number of ReadSharedReq accesses(hits+misses) 278611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 720712 # number of ReadSharedReq accesses(hits+misses) 278711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 568027 # number of ReadSharedReq accesses(hits+misses) 278811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8985 # number of ReadSharedReq accesses(hits+misses) 278911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8188 # number of ReadSharedReq accesses(hits+misses) 279011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 468438 # number of ReadSharedReq accesses(hits+misses) 279111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 679975 # number of ReadSharedReq accesses(hits+misses) 279211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 496732 # number of ReadSharedReq accesses(hits+misses) 279311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3429923 # number of ReadSharedReq accesses(hits+misses) 279411353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 584862 # number of InvalidateReq accesses(hits+misses) 279511353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 243078 # number of InvalidateReq accesses(hits+misses) 279611353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 827940 # number of InvalidateReq accesses(hits+misses) 279711353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 6531 # number of demand (read+write) accesses 279811353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 4826 # number of demand (read+write) accesses 279911353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 467509 # number of demand (read+write) accesses 280011353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 852662 # number of demand (read+write) accesses 280111353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 568027 # number of demand (read+write) accesses 280211353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8985 # number of demand (read+write) accesses 280311353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 8188 # number of demand (read+write) accesses 280411353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 468438 # number of demand (read+write) accesses 280511353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 797705 # number of demand (read+write) accesses 280611353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 496732 # number of demand (read+write) accesses 280711353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3679603 # number of demand (read+write) accesses 280811353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 6531 # number of overall (read+write) accesses 280911353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 4826 # number of overall (read+write) accesses 281011353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 467509 # number of overall (read+write) accesses 281111353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 852662 # number of overall (read+write) accesses 281211353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 568027 # number of overall (read+write) accesses 281311353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8985 # number of overall (read+write) accesses 281411353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 8188 # number of overall (read+write) accesses 281511353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 468438 # number of overall (read+write) accesses 281611353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 797705 # number of overall (read+write) accesses 281711353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 496732 # number of overall (read+write) accesses 281811353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3679603 # number of overall (read+write) accesses 281911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.274346 # miss rate for UpgradeReq accesses 282011353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.323972 # miss rate for UpgradeReq accesses 282111353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.297265 # miss rate for UpgradeReq accesses 282211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.255611 # miss rate for SCUpgradeReq accesses 282311353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.258556 # miss rate for SCUpgradeReq accesses 282411353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.257137 # miss rate for SCUpgradeReq accesses 282511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.647192 # miss rate for ReadExReq accesses 282611353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.513896 # miss rate for ReadExReq accesses 282711353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.584340 # miss rate for ReadExReq accesses 282811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for ReadSharedReq accesses 282911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.267302 # miss rate for ReadSharedReq accesses 283011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.105016 # miss rate for ReadSharedReq accesses 283111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses 283211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for ReadSharedReq accesses 283311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for ReadSharedReq accesses 283411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.439790 # miss rate for ReadSharedReq accesses 283511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.100573 # miss rate for ReadSharedReq accesses 283611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.206230 # miss rate for ReadSharedReq accesses 283711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for ReadSharedReq accesses 283811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.257696 # miss rate for ReadSharedReq accesses 283911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.805617 # miss rate for InvalidateReq accesses 284011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.484635 # miss rate for InvalidateReq accesses 284111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.711379 # miss rate for InvalidateReq accesses 284211353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for demand accesses 284311353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.267302 # miss rate for demand accesses 284411353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.105016 # miss rate for demand accesses 284511353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.264793 # miss rate for demand accesses 284611353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for demand accesses 284711353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for demand accesses 284811353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.439790 # miss rate for demand accesses 284911353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.100573 # miss rate for demand accesses 285011353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.251637 # miss rate for demand accesses 285111353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for demand accesses 285211353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.279861 # miss rate for demand accesses 285311353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for overall accesses 285411353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.267302 # miss rate for overall accesses 285511353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.105016 # miss rate for overall accesses 285611353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.264793 # miss rate for overall accesses 285711353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for overall accesses 285811353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for overall accesses 285911353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.439790 # miss rate for overall accesses 286011353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.100573 # miss rate for overall accesses 286111353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.251637 # miss rate for overall accesses 286211353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for overall accesses 286311353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.279861 # miss rate for overall accesses 286411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15955.388927 # average UpgradeReq miss latency 286511353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16235.305337 # average UpgradeReq miss latency 286611353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 16096.279851 # average UpgradeReq miss latency 286711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15253.857849 # average SCUpgradeReq miss latency 286811353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15864.696843 # average SCUpgradeReq miss latency 286911353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 15572.185213 # average SCUpgradeReq miss latency 287011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 137631.960127 # average ReadExReq miss latency 287111353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 134104.832978 # average ReadExReq miss latency 287211353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 136169.330621 # average ReadExReq miss latency 287311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average ReadSharedReq miss latency 287411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141885.271318 # average ReadSharedReq miss latency 287511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135691.604204 # average ReadSharedReq miss latency 287611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139482.501318 # average ReadSharedReq miss latency 287711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average ReadSharedReq miss latency 287811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average ReadSharedReq miss latency 287911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140975.284643 # average ReadSharedReq miss latency 288011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135624.840805 # average ReadSharedReq miss latency 288111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141053.846867 # average ReadSharedReq miss latency 288211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average ReadSharedReq miss latency 288311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 156844.815001 # average ReadSharedReq miss latency 288411353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 292.530376 # average InvalidateReq miss latency 288511353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1357.020984 # average InvalidateReq miss latency 288611353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 505.443318 # average InvalidateReq miss latency 288711353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average overall miss latency 288811353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 141885.271318 # average overall miss latency 288911353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 135691.604204 # average overall miss latency 289011353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 138782.566133 # average overall miss latency 289111353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average overall miss latency 289211353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average overall miss latency 289311353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 140975.284643 # average overall miss latency 289411353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 135624.840805 # average overall miss latency 289511353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 138959.401092 # average overall miss latency 289611353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average overall miss latency 289711353Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 153915.528544 # average overall miss latency 289811353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average overall miss latency 289911353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 141885.271318 # average overall miss latency 290011353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 135691.604204 # average overall miss latency 290111353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 138782.566133 # average overall miss latency 290211353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average overall miss latency 290311353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average overall miss latency 290411353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 140975.284643 # average overall miss latency 290511353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 135624.840805 # average overall miss latency 290611353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 138959.401092 # average overall miss latency 290711353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average overall miss latency 290811353Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 153915.528544 # average overall miss latency 290911353Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 442 # number of cycles access was blocked 291010515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 291111353Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 7 # number of cycles access was blocked 291210515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 291311353Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 63.142857 # average number of cycles each access was blocked 291410515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 291510515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 291610515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 291711353Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1210545 # number of writebacks 291811353Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1210545 # number of writebacks 291911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 196 # number of ReadSharedReq MSHR hits 292011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 72 # number of ReadSharedReq MSHR hits 292111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 242 # number of ReadSharedReq MSHR hits 292211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 69 # number of ReadSharedReq MSHR hits 292311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 10 # number of ReadSharedReq MSHR hits 292411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 589 # number of ReadSharedReq MSHR hits 292511353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 196 # number of demand (read+write) MSHR hits 292611353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 72 # number of demand (read+write) MSHR hits 292711353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 242 # number of demand (read+write) MSHR hits 292811353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 69 # number of demand (read+write) MSHR hits 292911353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 10 # number of demand (read+write) MSHR hits 293011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits 293111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 196 # number of overall MSHR hits 293211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 72 # number of overall MSHR hits 293311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 242 # number of overall MSHR hits 293411353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 69 # number of overall MSHR hits 293511353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 10 # number of overall MSHR hits 293611353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 589 # number of overall MSHR hits 293711353Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 56231 # number of CleanEvict MSHR misses 293811353Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 56231 # number of CleanEvict MSHR misses 293911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 62081 # number of UpgradeReq MSHR misses 294011353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 62914 # number of UpgradeReq MSHR misses 294111353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 124995 # number of UpgradeReq MSHR misses 294211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13155 # number of SCUpgradeReq MSHR misses 294311353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 14316 # number of SCUpgradeReq MSHR misses 294411353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 27471 # number of SCUpgradeReq MSHR misses 294511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 85397 # number of ReadExReq MSHR misses 294611353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 60501 # number of ReadExReq MSHR misses 294711353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 145898 # number of ReadExReq MSHR misses 294811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1497 # number of ReadSharedReq MSHR misses 294911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1290 # number of ReadSharedReq MSHR misses 295011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48900 # number of ReadSharedReq MSHR misses 295111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 140310 # number of ReadSharedReq MSHR misses 295211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of ReadSharedReq MSHR misses 295311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3412 # number of ReadSharedReq MSHR misses 295411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 3601 # number of ReadSharedReq MSHR misses 295511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46870 # number of ReadSharedReq MSHR misses 295611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 140162 # number of ReadSharedReq MSHR misses 295711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of ReadSharedReq MSHR misses 295811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 883290 # number of ReadSharedReq MSHR misses 295911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 471175 # number of InvalidateReq MSHR misses 296011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 117804 # number of InvalidateReq MSHR misses 296111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 588979 # number of InvalidateReq MSHR misses 296211353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1497 # number of demand (read+write) MSHR misses 296311353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1290 # number of demand (read+write) MSHR misses 296411353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 48900 # number of demand (read+write) MSHR misses 296511353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 225707 # number of demand (read+write) MSHR misses 296611353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of demand (read+write) MSHR misses 296711353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 3412 # number of demand (read+write) MSHR misses 296811353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 3601 # number of demand (read+write) MSHR misses 296911353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 46870 # number of demand (read+write) MSHR misses 297011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 200663 # number of demand (read+write) MSHR misses 297111353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of demand (read+write) MSHR misses 297211353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1029188 # number of demand (read+write) MSHR misses 297311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1497 # number of overall MSHR misses 297411353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1290 # number of overall MSHR misses 297511353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 48900 # number of overall MSHR misses 297611353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 225707 # number of overall MSHR misses 297711353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of overall MSHR misses 297811353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 3412 # number of overall MSHR misses 297911353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 3601 # number of overall MSHR misses 298011353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 46870 # number of overall MSHR misses 298111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 200663 # number of overall MSHR misses 298211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of overall MSHR misses 298311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 1029188 # number of overall MSHR misses 298410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 298511353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable 298610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 298711353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 10147 # number of ReadReq MSHR uncacheable 298811353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81896 # number of ReadReq MSHR uncacheable 298911353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable 299011353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable 299111353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38489 # number of WriteReq MSHR uncacheable 299210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 299311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses 299410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 299511353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 20765 # number of overall MSHR uncacheable misses 299611353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 120385 # number of overall MSHR uncacheable misses 299711353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4385750000 # number of UpgradeReq MSHR miss cycles 299811353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4455748500 # number of UpgradeReq MSHR miss cycles 299911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 8841498500 # number of UpgradeReq MSHR miss cycles 300011353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 969977000 # number of SCUpgradeReq MSHR miss cycles 300111353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1055544500 # number of SCUpgradeReq MSHR miss cycles 300211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 2025521500 # number of SCUpgradeReq MSHR miss cycles 300311353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10899069105 # number of ReadExReq MSHR miss cycles 300411353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7507982381 # number of ReadExReq MSHR miss cycles 300511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 18407051486 # number of ReadExReq MSHR miss cycles 300611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of ReadSharedReq MSHR miss cycles 300711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 170123517 # number of ReadSharedReq MSHR miss cycles 300811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6149223860 # number of ReadSharedReq MSHR miss cycles 300911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18166902374 # number of ReadSharedReq MSHR miss cycles 301011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of ReadSharedReq MSHR miss cycles 301111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of ReadSharedReq MSHR miss cycles 301211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 471618547 # number of ReadSharedReq MSHR miss cycles 301311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5891103441 # number of ReadSharedReq MSHR miss cycles 301411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 18366630812 # number of ReadSharedReq MSHR miss cycles 301511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of ReadSharedReq MSHR miss cycles 301611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 129716566457 # number of ReadSharedReq MSHR miss cycles 301711353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 32475619499 # number of InvalidateReq MSHR miss cycles 301811353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 8166236998 # number of InvalidateReq MSHR miss cycles 301911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 40641856497 # number of InvalidateReq MSHR miss cycles 302011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of demand (read+write) MSHR miss cycles 302111353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 170123517 # number of demand (read+write) MSHR miss cycles 302211353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 6149223860 # number of demand (read+write) MSHR miss cycles 302311353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 29065971479 # number of demand (read+write) MSHR miss cycles 302411353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of demand (read+write) MSHR miss cycles 302511353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of demand (read+write) MSHR miss cycles 302611353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 471618547 # number of demand (read+write) MSHR miss cycles 302711353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 5891103441 # number of demand (read+write) MSHR miss cycles 302811353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 25874613193 # number of demand (read+write) MSHR miss cycles 302911353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of demand (read+write) MSHR miss cycles 303011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 148123617943 # number of demand (read+write) MSHR miss cycles 303111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of overall MSHR miss cycles 303211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 170123517 # number of overall MSHR miss cycles 303311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 6149223860 # number of overall MSHR miss cycles 303411353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 29065971479 # number of overall MSHR miss cycles 303511353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of overall MSHR miss cycles 303611353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of overall MSHR miss cycles 303711353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 471618547 # number of overall MSHR miss cycles 303811353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 5891103441 # number of overall MSHR miss cycles 303911353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 25874613193 # number of overall MSHR miss cycles 304011353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of overall MSHR miss cycles 304111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 148123617943 # number of overall MSHR miss cycles 304211201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 304311353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4538545031 # number of ReadReq MSHR uncacheable cycles 304411353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles 304511353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1387996535 # number of ReadReq MSHR uncacheable cycles 304611353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 10793019566 # number of ReadReq MSHR uncacheable cycles 304711353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4403248038 # number of WriteReq MSHR uncacheable cycles 304811353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1559838113 # number of WriteReq MSHR uncacheable cycles 304911353Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5963086151 # number of WriteReq MSHR uncacheable cycles 305011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 305111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 8941793069 # number of overall MSHR uncacheable cycles 305211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles 305311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 2947834648 # number of overall MSHR uncacheable cycles 305411353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 16756105717 # number of overall MSHR uncacheable cycles 305510892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 305610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 305711353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.274346 # mshr miss rate for UpgradeReq accesses 305811353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.323972 # mshr miss rate for UpgradeReq accesses 305911353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.297265 # mshr miss rate for UpgradeReq accesses 306011353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.255611 # mshr miss rate for SCUpgradeReq accesses 306111353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.258556 # mshr miss rate for SCUpgradeReq accesses 306211353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257137 # mshr miss rate for SCUpgradeReq accesses 306311353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.647192 # mshr miss rate for ReadExReq accesses 306411353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.513896 # mshr miss rate for ReadExReq accesses 306511353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.584340 # mshr miss rate for ReadExReq accesses 306611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for ReadSharedReq accesses 306711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for ReadSharedReq accesses 306811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for ReadSharedReq accesses 306911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.194682 # mshr miss rate for ReadSharedReq accesses 307011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for ReadSharedReq accesses 307111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for ReadSharedReq accesses 307211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for ReadSharedReq accesses 307311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for ReadSharedReq accesses 307411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.206128 # mshr miss rate for ReadSharedReq accesses 307511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for ReadSharedReq accesses 307611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.257525 # mshr miss rate for ReadSharedReq accesses 307711353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.805617 # mshr miss rate for InvalidateReq accesses 307811353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.484635 # mshr miss rate for InvalidateReq accesses 307911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.711379 # mshr miss rate for InvalidateReq accesses 308011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for demand accesses 308111353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for demand accesses 308211353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for demand accesses 308311353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for demand accesses 308411353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for demand accesses 308511353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for demand accesses 308611353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for demand accesses 308711353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for demand accesses 308811353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for demand accesses 308911353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for demand accesses 309011353Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.279701 # mshr miss rate for demand accesses 309111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for overall accesses 309211353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for overall accesses 309311353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for overall accesses 309411353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for overall accesses 309511353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for overall accesses 309611353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for overall accesses 309711353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for overall accesses 309811353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for overall accesses 309911353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for overall accesses 310011353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for overall accesses 310111353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.279701 # mshr miss rate for overall accesses 310211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70645.608157 # average UpgradeReq mshr miss latency 310311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70822.845472 # average UpgradeReq mshr miss latency 310411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 70734.817393 # average UpgradeReq mshr miss latency 310511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73734.473584 # average SCUpgradeReq mshr miss latency 310611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73731.803576 # average SCUpgradeReq mshr miss latency 310711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73733.082159 # average SCUpgradeReq mshr miss latency 310811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127628.243439 # average ReadExReq mshr miss latency 310911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124096.831143 # average ReadExReq mshr miss latency 311011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 126163.836968 # average ReadExReq mshr miss latency 311111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average ReadSharedReq mshr miss latency 311211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average ReadSharedReq mshr miss latency 311311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average ReadSharedReq mshr miss latency 311411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129476.889559 # average ReadSharedReq mshr miss latency 311511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average ReadSharedReq mshr miss latency 311611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average ReadSharedReq mshr miss latency 311711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average ReadSharedReq mshr miss latency 311811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average ReadSharedReq mshr miss latency 311911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131038.589718 # average ReadSharedReq mshr miss latency 312011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average ReadSharedReq mshr miss latency 312111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146856.147423 # average ReadSharedReq mshr miss latency 312211353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68924.750887 # average InvalidateReq mshr miss latency 312311353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881 # average InvalidateReq mshr miss latency 312411353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396 # average InvalidateReq mshr miss latency 312511353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency 312611353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency 312711353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency 312811353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency 312911353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency 313011353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency 313111353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency 313211353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency 313311353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency 313411353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency 313511353Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency 313611353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency 313711353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency 313811353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency 313911353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency 314011353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency 314111353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency 314211353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency 314311353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency 314411353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency 314511353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency 314611353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency 314711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 314811353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787 # average ReadReq mshr uncacheable latency 314911353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency 315011353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency 315111353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency 315211353Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency 315311353Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510 # average WriteReq mshr uncacheable latency 315411353Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency 315511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 315611353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059 # average overall mshr uncacheable latency 315711353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency 315811353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472 # average overall mshr uncacheable latency 315911353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919 # average overall mshr uncacheable latency 316010515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 316111353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 81896 # Transaction distribution 316211353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 974121 # Transaction distribution 316311353Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38489 # Transaction distribution 316411353Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38489 # Transaction distribution 316511353Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution 316611353Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 246913 # Transaction distribution 316711353Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 405326 # Transaction distribution 316811353Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution 316911353Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 317011353Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 317111353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 159351 # Transaction distribution 317211353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 141190 # Transaction distribution 317311353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution 317411353Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 691970 # Transaction distribution 317511353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) 317610535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 317711353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes) 317811353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes) 317911353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes) 318011353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) 318111353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) 318211353Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes) 318311353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) 318410535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 318511353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes) 318611353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes) 318711353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes) 318811353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes) 318911353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes) 319011353Sandreas.hansson@arm.comsystem.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes) 319111353Sandreas.hansson@arm.comsystem.membus.snoops 585601 # Total snoops (count) 319211353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4153558 # Request fanout histogram 319310535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 319410535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 319510535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 319610535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 319711353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram 319810535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 319910535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 320010535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 320110535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 320211353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4153558 # Request fanout histogram 320311353Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks) 320410535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 320511138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 320610535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 320711353Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks) 320810535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 320911353Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks) 321010535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 321111353Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks) 321210535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 321311353Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks) 321410535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 321511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 321611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 321711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 321811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 321911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 322011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 322110515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 322210515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 322310515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 322410515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 322510515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 322610515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 322710515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 322810515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 322910515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 323011201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 323110515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 323210515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 323310515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 323411201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 323510515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 323610515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 323710515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 323810515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 323910515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 324010515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 324110515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 324210515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 324310515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 324410515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 324510515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 324610515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 324710515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 324810515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 324910515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 325010515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 325110515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 325210515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 325310515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 325410515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 325510515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 325610515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 325710515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 325810515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 325910515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 326010515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 326110515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 326210515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 326311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 326411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 326511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 326611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 326711353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter. 326811353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data. 326911353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 327011353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter. 327111353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 327211353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 327311353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution 327411353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution 327511353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution 327611353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution 327711353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution 327811353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution 327911353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution 328011353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution 328111353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution 328211353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution 328311353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 328411353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution 328511353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution 328611353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution 328711353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution 328811353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution 328911353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes) 329011353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes) 329111353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes) 329211353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes) 329311353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes) 329411353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes) 329511353Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3137723 # Total snoops (count) 329611353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram 329711353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram 329811353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram 329910515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 330011353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram 330111353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram 330211353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram 330310515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 330411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 330510515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 330611353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram 330711353Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks) 330810515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 330911353Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks) 331010515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 331111353Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks) 331210515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 331311353Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks) 331410515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 331510515SN/A 331610515SN/A---------- End Simulation Statistics ---------- 3317