stats.txt revision 11167
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311138Sandreas.hansson@arm.comsim_seconds 47.474700 # Number of seconds simulated 411138Sandreas.hansson@arm.comsim_ticks 47474700369500 # Number of ticks simulated 511138Sandreas.hansson@arm.comfinal_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711167Sjthestness@gmail.comhost_inst_rate 794386 # Simulator instruction rate (inst/s) 811167Sjthestness@gmail.comhost_op_rate 934446 # Simulator op (including micro ops) rate (op/s) 911167Sjthestness@gmail.comhost_tick_rate 42775515400 # Simulator tick rate (ticks/s) 1011167Sjthestness@gmail.comhost_mem_usage 715280 # Number of bytes of host memory used 1111167Sjthestness@gmail.comhost_seconds 1109.86 # Real time elapsed on the host 1211138Sandreas.hansson@arm.comsim_insts 881655060 # Number of instructions simulated 1311138Sandreas.hansson@arm.comsim_ops 1037101350 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 127360 # Number of bytes read from this memory 1711138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 143744 # Number of bytes read from this memory 1811138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3459124 # Number of bytes read from this memory 1911138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 40376840 # Number of bytes read from this memory 2011138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 12078528 # Number of bytes read from this memory 2111138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 91584 # Number of bytes read from this memory 2211138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 86464 # Number of bytes read from this memory 2311138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2488056 # Number of bytes read from this memory 2411138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 17058000 # Number of bytes read from this memory 2511138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 14991744 # Number of bytes read from this memory 2611138Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 410816 # Number of bytes read from this memory 2711138Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 91312260 # Number of bytes read from this memory 2811138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3459124 # Number of instructions bytes read from this memory 2911138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2488056 # Number of instructions bytes read from this memory 3011138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5947180 # Number of instructions bytes read from this memory 3111138Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 77042688 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411138Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 77063272 # Number of bytes written to this memory 3511138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1990 # Number of read requests responded to by this memory 3611138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2246 # Number of read requests responded to by this memory 3711138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 94456 # Number of read requests responded to by this memory 3811138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 630901 # Number of read requests responded to by this memory 3911138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 188727 # Number of read requests responded to by this memory 4011138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1431 # Number of read requests responded to by this memory 4111138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1351 # Number of read requests responded to by this memory 4211138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 38964 # Number of read requests responded to by this memory 4311138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 266544 # Number of read requests responded to by this memory 4411138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 234246 # Number of read requests responded to by this memory 4511138Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6419 # Number of read requests responded to by this memory 4611138Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1467275 # Number of read requests responded to by this memory 4711138Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1203792 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011138Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1206366 # Number of write requests responded to by this memory 5111138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2683 # Total read bandwidth from this memory (bytes/s) 5211138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 3028 # Total read bandwidth from this memory (bytes/s) 5311138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 72862 # Total read bandwidth from this memory (bytes/s) 5411138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 850492 # Total read bandwidth from this memory (bytes/s) 5511138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 254420 # Total read bandwidth from this memory (bytes/s) 5611138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 1929 # Total read bandwidth from this memory (bytes/s) 5711138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 1821 # Total read bandwidth from this memory (bytes/s) 5811138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 52408 # Total read bandwidth from this memory (bytes/s) 5911138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 359307 # Total read bandwidth from this memory (bytes/s) 6011138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 315784 # Total read bandwidth from this memory (bytes/s) 6111138Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8653 # Total read bandwidth from this memory (bytes/s) 6211138Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1923388 # Total read bandwidth from this memory (bytes/s) 6311138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 72862 # Instruction read bandwidth from this memory (bytes/s) 6411138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 52408 # Instruction read bandwidth from this memory (bytes/s) 6511138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 125271 # Instruction read bandwidth from this memory (bytes/s) 6611138Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1622816 # Write bandwidth from this memory (bytes/s) 6711138Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911138Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1623249 # Write bandwidth from this memory (bytes/s) 7011138Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1622816 # Total bandwidth to/from this memory (bytes/s) 7111138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2683 # Total bandwidth to/from this memory (bytes/s) 7211138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 3028 # Total bandwidth to/from this memory (bytes/s) 7311138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 72862 # Total bandwidth to/from this memory (bytes/s) 7411138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 850925 # Total bandwidth to/from this memory (bytes/s) 7511138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 254420 # Total bandwidth to/from this memory (bytes/s) 7611138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 1929 # Total bandwidth to/from this memory (bytes/s) 7711138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 1821 # Total bandwidth to/from this memory (bytes/s) 7811138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 52408 # Total bandwidth to/from this memory (bytes/s) 7911138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 359307 # Total bandwidth to/from this memory (bytes/s) 8011138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 315784 # Total bandwidth to/from this memory (bytes/s) 8111138Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8653 # Total bandwidth to/from this memory (bytes/s) 8211138Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3546637 # Total bandwidth to/from this memory (bytes/s) 8311138Sandreas.hansson@arm.comsystem.physmem.readReqs 1467275 # Number of read requests accepted 8411138Sandreas.hansson@arm.comsystem.physmem.writeReqs 1206366 # Number of write requests accepted 8511138Sandreas.hansson@arm.comsystem.physmem.readBursts 1467275 # Number of DRAM read bursts, including those serviced by the write queue 8611138Sandreas.hansson@arm.comsystem.physmem.writeBursts 1206366 # Number of DRAM write bursts, including those merged in the write queue 8711138Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 93873920 # Total number of bytes read from DRAM 8811138Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 31680 # Total number of bytes read from write queue 8911138Sandreas.hansson@arm.comsystem.physmem.bytesWritten 77062336 # Total number of bytes written to DRAM 9011138Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 91312260 # Total read bytes from the system interface side 9111138Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 77063272 # Total written bytes from the system interface side 9211138Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 495 # Number of DRAM read bursts serviced by the write queue 9310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 9411138Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 220616 # Number of requests that are neither read nor write 9511138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 87562 # Per bank write bursts 9611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 88840 # Per bank write bursts 9711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 82797 # Per bank write bursts 9811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 92927 # Per bank write bursts 9911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 90148 # Per bank write bursts 10011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 93986 # Per bank write bursts 10111138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 87799 # Per bank write bursts 10211138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 94269 # Per bank write bursts 10311138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 90753 # Per bank write bursts 10411138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 132105 # Per bank write bursts 10511138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 81290 # Per bank write bursts 10611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 92144 # Per bank write bursts 10711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 81361 # Per bank write bursts 10811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 87555 # Per bank write bursts 10911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 92182 # Per bank write bursts 11011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 91062 # Per bank write bursts 11111138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 71771 # Per bank write bursts 11211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 74672 # Per bank write bursts 11311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 72652 # Per bank write bursts 11411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 78055 # Per bank write bursts 11511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 74620 # Per bank write bursts 11611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 78875 # Per bank write bursts 11711138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 73591 # Per bank write bursts 11811138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 76891 # Per bank write bursts 11911138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 77107 # Per bank write bursts 12011138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 78277 # Per bank write bursts 12111138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 71128 # Per bank write bursts 12211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 78119 # Per bank write bursts 12311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 70456 # Per bank write bursts 12411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 74533 # Per bank write bursts 12511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 76600 # Per bank write bursts 12611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 76752 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811138Sandreas.hansson@arm.comsystem.physmem.numWrRetry 39 # Number of times write queue was full causing retry 12911138Sandreas.hansson@arm.comsystem.physmem.totGap 47474697259000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611138Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1424050 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311138Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1203792 # Write request sizes (log2) 14411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1195881 # What read queue length does an incoming req see 14511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 91231 # What read queue length does an incoming req see 14611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 37643 # What read queue length does an incoming req see 14711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 32050 # What read queue length does an incoming req see 14811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 26760 # What read queue length does an incoming req see 14911138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 23675 # What read queue length does an incoming req see 15011138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 20974 # What read queue length does an incoming req see 15111138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 18326 # What read queue length does an incoming req see 15211138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 14619 # What read queue length does an incoming req see 15311138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2367 # What read queue length does an incoming req see 15411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 941 # What read queue length does an incoming req see 15511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 584 # What read queue length does an incoming req see 15611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 447 # What read queue length does an incoming req see 15711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 348 # What read queue length does an incoming req see 15811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 253 # What read queue length does an incoming req see 15911138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 224 # What read queue length does an incoming req see 16011138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see 16110944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see 16211138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see 16311138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see 16411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 16511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 16611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 16711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 18047 # What write queue length does an incoming req see 19211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 20216 # What write queue length does an incoming req see 19311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 49731 # What write queue length does an incoming req see 19411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 58137 # What write queue length does an incoming req see 19511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 63836 # What write queue length does an incoming req see 19611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 67727 # What write queue length does an incoming req see 19711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 72112 # What write queue length does an incoming req see 19811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 73557 # What write queue length does an incoming req see 19911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 75338 # What write queue length does an incoming req see 20011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 76158 # What write queue length does an incoming req see 20111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 77610 # What write queue length does an incoming req see 20211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 81366 # What write queue length does an incoming req see 20311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 78544 # What write queue length does an incoming req see 20411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 78356 # What write queue length does an incoming req see 20511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 81800 # What write queue length does an incoming req see 20611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 76571 # What write queue length does an incoming req see 20711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 72953 # What write queue length does an incoming req see 20811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 70532 # What write queue length does an incoming req see 20911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1899 # What write queue length does an incoming req see 21011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1287 # What write queue length does an incoming req see 21111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 892 # What write queue length does an incoming req see 21211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 734 # What write queue length does an incoming req see 21311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 591 # What write queue length does an incoming req see 21411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 574 # What write queue length does an incoming req see 21511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see 21611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 376 # What write queue length does an incoming req see 21711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see 21811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see 21911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 359 # What write queue length does an incoming req see 22011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 330 # What write queue length does an incoming req see 22111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 302 # What write queue length does an incoming req see 22211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see 22311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see 22411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see 22511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see 22611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 246 # What write queue length does an incoming req see 22711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see 22811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see 22911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see 23011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see 23111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see 23211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see 23311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 118 # What write queue length does an incoming req see 23411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see 23511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see 23611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see 23711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see 23811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see 23911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see 24011138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 940579 # Bytes accessed per row activation 24111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 181.734800 # Bytes accessed per row activation 24211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 113.091903 # Bytes accessed per row activation 24311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 237.596263 # Bytes accessed per row activation 24411138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 569137 60.51% 60.51% # Bytes accessed per row activation 24511138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 185879 19.76% 80.27% # Bytes accessed per row activation 24611138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 61156 6.50% 86.77% # Bytes accessed per row activation 24711138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 31438 3.34% 90.12% # Bytes accessed per row activation 24811138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 21576 2.29% 92.41% # Bytes accessed per row activation 24911138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 13250 1.41% 93.82% # Bytes accessed per row activation 25011138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 9973 1.06% 94.88% # Bytes accessed per row activation 25111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 9805 1.04% 95.92% # Bytes accessed per row activation 25211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 38365 4.08% 100.00% # Bytes accessed per row activation 25311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 940579 # Bytes accessed per row activation 25411138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 68336 # Reads before turning the bus around for writes 25511138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 21.464104 # Reads before turning the bus around for writes 25611138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 309.922160 # Reads before turning the bus around for writes 25711138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 68334 100.00% 100.00% # Reads before turning the bus around for writes 25810892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 26011138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 68336 # Reads before turning the bus around for writes 26111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 68336 # Writes before turning the bus around for reads 26211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.620273 # Writes before turning the bus around for reads 26311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.104093 # Writes before turning the bus around for reads 26411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 6.841865 # Writes before turning the bus around for reads 26511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 64690 94.66% 94.66% # Writes before turning the bus around for reads 26611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 1540 2.25% 96.92% # Writes before turning the bus around for reads 26711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 239 0.35% 97.27% # Writes before turning the bus around for reads 26811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 282 0.41% 97.68% # Writes before turning the bus around for reads 26911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 82 0.12% 97.80% # Writes before turning the bus around for reads 27011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 291 0.43% 98.23% # Writes before turning the bus around for reads 27111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 162 0.24% 98.46% # Writes before turning the bus around for reads 27211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 86 0.13% 98.59% # Writes before turning the bus around for reads 27311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 81 0.12% 98.71% # Writes before turning the bus around for reads 27411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 117 0.17% 98.88% # Writes before turning the bus around for reads 27511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 30 0.04% 98.92% # Writes before turning the bus around for reads 27611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 46 0.07% 98.99% # Writes before turning the bus around for reads 27711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 391 0.57% 99.56% # Writes before turning the bus around for reads 27811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 42 0.06% 99.62% # Writes before turning the bus around for reads 27911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 42 0.06% 99.69% # Writes before turning the bus around for reads 28011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 142 0.21% 99.89% # Writes before turning the bus around for reads 28111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 21 0.03% 99.92% # Writes before turning the bus around for reads 28211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 28311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads 28411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads 28511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 7 0.01% 99.94% # Writes before turning the bus around for reads 28611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads 28711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads 28811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads 28911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 29010944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 29111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads 29211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads 29311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads 29411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads 29510944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 29611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 29711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 68336 # Writes before turning the bus around for reads 29811138Sandreas.hansson@arm.comsystem.physmem.totQLat 37142962355 # Total ticks spent queuing 29911138Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 64645087355 # Total ticks spent from burst creation until serviced by the DRAM 30011138Sandreas.hansson@arm.comsystem.physmem.totBusLat 7333900000 # Total ticks spent in databus transfers 30111138Sandreas.hansson@arm.comsystem.physmem.avgQLat 25322.79 # Average queueing delay per DRAM burst 30210515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30311138Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 44072.79 # Average memory access latency per DRAM burst 30411138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.98 # Average DRAM read bandwidth in MiByte/s 30511138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s 30611138Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s 30711138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s 30810515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 30910827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31011138Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 31110892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31211138Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 31311138Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 31411138Sandreas.hansson@arm.comsystem.physmem.readRowHits 1168360 # Number of row buffer hits during reads 31511138Sandreas.hansson@arm.comsystem.physmem.writeRowHits 561939 # Number of row buffer hits during writes 31611138Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads 31711138Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 46.67 # Row buffer hit rate for writes 31811138Sandreas.hansson@arm.comsystem.physmem.avgGap 17756571.38 # Average gap between requests 31911138Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.78 # Row buffer hit rate, read and write combined 32011138Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3585949920 # Energy for activate commands per rank (pJ) 32111138Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1956619500 # Energy for precharge commands per rank (pJ) 32211138Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 5602958400 # Energy for read commands per rank (pJ) 32311138Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3895302960 # Energy for write commands per rank (pJ) 32411138Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) 32511138Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1230768339570 # Energy for active background per rank (pJ) 32611138Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27405197149500 # Energy for precharge background per rank (pJ) 32711138Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31751822762730 # Total energy per rank (pJ) 32811138Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.815694 # Core power per rank (mW) 32911138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45589938065590 # Time in different power states 33011138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1585284480000 # Time in different power states 33110628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33211138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 299474968160 # Time in different power states 33310628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33411138Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3524827320 # Energy for activate commands per rank (pJ) 33511138Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1923268875 # Energy for precharge commands per rank (pJ) 33611138Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 5837886600 # Energy for read commands per rank (pJ) 33711138Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3907258560 # Energy for write commands per rank (pJ) 33811138Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) 33911138Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1224297828675 # Energy for active background per rank (pJ) 34011138Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27410873036250 # Energy for precharge background per rank (pJ) 34111138Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31751180549160 # Total energy per rank (pJ) 34211138Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.802167 # Core power per rank (mW) 34311138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45599398366763 # Time in different power states 34411138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1585284480000 # Time in different power states 34510628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34611138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 290016828237 # Time in different power states 34710628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 34810515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 34910515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35010515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35110515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35210515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35310515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 35610515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 35710515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 35810515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 35910515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36010515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36110515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36210515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36310515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36410515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36510515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 36610515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37410535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37510535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37610535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37710726SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 37810726SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 37910726SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38010515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41011138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 101051 # Table walker walks requested 41111138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 101051 # Table walker walks initiated with long descriptors 41211138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8300 # Level at which table walker walks with long descriptors terminate 41311138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 78014 # Level at which table walker walks with long descriptors terminate 41411138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 41511138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 101044 # Table walker wait (enqueue to first request) latency 41611138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 101044 100.00% 100.00% # Table walker wait (enqueue to first request) latency 41711138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 101044 # Table walker wait (enqueue to first request) latency 41811138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 86321 # Table walker service (enqueue to completion) latency 41911138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013 # Table walker service (enqueue to completion) latency 42011138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020 # Table walker service (enqueue to completion) latency 42111138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382 # Table walker service (enqueue to completion) latency 42211138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 84871 98.32% 98.32% # Table walker service (enqueue to completion) latency 42311138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 161 0.19% 98.51% # Table walker service (enqueue to completion) latency 42411138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 1103 1.28% 99.78% # Table walker service (enqueue to completion) latency 42511138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.83% # Table walker service (enqueue to completion) latency 42611138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 57 0.07% 99.90% # Table walker service (enqueue to completion) latency 42711138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.93% # Table walker service (enqueue to completion) latency 42811138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency 42911138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.02% 99.99% # Table walker service (enqueue to completion) latency 43011138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 43111138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 43211138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 43311138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 86321 # Table walker service (enqueue to completion) latency 43411138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 1368339312 # Table walker pending requests distribution 43511138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean -0.519630 # Table walker pending requests distribution 43611138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 2079369704 151.96% 151.96% # Table walker pending requests distribution 43711138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 -711030392 -51.96% 100.00% # Table walker pending requests distribution 43811138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 1368339312 # Table walker pending requests distribution 43911138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 78015 90.38% 90.38% # Table walker page sizes translated 44011138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 8300 9.62% 100.00% # Table walker page sizes translated 44111138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 86315 # Table walker page sizes translated 44211138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101051 # Table walker requests started/completed, data/inst 44310628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44411138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101051 # Table walker requests started/completed, data/inst 44511138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 86315 # Table walker requests started/completed, data/inst 44610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44711138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 86315 # Table walker requests started/completed, data/inst 44811138Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 187366 # Table walker requests started/completed, data/inst 44910535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45010535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45111138Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 83039604 # DTB read hits 45211138Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 74585 # DTB read misses 45311138Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 76137695 # DTB write hits 45411138Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 26466 # DTB write misses 45510535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 45610535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45711138Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 45811138Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 45911138Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 37690 # Number of entries that have been flushed from TLB 46010535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 46111138Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 4076 # Number of TLB faults due to prefetch 46210535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46311138Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10173 # Number of TLB faults due to permissions restrictions 46411138Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 83114189 # DTB read accesses 46511138Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 76164161 # DTB write accesses 46610535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 46711138Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 159177299 # DTB hits 46811138Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 101051 # DTB misses 46911138Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 159278350 # DTB accesses 47010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 47910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 48710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 49911138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 61250 # Table walker walks requested 50011138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 61250 # Table walker walks initiated with long descriptors 50111138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 499 # Level at which table walker walks with long descriptors terminate 50211138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 55525 # Level at which table walker walks with long descriptors terminate 50311138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 61250 # Table walker wait (enqueue to first request) latency 50411138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 61250 100.00% 100.00% # Table walker wait (enqueue to first request) latency 50511138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 61250 # Table walker wait (enqueue to first request) latency 50611138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 56024 # Table walker service (enqueue to completion) latency 50711138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26762.682065 # Table walker service (enqueue to completion) latency 50811138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992 # Table walker service (enqueue to completion) latency 50911138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128 # Table walker service (enqueue to completion) latency 51011138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 54387 97.08% 97.08% # Table walker service (enqueue to completion) latency 51111138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.07% 97.15% # Table walker service (enqueue to completion) latency 51211138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 1384 2.47% 99.62% # Table walker service (enqueue to completion) latency 51311138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 41 0.07% 99.69% # Table walker service (enqueue to completion) latency 51411138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 72 0.13% 99.82% # Table walker service (enqueue to completion) latency 51511138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 22 0.04% 99.86% # Table walker service (enqueue to completion) latency 51611138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 55 0.10% 99.96% # Table walker service (enqueue to completion) latency 51711138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 51811138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 51911138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 52011138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52111138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52211138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 56024 # Table walker service (enqueue to completion) latency 52311138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 1978837204 # Table walker pending requests distribution 52411138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 1978837204 100.00% 100.00% # Table walker pending requests distribution 52511138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 1978837204 # Table walker pending requests distribution 52611138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 55525 99.11% 99.11% # Table walker page sizes translated 52711138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 499 0.89% 100.00% # Table walker page sizes translated 52811138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 56024 # Table walker page sizes translated 52910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53011138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61250 # Table walker requests started/completed, data/inst 53111138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61250 # Table walker requests started/completed, data/inst 53210628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53311138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56024 # Table walker requests started/completed, data/inst 53411138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56024 # Table walker requests started/completed, data/inst 53511138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 117274 # Table walker requests started/completed, data/inst 53611138Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 441205116 # ITB inst hits 53711138Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 61250 # ITB inst misses 53810535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 53910535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 54010535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 54110535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 54210535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 54310535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54411138Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 54511138Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 54611138Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 26202 # Number of entries that have been flushed from TLB 54710535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54810535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 54910535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55010535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 55110535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 55210535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 55311138Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 441266366 # ITB inst accesses 55411138Sandreas.hansson@arm.comsystem.cpu0.itb.hits 441205116 # DTB hits 55511138Sandreas.hansson@arm.comsystem.cpu0.itb.misses 61250 # DTB misses 55611138Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 441266366 # DTB accesses 55711138Sandreas.hansson@arm.comsystem.cpu0.numCycles 94949400739 # number of cpu cycles simulated 55810535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 55910535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56011167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 56111167Sjthestness@gmail.comsystem.cpu0.kern.inst.quiesce 5268 # number of quiesce instructions executed 56211138Sandreas.hansson@arm.comsystem.cpu0.committedInsts 440958495 # Number of instructions committed 56311138Sandreas.hansson@arm.comsystem.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed 56411138Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses 56511138Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 531836 # Number of float alu accesses 56611138Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 26928397 # number of times a function call or return occured 56711138Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 66358328 # number of instructions that are conditional controls 56811138Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 478066113 # number of integer instructions 56911138Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 531836 # number of float instructions 57011138Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 691558601 # number of times the integer registers were read 57111138Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 378884875 # number of times the integer registers were written 57211138Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 853461 # number of times the floating registers were read 57311138Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 460304 # number of times the floating registers were written 57411138Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 113354931 # number of times the CC registers were read 57511138Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 113143261 # number of times the CC registers were written 57611138Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 159167445 # number of memory refs 57711138Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 83034076 # Number of load instructions 57811138Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 76133369 # Number of store instructions 57911138Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93735186324.296036 # Number of idle cycles 58011138Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1214214414.703974 # Number of busy cycles 58111138Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.012788 # Percentage of non-idle cycles 58211138Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.987212 # Percentage of idle cycles 58311138Sandreas.hansson@arm.comsystem.cpu0.Branches 98314010 # Number of branches fetched 58410944Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 58511138Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 359396375 69.13% 69.13% # Class of executed instruction 58611138Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1169846 0.23% 69.36% # Class of executed instruction 58711138Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 59621 0.01% 69.37% # Class of executed instruction 58811138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction 58911138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction 59011138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction 59111138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction 59211138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction 59311138Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction 59411138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction 59511138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction 59611138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction 59711138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction 59811138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction 59911138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction 60011138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction 60111138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction 60211138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction 60311138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction 60411138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction 60511138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction 60611138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction 60711138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction 60811138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.37% # Class of executed instruction 60911138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction 61011138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 75402 0.01% 69.38% # Class of executed instruction 61111138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction 61211138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction 61311138Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction 61411138Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 83034076 15.97% 85.36% # Class of executed instruction 61511138Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Class of executed instruction 61610535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 61710535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 61811138Sandreas.hansson@arm.comsystem.cpu0.op_class::total 519868732 # Class of executed instruction 61911138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5565465 # number of replacements 62011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use 62111138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks. 62211138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5565977 # Sample count of references to valid blocks. 62311138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.554484 # Average number of references to valid blocks. 62411138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 6293402000 # Cycle when the warmup percentage was hit. 62511138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 503.695844 # Average occupied blocks per requestor 62611138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.983781 # Average percentage of cache occupancy 62711138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.983781 # Average percentage of cache occupancy 62810892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 62911138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 63011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 429 # Occupied blocks per task id 63111138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 63210892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63311138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 323920102 # Number of tag accesses 63411138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 323920102 # Number of data accesses 63511138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 77284320 # number of ReadReq hits 63611138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 77284320 # number of ReadReq hits 63711138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 71935312 # number of WriteReq hits 63811138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 71935312 # number of WriteReq hits 63911138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 189585 # number of SoftPFReq hits 64011138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 189585 # number of SoftPFReq hits 64111138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 125588 # number of WriteLineReq hits 64211138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 125588 # number of WriteLineReq hits 64311138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1730584 # number of LoadLockedReq hits 64411138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1730584 # number of LoadLockedReq hits 64511138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1699772 # number of StoreCondReq hits 64611138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1699772 # number of StoreCondReq hits 64711138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 149219632 # number of demand (read+write) hits 64811138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 149219632 # number of demand (read+write) hits 64911138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 149409217 # number of overall hits 65011138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 149409217 # number of overall hits 65111138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3014242 # number of ReadReq misses 65211138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3014242 # number of ReadReq misses 65311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1370827 # number of WriteReq misses 65411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1370827 # number of WriteReq misses 65511138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 635540 # number of SoftPFReq misses 65611138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 635540 # number of SoftPFReq misses 65711138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 782263 # number of WriteLineReq misses 65811138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 782263 # number of WriteLineReq misses 65911138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168057 # number of LoadLockedReq misses 66011138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 168057 # number of LoadLockedReq misses 66111138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 197269 # number of StoreCondReq misses 66211138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 197269 # number of StoreCondReq misses 66311138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4385069 # number of demand (read+write) misses 66411138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4385069 # number of demand (read+write) misses 66511138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5020609 # number of overall misses 66611138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5020609 # number of overall misses 66711138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52298763500 # number of ReadReq miss cycles 66811138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52298763500 # number of ReadReq miss cycles 66911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33070874000 # number of WriteReq miss cycles 67011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 33070874000 # number of WriteReq miss cycles 67111138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65701301500 # number of WriteLineReq miss cycles 67211138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 65701301500 # number of WriteLineReq miss cycles 67311138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2847254500 # number of LoadLockedReq miss cycles 67411138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2847254500 # number of LoadLockedReq miss cycles 67511138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4866222000 # number of StoreCondReq miss cycles 67611138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4866222000 # number of StoreCondReq miss cycles 67711138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3481500 # number of StoreCondFailReq miss cycles 67811138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 3481500 # number of StoreCondFailReq miss cycles 67911138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 85369637500 # number of demand (read+write) miss cycles 68011138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 85369637500 # number of demand (read+write) miss cycles 68111138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 85369637500 # number of overall miss cycles 68211138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 85369637500 # number of overall miss cycles 68311138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 80298562 # number of ReadReq accesses(hits+misses) 68411138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 80298562 # number of ReadReq accesses(hits+misses) 68511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 73306139 # number of WriteReq accesses(hits+misses) 68611138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 73306139 # number of WriteReq accesses(hits+misses) 68711138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825125 # number of SoftPFReq accesses(hits+misses) 68811138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 825125 # number of SoftPFReq accesses(hits+misses) 68911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 907851 # number of WriteLineReq accesses(hits+misses) 69011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 907851 # number of WriteLineReq accesses(hits+misses) 69111138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898641 # number of LoadLockedReq accesses(hits+misses) 69211138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1898641 # number of LoadLockedReq accesses(hits+misses) 69311138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897041 # number of StoreCondReq accesses(hits+misses) 69411138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1897041 # number of StoreCondReq accesses(hits+misses) 69511138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 153604701 # number of demand (read+write) accesses 69611138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 153604701 # number of demand (read+write) accesses 69711138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 154429826 # number of overall (read+write) accesses 69811138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 154429826 # number of overall (read+write) accesses 69911138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037538 # miss rate for ReadReq accesses 70011138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037538 # miss rate for ReadReq accesses 70111138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018700 # miss rate for WriteReq accesses 70211138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018700 # miss rate for WriteReq accesses 70311138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770235 # miss rate for SoftPFReq accesses 70411138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.770235 # miss rate for SoftPFReq accesses 70511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.861665 # miss rate for WriteLineReq accesses 70611138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.861665 # miss rate for WriteLineReq accesses 70711138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088514 # miss rate for LoadLockedReq accesses 70811138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088514 # miss rate for LoadLockedReq accesses 70911138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103988 # miss rate for StoreCondReq accesses 71011138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.103988 # miss rate for StoreCondReq accesses 71111138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.028548 # miss rate for demand accesses 71211138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.028548 # miss rate for demand accesses 71311138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032511 # miss rate for overall accesses 71411138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032511 # miss rate for overall accesses 71511138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311 # average ReadReq miss latency 71611138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311 # average ReadReq miss latency 71711138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184 # average WriteReq miss latency 71811138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184 # average WriteReq miss latency 71911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731 # average WriteLineReq miss latency 72011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731 # average WriteLineReq miss latency 72111138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208 # average LoadLockedReq miss latency 72211138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208 # average LoadLockedReq miss latency 72311138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869 # average StoreCondReq miss latency 72411138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869 # average StoreCondReq miss latency 72510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 72610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 72711138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091 # average overall miss latency 72811138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19468.254091 # average overall miss latency 72911138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068 # average overall miss latency 73011138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17003.841068 # average overall miss latency 73110535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73210535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73310535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 73410535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 73510535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73710585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 73810535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 73911138Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3771246 # number of writebacks 74011138Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3771246 # number of writebacks 74111138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 38597 # number of ReadReq MSHR hits 74211138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 38597 # number of ReadReq MSHR hits 74311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21414 # number of WriteReq MSHR hits 74411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21414 # number of WriteReq MSHR hits 74511138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46766 # number of LoadLockedReq MSHR hits 74611138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 46766 # number of LoadLockedReq MSHR hits 74711138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 60011 # number of demand (read+write) MSHR hits 74811138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 60011 # number of demand (read+write) MSHR hits 74911138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 60011 # number of overall MSHR hits 75011138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 60011 # number of overall MSHR hits 75111138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2975645 # number of ReadReq MSHR misses 75211138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2975645 # number of ReadReq MSHR misses 75311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1349413 # number of WriteReq MSHR misses 75411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1349413 # number of WriteReq MSHR misses 75511138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 629920 # number of SoftPFReq MSHR misses 75611138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 629920 # number of SoftPFReq MSHR misses 75711138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 782263 # number of WriteLineReq MSHR misses 75811138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 782263 # number of WriteLineReq MSHR misses 75911138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121291 # number of LoadLockedReq MSHR misses 76011138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 121291 # number of LoadLockedReq MSHR misses 76111138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197269 # number of StoreCondReq MSHR misses 76211138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 197269 # number of StoreCondReq MSHR misses 76311138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4325058 # number of demand (read+write) MSHR misses 76411138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4325058 # number of demand (read+write) MSHR misses 76511138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4954978 # number of overall MSHR misses 76611138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4954978 # number of overall MSHR misses 76711138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable 76811138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 17296 # number of ReadReq MSHR uncacheable 76911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable 77011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable 77111138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses 77211138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 35915 # number of overall MSHR uncacheable misses 77311138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46589316500 # number of ReadReq MSHR miss cycles 77411138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 46589316500 # number of ReadReq MSHR miss cycles 77511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30941514500 # number of WriteReq MSHR miss cycles 77611138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 30941514500 # number of WriteReq MSHR miss cycles 77711138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17872150500 # number of SoftPFReq MSHR miss cycles 77811138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17872150500 # number of SoftPFReq MSHR miss cycles 77911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64919038500 # number of WriteLineReq MSHR miss cycles 78011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64919038500 # number of WriteLineReq MSHR miss cycles 78111138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795061500 # number of LoadLockedReq MSHR miss cycles 78211138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795061500 # number of LoadLockedReq MSHR miss cycles 78311138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4668993000 # number of StoreCondReq MSHR miss cycles 78411138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4668993000 # number of StoreCondReq MSHR miss cycles 78511138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles 78611138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles 78711138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77530831000 # number of demand (read+write) MSHR miss cycles 78811138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 77530831000 # number of demand (read+write) MSHR miss cycles 78911138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 95402981500 # number of overall MSHR miss cycles 79011138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 95402981500 # number of overall MSHR miss cycles 79111138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2879350000 # number of ReadReq MSHR uncacheable cycles 79211138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2879350000 # number of ReadReq MSHR uncacheable cycles 79311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3091479000 # number of WriteReq MSHR uncacheable cycles 79411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3091479000 # number of WriteReq MSHR uncacheable cycles 79511138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5970829000 # number of overall MSHR uncacheable cycles 79611138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5970829000 # number of overall MSHR uncacheable cycles 79711138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037057 # mshr miss rate for ReadReq accesses 79811138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037057 # mshr miss rate for ReadReq accesses 79911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018408 # mshr miss rate for WriteReq accesses 80011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018408 # mshr miss rate for WriteReq accesses 80111138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763424 # mshr miss rate for SoftPFReq accesses 80211138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763424 # mshr miss rate for SoftPFReq accesses 80311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.861665 # mshr miss rate for WriteLineReq accesses 80411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.861665 # mshr miss rate for WriteLineReq accesses 80511138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063883 # mshr miss rate for LoadLockedReq accesses 80611138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063883 # mshr miss rate for LoadLockedReq accesses 80711138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103988 # mshr miss rate for StoreCondReq accesses 80811138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103988 # mshr miss rate for StoreCondReq accesses 80911138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028157 # mshr miss rate for demand accesses 81011138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028157 # mshr miss rate for demand accesses 81111138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032086 # mshr miss rate for overall accesses 81211138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.032086 # mshr miss rate for overall accesses 81311138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937 # average ReadReq mshr miss latency 81411138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937 # average ReadReq mshr miss latency 81511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505 # average WriteReq mshr miss latency 81611138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505 # average WriteReq mshr miss latency 81711138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663 # average SoftPFReq mshr miss latency 81811138Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663 # average SoftPFReq mshr miss latency 81911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731 # average WriteLineReq mshr miss latency 82011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731 # average WriteLineReq mshr miss latency 82111138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518 # average LoadLockedReq mshr miss latency 82211138Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518 # average LoadLockedReq mshr miss latency 82311138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638 # average StoreCondReq mshr miss latency 82411138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638 # average StoreCondReq mshr miss latency 82510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 82610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 82711138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305 # average overall mshr miss latency 82811138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305 # average overall mshr miss latency 82911138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718 # average overall mshr miss latency 83011138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718 # average overall mshr miss latency 83111138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493 # average ReadReq mshr uncacheable latency 83211138Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493 # average ReadReq mshr uncacheable latency 83311138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719 # average WriteReq mshr uncacheable latency 83411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719 # average WriteReq mshr uncacheable latency 83511138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220 # average overall mshr uncacheable latency 83611138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220 # average overall mshr uncacheable latency 83710535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 83811138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5319178 # number of replacements 83911138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.824621 # Cycle average of tags in use 84011138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 435885421 # Total number of references to valid blocks. 84111138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5319690 # Sample count of references to valid blocks. 84211138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 81.938124 # Average number of references to valid blocks. 84311138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 59948153000 # Cycle when the warmup percentage was hit. 84411138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.824621 # Average occupied blocks per requestor 84511138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999657 # Average percentage of cache occupancy 84611138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999657 # Average percentage of cache occupancy 84710535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84811138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 84911138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 85011138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 85110535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85211138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 887729927 # Number of tag accesses 85311138Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 887729927 # Number of data accesses 85411138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 435885421 # number of ReadReq hits 85511138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 435885421 # number of ReadReq hits 85611138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 435885421 # number of demand (read+write) hits 85711138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 435885421 # number of demand (read+write) hits 85811138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 435885421 # number of overall hits 85911138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 435885421 # number of overall hits 86011138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5319695 # number of ReadReq misses 86111138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5319695 # number of ReadReq misses 86211138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5319695 # number of demand (read+write) misses 86311138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5319695 # number of demand (read+write) misses 86411138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5319695 # number of overall misses 86511138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5319695 # number of overall misses 86611138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 59521353000 # number of ReadReq miss cycles 86711138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 59521353000 # number of ReadReq miss cycles 86811138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 59521353000 # number of demand (read+write) miss cycles 86911138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 59521353000 # number of demand (read+write) miss cycles 87011138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 59521353000 # number of overall miss cycles 87111138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 59521353000 # number of overall miss cycles 87211138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 441205116 # number of ReadReq accesses(hits+misses) 87311138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 441205116 # number of ReadReq accesses(hits+misses) 87411138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 441205116 # number of demand (read+write) accesses 87511138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 441205116 # number of demand (read+write) accesses 87611138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 441205116 # number of overall (read+write) accesses 87711138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 441205116 # number of overall (read+write) accesses 87811138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012057 # miss rate for ReadReq accesses 87911138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.012057 # miss rate for ReadReq accesses 88011138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.012057 # miss rate for demand accesses 88111138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.012057 # miss rate for demand accesses 88211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.012057 # miss rate for overall accesses 88311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.012057 # miss rate for overall accesses 88411138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715 # average ReadReq miss latency 88511138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715 # average ReadReq miss latency 88611138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency 88711138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11188.865715 # average overall miss latency 88811138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency 88911138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11188.865715 # average overall miss latency 89010535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89110535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89210535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89310535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 89410535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89510535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89610535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 89710535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 89811138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5319695 # number of ReadReq MSHR misses 89911138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 5319695 # number of ReadReq MSHR misses 90011138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 5319695 # number of demand (read+write) MSHR misses 90111138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 5319695 # number of demand (read+write) MSHR misses 90211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 5319695 # number of overall MSHR misses 90311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 5319695 # number of overall MSHR misses 90410827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 90510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 90610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 90710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 90811138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 56861505500 # number of ReadReq MSHR miss cycles 90911138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 56861505500 # number of ReadReq MSHR miss cycles 91011138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 56861505500 # number of demand (read+write) MSHR miss cycles 91111138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 56861505500 # number of demand (read+write) MSHR miss cycles 91211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 56861505500 # number of overall MSHR miss cycles 91311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 56861505500 # number of overall MSHR miss cycles 91411138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of ReadReq MSHR uncacheable cycles 91511138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5953877000 # number of ReadReq MSHR uncacheable cycles 91611138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of overall MSHR uncacheable cycles 91711138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5953877000 # number of overall MSHR uncacheable cycles 91811138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for ReadReq accesses 91911138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012057 # mshr miss rate for ReadReq accesses 92011138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for demand accesses 92111138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.012057 # mshr miss rate for demand accesses 92211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for overall accesses 92311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.012057 # mshr miss rate for overall accesses 92411138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average ReadReq mshr miss latency 92511138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715 # average ReadReq mshr miss latency 92611138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency 92711138Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency 92811138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency 92911138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency 93011138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average ReadReq mshr uncacheable latency 93111138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942 # average ReadReq mshr uncacheable latency 93211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average overall mshr uncacheable latency 93311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942 # average overall mshr uncacheable latency 93410535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 93511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7344223 # number of hwpf issued 93611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7344239 # number of prefetch candidates identified 93711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 93810628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 93910628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 976449 # number of prefetches not generated due to page crossing 94111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2329725 # number of replacements 94211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16186.065873 # Cycle average of tags in use 94311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 18053337 # Total number of references to valid blocks. 94411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2345760 # Sample count of references to valid blocks. 94511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 7.696157 # Average number of references to valid blocks. 94611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 55834398000 # Cycle when the warmup percentage was hit. 94711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 6981.301122 # Average occupied blocks per requestor 94811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.056568 # Average occupied blocks per requestor 94911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 81.620115 # Average occupied blocks per requestor 95011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4075.206909 # Average occupied blocks per requestor 95111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 4054.876060 # Average occupied blocks per requestor 95211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 929.005098 # Average occupied blocks per requestor 95311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.426105 # Average percentage of cache occupancy 95411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003910 # Average percentage of cache occupancy 95511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004982 # Average percentage of cache occupancy 95611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.248731 # Average percentage of cache occupancy 95711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.247490 # Average percentage of cache occupancy 95811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056702 # Average percentage of cache occupancy 95911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.987919 # Average percentage of cache occupancy 96011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id 96111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 96211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14643 # Occupied blocks per task id 96311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 96411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id 96511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id 96611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id 96711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id 96811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 96911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 97011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 97111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 806 # Occupied blocks per task id 97211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4474 # Occupied blocks per task id 97311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5446 # Occupied blocks per task id 97411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3835 # Occupied blocks per task id 97511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082092 # Percentage of cache occupancy per task id 97611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id 97711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.893738 # Percentage of cache occupancy per task id 97811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 367456425 # Number of tag accesses 97911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 367456425 # Number of data accesses 98011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 210868 # number of ReadReq hits 98111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 144785 # number of ReadReq hits 98211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 355653 # number of ReadReq hits 98311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3771244 # number of Writeback hits 98411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3771244 # number of Writeback hits 98511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 99488 # number of UpgradeReq hits 98611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 99488 # number of UpgradeReq hits 98711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31647 # number of SCUpgradeReq hits 98811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 31647 # number of SCUpgradeReq hits 98911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 896733 # number of ReadExReq hits 99011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 896733 # number of ReadExReq hits 99111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4806679 # number of ReadCleanReq hits 99211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4806679 # number of ReadCleanReq hits 99311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2773726 # number of ReadSharedReq hits 99411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2773726 # number of ReadSharedReq hits 99511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 232290 # number of InvalidateReq hits 99611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 232290 # number of InvalidateReq hits 99711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 210868 # number of demand (read+write) hits 99811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 144785 # number of demand (read+write) hits 99911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4806679 # number of demand (read+write) hits 100011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3670459 # number of demand (read+write) hits 100111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8832791 # number of demand (read+write) hits 100211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 210868 # number of overall hits 100311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 144785 # number of overall hits 100411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4806679 # number of overall hits 100511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3670459 # number of overall hits 100611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8832791 # number of overall hits 100711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10391 # number of ReadReq misses 100811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9054 # number of ReadReq misses 100911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 19445 # number of ReadReq misses 101011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121662 # number of UpgradeReq misses 101111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 121662 # number of UpgradeReq misses 101211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 165610 # number of SCUpgradeReq misses 101311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 165610 # number of SCUpgradeReq misses 101411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses 101511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses 101611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 248725 # number of ReadExReq misses 101711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 248725 # number of ReadExReq misses 101811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 513016 # number of ReadCleanReq misses 101911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 513016 # number of ReadCleanReq misses 102011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953130 # number of ReadSharedReq misses 102111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 953130 # number of ReadSharedReq misses 102211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 548738 # number of InvalidateReq misses 102311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 548738 # number of InvalidateReq misses 102411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10391 # number of demand (read+write) misses 102511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 9054 # number of demand (read+write) misses 102611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 513016 # number of demand (read+write) misses 102711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1201855 # number of demand (read+write) misses 102811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1734316 # number of demand (read+write) misses 102911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10391 # number of overall misses 103011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 9054 # number of overall misses 103111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 513016 # number of overall misses 103211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1201855 # number of overall misses 103311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1734316 # number of overall misses 103411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 495108500 # number of ReadReq miss cycles 103511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 493404500 # number of ReadReq miss cycles 103611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 988513000 # number of ReadReq miss cycles 103711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3820404000 # number of UpgradeReq miss cycles 103811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3820404000 # number of UpgradeReq miss cycles 103911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3956624500 # number of SCUpgradeReq miss cycles 104011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3956624500 # number of SCUpgradeReq miss cycles 104111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3380498 # number of SCUpgradeFailReq miss cycles 104211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3380498 # number of SCUpgradeFailReq miss cycles 104311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16864079500 # number of ReadExReq miss cycles 104411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 16864079500 # number of ReadExReq miss cycles 104511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20224946500 # number of ReadCleanReq miss cycles 104611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 20224946500 # number of ReadCleanReq miss cycles 104711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 42635415000 # number of ReadSharedReq miss cycles 104811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 42635415000 # number of ReadSharedReq miss cycles 104911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62221144000 # number of InvalidateReq miss cycles 105011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 62221144000 # number of InvalidateReq miss cycles 105111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 495108500 # number of demand (read+write) miss cycles 105211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 493404500 # number of demand (read+write) miss cycles 105311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 20224946500 # number of demand (read+write) miss cycles 105411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 59499494500 # number of demand (read+write) miss cycles 105511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 80712954000 # number of demand (read+write) miss cycles 105611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 495108500 # number of overall miss cycles 105711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 493404500 # number of overall miss cycles 105811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 20224946500 # number of overall miss cycles 105911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 59499494500 # number of overall miss cycles 106011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 80712954000 # number of overall miss cycles 106111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221259 # number of ReadReq accesses(hits+misses) 106211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 153839 # number of ReadReq accesses(hits+misses) 106311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 375098 # number of ReadReq accesses(hits+misses) 106411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3771244 # number of Writeback accesses(hits+misses) 106511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3771244 # number of Writeback accesses(hits+misses) 106611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 221150 # number of UpgradeReq accesses(hits+misses) 106711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 221150 # number of UpgradeReq accesses(hits+misses) 106811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197257 # number of SCUpgradeReq accesses(hits+misses) 106911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 197257 # number of SCUpgradeReq accesses(hits+misses) 107011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses) 107111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) 107211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1145458 # number of ReadExReq accesses(hits+misses) 107311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1145458 # number of ReadExReq accesses(hits+misses) 107411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5319695 # number of ReadCleanReq accesses(hits+misses) 107511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5319695 # number of ReadCleanReq accesses(hits+misses) 107611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3726856 # number of ReadSharedReq accesses(hits+misses) 107711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3726856 # number of ReadSharedReq accesses(hits+misses) 107811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 781028 # number of InvalidateReq accesses(hits+misses) 107911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 781028 # number of InvalidateReq accesses(hits+misses) 108011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221259 # number of demand (read+write) accesses 108111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 153839 # number of demand (read+write) accesses 108211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5319695 # number of demand (read+write) accesses 108311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4872314 # number of demand (read+write) accesses 108411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 10567107 # number of demand (read+write) accesses 108511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221259 # number of overall (read+write) accesses 108611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 153839 # number of overall (read+write) accesses 108711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5319695 # number of overall (read+write) accesses 108811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4872314 # number of overall (read+write) accesses 108911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 10567107 # number of overall (read+write) accesses 109011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for ReadReq accesses 109111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058854 # miss rate for ReadReq accesses 109211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.051840 # miss rate for ReadReq accesses 109311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550133 # miss rate for UpgradeReq accesses 109411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550133 # miss rate for UpgradeReq accesses 109511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.839565 # miss rate for SCUpgradeReq accesses 109611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.839565 # miss rate for SCUpgradeReq accesses 109710535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 109810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 109911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217140 # miss rate for ReadExReq accesses 110011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.217140 # miss rate for ReadExReq accesses 110111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096437 # miss rate for ReadCleanReq accesses 110211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096437 # miss rate for ReadCleanReq accesses 110311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255746 # miss rate for ReadSharedReq accesses 110411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255746 # miss rate for ReadSharedReq accesses 110511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.702584 # miss rate for InvalidateReq accesses 110611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.702584 # miss rate for InvalidateReq accesses 110711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for demand accesses 110811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058854 # miss rate for demand accesses 110911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096437 # miss rate for demand accesses 111011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246670 # miss rate for demand accesses 111111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.164124 # miss rate for demand accesses 111211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for overall accesses 111311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058854 # miss rate for overall accesses 111411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096437 # miss rate for overall accesses 111511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246670 # miss rate for overall accesses 111611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.164124 # miss rate for overall accesses 111711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average ReadReq miss latency 111811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54495.747736 # average ReadReq miss latency 111911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 50836.358961 # average ReadReq miss latency 112011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31401.785274 # average UpgradeReq miss latency 112111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31401.785274 # average UpgradeReq miss latency 112211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23891.217318 # average SCUpgradeReq miss latency 112311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23891.217318 # average SCUpgradeReq miss latency 112411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 281708.166667 # average SCUpgradeFailReq miss latency 112511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 281708.166667 # average SCUpgradeFailReq miss latency 112611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67802.108755 # average ReadExReq miss latency 112711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67802.108755 # average ReadExReq miss latency 112811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39423.617392 # average ReadCleanReq miss latency 112911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39423.617392 # average ReadCleanReq miss latency 113011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44732.004029 # average ReadSharedReq miss latency 113111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44732.004029 # average ReadSharedReq miss latency 113211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113389.530158 # average InvalidateReq miss latency 113311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113389.530158 # average InvalidateReq miss latency 113411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency 113511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency 113611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency 113711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency 113811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 46538.781860 # average overall miss latency 113911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency 114011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency 114111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency 114211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency 114311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 46538.781860 # average overall miss latency 114410628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114510535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114610628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 114710535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 114810628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 114910535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 115010535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 115110535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 115211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1299353 # number of writebacks 115311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1299353 # number of writebacks 115411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4520 # number of ReadExReq MSHR hits 115511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 4520 # number of ReadExReq MSHR hits 115611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 530 # number of ReadSharedReq MSHR hits 115711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 530 # number of ReadSharedReq MSHR hits 115811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5050 # number of demand (read+write) MSHR hits 115911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5050 # number of demand (read+write) MSHR hits 116011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5050 # number of overall MSHR hits 116111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5050 # number of overall MSHR hits 116211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10391 # number of ReadReq MSHR misses 116311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9054 # number of ReadReq MSHR misses 116411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 19445 # number of ReadReq MSHR misses 116511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 93813 # number of CleanEvict MSHR misses 116611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::total 93813 # number of CleanEvict MSHR misses 116711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of HardPFReq MSHR misses 116811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 630880 # number of HardPFReq MSHR misses 116911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121662 # number of UpgradeReq MSHR misses 117011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 121662 # number of UpgradeReq MSHR misses 117111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 165610 # number of SCUpgradeReq MSHR misses 117211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 165610 # number of SCUpgradeReq MSHR misses 117311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 12 # number of SCUpgradeFailReq MSHR misses 117411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 12 # number of SCUpgradeFailReq MSHR misses 117511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 244205 # number of ReadExReq MSHR misses 117611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 244205 # number of ReadExReq MSHR misses 117711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 513016 # number of ReadCleanReq MSHR misses 117811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 513016 # number of ReadCleanReq MSHR misses 117911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 952600 # number of ReadSharedReq MSHR misses 118011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 952600 # number of ReadSharedReq MSHR misses 118111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 548738 # number of InvalidateReq MSHR misses 118211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 548738 # number of InvalidateReq MSHR misses 118311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10391 # number of demand (read+write) MSHR misses 118411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9054 # number of demand (read+write) MSHR misses 118511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 513016 # number of demand (read+write) MSHR misses 118611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1196805 # number of demand (read+write) MSHR misses 118711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1729266 # number of demand (read+write) MSHR misses 118811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10391 # number of overall MSHR misses 118911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9054 # number of overall MSHR misses 119011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 513016 # number of overall MSHR misses 119111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1196805 # number of overall MSHR misses 119211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of overall MSHR misses 119311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2360146 # number of overall MSHR misses 119410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 119511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable 119611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 60421 # number of ReadReq MSHR uncacheable 119711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable 119811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable 119910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 120011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses 120111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 79040 # number of overall MSHR uncacheable misses 120211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of ReadReq MSHR miss cycles 120311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 439080500 # number of ReadReq MSHR miss cycles 120411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 871843000 # number of ReadReq MSHR miss cycles 120511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of HardPFReq MSHR miss cycles 120611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35559655965 # number of HardPFReq MSHR miss cycles 120711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4486256000 # number of UpgradeReq MSHR miss cycles 120811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4486256000 # number of UpgradeReq MSHR miss cycles 120911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3173949000 # number of SCUpgradeReq MSHR miss cycles 121011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3173949000 # number of SCUpgradeReq MSHR miss cycles 121111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3140498 # number of SCUpgradeFailReq MSHR miss cycles 121211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3140498 # number of SCUpgradeFailReq MSHR miss cycles 121311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14883734000 # number of ReadExReq MSHR miss cycles 121411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14883734000 # number of ReadExReq MSHR miss cycles 121511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17146850500 # number of ReadCleanReq MSHR miss cycles 121611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17146850500 # number of ReadCleanReq MSHR miss cycles 121711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36873595000 # number of ReadSharedReq MSHR miss cycles 121811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36873595000 # number of ReadSharedReq MSHR miss cycles 121911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58928716000 # number of InvalidateReq MSHR miss cycles 122011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58928716000 # number of InvalidateReq MSHR miss cycles 122111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of demand (read+write) MSHR miss cycles 122211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 439080500 # number of demand (read+write) MSHR miss cycles 122311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17146850500 # number of demand (read+write) MSHR miss cycles 122411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51757329000 # number of demand (read+write) MSHR miss cycles 122511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 69776022500 # number of demand (read+write) MSHR miss cycles 122611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of overall MSHR miss cycles 122711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 439080500 # number of overall MSHR miss cycles 122811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17146850500 # number of overall MSHR miss cycles 122911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51757329000 # number of overall MSHR miss cycles 123011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of overall MSHR miss cycles 123111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 105335678465 # number of overall MSHR miss cycles 123211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of ReadReq MSHR uncacheable cycles 123311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2740982000 # number of ReadReq MSHR uncacheable cycles 123411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8371421500 # number of ReadReq MSHR uncacheable cycles 123511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2951836500 # number of WriteReq MSHR uncacheable cycles 123611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2951836500 # number of WriteReq MSHR uncacheable cycles 123711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of overall MSHR uncacheable cycles 123811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5692818500 # number of overall MSHR uncacheable cycles 123911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11323258000 # number of overall MSHR uncacheable cycles 124011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for ReadReq accesses 124111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for ReadReq accesses 124211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.051840 # mshr miss rate for ReadReq accesses 124310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 124410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 124510535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 124610535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 124711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550133 # mshr miss rate for UpgradeReq accesses 124811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550133 # mshr miss rate for UpgradeReq accesses 124911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.839565 # mshr miss rate for SCUpgradeReq accesses 125011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839565 # mshr miss rate for SCUpgradeReq accesses 125110535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 125210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 125311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213194 # mshr miss rate for ReadExReq accesses 125411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213194 # mshr miss rate for ReadExReq accesses 125511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for ReadCleanReq accesses 125611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096437 # mshr miss rate for ReadCleanReq accesses 125711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255604 # mshr miss rate for ReadSharedReq accesses 125811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255604 # mshr miss rate for ReadSharedReq accesses 125911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.702584 # mshr miss rate for InvalidateReq accesses 126011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.702584 # mshr miss rate for InvalidateReq accesses 126111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for demand accesses 126211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for demand accesses 126311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for demand accesses 126411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for demand accesses 126511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.163646 # mshr miss rate for demand accesses 126611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for overall accesses 126711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for overall accesses 126811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for overall accesses 126911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for overall accesses 127010535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 127111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.223348 # mshr miss rate for overall accesses 127211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average ReadReq mshr miss latency 127311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average ReadReq mshr miss latency 127411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961 # average ReadReq mshr miss latency 127511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average HardPFReq mshr miss latency 127611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062 # average HardPFReq mshr miss latency 127711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360 # average UpgradeReq mshr miss latency 127811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360 # average UpgradeReq mshr miss latency 127911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377 # average SCUpgradeReq mshr miss latency 128011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377 # average SCUpgradeReq mshr miss latency 128111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667 # average SCUpgradeFailReq mshr miss latency 128211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667 # average SCUpgradeFailReq mshr miss latency 128311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773 # average ReadExReq mshr miss latency 128411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773 # average ReadExReq mshr miss latency 128511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average ReadCleanReq mshr miss latency 128611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392 # average ReadCleanReq mshr miss latency 128711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824 # average ReadSharedReq mshr miss latency 128811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824 # average ReadSharedReq mshr miss latency 128911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158 # average InvalidateReq mshr miss latency 129011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158 # average InvalidateReq mshr miss latency 129111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency 129211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency 129311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency 129411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency 129511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612 # average overall mshr miss latency 129611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency 129711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency 129811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency 129911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency 130011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average overall mshr miss latency 130111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991 # average overall mshr miss latency 130211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average ReadReq mshr uncacheable latency 130311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493 # average ReadReq mshr uncacheable latency 130411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822 # average ReadReq mshr uncacheable latency 130511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719 # average WriteReq mshr uncacheable latency 130611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719 # average WriteReq mshr uncacheable latency 130711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average overall mshr uncacheable latency 130811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464 # average overall mshr uncacheable latency 130911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117 # average overall mshr uncacheable latency 131010535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 131111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 22509328 # Total number of requests made to the snoop filter. 131211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11536373 # Number of requests hitting in the snoop filter with a single holder of the requested data. 131311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 848 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 131411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 485130 # Total number of snoops made to the snoop filter. 131511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 485124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 131611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 131711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 537841 # Transaction distribution 131811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9675681 # Transaction distribution 131911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 18620 # Transaction distribution 132011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 18619 # Transaction distribution 132111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 5107009 # Transaction distribution 132211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 8757288 # Transaction distribution 132311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 798537 # Transaction distribution 132411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 405076 # Transaction distribution 132511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363715 # Transaction distribution 132611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 481157 # Transaction distribution 132711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 40 # Transaction distribution 132811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 132911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1220841 # Transaction distribution 133011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1155337 # Transaction distribution 133111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5319695 # Transaction distribution 133211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4658319 # Transaction distribution 133311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 788798 # Transaction distribution 133411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 781028 # Transaction distribution 133511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16044388 # Packet count per connected master and slave (bytes) 133611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17944373 # Packet count per connected master and slave (bytes) 133711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 336960 # Packet count per connected master and slave (bytes) 133811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 515556 # Packet count per connected master and slave (bytes) 133911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 34841277 # Packet count per connected master and slave (bytes) 134011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 340632980 # Cumulative packet size per connected master and slave (bytes) 134111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 559762054 # Cumulative packet size per connected master and slave (bytes) 134211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1230712 # Cumulative packet size per connected master and slave (bytes) 134311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1770072 # Cumulative packet size per connected master and slave (bytes) 134411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 903395818 # Cumulative packet size per connected master and slave (bytes) 134511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 5410368 # Total snoops (count) 134611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 27976627 # Request fanout histogram 134711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.025738 # Request fanout histogram 134811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.158355 # Request fanout histogram 134910535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 27256564 97.43% 97.43% # Request fanout histogram 135111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 720057 2.57% 100.00% # Request fanout histogram 135211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 135310535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 135411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 135510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 135611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 27976627 # Request fanout histogram 135711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 15196832497 # Layer occupancy (ticks) 135810535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 135911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 183439903 # Layer occupancy (ticks) 136010535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 8022667500 # Layer occupancy (ticks) 136210535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 136311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7935130422 # Layer occupancy (ticks) 136410535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 136511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 183121000 # Layer occupancy (ticks) 136610535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 136711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 294297000 # Layer occupancy (ticks) 136810535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 136910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 137010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 137110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 137210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 137610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 137710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 137810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 137910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 138010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 138110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 138210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 138310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 138410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 139010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 139110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 139310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 139510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 139610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 139710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139811138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 111674 # Table walker walks requested 139911138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 111674 # Table walker walks initiated with long descriptors 140011138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10360 # Level at which table walker walks with long descriptors terminate 140111138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85053 # Level at which table walker walks with long descriptors terminate 140211138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting 140311138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 111653 # Table walker wait (enqueue to first request) latency 140411138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.241821 # Table walker wait (enqueue to first request) latency 140511138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 61.696123 # Table walker wait (enqueue to first request) latency 140611138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-2047 111651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 140711138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 140811138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 140911138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 111653 # Table walker wait (enqueue to first request) latency 141011138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 95434 # Table walker service (enqueue to completion) latency 141111138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778 # Table walker service (enqueue to completion) latency 141211138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562 # Table walker service (enqueue to completion) latency 141311138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011 # Table walker service (enqueue to completion) latency 141411138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 94629 99.16% 99.16% # Table walker service (enqueue to completion) latency 141511138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 150 0.16% 99.31% # Table walker service (enqueue to completion) latency 141611138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 551 0.58% 99.89% # Table walker service (enqueue to completion) latency 141711138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.91% # Table walker service (enqueue to completion) latency 141811138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.95% # Table walker service (enqueue to completion) latency 141911138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 99.96% # Table walker service (enqueue to completion) latency 142011138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 99.98% # Table walker service (enqueue to completion) latency 142111138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 142211138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142411138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 95434 # Table walker service (enqueue to completion) latency 142511138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 10744163364 # Table walker pending requests distribution 142611138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 1.061708 # Table walker pending requests distribution 142711138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -663005280 -6.17% -6.17% # Table walker pending requests distribution 142811138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 11407168644 106.17% 100.00% # Table walker pending requests distribution 142911138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 10744163364 # Table walker pending requests distribution 143011138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 85053 89.14% 89.14% # Table walker page sizes translated 143111138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 10360 10.86% 100.00% # Table walker page sizes translated 143211138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 95413 # Table walker page sizes translated 143311138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 111674 # Table walker requests started/completed, data/inst 143410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143511138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 111674 # Table walker requests started/completed, data/inst 143611138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95413 # Table walker requests started/completed, data/inst 143710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143811138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95413 # Table walker requests started/completed, data/inst 143911138Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 207087 # Table walker requests started/completed, data/inst 144010535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 144110535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 144211138Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 82869257 # DTB read hits 144311138Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 83659 # DTB read misses 144411138Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 74681159 # DTB write hits 144511138Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 28015 # DTB write misses 144610535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 144710535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144811138Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 144911138Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 145011138Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 37721 # Number of entries that have been flushed from TLB 145110535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 145211138Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4459 # Number of TLB faults due to prefetch 145310535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145411138Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10437 # Number of TLB faults due to permissions restrictions 145511138Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 82952916 # DTB read accesses 145611138Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 74709174 # DTB write accesses 145710535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 145811138Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 157550416 # DTB hits 145911138Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 111674 # DTB misses 146011138Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 157662090 # DTB accesses 146110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 146310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 146510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 146710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 146810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 146910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 147010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 147110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 147210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 147310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 147410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 147510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 147610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 147810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 148210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 148310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 148410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 148510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 148610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 148710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 148810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 148910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 149011138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 54727 # Table walker walks requested 149111138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 54727 # Table walker walks initiated with long descriptors 149211138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 669 # Level at which table walker walks with long descriptors terminate 149311138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 48424 # Level at which table walker walks with long descriptors terminate 149411138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 54727 # Table walker wait (enqueue to first request) latency 149511138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 54727 100.00% 100.00% # Table walker wait (enqueue to first request) latency 149611138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 54727 # Table walker wait (enqueue to first request) latency 149711138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 49093 # Table walker service (enqueue to completion) latency 149811138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 23909.080724 # Table walker service (enqueue to completion) latency 149911138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913 # Table walker service (enqueue to completion) latency 150011138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713 # Table walker service (enqueue to completion) latency 150111138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 48315 98.42% 98.42% # Table walker service (enqueue to completion) latency 150211138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 33 0.07% 98.48% # Table walker service (enqueue to completion) latency 150311138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 627 1.28% 99.76% # Table walker service (enqueue to completion) latency 150411138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 24 0.05% 99.81% # Table walker service (enqueue to completion) latency 150511138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency 150611138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency 150711138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency 150811138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 150911138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 151011138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 49093 # Table walker service (enqueue to completion) latency 151111138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1309982220 # Table walker pending requests distribution 151211138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1309982220 100.00% 100.00% # Table walker pending requests distribution 151311138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1309982220 # Table walker pending requests distribution 151411138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 48424 98.64% 98.64% # Table walker page sizes translated 151511138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 669 1.36% 100.00% # Table walker page sizes translated 151611138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 49093 # Table walker page sizes translated 151710628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151811138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54727 # Table walker requests started/completed, data/inst 151911138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 54727 # Table walker requests started/completed, data/inst 152010628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 152111138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49093 # Table walker requests started/completed, data/inst 152211138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 49093 # Table walker requests started/completed, data/inst 152311138Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 103820 # Table walker requests started/completed, data/inst 152411138Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 441006552 # ITB inst hits 152511138Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 54727 # ITB inst misses 152610535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 152710535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 152810535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 152910535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 153010535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 153110535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 153211138Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID 153311138Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 153411138Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 26047 # Number of entries that have been flushed from TLB 153510535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153610535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153710535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 153810535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153910535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 154010535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 154111138Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 441061279 # ITB inst accesses 154211138Sandreas.hansson@arm.comsystem.cpu1.itb.hits 441006552 # DTB hits 154311138Sandreas.hansson@arm.comsystem.cpu1.itb.misses 54727 # DTB misses 154411138Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 441061279 # DTB accesses 154511138Sandreas.hansson@arm.comsystem.cpu1.numCycles 94949400719 # number of cpu cycles simulated 154610535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 154710535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 154811167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 154911167Sjthestness@gmail.comsystem.cpu1.kern.inst.quiesce 13508 # number of quiesce instructions executed 155011138Sandreas.hansson@arm.comsystem.cpu1.committedInsts 440696565 # Number of instructions committed 155111138Sandreas.hansson@arm.comsystem.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed 155211138Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses 155311138Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 365483 # Number of float alu accesses 155411138Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 25816030 # number of times a function call or return occured 155511138Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 67531060 # number of instructions that are conditional controls 155611138Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 474820793 # number of integer instructions 155711138Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 365483 # number of float instructions 155811138Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 694878928 # number of times the integer registers were read 155911138Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 377300064 # number of times the integer registers were written 156011138Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 605102 # number of times the floating registers were read 156111138Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 276864 # number of times the floating registers were written 156211138Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 116712375 # number of times the CC registers were read 156311138Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 116303175 # number of times the CC registers were written 156411138Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 157542729 # number of memory refs 156511138Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 82867724 # Number of load instructions 156611138Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 74675005 # Number of store instructions 156711138Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93871458813.181076 # Number of idle cycles 156811138Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1077941905.818921 # Number of busy cycles 156911138Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011353 # Percentage of non-idle cycles 157011138Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988647 # Percentage of idle cycles 157111138Sandreas.hansson@arm.comsystem.cpu1.Branches 98303933 # Number of branches fetched 157210944Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 157311138Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 359137164 69.35% 69.35% # Class of executed instruction 157411138Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1056908 0.20% 69.56% # Class of executed instruction 157511138Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 59454 0.01% 69.57% # Class of executed instruction 157611138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction 157711138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction 157811138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction 157911138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction 158011138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction 158111138Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction 158211138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction 158311138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction 158411138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction 158511138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction 158611138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction 158711138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction 158811138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction 158911138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction 159011138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction 159111138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction 159211138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction 159311138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction 159411138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction 159511138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction 159611138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction 159711138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction 159811138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 36204 0.01% 69.58% # Class of executed instruction 159911138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction 160011138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction 160111138Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction 160211138Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 82867724 16.00% 85.58% # Class of executed instruction 160311138Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Class of executed instruction 160410535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 160510535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 160611138Sandreas.hansson@arm.comsystem.cpu1.op_class::total 517832459 # Class of executed instruction 160711138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5147651 # number of replacements 160811138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use 160911138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks. 161011138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5148159 # Sample count of references to valid blocks. 161111138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.564853 # Average number of references to valid blocks. 161211138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8409197794000 # Cycle when the warmup percentage was hit. 161311138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 420.489425 # Average occupied blocks per requestor 161411138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.821268 # Average percentage of cache occupancy 161511138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.821268 # Average percentage of cache occupancy 161611138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 161711138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 161811138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 161911138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 443 # Occupied blocks per task id 162011138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 162111138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 320234661 # Number of tag accesses 162211138Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 320234661 # Number of data accesses 162311138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 77182580 # number of ReadReq hits 162411138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 77182580 # number of ReadReq hits 162511138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 70763723 # number of WriteReq hits 162611138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 70763723 # number of WriteReq hits 162711138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 181716 # number of SoftPFReq hits 162811138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 181716 # number of SoftPFReq hits 162911138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 197136 # number of WriteLineReq hits 163011138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 197136 # number of WriteLineReq hits 163111138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768276 # number of LoadLockedReq hits 163211138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1768276 # number of LoadLockedReq hits 163311138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1725683 # number of StoreCondReq hits 163411138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1725683 # number of StoreCondReq hits 163511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 147946303 # number of demand (read+write) hits 163611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 147946303 # number of demand (read+write) hits 163711138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 148128019 # number of overall hits 163811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 148128019 # number of overall hits 163911138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2911211 # number of ReadReq misses 164011138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2911211 # number of ReadReq misses 164111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1304261 # number of WriteReq misses 164211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1304261 # number of WriteReq misses 164311138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 646630 # number of SoftPFReq misses 164411138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 646630 # number of SoftPFReq misses 164511138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 461157 # number of WriteLineReq misses 164611138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 461157 # number of WriteLineReq misses 164711138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158092 # number of LoadLockedReq misses 164811138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 158092 # number of LoadLockedReq misses 164911138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 198973 # number of StoreCondReq misses 165011138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 198973 # number of StoreCondReq misses 165111138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4215472 # number of demand (read+write) misses 165211138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4215472 # number of demand (read+write) misses 165311138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 4862102 # number of overall misses 165411138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 4862102 # number of overall misses 165511138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46228111000 # number of ReadReq miss cycles 165611138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 46228111000 # number of ReadReq miss cycles 165711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27445585000 # number of WriteReq miss cycles 165811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 27445585000 # number of WriteReq miss cycles 165911138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22477695000 # number of WriteLineReq miss cycles 166011138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 22477695000 # number of WriteLineReq miss cycles 166111138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2400515000 # number of LoadLockedReq miss cycles 166211138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2400515000 # number of LoadLockedReq miss cycles 166311138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4867748500 # number of StoreCondReq miss cycles 166411138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4867748500 # number of StoreCondReq miss cycles 166511138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2101500 # number of StoreCondFailReq miss cycles 166611138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2101500 # number of StoreCondFailReq miss cycles 166711138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 73673696000 # number of demand (read+write) miss cycles 166811138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 73673696000 # number of demand (read+write) miss cycles 166911138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 73673696000 # number of overall miss cycles 167011138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 73673696000 # number of overall miss cycles 167111138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 80093791 # number of ReadReq accesses(hits+misses) 167211138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 80093791 # number of ReadReq accesses(hits+misses) 167311138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 72067984 # number of WriteReq accesses(hits+misses) 167411138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 72067984 # number of WriteReq accesses(hits+misses) 167511138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828346 # number of SoftPFReq accesses(hits+misses) 167611138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 828346 # number of SoftPFReq accesses(hits+misses) 167711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 658293 # number of WriteLineReq accesses(hits+misses) 167811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 658293 # number of WriteLineReq accesses(hits+misses) 167911138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1926368 # number of LoadLockedReq accesses(hits+misses) 168011138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1926368 # number of LoadLockedReq accesses(hits+misses) 168111138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1924656 # number of StoreCondReq accesses(hits+misses) 168211138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1924656 # number of StoreCondReq accesses(hits+misses) 168311138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 152161775 # number of demand (read+write) accesses 168411138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 152161775 # number of demand (read+write) accesses 168511138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 152990121 # number of overall (read+write) accesses 168611138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 152990121 # number of overall (read+write) accesses 168711138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036348 # miss rate for ReadReq accesses 168811138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036348 # miss rate for ReadReq accesses 168911138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018098 # miss rate for WriteReq accesses 169011138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018098 # miss rate for WriteReq accesses 169111138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780628 # miss rate for SoftPFReq accesses 169211138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.780628 # miss rate for SoftPFReq accesses 169311138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.700535 # miss rate for WriteLineReq accesses 169411138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.700535 # miss rate for WriteLineReq accesses 169511138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082067 # miss rate for LoadLockedReq accesses 169611138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082067 # miss rate for LoadLockedReq accesses 169711138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103381 # miss rate for StoreCondReq accesses 169811138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.103381 # miss rate for StoreCondReq accesses 169911138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027704 # miss rate for demand accesses 170011138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.027704 # miss rate for demand accesses 170111138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031780 # miss rate for overall accesses 170211138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031780 # miss rate for overall accesses 170311138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591 # average ReadReq miss latency 170411138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591 # average ReadReq miss latency 170511138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930 # average WriteReq miss latency 170611138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930 # average WriteReq miss latency 170711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728 # average WriteLineReq miss latency 170811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728 # average WriteLineReq miss latency 170911138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425 # average LoadLockedReq miss latency 171011138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425 # average LoadLockedReq miss latency 171111138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025 # average StoreCondReq miss latency 171211138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025 # average StoreCondReq miss latency 171310535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 171410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 171511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346 # average overall miss latency 171611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17476.974346 # average overall miss latency 171711138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034 # average overall miss latency 171811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15152.643034 # average overall miss latency 171910535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172010535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172110535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172210535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 172310535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172410535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172510585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 172610535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 172711138Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3396408 # number of writebacks 172811138Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3396408 # number of writebacks 172911138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16912 # number of ReadReq MSHR hits 173011138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 16912 # number of ReadReq MSHR hits 173111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 462 # number of WriteReq MSHR hits 173211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 462 # number of WriteReq MSHR hits 173311138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41725 # number of LoadLockedReq MSHR hits 173411138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 41725 # number of LoadLockedReq MSHR hits 173511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 17374 # number of demand (read+write) MSHR hits 173611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 17374 # number of demand (read+write) MSHR hits 173711138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 17374 # number of overall MSHR hits 173811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 17374 # number of overall MSHR hits 173911138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2894299 # number of ReadReq MSHR misses 174011138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2894299 # number of ReadReq MSHR misses 174111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1303799 # number of WriteReq MSHR misses 174211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1303799 # number of WriteReq MSHR misses 174311138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 646630 # number of SoftPFReq MSHR misses 174411138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 646630 # number of SoftPFReq MSHR misses 174511138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 461157 # number of WriteLineReq MSHR misses 174611138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 461157 # number of WriteLineReq MSHR misses 174711138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116367 # number of LoadLockedReq MSHR misses 174811138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 116367 # number of LoadLockedReq MSHR misses 174911138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198973 # number of StoreCondReq MSHR misses 175011138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 198973 # number of StoreCondReq MSHR misses 175111138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4198098 # number of demand (read+write) MSHR misses 175211138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4198098 # number of demand (read+write) MSHR misses 175311138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4844728 # number of overall MSHR misses 175411138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4844728 # number of overall MSHR misses 175511138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable 175611138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 20770 # number of ReadReq MSHR uncacheable 175711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable 175811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable 175911138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses 176011138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 40100 # number of overall MSHR uncacheable misses 176111138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41851387000 # number of ReadReq MSHR miss cycles 176211138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 41851387000 # number of ReadReq MSHR miss cycles 176311138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26109084500 # number of WriteReq MSHR miss cycles 176411138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 26109084500 # number of WriteReq MSHR miss cycles 176511138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14515592000 # number of SoftPFReq MSHR miss cycles 176611138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14515592000 # number of SoftPFReq MSHR miss cycles 176711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 22016538000 # number of WriteLineReq MSHR miss cycles 176811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 22016538000 # number of WriteLineReq MSHR miss cycles 176911138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587242500 # number of LoadLockedReq MSHR miss cycles 177011138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587242500 # number of LoadLockedReq MSHR miss cycles 177111138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4668803500 # number of StoreCondReq MSHR miss cycles 177211138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4668803500 # number of StoreCondReq MSHR miss cycles 177311138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2073500 # number of StoreCondFailReq MSHR miss cycles 177411138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2073500 # number of StoreCondFailReq MSHR miss cycles 177511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67960471500 # number of demand (read+write) MSHR miss cycles 177611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 67960471500 # number of demand (read+write) MSHR miss cycles 177711138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 82476063500 # number of overall MSHR miss cycles 177811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 82476063500 # number of overall MSHR miss cycles 177911138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3614060000 # number of ReadReq MSHR uncacheable cycles 178011138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3614060000 # number of ReadReq MSHR uncacheable cycles 178111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3361466500 # number of WriteReq MSHR uncacheable cycles 178211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3361466500 # number of WriteReq MSHR uncacheable cycles 178311138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975526500 # number of overall MSHR uncacheable cycles 178411138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 6975526500 # number of overall MSHR uncacheable cycles 178511138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036136 # mshr miss rate for ReadReq accesses 178611138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036136 # mshr miss rate for ReadReq accesses 178711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses 178811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses 178911138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780628 # mshr miss rate for SoftPFReq accesses 179011138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780628 # mshr miss rate for SoftPFReq accesses 179111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.700535 # mshr miss rate for WriteLineReq accesses 179211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.700535 # mshr miss rate for WriteLineReq accesses 179311138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060407 # mshr miss rate for LoadLockedReq accesses 179411138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060407 # mshr miss rate for LoadLockedReq accesses 179511138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103381 # mshr miss rate for StoreCondReq accesses 179611138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103381 # mshr miss rate for StoreCondReq accesses 179711138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027590 # mshr miss rate for demand accesses 179811138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses 179911138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031667 # mshr miss rate for overall accesses 180011138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031667 # mshr miss rate for overall accesses 180111138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004 # average ReadReq mshr miss latency 180211138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004 # average ReadReq mshr miss latency 180311138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800 # average WriteReq mshr miss latency 180411138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800 # average WriteReq mshr miss latency 180511138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581 # average SoftPFReq mshr miss latency 180611138Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581 # average SoftPFReq mshr miss latency 180711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728 # average WriteLineReq mshr miss latency 180811138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728 # average WriteLineReq mshr miss latency 180911138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954 # average LoadLockedReq mshr miss latency 181011138Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954 # average LoadLockedReq mshr miss latency 181111138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747 # average StoreCondReq mshr miss latency 181211138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747 # average StoreCondReq mshr miss latency 181310535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 181410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 181511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673 # average overall mshr miss latency 181611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673 # average overall mshr miss latency 181711138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050 # average overall mshr miss latency 181811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050 # average overall mshr miss latency 181911138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709 # average ReadReq mshr uncacheable latency 182011138Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709 # average ReadReq mshr uncacheable latency 182111138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472 # average WriteReq mshr uncacheable latency 182211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472 # average WriteReq mshr uncacheable latency 182311138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302 # average overall mshr uncacheable latency 182411138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302 # average overall mshr uncacheable latency 182510535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 182611138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 4679241 # number of replacements 182711138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 495.918258 # Cycle average of tags in use 182811138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 436326798 # Total number of references to valid blocks. 182911138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 4679753 # Sample count of references to valid blocks. 183011138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 93.237143 # Average number of references to valid blocks. 183111138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8409166313000 # Cycle when the warmup percentage was hit. 183211138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 495.918258 # Average occupied blocks per requestor 183311138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.968590 # Average percentage of cache occupancy 183411138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.968590 # Average percentage of cache occupancy 183510535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 183611138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 183711138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id 183811138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id 183910944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 184010535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 184111138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 886692857 # Number of tag accesses 184211138Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 886692857 # Number of data accesses 184311138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 436326798 # number of ReadReq hits 184411138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 436326798 # number of ReadReq hits 184511138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 436326798 # number of demand (read+write) hits 184611138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 436326798 # number of demand (read+write) hits 184711138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 436326798 # number of overall hits 184811138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 436326798 # number of overall hits 184911138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4679754 # number of ReadReq misses 185011138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 4679754 # number of ReadReq misses 185111138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4679754 # number of demand (read+write) misses 185211138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 4679754 # number of demand (read+write) misses 185311138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4679754 # number of overall misses 185411138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 4679754 # number of overall misses 185511138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52951180000 # number of ReadReq miss cycles 185611138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 52951180000 # number of ReadReq miss cycles 185711138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 52951180000 # number of demand (read+write) miss cycles 185811138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 52951180000 # number of demand (read+write) miss cycles 185911138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 52951180000 # number of overall miss cycles 186011138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 52951180000 # number of overall miss cycles 186111138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 441006552 # number of ReadReq accesses(hits+misses) 186211138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 441006552 # number of ReadReq accesses(hits+misses) 186311138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 441006552 # number of demand (read+write) accesses 186411138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 441006552 # number of demand (read+write) accesses 186511138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 441006552 # number of overall (read+write) accesses 186611138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 441006552 # number of overall (read+write) accesses 186711138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010612 # miss rate for ReadReq accesses 186811138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.010612 # miss rate for ReadReq accesses 186911138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.010612 # miss rate for demand accesses 187011138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.010612 # miss rate for demand accesses 187111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.010612 # miss rate for overall accesses 187211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.010612 # miss rate for overall accesses 187311138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461 # average ReadReq miss latency 187411138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461 # average ReadReq miss latency 187511138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency 187611138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 11314.949461 # average overall miss latency 187711138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency 187811138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 11314.949461 # average overall miss latency 187910535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 188010535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188110535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188210535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 188310535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 188410535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188510535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 188610535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 188711138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4679754 # number of ReadReq MSHR misses 188811138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4679754 # number of ReadReq MSHR misses 188911138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4679754 # number of demand (read+write) MSHR misses 189011138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 4679754 # number of demand (read+write) MSHR misses 189111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4679754 # number of overall MSHR misses 189211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 4679754 # number of overall MSHR misses 189310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 189410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 189510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 189610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 189711138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50611303500 # number of ReadReq MSHR miss cycles 189811138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 50611303500 # number of ReadReq MSHR miss cycles 189911138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50611303500 # number of demand (read+write) MSHR miss cycles 190011138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 50611303500 # number of demand (read+write) MSHR miss cycles 190111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50611303500 # number of overall MSHR miss cycles 190211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 50611303500 # number of overall MSHR miss cycles 190311138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14521500 # number of ReadReq MSHR uncacheable cycles 190411138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14521500 # number of ReadReq MSHR uncacheable cycles 190511138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14521500 # number of overall MSHR uncacheable cycles 190611138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 14521500 # number of overall MSHR uncacheable cycles 190711138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for ReadReq accesses 190811138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010612 # mshr miss rate for ReadReq accesses 190911138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for demand accesses 191011138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.010612 # mshr miss rate for demand accesses 191111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for overall accesses 191211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.010612 # mshr miss rate for overall accesses 191311138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average ReadReq mshr miss latency 191411138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568 # average ReadReq mshr miss latency 191511138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency 191611138Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency 191711138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency 191811138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency 191911138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average ReadReq mshr uncacheable latency 192011138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364 # average ReadReq mshr uncacheable latency 192111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average overall mshr uncacheable latency 192211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364 # average overall mshr uncacheable latency 192310535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 192411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7337880 # number of hwpf issued 192511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7337888 # number of prefetch candidates identified 192611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 192710628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 192810628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 192911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 899040 # number of prefetches not generated due to page crossing 193011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2034185 # number of replacements 193111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13437.783654 # Cycle average of tags in use 193211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 16644740 # Total number of references to valid blocks. 193311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2049737 # Sample count of references to valid blocks. 193411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 8.120427 # Average number of references to valid blocks. 193511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9820320151000 # Cycle when the warmup percentage was hit. 193611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 6510.894270 # Average occupied blocks per requestor 193711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.649917 # Average occupied blocks per requestor 193811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 96.755911 # Average occupied blocks per requestor 193911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2809.884427 # Average occupied blocks per requestor 194011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3040.183540 # Average occupied blocks per requestor 194111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 908.415590 # Average occupied blocks per requestor 194211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.397393 # Average percentage of cache occupancy 194311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004373 # Average percentage of cache occupancy 194411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005906 # Average percentage of cache occupancy 194511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.171502 # Average percentage of cache occupancy 194611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.185558 # Average percentage of cache occupancy 194711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055445 # Average percentage of cache occupancy 194811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.820177 # Average percentage of cache occupancy 194911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id 195011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 195111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 13928 # Occupied blocks per task id 195211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 195311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id 195411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 636 # Occupied blocks per task id 195511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 195611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id 195711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id 195811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 195911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 196011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2599 # Occupied blocks per task id 196111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5864 # Occupied blocks per task id 196211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5395 # Occupied blocks per task id 196311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id 196411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 196511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id 196611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 332457854 # Number of tag accesses 196711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 332457854 # Number of data accesses 196811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236423 # number of ReadReq hits 196911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 125548 # number of ReadReq hits 197011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 361971 # number of ReadReq hits 197111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3396406 # number of Writeback hits 197211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3396406 # number of Writeback hits 197311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 63344 # number of UpgradeReq hits 197411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 63344 # number of UpgradeReq hits 197511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31004 # number of SCUpgradeReq hits 197611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 31004 # number of SCUpgradeReq hits 197711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 898756 # number of ReadExReq hits 197811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 898756 # number of ReadExReq hits 197911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4166985 # number of ReadCleanReq hits 198011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4166985 # number of ReadCleanReq hits 198111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2749875 # number of ReadSharedReq hits 198211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2749875 # number of ReadSharedReq hits 198311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193932 # number of InvalidateReq hits 198411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 193932 # number of InvalidateReq hits 198511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236423 # number of demand (read+write) hits 198611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 125548 # number of demand (read+write) hits 198711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4166985 # number of demand (read+write) hits 198811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3648631 # number of demand (read+write) hits 198911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8177587 # number of demand (read+write) hits 199011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236423 # number of overall hits 199111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 125548 # number of overall hits 199211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4166985 # number of overall hits 199311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3648631 # number of overall hits 199411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8177587 # number of overall hits 199511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9552 # number of ReadReq misses 199611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7233 # number of ReadReq misses 199711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 16785 # number of ReadReq misses 199811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 199911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 200011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 123356 # number of UpgradeReq misses 200111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 123356 # number of UpgradeReq misses 200211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167961 # number of SCUpgradeReq misses 200311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 167961 # number of SCUpgradeReq misses 200411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses 200511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 200611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 219942 # number of ReadExReq misses 200711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 219942 # number of ReadExReq misses 200811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 512769 # number of ReadCleanReq misses 200911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 512769 # number of ReadCleanReq misses 201011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 907421 # number of ReadSharedReq misses 201111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 907421 # number of ReadSharedReq misses 201211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265828 # number of InvalidateReq misses 201311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 265828 # number of InvalidateReq misses 201411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9552 # number of demand (read+write) misses 201511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 7233 # number of demand (read+write) misses 201611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 512769 # number of demand (read+write) misses 201711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1127363 # number of demand (read+write) misses 201811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1656917 # number of demand (read+write) misses 201911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9552 # number of overall misses 202011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 7233 # number of overall misses 202111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 512769 # number of overall misses 202211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1127363 # number of overall misses 202311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1656917 # number of overall misses 202411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 404155000 # number of ReadReq miss cycles 202511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 336372500 # number of ReadReq miss cycles 202611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 740527500 # number of ReadReq miss cycles 202711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3749073000 # number of UpgradeReq miss cycles 202811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3749073000 # number of UpgradeReq miss cycles 202911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 4008183000 # number of SCUpgradeReq miss cycles 203011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 4008183000 # number of SCUpgradeReq miss cycles 203111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2030999 # number of SCUpgradeFailReq miss cycles 203211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2030999 # number of SCUpgradeFailReq miss cycles 203311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12972852500 # number of ReadExReq miss cycles 203411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 12972852500 # number of ReadExReq miss cycles 203511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18777464000 # number of ReadCleanReq miss cycles 203611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 18777464000 # number of ReadCleanReq miss cycles 203711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34592386500 # number of ReadSharedReq miss cycles 203811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 34592386500 # number of ReadSharedReq miss cycles 203911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 20042243500 # number of InvalidateReq miss cycles 204011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 20042243500 # number of InvalidateReq miss cycles 204111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 404155000 # number of demand (read+write) miss cycles 204211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 336372500 # number of demand (read+write) miss cycles 204311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 18777464000 # number of demand (read+write) miss cycles 204411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 47565239000 # number of demand (read+write) miss cycles 204511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 67083230500 # number of demand (read+write) miss cycles 204611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 404155000 # number of overall miss cycles 204711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 336372500 # number of overall miss cycles 204811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 18777464000 # number of overall miss cycles 204911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 47565239000 # number of overall miss cycles 205011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 67083230500 # number of overall miss cycles 205111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 245975 # number of ReadReq accesses(hits+misses) 205211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 132781 # number of ReadReq accesses(hits+misses) 205311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 378756 # number of ReadReq accesses(hits+misses) 205411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3396407 # number of Writeback accesses(hits+misses) 205511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3396407 # number of Writeback accesses(hits+misses) 205611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186700 # number of UpgradeReq accesses(hits+misses) 205711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 186700 # number of UpgradeReq accesses(hits+misses) 205811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198965 # number of SCUpgradeReq accesses(hits+misses) 205911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 198965 # number of SCUpgradeReq accesses(hits+misses) 206011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 206111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 206211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1118698 # number of ReadExReq accesses(hits+misses) 206311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1118698 # number of ReadExReq accesses(hits+misses) 206411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4679754 # number of ReadCleanReq accesses(hits+misses) 206511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4679754 # number of ReadCleanReq accesses(hits+misses) 206611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3657296 # number of ReadSharedReq accesses(hits+misses) 206711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3657296 # number of ReadSharedReq accesses(hits+misses) 206811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 459760 # number of InvalidateReq accesses(hits+misses) 206911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 459760 # number of InvalidateReq accesses(hits+misses) 207011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 245975 # number of demand (read+write) accesses 207111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 132781 # number of demand (read+write) accesses 207211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4679754 # number of demand (read+write) accesses 207311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4775994 # number of demand (read+write) accesses 207411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 9834504 # number of demand (read+write) accesses 207511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 245975 # number of overall (read+write) accesses 207611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 132781 # number of overall (read+write) accesses 207711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4679754 # number of overall (read+write) accesses 207811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4775994 # number of overall (read+write) accesses 207911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 9834504 # number of overall (read+write) accesses 208011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for ReadReq accesses 208111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.054473 # miss rate for ReadReq accesses 208211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.044316 # miss rate for ReadReq accesses 208311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 208411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 208511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660718 # miss rate for UpgradeReq accesses 208611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660718 # miss rate for UpgradeReq accesses 208711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.844174 # miss rate for SCUpgradeReq accesses 208811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.844174 # miss rate for SCUpgradeReq accesses 208910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 209010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 209111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.196605 # miss rate for ReadExReq accesses 209211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.196605 # miss rate for ReadExReq accesses 209311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.109572 # miss rate for ReadCleanReq accesses 209411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.109572 # miss rate for ReadCleanReq accesses 209511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248113 # miss rate for ReadSharedReq accesses 209611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248113 # miss rate for ReadSharedReq accesses 209711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.578189 # miss rate for InvalidateReq accesses 209811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.578189 # miss rate for InvalidateReq accesses 209911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for demand accesses 210011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.054473 # miss rate for demand accesses 210111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109572 # miss rate for demand accesses 210211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.236048 # miss rate for demand accesses 210311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.168480 # miss rate for demand accesses 210411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for overall accesses 210511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.054473 # miss rate for overall accesses 210611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109572 # miss rate for overall accesses 210711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.236048 # miss rate for overall accesses 210811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.168480 # miss rate for overall accesses 210911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average ReadReq miss latency 211011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46505.253698 # average ReadReq miss latency 211111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 44118.409294 # average ReadReq miss latency 211211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30392.303577 # average UpgradeReq miss latency 211311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30392.303577 # average UpgradeReq miss latency 211411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23863.771947 # average SCUpgradeReq miss latency 211511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23863.771947 # average SCUpgradeReq miss latency 211611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 253874.875000 # average SCUpgradeFailReq miss latency 211711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 253874.875000 # average SCUpgradeFailReq miss latency 211811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58983.061443 # average ReadExReq miss latency 211911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58983.061443 # average ReadExReq miss latency 212011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36619.733252 # average ReadCleanReq miss latency 212111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36619.733252 # average ReadCleanReq miss latency 212211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38121.650810 # average ReadSharedReq miss latency 212311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38121.650810 # average ReadSharedReq miss latency 212411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 75395.532073 # average InvalidateReq miss latency 212511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 75395.532073 # average InvalidateReq miss latency 212611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency 212711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency 212811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency 212911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency 213011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 40486.777853 # average overall miss latency 213111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency 213211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency 213311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency 213411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency 213511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 40486.777853 # average overall miss latency 213610628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213710535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213810628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 213910535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 214010628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 214110535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 214210535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 214310535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 214411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1015409 # number of writebacks 214511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1015409 # number of writebacks 214611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7242 # number of ReadExReq MSHR hits 214711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 7242 # number of ReadExReq MSHR hits 214811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 595 # number of ReadSharedReq MSHR hits 214911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 595 # number of ReadSharedReq MSHR hits 215011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 215111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 215211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 7837 # number of demand (read+write) MSHR hits 215311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 7837 # number of demand (read+write) MSHR hits 215411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 7837 # number of overall MSHR hits 215511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 7837 # number of overall MSHR hits 215611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9552 # number of ReadReq MSHR misses 215711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7233 # number of ReadReq MSHR misses 215811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 16785 # number of ReadReq MSHR misses 215911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 216011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 216111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 96130 # number of CleanEvict MSHR misses 216211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::total 96130 # number of CleanEvict MSHR misses 216311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of HardPFReq MSHR misses 216411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 687356 # number of HardPFReq MSHR misses 216511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 123356 # number of UpgradeReq MSHR misses 216611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 123356 # number of UpgradeReq MSHR misses 216711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167961 # number of SCUpgradeReq MSHR misses 216811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167961 # number of SCUpgradeReq MSHR misses 216911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses 217011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 217111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 212700 # number of ReadExReq MSHR misses 217211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 212700 # number of ReadExReq MSHR misses 217311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 512769 # number of ReadCleanReq MSHR misses 217411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 512769 # number of ReadCleanReq MSHR misses 217511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 906826 # number of ReadSharedReq MSHR misses 217611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 906826 # number of ReadSharedReq MSHR misses 217711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 265827 # number of InvalidateReq MSHR misses 217811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 265827 # number of InvalidateReq MSHR misses 217911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9552 # number of demand (read+write) MSHR misses 218011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7233 # number of demand (read+write) MSHR misses 218111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 512769 # number of demand (read+write) MSHR misses 218211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1119526 # number of demand (read+write) MSHR misses 218311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1649080 # number of demand (read+write) MSHR misses 218411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9552 # number of overall MSHR misses 218511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7233 # number of overall MSHR misses 218611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 512769 # number of overall MSHR misses 218711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1119526 # number of overall MSHR misses 218811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of overall MSHR misses 218911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2336436 # number of overall MSHR misses 219010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 219111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable 219211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 20880 # number of ReadReq MSHR uncacheable 219311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable 219411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable 219510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 219611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses 219711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40210 # number of overall MSHR uncacheable misses 219811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of ReadReq MSHR miss cycles 219911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 292974500 # number of ReadReq MSHR miss cycles 220011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 639817500 # number of ReadReq MSHR miss cycles 220111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of HardPFReq MSHR miss cycles 220211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44220457933 # number of HardPFReq MSHR miss cycles 220311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4206113500 # number of UpgradeReq MSHR miss cycles 220411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4206113500 # number of UpgradeReq MSHR miss cycles 220511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3161211000 # number of SCUpgradeReq MSHR miss cycles 220611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3161211000 # number of SCUpgradeReq MSHR miss cycles 220711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1862999 # number of SCUpgradeFailReq MSHR miss cycles 220811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1862999 # number of SCUpgradeFailReq MSHR miss cycles 220911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10724509000 # number of ReadExReq MSHR miss cycles 221011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10724509000 # number of ReadExReq MSHR miss cycles 221111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15700856000 # number of ReadCleanReq MSHR miss cycles 221211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15700856000 # number of ReadCleanReq MSHR miss cycles 221311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29099850500 # number of ReadSharedReq MSHR miss cycles 221411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29099850500 # number of ReadSharedReq MSHR miss cycles 221511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 18447195500 # number of InvalidateReq MSHR miss cycles 221611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 18447195500 # number of InvalidateReq MSHR miss cycles 221711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of demand (read+write) MSHR miss cycles 221811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 292974500 # number of demand (read+write) MSHR miss cycles 221911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15700856000 # number of demand (read+write) MSHR miss cycles 222011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39824359500 # number of demand (read+write) MSHR miss cycles 222111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 56165033000 # number of demand (read+write) MSHR miss cycles 222211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of overall MSHR miss cycles 222311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 292974500 # number of overall MSHR miss cycles 222411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15700856000 # number of overall MSHR miss cycles 222511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39824359500 # number of overall MSHR miss cycles 222611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of overall MSHR miss cycles 222711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 100385490933 # number of overall MSHR miss cycles 222811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13696500 # number of ReadReq MSHR uncacheable cycles 222911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3447900000 # number of ReadReq MSHR uncacheable cycles 223011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3461596500 # number of ReadReq MSHR uncacheable cycles 223111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3216491500 # number of WriteReq MSHR uncacheable cycles 223211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3216491500 # number of WriteReq MSHR uncacheable cycles 223311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13696500 # number of overall MSHR uncacheable cycles 223411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6664391500 # number of overall MSHR uncacheable cycles 223511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6678088000 # number of overall MSHR uncacheable cycles 223611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for ReadReq accesses 223711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for ReadReq accesses 223811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044316 # mshr miss rate for ReadReq accesses 223911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 224011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 224110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 224210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 224310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 224410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 224511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660718 # mshr miss rate for UpgradeReq accesses 224611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660718 # mshr miss rate for UpgradeReq accesses 224711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.844174 # mshr miss rate for SCUpgradeReq accesses 224811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.844174 # mshr miss rate for SCUpgradeReq accesses 224910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 225010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 225111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.190132 # mshr miss rate for ReadExReq accesses 225211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.190132 # mshr miss rate for ReadExReq accesses 225311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for ReadCleanReq accesses 225411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109572 # mshr miss rate for ReadCleanReq accesses 225511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247950 # mshr miss rate for ReadSharedReq accesses 225611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247950 # mshr miss rate for ReadSharedReq accesses 225711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578186 # mshr miss rate for InvalidateReq accesses 225811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578186 # mshr miss rate for InvalidateReq accesses 225911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for demand accesses 226011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for demand accesses 226111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for demand accesses 226211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for demand accesses 226311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.167683 # mshr miss rate for demand accesses 226411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for overall accesses 226511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for overall accesses 226611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for overall accesses 226711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for overall accesses 226810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 226911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.237575 # mshr miss rate for overall accesses 227011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average ReadReq mshr miss latency 227111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average ReadReq mshr miss latency 227211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294 # average ReadReq mshr miss latency 227311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average HardPFReq mshr miss latency 227411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163 # average HardPFReq mshr miss latency 227511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432 # average UpgradeReq mshr miss latency 227611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432 # average UpgradeReq mshr miss latency 227711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327 # average SCUpgradeReq mshr miss latency 227811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327 # average SCUpgradeReq mshr miss latency 227911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000 # average SCUpgradeFailReq mshr miss latency 228011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000 # average SCUpgradeFailReq mshr miss latency 228111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755 # average ReadExReq mshr miss latency 228211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755 # average ReadExReq mshr miss latency 228311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average ReadCleanReq mshr miss latency 228411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953 # average ReadCleanReq mshr miss latency 228511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038 # average ReadSharedReq mshr miss latency 228611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038 # average ReadSharedReq mshr miss latency 228711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181 # average InvalidateReq mshr miss latency 228811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181 # average InvalidateReq mshr miss latency 228911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency 229011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency 229111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency 229211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency 229311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080 # average overall mshr miss latency 229411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency 229511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency 229611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency 229711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency 229811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average overall mshr miss latency 229911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788 # average overall mshr miss latency 230011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average ReadReq mshr uncacheable latency 230111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709 # average ReadReq mshr uncacheable latency 230211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989 # average ReadReq mshr uncacheable latency 230311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472 # average WriteReq mshr uncacheable latency 230411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472 # average WriteReq mshr uncacheable latency 230511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average overall mshr uncacheable latency 230611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746 # average overall mshr uncacheable latency 230711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538 # average overall mshr uncacheable latency 230810535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 230911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 20369965 # Total number of requests made to the snoop filter. 231011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10454543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 231111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 231211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 477453 # Total number of snoops made to the snoop filter. 231311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 477447 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 231411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 231511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 508237 # Transaction distribution 231611138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 8929000 # Transaction distribution 231711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 19330 # Transaction distribution 231811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 19330 # Transaction distribution 231911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 4444983 # Transaction distribution 232011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 8042862 # Transaction distribution 232111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 852297 # Transaction distribution 232211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 366971 # Transaction distribution 232311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363003 # Transaction distribution 232411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 446864 # Transaction distribution 232511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution 232611138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 232711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1185291 # Transaction distribution 232811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1125998 # Transaction distribution 232911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4679754 # Transaction distribution 233011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4554667 # Transaction distribution 233111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 467005 # Transaction distribution 233211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 459760 # Transaction distribution 233311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14038440 # Packet count per connected master and slave (bytes) 233411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16622497 # Packet count per connected master and slave (bytes) 233511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 296146 # Packet count per connected master and slave (bytes) 233611138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 569967 # Packet count per connected master and slave (bytes) 233711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 31527050 # Packet count per connected master and slave (bytes) 233811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 299504632 # Cumulative packet size per connected master and slave (bytes) 233911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 528992733 # Cumulative packet size per connected master and slave (bytes) 234011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1062248 # Cumulative packet size per connected master and slave (bytes) 234111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1967800 # Cumulative packet size per connected master and slave (bytes) 234211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 831527413 # Cumulative packet size per connected master and slave (bytes) 234311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5090691 # Total snoops (count) 234411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 25485456 # Request fanout histogram 234511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.028305 # Request fanout histogram 234611138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.165844 # Request fanout histogram 234710535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 234811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 24764094 97.17% 97.17% # Request fanout histogram 234911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 721356 2.83% 100.00% # Request fanout histogram 235011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 235110535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 235211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 235310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 235411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 25485456 # Request fanout histogram 235511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 13733891999 # Layer occupancy (ticks) 235610535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 235711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 167318993 # Layer occupancy (ticks) 235810535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 235911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7019739500 # Layer occupancy (ticks) 236010535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 236111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7617418010 # Layer occupancy (ticks) 236210535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 236311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 163365000 # Layer occupancy (ticks) 236410535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 236511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 323992499 # Layer occupancy (ticks) 236610535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 236711138Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40317 # Transaction distribution 236811138Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40317 # Transaction distribution 236911138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136619 # Transaction distribution 237011138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136619 # Transaction distribution 237111138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47666 # Packet count per connected master and slave (bytes) 237210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 237310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 237410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 237510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 237710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 237810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 237910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 238010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 238110726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 238210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 238310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 238410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 238510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 238611138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122600 # Packet count per connected master and slave (bytes) 238711138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) 238811138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) 238910535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 239010535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 239111138Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353872 # Packet count per connected master and slave (bytes) 239211138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47686 # Cumulative packet size per connected master and slave (bytes) 239310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 239410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 239510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 239610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 239710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 240110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240210726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 240310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 240410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 240510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 240610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 240711138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155707 # Cumulative packet size per connected master and slave (bytes) 240811138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) 240911138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) 241010535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 241110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 241211138Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) 241311138Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36194000 # Layer occupancy (ticks) 241410535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 241510535SN/Asystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 241610535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 241710535SN/Asystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 241810535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 241910535SN/Asystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 242010535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 242110535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 242210535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 242310535SN/Asystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 242410535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 242510535SN/Asystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 242610535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 242710535SN/Asystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 242810535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 242910535SN/Asystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 243010535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 243110535SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 243210535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 243310726SN/Asystem.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 243410535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 243510535SN/Asystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 243610535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 243710535SN/Asystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 243810535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 243910535SN/Asystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 244010535SN/Asystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 244111138Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 565735913 # Layer occupancy (ticks) 244210535SN/Asystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 244310535SN/Asystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 244410535SN/Asystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 244511138Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92712000 # Layer occupancy (ticks) 244610535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 244711138Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) 244810535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 244910892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 245010535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 245111138Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115577 # number of replacements 245211138Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.281807 # Cycle average of tags in use 245310535SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 245411138Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. 245510535SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 245611138Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9206321837000 # Cycle when the warmup percentage was hit. 245711138Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.831702 # Average occupied blocks per requestor 245811138Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.450105 # Average occupied blocks per requestor 245911138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239481 # Average percentage of cache occupancy 246011138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465632 # Average percentage of cache occupancy 246111138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705113 # Average percentage of cache occupancy 246210535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 246310535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 246410535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 246511138Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040721 # Number of tag accesses 246611138Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040721 # Number of data accesses 246710535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 246811138Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses 246911138Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8905 # number of ReadReq misses 247010535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 247110535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 247210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 247310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 247410535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 247511138Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses 247611138Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8908 # number of demand (read+write) misses 247710535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 247811138Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8868 # number of overall misses 247911138Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8908 # number of overall misses 248010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 248111138Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1668103306 # number of ReadReq miss cycles 248211138Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1673298306 # number of ReadReq miss cycles 248310726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 248410726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 248511138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13929903607 # number of WriteLineReq miss cycles 248611138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13929903607 # number of WriteLineReq miss cycles 248710892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 248811138Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1668103306 # number of demand (read+write) miss cycles 248911138Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1673667306 # number of demand (read+write) miss cycles 249010892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 249111138Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1668103306 # number of overall miss cycles 249211138Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1673667306 # number of overall miss cycles 249310535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 249411138Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) 249511138Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) 249610535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 249710535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 249810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 249910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 250010535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 250111138Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses 250211138Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses 250310535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 250411138Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses 250511138Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses 250610535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 250710535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 250810535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 250910535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 251010535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 251110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 251210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 251310535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 251410535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 251510535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 251610535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 251710535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 251810535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 251910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 252011138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539 # average ReadReq miss latency 252111138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 187905.480741 # average ReadReq miss latency 252210726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 252310726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 252411138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581 # average WriteLineReq miss latency 252511138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 130517.798581 # average WriteLineReq miss latency 252610892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 252711138Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency 252811138Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 187883.622137 # average overall miss latency 252910892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 253011138Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency 253111138Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 187883.622137 # average overall miss latency 253211138Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 33272 # number of cycles access was blocked 253310535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253411138Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3491 # number of cycles access was blocked 253510535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 253611138Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.530793 # average number of cycles each access was blocked 253710535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253810585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 253910535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 254011138Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 254111138Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 254210535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 254311138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses 254411138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses 254510535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 254610535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 254710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 254810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 254910535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 255011138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses 255111138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses 255210535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 255311138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses 255411138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses 255510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 255611138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1224703306 # number of ReadReq MSHR miss cycles 255711138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1228048306 # number of ReadReq MSHR miss cycles 255810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 255910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 256011138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8593503607 # number of WriteLineReq MSHR miss cycles 256111138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8593503607 # number of WriteLineReq MSHR miss cycles 256210892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 256311138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1224703306 # number of demand (read+write) MSHR miss cycles 256411138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1228267306 # number of demand (read+write) MSHR miss cycles 256510892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 256611138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1224703306 # number of overall MSHR miss cycles 256711138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1228267306 # number of overall MSHR miss cycles 256810535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 256910535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 257010535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 257110535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 257210535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 257310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 257410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 257510535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 257610535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 257710535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 257810535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 257910535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 258010535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 258110892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 258211138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539 # average ReadReq mshr miss latency 258311138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741 # average ReadReq mshr miss latency 258410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 258510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 258611138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581 # average WriteLineReq mshr miss latency 258711138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581 # average WriteLineReq mshr miss latency 258810892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 258911138Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency 259011138Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency 259110892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 259211138Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency 259311138Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency 259410535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 259511138Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1400633 # number of replacements 259611138Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63705.794368 # Cycle average of tags in use 259711138Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5028924 # Total number of references to valid blocks. 259811138Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1460176 # Sample count of references to valid blocks. 259911138Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.444053 # Average number of references to valid blocks. 260010892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 260111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 18928.346727 # Average occupied blocks per requestor 260211138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 167.390384 # Average occupied blocks per requestor 260311138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 216.986390 # Average occupied blocks per requestor 260411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4428.367994 # Average occupied blocks per requestor 260511138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 11717.643832 # Average occupied blocks per requestor 260611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344 # Average occupied blocks per requestor 260711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 156.822011 # Average occupied blocks per requestor 260811138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 230.353384 # Average occupied blocks per requestor 260911138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2614.971757 # Average occupied blocks per requestor 261011138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 4665.203250 # Average occupied blocks per requestor 261111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9239.567296 # Average occupied blocks per requestor 261211138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.288824 # Average percentage of cache occupancy 261311138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002554 # Average percentage of cache occupancy 261411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003311 # Average percentage of cache occupancy 261511138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.067572 # Average percentage of cache occupancy 261611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.178797 # Average percentage of cache occupancy 261711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173037 # Average percentage of cache occupancy 261811138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002393 # Average percentage of cache occupancy 261911138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.003515 # Average percentage of cache occupancy 262011138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.039901 # Average percentage of cache occupancy 262111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.071185 # Average percentage of cache occupancy 262211138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140985 # Average percentage of cache occupancy 262311138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.972073 # Average percentage of cache occupancy 262411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10769 # Occupied blocks per task id 262511138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id 262611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48480 # Occupied blocks per task id 262711138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 265 # Occupied blocks per task id 262811138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 409 # Occupied blocks per task id 262911138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10095 # Occupied blocks per task id 263011138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id 263111138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 263211138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 263311138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1411 # Occupied blocks per task id 263411138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id 263511138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 41942 # Occupied blocks per task id 263611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.164322 # Percentage of cache occupancy per task id 263711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id 263811138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.739746 # Percentage of cache occupancy per task id 263911138Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 64230359 # Number of tag accesses 264011138Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 64230359 # Number of data accesses 264111138Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2314762 # number of Writeback hits 264211138Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2314762 # number of Writeback hits 264311138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 28623 # number of UpgradeReq hits 264411138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 30874 # number of UpgradeReq hits 264511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 59497 # number of UpgradeReq hits 264611138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 6079 # number of SCUpgradeReq hits 264711138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 5789 # number of SCUpgradeReq hits 264811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 11868 # number of SCUpgradeReq hits 264911138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 160432 # number of ReadExReq hits 265011138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 145801 # number of ReadExReq hits 265111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 306233 # number of ReadExReq hits 265211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5516 # number of ReadSharedReq hits 265311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4550 # number of ReadSharedReq hits 265411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 461560 # number of ReadSharedReq hits 265511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 521601 # number of ReadSharedReq hits 265611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 265120 # number of ReadSharedReq hits 265711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 4769 # number of ReadSharedReq hits 265811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3407 # number of ReadSharedReq hits 265911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 473807 # number of ReadSharedReq hits 266011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 524703 # number of ReadSharedReq hits 266111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 267683 # number of ReadSharedReq hits 266211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2532716 # number of ReadSharedReq hits 266311138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5516 # number of demand (read+write) hits 266411138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4550 # number of demand (read+write) hits 266511138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 461560 # number of demand (read+write) hits 266611138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 682033 # number of demand (read+write) hits 266711138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 265120 # number of demand (read+write) hits 266811138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 4769 # number of demand (read+write) hits 266911138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3407 # number of demand (read+write) hits 267011138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 473807 # number of demand (read+write) hits 267111138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 670504 # number of demand (read+write) hits 267211138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 267683 # number of demand (read+write) hits 267311138Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2838949 # number of demand (read+write) hits 267411138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5516 # number of overall hits 267511138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4550 # number of overall hits 267611138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 461560 # number of overall hits 267711138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 682033 # number of overall hits 267811138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 265120 # number of overall hits 267911138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 4769 # number of overall hits 268011138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3407 # number of overall hits 268111138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 473807 # number of overall hits 268211138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 670504 # number of overall hits 268311138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 267683 # number of overall hits 268411138Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2838949 # number of overall hits 268511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 45739 # number of UpgradeReq misses 268611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 41402 # number of UpgradeReq misses 268711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 87141 # number of UpgradeReq misses 268811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 10551 # number of SCUpgradeReq misses 268911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 10041 # number of SCUpgradeReq misses 269011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 20592 # number of SCUpgradeReq misses 269111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 478288 # number of ReadExReq misses 269211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 167740 # number of ReadExReq misses 269311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 646028 # number of ReadExReq misses 269411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq misses 269511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2246 # number of ReadSharedReq misses 269611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 51456 # number of ReadSharedReq misses 269711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 156048 # number of ReadSharedReq misses 269811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq misses 269911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1431 # number of ReadSharedReq misses 270011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1351 # number of ReadSharedReq misses 270111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 38962 # number of ReadSharedReq misses 270211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 102025 # number of ReadSharedReq misses 270311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 234272 # number of ReadSharedReq misses 270411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 778714 # number of ReadSharedReq misses 270511138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1990 # number of demand (read+write) misses 270611138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2246 # number of demand (read+write) misses 270711138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 51456 # number of demand (read+write) misses 270811138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 634336 # number of demand (read+write) misses 270911138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) misses 271011138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1431 # number of demand (read+write) misses 271111138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1351 # number of demand (read+write) misses 271211138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 38962 # number of demand (read+write) misses 271311138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 269765 # number of demand (read+write) misses 271411138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) misses 271511138Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1424742 # number of demand (read+write) misses 271611138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1990 # number of overall misses 271711138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2246 # number of overall misses 271811138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 51456 # number of overall misses 271911138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 634336 # number of overall misses 272011138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 188933 # number of overall misses 272111138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1431 # number of overall misses 272211138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1351 # number of overall misses 272311138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 38962 # number of overall misses 272411138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 269765 # number of overall misses 272511138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 234272 # number of overall misses 272611138Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1424742 # number of overall misses 272711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 656419000 # number of UpgradeReq miss cycles 272811138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 602429500 # number of UpgradeReq miss cycles 272911138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 1258848500 # number of UpgradeReq miss cycles 273011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 138505500 # number of SCUpgradeReq miss cycles 273111138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 121106000 # number of SCUpgradeReq miss cycles 273211138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 259611500 # number of SCUpgradeReq miss cycles 273311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 64575954000 # number of ReadExReq miss cycles 273411138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 22241696500 # number of ReadExReq miss cycles 273511138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 86817650500 # number of ReadExReq miss cycles 273611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 275343500 # number of ReadSharedReq miss cycles 273711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 312648500 # number of ReadSharedReq miss cycles 273811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6939841000 # number of ReadSharedReq miss cycles 273911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 21911323500 # number of ReadSharedReq miss cycles 274011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of ReadSharedReq miss cycles 274111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 199825500 # number of ReadSharedReq miss cycles 274211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 189752500 # number of ReadSharedReq miss cycles 274311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5267042000 # number of ReadSharedReq miss cycles 274411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 14361628000 # number of ReadSharedReq miss cycles 274511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of ReadSharedReq miss cycles 274611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 119572711026 # number of ReadSharedReq miss cycles 274711138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 275343500 # number of demand (read+write) miss cycles 274811138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 312648500 # number of demand (read+write) miss cycles 274911138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6939841000 # number of demand (read+write) miss cycles 275011138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 86487277500 # number of demand (read+write) miss cycles 275111138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of demand (read+write) miss cycles 275211138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 199825500 # number of demand (read+write) miss cycles 275311138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 189752500 # number of demand (read+write) miss cycles 275411138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5267042000 # number of demand (read+write) miss cycles 275511138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 36603324500 # number of demand (read+write) miss cycles 275611138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of demand (read+write) miss cycles 275711138Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 206390361526 # number of demand (read+write) miss cycles 275811138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 275343500 # number of overall miss cycles 275911138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 312648500 # number of overall miss cycles 276011138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6939841000 # number of overall miss cycles 276111138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 86487277500 # number of overall miss cycles 276211138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of overall miss cycles 276311138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 199825500 # number of overall miss cycles 276411138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 189752500 # number of overall miss cycles 276511138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5267042000 # number of overall miss cycles 276611138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 36603324500 # number of overall miss cycles 276711138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of overall miss cycles 276811138Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 206390361526 # number of overall miss cycles 276911138Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2314762 # number of Writeback accesses(hits+misses) 277011138Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2314762 # number of Writeback accesses(hits+misses) 277111138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 74362 # number of UpgradeReq accesses(hits+misses) 277211138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 72276 # number of UpgradeReq accesses(hits+misses) 277311138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 146638 # number of UpgradeReq accesses(hits+misses) 277411138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 16630 # number of SCUpgradeReq accesses(hits+misses) 277511138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 15830 # number of SCUpgradeReq accesses(hits+misses) 277611138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 32460 # number of SCUpgradeReq accesses(hits+misses) 277711138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 638720 # number of ReadExReq accesses(hits+misses) 277811138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 313541 # number of ReadExReq accesses(hits+misses) 277911138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 952261 # number of ReadExReq accesses(hits+misses) 278011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7506 # number of ReadSharedReq accesses(hits+misses) 278111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6796 # number of ReadSharedReq accesses(hits+misses) 278211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 513016 # number of ReadSharedReq accesses(hits+misses) 278311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 677649 # number of ReadSharedReq accesses(hits+misses) 278411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 454053 # number of ReadSharedReq accesses(hits+misses) 278511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6200 # number of ReadSharedReq accesses(hits+misses) 278611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 4758 # number of ReadSharedReq accesses(hits+misses) 278711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 512769 # number of ReadSharedReq accesses(hits+misses) 278811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 626728 # number of ReadSharedReq accesses(hits+misses) 278911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 501955 # number of ReadSharedReq accesses(hits+misses) 279011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3311430 # number of ReadSharedReq accesses(hits+misses) 279111138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 7506 # number of demand (read+write) accesses 279211138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6796 # number of demand (read+write) accesses 279311138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 513016 # number of demand (read+write) accesses 279411138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1316369 # number of demand (read+write) accesses 279511138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 454053 # number of demand (read+write) accesses 279611138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 6200 # number of demand (read+write) accesses 279711138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 4758 # number of demand (read+write) accesses 279811138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 512769 # number of demand (read+write) accesses 279911138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 940269 # number of demand (read+write) accesses 280011138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 501955 # number of demand (read+write) accesses 280111138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4263691 # number of demand (read+write) accesses 280211138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 7506 # number of overall (read+write) accesses 280311138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6796 # number of overall (read+write) accesses 280411138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 513016 # number of overall (read+write) accesses 280511138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1316369 # number of overall (read+write) accesses 280611138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 454053 # number of overall (read+write) accesses 280711138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 6200 # number of overall (read+write) accesses 280811138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 4758 # number of overall (read+write) accesses 280911138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 512769 # number of overall (read+write) accesses 281011138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 940269 # number of overall (read+write) accesses 281111138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 501955 # number of overall (read+write) accesses 281211138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4263691 # number of overall (read+write) accesses 281311138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.615086 # miss rate for UpgradeReq accesses 281411138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.572832 # miss rate for UpgradeReq accesses 281511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.594259 # miss rate for UpgradeReq accesses 281611138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634456 # miss rate for SCUpgradeReq accesses 281711138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.634302 # miss rate for SCUpgradeReq accesses 281811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.634381 # miss rate for SCUpgradeReq accesses 281911138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.748823 # miss rate for ReadExReq accesses 282011138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.534986 # miss rate for ReadExReq accesses 282111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.678415 # miss rate for ReadExReq accesses 282211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for ReadSharedReq accesses 282311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.330489 # miss rate for ReadSharedReq accesses 282411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100301 # miss rate for ReadSharedReq accesses 282511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.230279 # miss rate for ReadSharedReq accesses 282611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for ReadSharedReq accesses 282711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for ReadSharedReq accesses 282811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.283943 # miss rate for ReadSharedReq accesses 282911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075984 # miss rate for ReadSharedReq accesses 283011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162790 # miss rate for ReadSharedReq accesses 283111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for ReadSharedReq accesses 283211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.235159 # miss rate for ReadSharedReq accesses 283311138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for demand accesses 283411138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.330489 # miss rate for demand accesses 283511138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.100301 # miss rate for demand accesses 283611138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.481883 # miss rate for demand accesses 283711138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for demand accesses 283811138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for demand accesses 283911138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.283943 # miss rate for demand accesses 284011138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.075984 # miss rate for demand accesses 284111138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.286902 # miss rate for demand accesses 284211138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for demand accesses 284311138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.334157 # miss rate for demand accesses 284411138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for overall accesses 284511138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.330489 # miss rate for overall accesses 284611138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.100301 # miss rate for overall accesses 284711138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.481883 # miss rate for overall accesses 284811138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for overall accesses 284911138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for overall accesses 285011138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.283943 # miss rate for overall accesses 285111138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.075984 # miss rate for overall accesses 285211138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.286902 # miss rate for overall accesses 285311138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for overall accesses 285411138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.334157 # miss rate for overall accesses 285511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14351.406896 # average UpgradeReq miss latency 285611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14550.734264 # average UpgradeReq miss latency 285711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 14446.110327 # average UpgradeReq miss latency 285811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13127.239124 # average SCUpgradeReq miss latency 285911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12061.149288 # average SCUpgradeReq miss latency 286011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 12607.396076 # average SCUpgradeReq miss latency 286111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 135014.790252 # average ReadExReq miss latency 286211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 132596.259091 # average ReadExReq miss latency 286311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 134386.823017 # average ReadExReq miss latency 286411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average ReadSharedReq miss latency 286511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 139202.359751 # average ReadSharedReq miss latency 286611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134869.422419 # average ReadSharedReq miss latency 286711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140413.997616 # average ReadSharedReq miss latency 286811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average ReadSharedReq miss latency 286911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average ReadSharedReq miss latency 287011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140453.367876 # average ReadSharedReq miss latency 287111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135184.076793 # average ReadSharedReq miss latency 287211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140765.773095 # average ReadSharedReq miss latency 287311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average ReadSharedReq miss latency 287411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 153551.510601 # average ReadSharedReq miss latency 287511138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency 287611138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency 287711138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency 287811138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency 287911138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency 288011138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency 288111138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency 288211138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency 288311138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency 288411138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency 288511138Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 144861.568990 # average overall miss latency 288611138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency 288711138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency 288811138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency 288911138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency 289011138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency 289111138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency 289211138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency 289311138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency 289411138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency 289511138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency 289611138Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 144861.568990 # average overall miss latency 289711138Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 455 # number of cycles access was blocked 289810515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 289911138Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 290010515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 290111138Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked 290210515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 290310515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 290410515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 290511138Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1097098 # number of writebacks 290611138Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1097098 # number of writebacks 290711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 101 # number of ReadSharedReq MSHR hits 290811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits 290911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 79 # number of ReadSharedReq MSHR hits 291011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits 291111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 220 # number of ReadSharedReq MSHR hits 291211138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 101 # number of demand (read+write) MSHR hits 291311138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits 291411138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 79 # number of demand (read+write) MSHR hits 291511138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits 291611138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits 291711138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 101 # number of overall MSHR hits 291811138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits 291911138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 79 # number of overall MSHR hits 292011138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits 292111138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 220 # number of overall MSHR hits 292211138Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 44502 # number of CleanEvict MSHR misses 292311138Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 44502 # number of CleanEvict MSHR misses 292411138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 45739 # number of UpgradeReq MSHR misses 292511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 41402 # number of UpgradeReq MSHR misses 292611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 87141 # number of UpgradeReq MSHR misses 292711138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10551 # number of SCUpgradeReq MSHR misses 292811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10041 # number of SCUpgradeReq MSHR misses 292911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 20592 # number of SCUpgradeReq MSHR misses 293011138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 478288 # number of ReadExReq MSHR misses 293111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 167740 # number of ReadExReq MSHR misses 293211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 646028 # number of ReadExReq MSHR misses 293311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq MSHR misses 293411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2246 # number of ReadSharedReq MSHR misses 293511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 51355 # number of ReadSharedReq MSHR misses 293611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 156019 # number of ReadSharedReq MSHR misses 293711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq MSHR misses 293811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1431 # number of ReadSharedReq MSHR misses 293911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1351 # number of ReadSharedReq MSHR misses 294011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38883 # number of ReadSharedReq MSHR misses 294111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 102014 # number of ReadSharedReq MSHR misses 294211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of ReadSharedReq MSHR misses 294311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 778494 # number of ReadSharedReq MSHR misses 294411138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1990 # number of demand (read+write) MSHR misses 294511138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 2246 # number of demand (read+write) MSHR misses 294611138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 51355 # number of demand (read+write) MSHR misses 294711138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 634307 # number of demand (read+write) MSHR misses 294811138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) MSHR misses 294911138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1431 # number of demand (read+write) MSHR misses 295011138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1351 # number of demand (read+write) MSHR misses 295111138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 38883 # number of demand (read+write) MSHR misses 295211138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 269754 # number of demand (read+write) MSHR misses 295311138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) MSHR misses 295411138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1424522 # number of demand (read+write) MSHR misses 295511138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1990 # number of overall MSHR misses 295611138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 2246 # number of overall MSHR misses 295711138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 51355 # number of overall MSHR misses 295811138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 634307 # number of overall MSHR misses 295911138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of overall MSHR misses 296011138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1431 # number of overall MSHR misses 296111138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1351 # number of overall MSHR misses 296211138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 38883 # number of overall MSHR misses 296311138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 269754 # number of overall MSHR misses 296411138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 234272 # 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mshr miss rate for CleanEvict accesses 303510892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 303611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.615086 # mshr miss rate for UpgradeReq accesses 303711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.572832 # mshr miss rate for UpgradeReq accesses 303811138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.594259 # mshr miss rate for UpgradeReq accesses 303911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.634456 # mshr miss rate for SCUpgradeReq accesses 304011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.634302 # mshr miss rate for SCUpgradeReq accesses 304111138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.634381 # mshr miss rate for SCUpgradeReq accesses 304211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.748823 # mshr miss rate for ReadExReq accesses 304311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534986 # mshr miss rate for ReadExReq accesses 304411138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.678415 # mshr miss rate for ReadExReq accesses 304511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for ReadSharedReq accesses 304611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for ReadSharedReq accesses 304711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for ReadSharedReq accesses 304811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.230236 # mshr miss rate for ReadSharedReq accesses 304911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for ReadSharedReq accesses 305011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for ReadSharedReq accesses 305111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for ReadSharedReq accesses 305211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for ReadSharedReq accesses 305311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162772 # mshr miss rate for ReadSharedReq accesses 305411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for ReadSharedReq accesses 305511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.235093 # mshr miss rate for ReadSharedReq accesses 305611138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for demand accesses 305711138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for demand accesses 305811138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for demand accesses 305911138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for demand accesses 306011138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for demand accesses 306111138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for demand accesses 306211138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for demand accesses 306311138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for demand accesses 306411138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for demand accesses 306511138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for demand accesses 306611138Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.334105 # mshr miss rate for demand accesses 306711138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for overall accesses 306811138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for overall accesses 306911138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for overall accesses 307011138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for overall accesses 307111138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for overall accesses 307211138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for overall accesses 307311138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for overall accesses 307411138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for overall accesses 307511138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for overall accesses 307611138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for overall accesses 307711138Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.334105 # mshr miss rate for overall accesses 307811138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086 # average UpgradeReq mshr miss latency 307911138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012 # average UpgradeReq mshr miss latency 308011138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612 # average UpgradeReq mshr miss latency 308111138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785 # average SCUpgradeReq mshr miss latency 308211138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636 # average SCUpgradeReq mshr miss latency 308311138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371 # average SCUpgradeReq mshr miss latency 308411138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252 # average ReadExReq mshr miss latency 308511138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091 # average ReadExReq mshr miss latency 308611138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017 # average ReadExReq mshr miss latency 308711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average ReadSharedReq mshr miss latency 308811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average ReadSharedReq mshr miss latency 308911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average ReadSharedReq mshr miss latency 309011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983 # average ReadSharedReq mshr miss latency 309111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average ReadSharedReq mshr miss latency 309211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average ReadSharedReq mshr miss latency 309311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average ReadSharedReq mshr miss latency 309411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average ReadSharedReq mshr miss latency 309511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921 # average ReadSharedReq mshr miss latency 309611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average ReadSharedReq mshr miss latency 309711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621 # average ReadSharedReq mshr miss latency 309811138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency 309911138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency 310011138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency 310111138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency 310211138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency 310311138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency 310411138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency 310511138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency 310611138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency 310711138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency 310811138Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency 310911138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency 311011138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency 311111138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency 311211138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency 311311138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency 311411138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency 311511138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency 311611138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency 311711138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency 311811138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency 311911138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency 312011138Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average ReadReq mshr uncacheable latency 312111138Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790 # average ReadReq mshr uncacheable latency 312211138Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average ReadReq mshr uncacheable latency 312311138Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928 # average ReadReq mshr uncacheable latency 312411138Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086 # average ReadReq mshr uncacheable latency 312511138Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633 # average WriteReq mshr uncacheable latency 312611138Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540 # average WriteReq mshr uncacheable latency 312711138Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376 # average WriteReq mshr uncacheable latency 312811138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average overall mshr uncacheable latency 312911138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334 # average overall mshr uncacheable latency 313011138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average overall mshr uncacheable latency 313111138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466 # average overall mshr uncacheable latency 313211138Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113 # average overall mshr uncacheable latency 313310515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 313411138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 81299 # Transaction distribution 313511138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 868698 # Transaction distribution 313611138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 37949 # Transaction distribution 313711138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 37949 # Transaction distribution 313811138Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1203792 # Transaction distribution 313911138Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 220565 # Transaction distribution 314011138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 376258 # Transaction distribution 314111138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 321655 # Transaction distribution 314211138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 113911 # Transaction distribution 314311138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 314411138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 660250 # Transaction distribution 314511138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 639853 # Transaction distribution 314611138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 787399 # Transaction distribution 314710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 314810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 314911138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122600 # Packet count per connected master and slave (bytes) 315010535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 315111138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24206 # Packet count per connected master and slave (bytes) 315211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5071225 # Packet count per connected master and slave (bytes) 315311138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5218123 # Packet count per connected master and slave (bytes) 315411138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341689 # Packet count per connected master and slave (bytes) 315511138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 341689 # Packet count per connected master and slave (bytes) 315611138Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5559812 # Packet count per connected master and slave (bytes) 315711138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155707 # Cumulative packet size per connected master and slave (bytes) 315810535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 315911138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48412 # Cumulative packet size per connected master and slave (bytes) 316011138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 161136300 # Cumulative packet size per connected master and slave (bytes) 316111138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 161340623 # Cumulative packet size per connected master and slave (bytes) 316211138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7239232 # Cumulative packet size per connected master and slave (bytes) 316311138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7239232 # Cumulative packet size per connected master and slave (bytes) 316411138Sandreas.hansson@arm.comsystem.membus.pkt_size::total 168579855 # Cumulative packet size per connected master and slave (bytes) 316511138Sandreas.hansson@arm.comsystem.membus.snoops 607627 # Total snoops (count) 316611138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3798608 # Request fanout histogram 316710535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 316810535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 316910535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 317010535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 317111138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3798608 100.00% 100.00% # Request fanout histogram 317210535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 317310535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 317410535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 317510535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 317611138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3798608 # Request fanout histogram 317711138Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 101169498 # Layer occupancy (ticks) 317810535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 317911138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 318010535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 318111138Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20972999 # Layer occupancy (ticks) 318210535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 318311138Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 8203462570 # Layer occupancy (ticks) 318410535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 318511138Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 7924808506 # Layer occupancy (ticks) 318610535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 318711138Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 230064369 # Layer occupancy (ticks) 318810535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 318910515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 319010515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 319110515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 319210515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 319310515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 319410515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 319510515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 319610515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 319710515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 319810585SN/Asystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 319910515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 320010515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 320110515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 320210585SN/Asystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 320310515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 320410515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 320510515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 320610515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 320710515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 320810515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 320910515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 321010515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 321110515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 321210515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 321310515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 321410515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 321510515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 321610515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 321710515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 321810515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 321910515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 322010515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 322110515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 322210515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 322310515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 322410515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 322510515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 322610515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 322710515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 322810515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 322910515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 323010515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 323111103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 323211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 323311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 323411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 323511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 323611014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 323711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 323811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 323911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 324011014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 324111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10304168 # Total number of requests made to the snoop filter. 324211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5242935 # Number of requests hitting in the snoop filter with a single holder of the requested data. 324311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1823032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 324411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 155703 # Total number of snoops made to the snoop filter. 324511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 143721 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 324611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 11982 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 324711138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 81301 # Transaction distribution 324811138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4203748 # Transaction distribution 324911138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 37949 # Transaction distribution 325011138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 37949 # Transaction distribution 325111138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 3518592 # Transaction distribution 325211138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1268318 # Transaction distribution 325311138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 429580 # Transaction distribution 325411138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 333523 # Transaction distribution 325511138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 763103 # Transaction distribution 325611138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 68 # Transaction distribution 325711138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution 325811138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1086913 # Transaction distribution 325911138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1086913 # Transaction distribution 326011138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4129694 # Transaction distribution 326110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 326211138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7476293 # Packet count per connected master and slave (bytes) 326311138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6448186 # Packet count per connected master and slave (bytes) 326411138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 13924479 # Packet count per connected master and slave (bytes) 326511138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230559242 # Cumulative packet size per connected master and slave (bytes) 326611138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190965829 # Cumulative packet size per connected master and slave (bytes) 326711138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 421525071 # Cumulative packet size per connected master and slave (bytes) 326811138Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3161630 # Total snoops (count) 326911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 12055300 # Request fanout histogram 327011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.328437 # Request fanout histogram 327111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.471756 # Request fanout histogram 327210515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 327311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 8107870 67.26% 67.26% # Request fanout histogram 327411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3935448 32.64% 99.90% # Request fanout histogram 327511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 11982 0.10% 100.00% # Request fanout histogram 327610515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 327711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 327810515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 327911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 12055300 # Request fanout histogram 328011138Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 7945670452 # Layer occupancy (ticks) 328110515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 328211138Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2561165 # Layer occupancy (ticks) 328310515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 328411138Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4404072117 # Layer occupancy (ticks) 328510515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 328611138Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3899520231 # Layer occupancy (ticks) 328710515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 328810515SN/A 328910515SN/A---------- End Simulation Statistics ---------- 3290