stats.txt revision 10944
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310944Sandreas.hansson@arm.comsim_seconds 47.456680 # Number of seconds simulated 410944Sandreas.hansson@arm.comsim_ticks 47456679626500 # Number of ticks simulated 510944Sandreas.hansson@arm.comfinal_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710944Sandreas.hansson@arm.comhost_inst_rate 659863 # Simulator instruction rate (inst/s) 810944Sandreas.hansson@arm.comhost_op_rate 776251 # Simulator op (including micro ops) rate (op/s) 910944Sandreas.hansson@arm.comhost_tick_rate 36196220555 # Simulator tick rate (ticks/s) 1010944Sandreas.hansson@arm.comhost_mem_usage 759244 # Number of bytes of host memory used 1110944Sandreas.hansson@arm.comhost_seconds 1311.10 # Real time elapsed on the host 1210944Sandreas.hansson@arm.comsim_insts 865142471 # Number of instructions simulated 1310944Sandreas.hansson@arm.comsim_ops 1017738631 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 51904 # Number of bytes read from this memory 1710944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 48448 # Number of bytes read from this memory 1810944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 2877620 # Number of bytes read from this memory 1910944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 38342664 # Number of bytes read from this memory 2010944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 11776896 # Number of bytes read from this memory 2110944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 153536 # Number of bytes read from this memory 2210944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 163840 # Number of bytes read from this memory 2310944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2826616 # Number of bytes read from this memory 2410944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 16120336 # Number of bytes read from this memory 2510944Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 11259712 # Number of bytes read from this memory 2610944Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory 2710944Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 84057220 # Number of bytes read from this memory 2810944Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 2877620 # Number of instructions bytes read from this memory 2910944Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2826616 # Number of instructions bytes read from this memory 3010944Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5704236 # Number of instructions bytes read from this memory 3110944Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 70891776 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3410944Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 70912360 # Number of bytes written to this memory 3510944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 811 # Number of read requests responded to by this memory 3610944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 757 # Number of read requests responded to by this memory 3710944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 85370 # Number of read requests responded to by this memory 3810944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 599117 # Number of read requests responded to by this memory 3910944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 184014 # Number of read requests responded to by this memory 4010944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2399 # Number of read requests responded to by this memory 4110944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2560 # Number of read requests responded to by this memory 4210944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 44254 # Number of read requests responded to by this memory 4310944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 251893 # Number of read requests responded to by this memory 4410944Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 175933 # Number of read requests responded to by this memory 4510944Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory 4610944Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1353915 # Number of read requests responded to by this memory 4710944Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1107684 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5010944Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1110258 # Number of write requests responded to by this memory 5110944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 1094 # Total read bandwidth from this memory (bytes/s) 5210944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1021 # Total read bandwidth from this memory (bytes/s) 5310944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 60637 # Total read bandwidth from this memory (bytes/s) 5410944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 807951 # Total read bandwidth from this memory (bytes/s) 5510944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 248161 # Total read bandwidth from this memory (bytes/s) 5610944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3235 # Total read bandwidth from this memory (bytes/s) 5710944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3452 # Total read bandwidth from this memory (bytes/s) 5810944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 59562 # Total read bandwidth from this memory (bytes/s) 5910944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 339685 # Total read bandwidth from this memory (bytes/s) 6010944Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 237263 # Total read bandwidth from this memory (bytes/s) 6110944Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9180 # Total read bandwidth from this memory (bytes/s) 6210944Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1771241 # Total read bandwidth from this memory (bytes/s) 6310944Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 60637 # Instruction read bandwidth from this memory (bytes/s) 6410944Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59562 # Instruction read bandwidth from this memory (bytes/s) 6510944Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 120199 # Instruction read bandwidth from this memory (bytes/s) 6610944Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1493821 # Write bandwidth from this memory (bytes/s) 6710944Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6910944Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1494255 # Write bandwidth from this memory (bytes/s) 7010944Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1493821 # Total bandwidth to/from this memory (bytes/s) 7110944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 1094 # Total bandwidth to/from this memory (bytes/s) 7210944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1021 # Total bandwidth to/from this memory (bytes/s) 7310944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 60637 # Total bandwidth to/from this memory (bytes/s) 7410944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 808384 # Total bandwidth to/from this memory (bytes/s) 7510944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 248161 # Total bandwidth to/from this memory (bytes/s) 7610944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3235 # Total bandwidth to/from this memory (bytes/s) 7710944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3452 # Total bandwidth to/from this memory (bytes/s) 7810944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 59562 # Total bandwidth to/from this memory (bytes/s) 7910944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 339685 # Total bandwidth to/from this memory (bytes/s) 8010944Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 237263 # Total bandwidth to/from this memory (bytes/s) 8110944Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9180 # Total bandwidth to/from this memory (bytes/s) 8210944Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3265496 # Total bandwidth to/from this memory (bytes/s) 8310944Sandreas.hansson@arm.comsystem.physmem.readReqs 1353915 # Number of read requests accepted 8410944Sandreas.hansson@arm.comsystem.physmem.writeReqs 1110258 # Number of write requests accepted 8510944Sandreas.hansson@arm.comsystem.physmem.readBursts 1353915 # Number of DRAM read bursts, including those serviced by the write queue 8610944Sandreas.hansson@arm.comsystem.physmem.writeBursts 1110258 # Number of DRAM write bursts, including those merged in the write queue 8710944Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 86619200 # Total number of bytes read from DRAM 8810944Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue 8910944Sandreas.hansson@arm.comsystem.physmem.bytesWritten 70911104 # Total number of bytes written to DRAM 9010944Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 84057220 # Total read bytes from the system interface side 9110944Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 70912360 # Total written bytes from the system interface side 9210944Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue 9310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 9410944Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 220771 # Number of requests that are neither read nor write 9510944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 83838 # Per bank write bursts 9610944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 89540 # Per bank write bursts 9710944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 77326 # Per bank write bursts 9810944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 81695 # Per bank write bursts 9910944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 84097 # Per bank write bursts 10010944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 94926 # Per bank write bursts 10110944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 83322 # Per bank write bursts 10210944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 86179 # Per bank write bursts 10310944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 76741 # Per bank write bursts 10410944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 125350 # Per bank write bursts 10510944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 75788 # Per bank write bursts 10610944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 81366 # Per bank write bursts 10710944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 76482 # Per bank write bursts 10810944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 81797 # Per bank write bursts 10910944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 77630 # Per bank write bursts 11010944Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 77348 # Per bank write bursts 11110944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 68540 # Per bank write bursts 11210944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 72321 # Per bank write bursts 11310944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 65671 # Per bank write bursts 11410944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 69464 # Per bank write bursts 11510944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 70371 # Per bank write bursts 11610944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 77894 # Per bank write bursts 11710944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 70312 # Per bank write bursts 11810944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 72647 # Per bank write bursts 11910944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 65746 # Per bank write bursts 12010944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 72323 # Per bank write bursts 12110944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 65450 # Per bank write bursts 12210944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 68291 # Per bank write bursts 12310944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 65769 # Per bank write bursts 12410944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 69040 # Per bank write bursts 12510944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 66651 # Per bank write bursts 12610944Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 67496 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12810944Sandreas.hansson@arm.comsystem.physmem.numWrRetry 71 # Number of times write queue was full causing retry 12910944Sandreas.hansson@arm.comsystem.physmem.totGap 47456676566000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13610944Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1310690 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14310944Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1107684 # Write request sizes (log2) 14410944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1123748 # What read queue length does an incoming req see 14510944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 74620 # What read queue length does an incoming req see 14610944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 32556 # What read queue length does an incoming req see 14710944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 27437 # What read queue length does an incoming req see 14810944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 23297 # What read queue length does an incoming req see 14910944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 20472 # What read queue length does an incoming req see 15010944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 17890 # What read queue length does an incoming req see 15110944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 14951 # What read queue length does an incoming req see 15210944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 12831 # What read queue length does an incoming req see 15310944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2528 # What read queue length does an incoming req see 15410944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 983 # What read queue length does an incoming req see 15510944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 550 # What read queue length does an incoming req see 15610944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 416 # What read queue length does an incoming req see 15710944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 288 # What read queue length does an incoming req see 15810944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 209 # What read queue length does an incoming req see 15910944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 175 # What read queue length does an incoming req see 16010944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 158 # What read queue length does an incoming req see 16110944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see 16210944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see 16310944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see 16410944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 16510944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 16610944Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 16710628SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19110944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 16504 # What write queue length does an incoming req see 19210944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 19352 # What write queue length does an incoming req see 19310944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 48877 # What write queue length does an incoming req see 19410944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 56560 # What write queue length does an incoming req see 19510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 60723 # What write queue length does an incoming req see 19610944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 62814 # What write queue length does an incoming req see 19710944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 63983 # What write queue length does an incoming req see 19810944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 67411 # What write queue length does an incoming req see 19910944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 68337 # What write queue length does an incoming req see 20010944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 71503 # What write queue length does an incoming req see 20110944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 71245 # What write queue length does an incoming req see 20210944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 72329 # What write queue length does an incoming req see 20310944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 70408 # What write queue length does an incoming req see 20410944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 71228 # What write queue length does an incoming req see 20510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 74472 # What write queue length does an incoming req see 20610944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 69249 # What write queue length does an incoming req see 20710944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 66307 # What write queue length does an incoming req see 20810944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 64601 # What write queue length does an incoming req see 20910944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1352 # What write queue length does an incoming req see 21010944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1011 # What write queue length does an incoming req see 21110944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see 21210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see 21310944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 616 # What write queue length does an incoming req see 21410944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 534 # What write queue length does an incoming req see 21510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 469 # What write queue length does an incoming req see 21610944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 470 # What write queue length does an incoming req see 21710944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 437 # What write queue length does an incoming req see 21810944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 403 # What write queue length does an incoming req see 21910944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 372 # What write queue length does an incoming req see 22010944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 344 # What write queue length does an incoming req see 22110944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 308 # What write queue length does an incoming req see 22210944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 386 # What write queue length does an incoming req see 22310944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 390 # What write queue length does an incoming req see 22410944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see 22510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see 22610944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see 22710944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 345 # What write queue length does an incoming req see 22810944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see 22910944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 285 # What write queue length does an incoming req see 23010944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 247 # What write queue length does an incoming req see 23110944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 283 # What write queue length does an incoming req see 23210944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see 23310944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 156 # What write queue length does an incoming req see 23410944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see 23510944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see 23610944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 109 # What write queue length does an incoming req see 23710944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 115 # What write queue length does an incoming req see 23810944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 100 # What write queue length does an incoming req see 23910944Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 238 # What write queue length does an incoming req see 24010944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 850568 # Bytes accessed per row activation 24110944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 185.205557 # Bytes accessed per row activation 24210944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 113.971853 # Bytes accessed per row activation 24310944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 243.835447 # Bytes accessed per row activation 24410944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 513606 60.38% 60.38% # Bytes accessed per row activation 24510944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 167161 19.65% 80.04% # Bytes accessed per row activation 24610944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 54824 6.45% 86.48% # Bytes accessed per row activation 24710944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 28166 3.31% 89.79% # Bytes accessed per row activation 24810944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 18449 2.17% 91.96% # Bytes accessed per row activation 24910944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 11525 1.35% 93.32% # Bytes accessed per row activation 25010944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 9338 1.10% 94.42% # Bytes accessed per row activation 25110944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 9545 1.12% 95.54% # Bytes accessed per row activation 25210944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 37954 4.46% 100.00% # Bytes accessed per row activation 25310944Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 850568 # Bytes accessed per row activation 25410944Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 62842 # Reads before turning the bus around for writes 25510944Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 21.536775 # Reads before turning the bus around for writes 25610944Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 323.180031 # Reads before turning the bus around for writes 25710944Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 62840 100.00% 100.00% # Reads before turning the bus around for writes 25810892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 26010944Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 62842 # Reads before turning the bus around for writes 26110944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 62842 # Writes before turning the bus around for reads 26210944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.631298 # Writes before turning the bus around for reads 26310944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.120021 # Writes before turning the bus around for reads 26410944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 6.777595 # Writes before turning the bus around for reads 26510944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 59398 94.52% 94.52% # Writes before turning the bus around for reads 26610944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 1045 1.66% 96.18% # Writes before turning the bus around for reads 26710944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 473 0.75% 96.94% # Writes before turning the bus around for reads 26810944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 210 0.33% 97.27% # Writes before turning the bus around for reads 26910944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 336 0.53% 97.80% # Writes before turning the bus around for reads 27010944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 469 0.75% 98.55% # Writes before turning the bus around for reads 27110944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 106 0.17% 98.72% # Writes before turning the bus around for reads 27210944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 34 0.05% 98.77% # Writes before turning the bus around for reads 27310944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 31 0.05% 98.82% # Writes before turning the bus around for reads 27410944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 28 0.04% 98.87% # Writes before turning the bus around for reads 27510944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 37 0.06% 98.93% # Writes before turning the bus around for reads 27610944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 34 0.05% 98.98% # Writes before turning the bus around for reads 27710944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 449 0.71% 99.69% # Writes before turning the bus around for reads 27810944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 44 0.07% 99.76% # Writes before turning the bus around for reads 27910944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 47 0.07% 99.84% # Writes before turning the bus around for reads 28010944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 32 0.05% 99.89% # Writes before turning the bus around for reads 28110944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 9 0.01% 99.90% # Writes before turning the bus around for reads 28210944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 28310944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 28410944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 4 0.01% 99.92% # Writes before turning the bus around for reads 28510944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads 28610944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads 28710944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads 28810892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 28910944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 26 0.04% 99.97% # Writes before turning the bus around for reads 29010944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 29110944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 4 0.01% 99.98% # Writes before turning the bus around for reads 29210944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 29310944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 29410944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 29510944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 29610944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 29710944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads 29810944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 29910944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads 30010944Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 62842 # Writes before turning the bus around for reads 30110944Sandreas.hansson@arm.comsystem.physmem.totQLat 31787428314 # Total ticks spent queuing 30210944Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 57164147064 # Total ticks spent from burst creation until serviced by the DRAM 30310944Sandreas.hansson@arm.comsystem.physmem.totBusLat 6767125000 # Total ticks spent in databus transfers 30410944Sandreas.hansson@arm.comsystem.physmem.avgQLat 23486.66 # Average queueing delay per DRAM burst 30510515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30610944Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 42236.66 # Average memory access latency per DRAM burst 30710944Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s 30810944Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s 30910944Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.77 # Average system read bandwidth in MiByte/s 31010944Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s 31110515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31210827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31310515SN/Asystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31410892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31510944Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing 31610944Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.28 # Average write queue length when enqueuing 31710944Sandreas.hansson@arm.comsystem.physmem.readRowHits 1086313 # Number of row buffer hits during reads 31810944Sandreas.hansson@arm.comsystem.physmem.writeRowHits 524528 # Number of row buffer hits during writes 31910944Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.26 # Row buffer hit rate for reads 32010944Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 47.34 # Row buffer hit rate for writes 32110944Sandreas.hansson@arm.comsystem.physmem.avgGap 19258662.67 # Average gap between requests 32210944Sandreas.hansson@arm.comsystem.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined 32310944Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3335290560 # Energy for activate commands per rank (pJ) 32410944Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1819851000 # Energy for precharge commands per rank (pJ) 32510944Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 5311160400 # Energy for read commands per rank (pJ) 32610944Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3675585600 # Energy for write commands per rank (pJ) 32710944Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) 32810944Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1204726391325 # Energy for active background per rank (pJ) 32910944Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27417225862500 # Energy for precharge background per rank (pJ) 33010944Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31735733267865 # Total energy per rank (pJ) 33110944Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.730691 # Core power per rank (mW) 33210944Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45610216470982 # Time in different power states 33310944Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1584682580000 # Time in different power states 33410628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33510944Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 261780130518 # Time in different power states 33610628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33710944Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3095003520 # Energy for activate commands per rank (pJ) 33810944Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1688742000 # Energy for precharge commands per rank (pJ) 33910944Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 5245507800 # Energy for read commands per rank (pJ) 34010944Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3504163680 # Energy for write commands per rank (pJ) 34110944Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) 34210944Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1191482148060 # Energy for active background per rank (pJ) 34310944Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27428843611500 # Energy for precharge background per rank (pJ) 34410944Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31733498303040 # Total energy per rank (pJ) 34510944Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.683596 # Core power per rank (mW) 34610944Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45629577337540 # Time in different power states 34710944Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1584682580000 # Time in different power states 34810628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34910944Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 242414504460 # Time in different power states 35010628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35110515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35210515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35310515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 35810515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 35910515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36010515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36110515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36210515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36310515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36410515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36510515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36610515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37710535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37810535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37910535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38010726SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38110726SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38210726SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38310515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41310944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 105954 # Table walker walks requested 41410944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 105954 # Table walker walks initiated with long descriptors 41510944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10115 # Level at which table walker walks with long descriptors terminate 41610944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80576 # Level at which table walker walks with long descriptors terminate 41710944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting 41810944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 105928 # Table walker wait (enqueue to first request) latency 41910944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.169927 # Table walker wait (enqueue to first request) latency 42010944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 55.305347 # Table walker wait (enqueue to first request) latency 42110944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 105927 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42210892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42310944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 105928 # Table walker wait (enqueue to first request) latency 42410944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency 42510944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570 # Table walker service (enqueue to completion) latency 42610944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281 # Table walker service (enqueue to completion) latency 42710944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942 # Table walker service (enqueue to completion) latency 42810944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 87482 96.43% 96.43% # Table walker service (enqueue to completion) latency 42910944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 2786 3.07% 99.51% # Table walker service (enqueue to completion) latency 43010944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 233 0.26% 99.76% # Table walker service (enqueue to completion) latency 43110944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 145 0.16% 99.92% # Table walker service (enqueue to completion) latency 43210944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 15 0.02% 99.94% # Table walker service (enqueue to completion) latency 43310944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 6 0.01% 99.94% # Table walker service (enqueue to completion) latency 43410944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 19 0.02% 99.97% # Table walker service (enqueue to completion) latency 43510944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency 43610944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 43710944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 43810944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 43910944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44010944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44110944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency 44210944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 9139568088 # Table walker pending requests distribution 44310944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 1.172115 # Table walker pending requests distribution 44410944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 -1573058396 -17.21% -17.21% # Table walker pending requests distribution 44510944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 10712626484 117.21% 100.00% # Table walker pending requests distribution 44610944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 9139568088 # Table walker pending requests distribution 44710944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 80577 88.85% 88.85% # Table walker page sizes translated 44810944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10115 11.15% 100.00% # Table walker page sizes translated 44910944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 90692 # Table walker page sizes translated 45010944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105954 # Table walker requests started/completed, data/inst 45110628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45210944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105954 # Table walker requests started/completed, data/inst 45310944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90692 # Table walker requests started/completed, data/inst 45410628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45510944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90692 # Table walker requests started/completed, data/inst 45610944Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 196646 # Table walker requests started/completed, data/inst 45710535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45810535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45910944Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 80457124 # DTB read hits 46010944Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 79863 # DTB read misses 46110944Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 72637408 # DTB write hits 46210944Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 26091 # DTB write misses 46310535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46410535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46510944Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 46610944Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 46710944Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 34410 # Number of entries that have been flushed from TLB 46810535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 46910944Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 3731 # Number of TLB faults due to prefetch 47010535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47110944Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 8741 # Number of TLB faults due to permissions restrictions 47210944Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 80536987 # DTB read accesses 47310944Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 72663499 # DTB write accesses 47410535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47510944Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 153094532 # DTB hits 47610944Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 105954 # DTB misses 47710944Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 153200486 # DTB accesses 47810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50710944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 53482 # Table walker walks requested 50810944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 53482 # Table walker walks initiated with long descriptors 50910944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 578 # Level at which table walker walks with long descriptors terminate 51010944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 47523 # Level at which table walker walks with long descriptors terminate 51110944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 53482 # Table walker wait (enqueue to first request) latency 51210944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 53482 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51310944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 53482 # Table walker wait (enqueue to first request) latency 51410944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 48101 # Table walker service (enqueue to completion) latency 51510944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 21551.932392 # Table walker service (enqueue to completion) latency 51610944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685 # Table walker service (enqueue to completion) latency 51710944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067 # Table walker service (enqueue to completion) latency 51810944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 45094 93.75% 93.75% # Table walker service (enqueue to completion) latency 51910944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 2542 5.28% 99.03% # Table walker service (enqueue to completion) latency 52010944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 133 0.28% 99.31% # Table walker service (enqueue to completion) latency 52110944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 277 0.58% 99.89% # Table walker service (enqueue to completion) latency 52210944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 5 0.01% 99.90% # Table walker service (enqueue to completion) latency 52310944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 6 0.01% 99.91% # Table walker service (enqueue to completion) latency 52410944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 18 0.04% 99.95% # Table walker service (enqueue to completion) latency 52510944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 2 0.00% 99.95% # Table walker service (enqueue to completion) latency 52610944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency 52710944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.98% # Table walker service (enqueue to completion) latency 52810944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 52910944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 53010944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 53110944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53210944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 48101 # Table walker service (enqueue to completion) latency 53310892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution 53410892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution 53510892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution 53610944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 47523 98.80% 98.80% # Table walker page sizes translated 53710944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 578 1.20% 100.00% # Table walker page sizes translated 53810944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 48101 # Table walker page sizes translated 53910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54010944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53482 # Table walker requests started/completed, data/inst 54110944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 53482 # Table walker requests started/completed, data/inst 54210628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54310944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48101 # Table walker requests started/completed, data/inst 54410944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 48101 # Table walker requests started/completed, data/inst 54510944Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 101583 # Table walker requests started/completed, data/inst 54610944Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 428491503 # ITB inst hits 54710944Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 53482 # ITB inst misses 54810535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54910535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 55010535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 55110535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 55210535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55310535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55410944Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 55510944Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 55610944Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24315 # Number of entries that have been flushed from TLB 55710535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55810535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55910535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56010535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56110535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 56210535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 56310944Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 428544985 # ITB inst accesses 56410944Sandreas.hansson@arm.comsystem.cpu0.itb.hits 428491503 # DTB hits 56510944Sandreas.hansson@arm.comsystem.cpu0.itb.misses 53482 # DTB misses 56610944Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 428544985 # DTB accesses 56710944Sandreas.hansson@arm.comsystem.cpu0.numCycles 94913359253 # number of cpu cycles simulated 56810535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56910535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 57010944Sandreas.hansson@arm.comsystem.cpu0.committedInsts 428232691 # Number of instructions committed 57110944Sandreas.hansson@arm.comsystem.cpu0.committedOps 502476550 # Number of ops (including micro ops) committed 57210944Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 461534262 # Number of integer alu accesses 57310944Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 406829 # Number of float alu accesses 57410944Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 25466680 # number of times a function call or return occured 57510944Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 64818437 # number of instructions that are conditional controls 57610944Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 461534262 # number of integer instructions 57710944Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 406829 # number of float instructions 57810944Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 668961319 # number of times the integer registers were read 57910944Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 366250009 # number of times the integer registers were written 58010944Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 674435 # number of times the floating registers were read 58110944Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 305880 # number of times the floating registers were written 58210944Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 111832425 # number of times the CC registers were read 58310944Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 111484776 # number of times the CC registers were written 58410944Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 153083738 # number of memory refs 58510944Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 80450777 # Number of load instructions 58610944Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 72632961 # Number of store instructions 58710944Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93826651579.898026 # Number of idle cycles 58810944Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1086707673.101977 # Number of busy cycles 58910944Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.011449 # Percentage of non-idle cycles 59010944Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.988551 # Percentage of idle cycles 59110944Sandreas.hansson@arm.comsystem.cpu0.Branches 95423987 # Number of branches fetched 59210944Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 59310944Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 348470598 69.31% 69.31% # Class of executed instruction 59410944Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1120076 0.22% 69.53% # Class of executed instruction 59510944Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 60052 0.01% 69.54% # Class of executed instruction 59610944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 59710944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 59810944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 59910944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 60010944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 60110944Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 60210944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 60310944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 60410944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 60510944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 60610944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 60710944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 60810944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 60910944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 61010944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 61110944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 61210944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 61310944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 61410944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 61510944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 61610944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 61710944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 61810944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 44021 0.01% 69.55% # Class of executed instruction 61910944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 62010944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 62110944Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 62210944Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 80450777 16.00% 85.55% # Class of executed instruction 62310944Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 72632961 14.45% 100.00% # Class of executed instruction 62410535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 62510535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62610944Sandreas.hansson@arm.comsystem.cpu0.op_class::total 502778486 # Class of executed instruction 62710535SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 62810944Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 14022 # number of quiesce instructions executed 62910944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5233253 # number of replacements 63010944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use 63110944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks. 63210944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5233765 # Sample count of references to valid blocks. 63310944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 28.202863 # Average number of references to valid blocks. 63410944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 3987157000 # Cycle when the warmup percentage was hit. 63510944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 480.798924 # Average occupied blocks per requestor 63610944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.939060 # Average percentage of cache occupancy 63710944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.939060 # Average percentage of cache occupancy 63810892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63910944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 64010944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 64110944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 64210892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 64310944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 311404737 # Number of tag accesses 64410944Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 311404737 # Number of data accesses 64510944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 74943991 # number of ReadReq hits 64610944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 74943991 # number of ReadReq hits 64710944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 68564818 # number of WriteReq hits 64810944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 68564818 # number of WriteReq hits 64910944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 176894 # number of SoftPFReq hits 65010944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 176894 # number of SoftPFReq hits 65110944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 135340 # number of WriteLineReq hits 65210944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 135340 # number of WriteLineReq hits 65310944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1719391 # number of LoadLockedReq hits 65410944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1719391 # number of LoadLockedReq hits 65510944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1677698 # number of StoreCondReq hits 65610944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1677698 # number of StoreCondReq hits 65710944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 143508809 # number of demand (read+write) hits 65810944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 143508809 # number of demand (read+write) hits 65910944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 143685703 # number of overall hits 66010944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 143685703 # number of overall hits 66110944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2840159 # number of ReadReq misses 66210944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 2840159 # number of ReadReq misses 66310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1279764 # number of WriteReq misses 66410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1279764 # number of WriteReq misses 66510944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 601589 # number of SoftPFReq misses 66610944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 601589 # number of SoftPFReq misses 66710944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 758772 # number of WriteLineReq misses 66810944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 758772 # number of WriteLineReq misses 66910944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148889 # number of LoadLockedReq misses 67010944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 148889 # number of LoadLockedReq misses 67110944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 188945 # number of StoreCondReq misses 67210944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 188945 # number of StoreCondReq misses 67310944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4119923 # number of demand (read+write) misses 67410944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4119923 # number of demand (read+write) misses 67510944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 4721512 # number of overall misses 67610944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 4721512 # number of overall misses 67710944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41012776500 # number of ReadReq miss cycles 67810944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 41012776500 # number of ReadReq miss cycles 67910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24489617000 # number of WriteReq miss cycles 68010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 24489617000 # number of WriteReq miss cycles 68110944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46337666000 # number of WriteLineReq miss cycles 68210944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 46337666000 # number of WriteLineReq miss cycles 68310944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2203666500 # number of LoadLockedReq miss cycles 68410944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2203666500 # number of LoadLockedReq miss cycles 68510944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4074419000 # number of StoreCondReq miss cycles 68610944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4074419000 # number of StoreCondReq miss cycles 68710944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2847000 # number of StoreCondFailReq miss cycles 68810944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2847000 # number of StoreCondFailReq miss cycles 68910944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 65502393500 # number of demand (read+write) miss cycles 69010944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 65502393500 # number of demand (read+write) miss cycles 69110944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 65502393500 # number of overall miss cycles 69210944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 65502393500 # number of overall miss cycles 69310944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 77784150 # number of ReadReq accesses(hits+misses) 69410944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 77784150 # number of ReadReq accesses(hits+misses) 69510944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 69844582 # number of WriteReq accesses(hits+misses) 69610944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 69844582 # number of WriteReq accesses(hits+misses) 69710944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 778483 # number of SoftPFReq accesses(hits+misses) 69810944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 778483 # number of SoftPFReq accesses(hits+misses) 69910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894112 # number of WriteLineReq accesses(hits+misses) 70010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 894112 # number of WriteLineReq accesses(hits+misses) 70110944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1868280 # number of LoadLockedReq accesses(hits+misses) 70210944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1868280 # number of LoadLockedReq accesses(hits+misses) 70310944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1866643 # number of StoreCondReq accesses(hits+misses) 70410944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1866643 # number of StoreCondReq accesses(hits+misses) 70510944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 147628732 # number of demand (read+write) accesses 70610944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 147628732 # number of demand (read+write) accesses 70710944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 148407215 # number of overall (read+write) accesses 70810944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 148407215 # number of overall (read+write) accesses 70910944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036513 # miss rate for ReadReq accesses 71010944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036513 # miss rate for ReadReq accesses 71110944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018323 # miss rate for WriteReq accesses 71210944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018323 # miss rate for WriteReq accesses 71310944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772771 # miss rate for SoftPFReq accesses 71410944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.772771 # miss rate for SoftPFReq accesses 71510944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.848632 # miss rate for WriteLineReq accesses 71610944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.848632 # miss rate for WriteLineReq accesses 71710944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079693 # miss rate for LoadLockedReq accesses 71810944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079693 # miss rate for LoadLockedReq accesses 71910944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101222 # miss rate for StoreCondReq accesses 72010944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.101222 # miss rate for StoreCondReq accesses 72110944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027907 # miss rate for demand accesses 72210944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027907 # miss rate for demand accesses 72310944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses 72410944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses 72510944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14440.310032 # average ReadReq miss latency 72610944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14440.310032 # average ReadReq miss latency 72710944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19136.041489 # average WriteReq miss latency 72810944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 19136.041489 # average WriteReq miss latency 72910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61069.288271 # average WriteLineReq miss latency 73010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61069.288271 # average WriteLineReq miss latency 73110944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14800.734104 # average LoadLockedReq miss latency 73210944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14800.734104 # average LoadLockedReq miss latency 73310944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21564.047739 # average StoreCondReq miss latency 73410944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21564.047739 # average StoreCondReq miss latency 73510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 73610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 73710944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339 # average overall miss latency 73810944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 15898.936339 # average overall miss latency 73910944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621 # average overall miss latency 74010944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 13873.181621 # average overall miss latency 74110535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 74210535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74310535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 74410535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 74510535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74710585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 74810535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 74910944Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3560219 # number of writebacks 75010944Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3560219 # number of writebacks 75110944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30162 # number of ReadReq MSHR hits 75210944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 30162 # number of ReadReq MSHR hits 75310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21215 # number of WriteReq MSHR hits 75410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21215 # number of WriteReq MSHR hits 75510944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39917 # number of LoadLockedReq MSHR hits 75610944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 39917 # number of LoadLockedReq MSHR hits 75710944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 51377 # number of demand (read+write) MSHR hits 75810944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 51377 # number of demand (read+write) MSHR hits 75910944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 51377 # number of overall MSHR hits 76010944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 51377 # number of overall MSHR hits 76110944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2809997 # number of ReadReq MSHR misses 76210944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2809997 # number of ReadReq MSHR misses 76310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1258549 # number of WriteReq MSHR misses 76410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1258549 # number of WriteReq MSHR misses 76510944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595949 # number of SoftPFReq MSHR misses 76610944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 595949 # number of SoftPFReq MSHR misses 76710944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 758772 # number of WriteLineReq MSHR misses 76810944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 758772 # number of WriteLineReq MSHR misses 76910944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108972 # number of LoadLockedReq MSHR misses 77010944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 108972 # number of LoadLockedReq MSHR misses 77110944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188945 # number of StoreCondReq MSHR misses 77210944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 188945 # number of StoreCondReq MSHR misses 77310944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4068546 # number of demand (read+write) MSHR misses 77410944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4068546 # number of demand (read+write) MSHR misses 77510944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4664495 # number of overall MSHR misses 77610944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4664495 # number of overall MSHR misses 77710944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable 77810944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 26231 # number of ReadReq MSHR uncacheable 77910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable 78010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable 78110944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses 78210944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 51684 # number of overall MSHR uncacheable misses 78310944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36991828000 # number of ReadReq MSHR miss cycles 78410944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 36991828000 # number of ReadReq MSHR miss cycles 78510944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22707525500 # number of WriteReq MSHR miss cycles 78610944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 22707525500 # number of WriteReq MSHR miss cycles 78710944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12844611500 # number of SoftPFReq MSHR miss cycles 78810944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12844611500 # number of SoftPFReq MSHR miss cycles 78910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45578894000 # number of WriteLineReq MSHR miss cycles 79010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45578894000 # number of WriteLineReq MSHR miss cycles 79110944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1445565000 # number of LoadLockedReq MSHR miss cycles 79210944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1445565000 # number of LoadLockedReq MSHR miss cycles 79310944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3885534000 # number of StoreCondReq MSHR miss cycles 79410944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3885534000 # number of StoreCondReq MSHR miss cycles 79510944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2787000 # number of StoreCondFailReq MSHR miss cycles 79610944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2787000 # number of StoreCondFailReq MSHR miss cycles 79710944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 59699353500 # number of demand (read+write) MSHR miss cycles 79810944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 59699353500 # number of demand (read+write) MSHR miss cycles 79910944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 72543965000 # number of overall MSHR miss cycles 80010944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 72543965000 # number of overall MSHR miss cycles 80110944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4455810500 # number of ReadReq MSHR uncacheable cycles 80210944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4455810500 # number of ReadReq MSHR uncacheable cycles 80310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4073355500 # number of WriteReq MSHR uncacheable cycles 80410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4073355500 # number of WriteReq MSHR uncacheable cycles 80510944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8529166000 # number of overall MSHR uncacheable cycles 80610944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 8529166000 # number of overall MSHR uncacheable cycles 80710944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036126 # mshr miss rate for ReadReq accesses 80810944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses 80910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018019 # mshr miss rate for WriteReq accesses 81010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses 81110944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765526 # mshr miss rate for SoftPFReq accesses 81210944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765526 # mshr miss rate for SoftPFReq accesses 81310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.848632 # mshr miss rate for WriteLineReq accesses 81410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.848632 # mshr miss rate for WriteLineReq accesses 81510944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058327 # mshr miss rate for LoadLockedReq accesses 81610944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058327 # mshr miss rate for LoadLockedReq accesses 81710944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101222 # mshr miss rate for StoreCondReq accesses 81810944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101222 # mshr miss rate for StoreCondReq accesses 81910944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027559 # mshr miss rate for demand accesses 82010944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.027559 # mshr miss rate for demand accesses 82110944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031430 # mshr miss rate for overall accesses 82210944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031430 # mshr miss rate for overall accesses 82310944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656 # average ReadReq mshr miss latency 82410944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656 # average ReadReq mshr miss latency 82510944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291 # average WriteReq mshr miss latency 82610944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291 # average WriteReq mshr miss latency 82710944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895 # average SoftPFReq mshr miss latency 82810944Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895 # average SoftPFReq mshr miss latency 82910944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271 # average WriteLineReq mshr miss latency 83010944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271 # average WriteLineReq mshr miss latency 83110944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864 # average LoadLockedReq mshr miss latency 83210944Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864 # average LoadLockedReq mshr miss latency 83310944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291 # average StoreCondReq mshr miss latency 83410944Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291 # average StoreCondReq mshr miss latency 83510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 83610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 83710944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864 # average overall mshr miss latency 83810944Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864 # average overall mshr miss latency 83910944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765 # average overall mshr miss latency 84010944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765 # average overall mshr miss latency 84110944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064 # average ReadReq mshr uncacheable latency 84210944Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064 # average ReadReq mshr uncacheable latency 84310944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731 # average WriteReq mshr uncacheable latency 84410944Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731 # average WriteReq mshr uncacheable latency 84510944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942 # average overall mshr uncacheable latency 84610944Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942 # average overall mshr uncacheable latency 84710535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84810944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 4666970 # number of replacements 84910944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.880807 # Cycle average of tags in use 85010944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 423824020 # Total number of references to valid blocks. 85110944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 4667482 # Sample count of references to valid blocks. 85210944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 90.803568 # Average number of references to valid blocks. 85310944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 42558943000 # Cycle when the warmup percentage was hit. 85410944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.880807 # Average occupied blocks per requestor 85510944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999767 # Average percentage of cache occupancy 85610944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999767 # Average percentage of cache occupancy 85710535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85810944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 85910944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 86010944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id 86110535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 86210944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 861650489 # Number of tag accesses 86310944Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 861650489 # Number of data accesses 86410944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 423824020 # number of ReadReq hits 86510944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 423824020 # number of ReadReq hits 86610944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 423824020 # number of demand (read+write) hits 86710944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 423824020 # number of demand (read+write) hits 86810944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 423824020 # number of overall hits 86910944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 423824020 # number of overall hits 87010944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4667483 # number of ReadReq misses 87110944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 4667483 # number of ReadReq misses 87210944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4667483 # number of demand (read+write) misses 87310944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 4667483 # number of demand (read+write) misses 87410944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4667483 # number of overall misses 87510944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 4667483 # number of overall misses 87610944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48694088500 # number of ReadReq miss cycles 87710944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 48694088500 # number of ReadReq miss cycles 87810944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 48694088500 # number of demand (read+write) miss cycles 87910944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 48694088500 # number of demand (read+write) miss cycles 88010944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 48694088500 # number of overall miss cycles 88110944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 48694088500 # number of overall miss cycles 88210944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 428491503 # number of ReadReq accesses(hits+misses) 88310944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 428491503 # number of ReadReq accesses(hits+misses) 88410944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 428491503 # number of demand (read+write) accesses 88510944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 428491503 # number of demand (read+write) accesses 88610944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 428491503 # number of overall (read+write) accesses 88710944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 428491503 # number of overall (read+write) accesses 88810944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010893 # miss rate for ReadReq accesses 88910944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010893 # miss rate for ReadReq accesses 89010944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010893 # miss rate for demand accesses 89110944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.010893 # miss rate for demand accesses 89210944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010893 # miss rate for overall accesses 89310944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.010893 # miss rate for overall accesses 89410944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572 # average ReadReq miss latency 89510944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572 # average ReadReq miss latency 89610944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency 89710944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10432.622572 # average overall miss latency 89810944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency 89910944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10432.622572 # average overall miss latency 90010535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 90110535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90210535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 90310535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 90410535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90510535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90610535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 90710535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 90810944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4667483 # number of ReadReq MSHR misses 90910944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4667483 # number of ReadReq MSHR misses 91010944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4667483 # number of demand (read+write) MSHR misses 91110944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4667483 # number of demand (read+write) MSHR misses 91210944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4667483 # number of overall MSHR misses 91310944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4667483 # number of overall MSHR misses 91410827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 91510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 91610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 91710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 91810944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 46360347000 # number of ReadReq MSHR miss cycles 91910944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 46360347000 # number of ReadReq MSHR miss cycles 92010944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 46360347000 # number of demand (read+write) MSHR miss cycles 92110944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 46360347000 # number of demand (read+write) MSHR miss cycles 92210944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 46360347000 # number of overall MSHR miss cycles 92310944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 46360347000 # number of overall MSHR miss cycles 92410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles 92510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles 92610892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles 92710892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles 92810944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for ReadReq accesses 92910944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010893 # mshr miss rate for ReadReq accesses 93010944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for demand accesses 93110944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010893 # mshr miss rate for demand accesses 93210944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for overall accesses 93310944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010893 # mshr miss rate for overall accesses 93410944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average ReadReq mshr miss latency 93510944Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.622572 # average ReadReq mshr miss latency 93610944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency 93710944Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency 93810944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency 93910944Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency 94010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency 94110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency 94210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency 94310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency 94410535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7039817 # number of hwpf issued 94610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7039817 # number of prefetch candidates identified 94710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 94810628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94910628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 95010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 925071 # number of prefetches not generated due to page crossing 95110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2212798 # number of replacements 95210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16140.904175 # Cycle average of tags in use 95310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 16304400 # Total number of references to valid blocks. 95410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2228972 # Sample count of references to valid blocks. 95510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 7.314762 # Average number of references to valid blocks. 95610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 38965596000 # Cycle when the warmup percentage was hit. 95710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 7022.512638 # Average occupied blocks per requestor 95810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.899316 # Average occupied blocks per requestor 95910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.792978 # Average occupied blocks per requestor 96010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3705.081021 # Average occupied blocks per requestor 96110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 4185.062005 # Average occupied blocks per requestor 96210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1103.556217 # Average occupied blocks per requestor 96310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.428620 # Average percentage of cache occupancy 96410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy 96510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003833 # Average percentage of cache occupancy 96610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226140 # Average percentage of cache occupancy 96710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.255436 # Average percentage of cache occupancy 96810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.067356 # Average percentage of cache occupancy 96910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.985163 # Average percentage of cache occupancy 97010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1459 # Occupied blocks per task id 97110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id 97210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id 97310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 97410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id 97510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 603 # Occupied blocks per task id 97610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id 97710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id 97810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id 97910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 98010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 98110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 957 # Occupied blocks per task id 98210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4495 # Occupied blocks per task id 98310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id 98410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id 98510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089050 # Percentage of cache occupancy per task id 98610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 98710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id 98810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 335472623 # Number of tag accesses 98910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 335472623 # Number of data accesses 99010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224520 # number of ReadReq hits 99110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122258 # number of ReadReq hits 99210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 346778 # number of ReadReq hits 99310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3560218 # number of Writeback hits 99410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3560218 # number of Writeback hits 99510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 92512 # number of UpgradeReq hits 99610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 92512 # number of UpgradeReq hits 99710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 28864 # number of SCUpgradeReq hits 99810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 28864 # number of SCUpgradeReq hits 99910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 829198 # number of ReadExReq hits 100010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 829198 # number of ReadExReq hits 100110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4185639 # number of ReadCleanReq hits 100210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4185639 # number of ReadCleanReq hits 100310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2620915 # number of ReadSharedReq hits 100410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2620915 # number of ReadSharedReq hits 100510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 197417 # number of InvalidateReq hits 100610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 197417 # number of InvalidateReq hits 100710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224520 # number of demand (read+write) hits 100810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 122258 # number of demand (read+write) hits 100910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4185639 # number of demand (read+write) hits 101010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3450113 # number of demand (read+write) hits 101110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 7982530 # number of demand (read+write) hits 101210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224520 # number of overall hits 101310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 122258 # number of overall hits 101410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4185639 # number of overall hits 101510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3450113 # number of overall hits 101610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 7982530 # number of overall hits 101710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8873 # number of ReadReq misses 101810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6826 # number of ReadReq misses 101910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 15699 # number of ReadReq misses 102010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 123328 # number of UpgradeReq misses 102110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 123328 # number of UpgradeReq misses 102210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160077 # number of SCUpgradeReq misses 102310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 160077 # number of SCUpgradeReq misses 102410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 102510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 102610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 230435 # number of ReadExReq misses 102710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 230435 # number of ReadExReq misses 102810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 481844 # number of ReadCleanReq misses 102910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 481844 # number of ReadCleanReq misses 103010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 894003 # number of ReadSharedReq misses 103110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 894003 # number of ReadSharedReq misses 103210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 560192 # number of InvalidateReq misses 103310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 560192 # number of InvalidateReq misses 103410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8873 # number of demand (read+write) misses 103510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 6826 # number of demand (read+write) misses 103610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 481844 # number of demand (read+write) misses 103710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1124438 # number of demand (read+write) misses 103810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1621981 # number of demand (read+write) misses 103910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8873 # number of overall misses 104010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 6826 # number of overall misses 104110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 481844 # number of overall misses 104210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1124438 # number of overall misses 104310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1621981 # number of overall misses 104410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 259670000 # number of ReadReq miss cycles 104510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 210027000 # number of ReadReq miss cycles 104610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 469697000 # number of ReadReq miss cycles 104710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2651049500 # number of UpgradeReq miss cycles 104810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2651049500 # number of UpgradeReq miss cycles 104910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3319563500 # number of SCUpgradeReq miss cycles 105010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3319563500 # number of SCUpgradeReq miss cycles 105110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2697000 # number of SCUpgradeFailReq miss cycles 105210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2697000 # number of SCUpgradeFailReq miss cycles 105310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11221935999 # number of ReadExReq miss cycles 105410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 11221935999 # number of ReadExReq miss cycles 105510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 14420808000 # number of ReadCleanReq miss cycles 105610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 14420808000 # number of ReadCleanReq miss cycles 105710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 28972230000 # number of ReadSharedReq miss cycles 105810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 28972230000 # number of ReadSharedReq miss cycles 105910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 43145750500 # number of InvalidateReq miss cycles 106010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 43145750500 # number of InvalidateReq miss cycles 106110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 259670000 # number of demand (read+write) miss cycles 106210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 210027000 # number of demand (read+write) miss cycles 106310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 14420808000 # number of demand (read+write) miss cycles 106410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 40194165999 # number of demand (read+write) miss cycles 106510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 55084670999 # number of demand (read+write) miss cycles 106610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 259670000 # number of overall miss cycles 106710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 210027000 # number of overall miss cycles 106810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 14420808000 # number of overall miss cycles 106910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 40194165999 # number of overall miss cycles 107010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 55084670999 # number of overall miss cycles 107110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 233393 # number of ReadReq accesses(hits+misses) 107210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 129084 # number of ReadReq accesses(hits+misses) 107310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 362477 # number of ReadReq accesses(hits+misses) 107410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3560218 # number of Writeback accesses(hits+misses) 107510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3560218 # number of Writeback accesses(hits+misses) 107610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 215840 # number of UpgradeReq accesses(hits+misses) 107710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 215840 # number of UpgradeReq accesses(hits+misses) 107810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188941 # number of SCUpgradeReq accesses(hits+misses) 107910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 188941 # number of SCUpgradeReq accesses(hits+misses) 108010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 108110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 108210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1059633 # number of ReadExReq accesses(hits+misses) 108310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1059633 # number of ReadExReq accesses(hits+misses) 108410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4667483 # number of ReadCleanReq accesses(hits+misses) 108510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4667483 # number of ReadCleanReq accesses(hits+misses) 108610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3514918 # number of ReadSharedReq accesses(hits+misses) 108710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3514918 # number of ReadSharedReq accesses(hits+misses) 108810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 757609 # number of InvalidateReq accesses(hits+misses) 108910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 757609 # number of InvalidateReq accesses(hits+misses) 109010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 233393 # number of demand (read+write) accesses 109110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 129084 # number of demand (read+write) accesses 109210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4667483 # number of demand (read+write) accesses 109310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4574551 # number of demand (read+write) accesses 109410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 9604511 # number of demand (read+write) accesses 109510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 233393 # number of overall (read+write) accesses 109610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 129084 # number of overall (read+write) accesses 109710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4667483 # number of overall (read+write) accesses 109810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4574551 # number of overall (read+write) accesses 109910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 9604511 # number of overall (read+write) accesses 110010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for ReadReq accesses 110110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052880 # miss rate for ReadReq accesses 110210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.043310 # miss rate for ReadReq accesses 110310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.571386 # miss rate for UpgradeReq accesses 110410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.571386 # miss rate for UpgradeReq accesses 110510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.847233 # miss rate for SCUpgradeReq accesses 110610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.847233 # miss rate for SCUpgradeReq accesses 110710535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110810535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 110910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217467 # miss rate for ReadExReq accesses 111010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.217467 # miss rate for ReadExReq accesses 111110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103234 # miss rate for ReadCleanReq accesses 111210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103234 # miss rate for ReadCleanReq accesses 111310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.254345 # miss rate for ReadSharedReq accesses 111410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.254345 # miss rate for ReadSharedReq accesses 111510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.739421 # miss rate for InvalidateReq accesses 111610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.739421 # miss rate for InvalidateReq accesses 111710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for demand accesses 111810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052880 # miss rate for demand accesses 111910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103234 # miss rate for demand accesses 112010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.245803 # miss rate for demand accesses 112110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.168877 # miss rate for demand accesses 112210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for overall accesses 112310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052880 # miss rate for overall accesses 112410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103234 # miss rate for overall accesses 112510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.245803 # miss rate for overall accesses 112610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.168877 # miss rate for overall accesses 112710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average ReadReq miss latency 112810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 30768.678582 # average ReadReq miss latency 112910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 29918.912033 # average ReadReq miss latency 113010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21495.925499 # average UpgradeReq miss latency 113110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21495.925499 # average UpgradeReq miss latency 113210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20737.292053 # average SCUpgradeReq miss latency 113310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20737.292053 # average SCUpgradeReq miss latency 113410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 674250 # average SCUpgradeFailReq miss latency 113510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 674250 # average SCUpgradeFailReq miss latency 113610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48698.921600 # average ReadExReq miss latency 113710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48698.921600 # average ReadExReq miss latency 113810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29928.375159 # average ReadCleanReq miss latency 113910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29928.375159 # average ReadCleanReq miss latency 114010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32407.307358 # average ReadSharedReq miss latency 114110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32407.307358 # average ReadSharedReq miss latency 114210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 77019.576324 # average InvalidateReq miss latency 114310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 77019.576324 # average InvalidateReq miss latency 114410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency 114510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency 114610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency 114710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency 114810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 33961.354047 # average overall miss latency 114910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency 115010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency 115110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency 115210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency 115310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 33961.354047 # average overall miss latency 115410628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 115510535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115610628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 115710535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 115810628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 115910535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 116010535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 116110535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 116210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1248318 # number of writebacks 116310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1248318 # number of writebacks 116410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3799 # number of ReadExReq MSHR hits 116510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 3799 # number of ReadExReq MSHR hits 116610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 319 # number of ReadSharedReq MSHR hits 116710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 319 # number of ReadSharedReq MSHR hits 116810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 4118 # number of demand (read+write) MSHR hits 116910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 4118 # number of demand (read+write) MSHR hits 117010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 4118 # number of overall MSHR hits 117110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 4118 # number of overall MSHR hits 117210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8873 # number of ReadReq MSHR misses 117310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6826 # number of ReadReq MSHR misses 117410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 15699 # number of ReadReq MSHR misses 117510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 86363 # number of CleanEvict MSHR misses 117610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::total 86363 # number of CleanEvict MSHR misses 117710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 615430 # 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number of ReadExReq MSHR misses 118610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 226636 # number of ReadExReq MSHR misses 118710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 481844 # number of ReadCleanReq MSHR misses 118810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 481844 # number of ReadCleanReq MSHR misses 118910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 893684 # number of ReadSharedReq MSHR misses 119010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 893684 # number of ReadSharedReq MSHR misses 119110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 560192 # number of InvalidateReq MSHR misses 119210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 560192 # number of InvalidateReq MSHR misses 119310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8873 # number of demand (read+write) MSHR misses 119410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6826 # number of demand (read+write) MSHR misses 119510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 481844 # number of demand (read+write) MSHR misses 119610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1120320 # number of demand (read+write) MSHR misses 119710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1617863 # number of demand (read+write) MSHR misses 119810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8873 # number of overall MSHR misses 119910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6826 # number of overall MSHR misses 120010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 481844 # number of overall MSHR misses 120110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1120320 # number of overall MSHR misses 120210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 615430 # number of overall MSHR misses 120310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2233293 # number of overall MSHR misses 120410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 120510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable 120610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 69356 # number of ReadReq MSHR uncacheable 120710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable 120810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable 120910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 121010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses 121110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 94809 # number of overall MSHR uncacheable misses 121210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of ReadReq MSHR miss cycles 121310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 169071000 # number of ReadReq MSHR miss cycles 121410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 375503000 # number of ReadReq MSHR miss cycles 121510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of HardPFReq MSHR miss cycles 121610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 25855371219 # number of HardPFReq MSHR miss cycles 121710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2504859500 # number of UpgradeReq MSHR miss cycles 121810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2504859500 # number of UpgradeReq MSHR miss cycles 121910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2454464000 # number of SCUpgradeReq MSHR miss cycles 122010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2454464000 # number of SCUpgradeReq MSHR miss cycles 122110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2337000 # number of SCUpgradeFailReq MSHR miss cycles 122210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2337000 # number of SCUpgradeFailReq MSHR miss cycles 122310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9468370499 # number of ReadExReq MSHR miss cycles 122410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9468370499 # number of ReadExReq MSHR miss cycles 122510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 11529744000 # number of ReadCleanReq MSHR miss cycles 122610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 11529744000 # number of ReadCleanReq MSHR miss cycles 122710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 23586536500 # number of ReadSharedReq MSHR miss cycles 122810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 23586536500 # number of ReadSharedReq MSHR miss cycles 122910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39784598500 # number of InvalidateReq MSHR miss cycles 123010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39784598500 # number of InvalidateReq MSHR miss cycles 123110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of demand (read+write) MSHR miss cycles 123210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 169071000 # number of demand (read+write) MSHR miss cycles 123310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11529744000 # number of demand (read+write) MSHR miss cycles 123410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 33054906999 # number of demand (read+write) MSHR miss cycles 123510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 44960153999 # number of demand (read+write) MSHR miss cycles 123610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of overall MSHR miss cycles 123710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 169071000 # number of overall MSHR miss cycles 123810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11529744000 # number of overall MSHR miss cycles 123910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 33054906999 # number of overall MSHR miss cycles 124010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of overall MSHR miss cycles 124110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 70815525218 # number of overall MSHR miss cycles 124210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of ReadReq MSHR uncacheable cycles 124310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4245962500 # number of ReadReq MSHR uncacheable cycles 124410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7700240000 # number of ReadReq MSHR uncacheable cycles 124510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3882458000 # number of WriteReq MSHR uncacheable cycles 124610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3882458000 # number of WriteReq MSHR uncacheable cycles 124710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of overall MSHR uncacheable cycles 124810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8128420500 # number of overall MSHR uncacheable cycles 124910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11582698000 # number of overall MSHR uncacheable cycles 125010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for ReadReq accesses 125110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for ReadReq accesses 125210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043310 # mshr miss rate for ReadReq accesses 125310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 125410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 125510535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 125610535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 125710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.571386 # mshr miss rate for UpgradeReq accesses 125810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.571386 # mshr miss rate for UpgradeReq accesses 125910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.847233 # mshr miss rate for SCUpgradeReq accesses 126010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.847233 # mshr miss rate for SCUpgradeReq accesses 126110535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 126210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 126310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213882 # mshr miss rate for ReadExReq accesses 126410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213882 # mshr miss rate for ReadExReq accesses 126510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for ReadCleanReq accesses 126610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103234 # mshr miss rate for ReadCleanReq accesses 126710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254255 # mshr miss rate for ReadSharedReq accesses 126810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254255 # mshr miss rate for ReadSharedReq accesses 126910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.739421 # mshr miss rate for InvalidateReq accesses 127010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.739421 # mshr miss rate for InvalidateReq accesses 127110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for demand accesses 127210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for demand accesses 127310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for demand accesses 127410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for demand accesses 127510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.168448 # mshr miss rate for demand accesses 127610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for overall accesses 127710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for overall accesses 127810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for overall accesses 127910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for overall accesses 128010535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 128110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.232525 # mshr miss rate for overall accesses 128210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average ReadReq mshr miss latency 128310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average ReadReq mshr miss latency 128410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033 # average ReadReq mshr miss latency 128510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average HardPFReq mshr miss latency 128610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855 # average HardPFReq mshr miss latency 128710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916 # average UpgradeReq mshr miss latency 128810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916 # average UpgradeReq mshr miss latency 128910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984 # average SCUpgradeReq mshr miss latency 129010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984 # average SCUpgradeReq mshr miss latency 129110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 584250 # average SCUpgradeFailReq mshr miss latency 129210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 584250 # average SCUpgradeFailReq mshr miss latency 129310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090 # average ReadExReq mshr miss latency 129410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090 # average ReadExReq mshr miss latency 129510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average ReadCleanReq mshr miss latency 129610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159 # average ReadCleanReq mshr miss latency 129710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333 # average ReadSharedReq mshr miss latency 129810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333 # average ReadSharedReq mshr miss latency 129910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324 # average InvalidateReq mshr miss latency 130010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324 # average InvalidateReq mshr miss latency 130110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency 130210944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency 130310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency 130410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency 130510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054 # average overall mshr miss latency 130610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency 130710944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency 130810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency 130910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency 131010944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average overall mshr miss latency 131110944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783 # average overall mshr miss latency 131210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency 131310944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064 # average ReadReq mshr uncacheable latency 131410944Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258 # average ReadReq mshr uncacheable latency 131510944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731 # average WriteReq mshr uncacheable latency 131610944Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731 # average WriteReq mshr uncacheable latency 131710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency 131810944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688 # average overall mshr uncacheable latency 131910944Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350 # average overall mshr uncacheable latency 132010535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 132110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 548810 # Transaction distribution 132210944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 8811478 # Transaction distribution 132310944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 132410944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 25453 # Transaction distribution 132510944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 6868539 # Transaction distribution 132610944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 8637410 # Transaction distribution 132710944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 769123 # Transaction distribution 132810944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 445989 # Transaction distribution 132910944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution 133010944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 473125 # Transaction distribution 133110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution 133210944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 133310944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1446257 # Transaction distribution 133410944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1069406 # Transaction distribution 133510944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4667483 # Transaction distribution 133610944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5564741 # Transaction distribution 133710944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 864337 # Transaction distribution 133810944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 757609 # Transaction distribution 133910944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14087759 # Packet count per connected master and slave (bytes) 134010944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16981197 # Packet count per connected master and slave (bytes) 134110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 288818 # Packet count per connected master and slave (bytes) 134210944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 540500 # Packet count per connected master and slave (bytes) 134310944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 31898274 # Packet count per connected master and slave (bytes) 134410944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 298891412 # Cumulative packet size per connected master and slave (bytes) 134510944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 527370978 # Cumulative packet size per connected master and slave (bytes) 134610944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1032672 # Cumulative packet size per connected master and slave (bytes) 134710944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1867144 # Cumulative packet size per connected master and slave (bytes) 134810944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 829162206 # Cumulative packet size per connected master and slave (bytes) 134910944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 9613339 # Total snoops (count) 135010944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 30204161 # Request fanout histogram 135110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.324614 # Request fanout histogram 135210944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.468231 # Request fanout histogram 135310535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135410535SN/Asystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 135510944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 20399459 67.54% 67.54% # Request fanout histogram 135610944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 9804702 32.46% 100.00% # Request fanout histogram 135710535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 135810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 135910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 136010944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 30204161 # Request fanout histogram 136110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 14006094999 # Layer occupancy (ticks) 136210535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 136310944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 188261483 # Layer occupancy (ticks) 136410535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136510944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7044349500 # Layer occupancy (ticks) 136610535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 136710944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7482254107 # Layer occupancy (ticks) 136810535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 136910944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 159734000 # Layer occupancy (ticks) 137010535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 137110944Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 307107000 # Layer occupancy (ticks) 137210535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 137310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 137410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 137510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 137610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 138010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 138110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 138210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 138310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 138410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 139010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 139110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 139210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 139310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 139410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 139510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 139710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 139910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 140010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 140110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 140210944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 101352 # Table walker walks requested 140310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 101352 # Table walker walks initiated with long descriptors 140410944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8872 # Level at which table walker walks with long descriptors terminate 140510944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77968 # Level at which table walker walks with long descriptors terminate 140610944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting 140710944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 101349 # Table walker wait (enqueue to first request) latency 140810944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.078935 # Table walker wait (enqueue to first request) latency 140910944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 25.129292 # Table walker wait (enqueue to first request) latency 141010944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 101348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141110892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 141210944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 101349 # Table walker wait (enqueue to first request) latency 141310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 86843 # Table walker service (enqueue to completion) latency 141410944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874 # Table walker service (enqueue to completion) latency 141510944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286 # Table walker service (enqueue to completion) latency 141610944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789 # Table walker service (enqueue to completion) latency 141710944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 85298 98.22% 98.22% # Table walker service (enqueue to completion) latency 141810944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1315 1.51% 99.74% # Table walker service (enqueue to completion) latency 141910944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 45 0.05% 99.79% # Table walker service (enqueue to completion) latency 142010944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 84 0.10% 99.88% # Table walker service (enqueue to completion) latency 142110944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 70 0.08% 99.96% # Table walker service (enqueue to completion) latency 142210944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.99% # Table walker service (enqueue to completion) latency 142310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 142410944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142510944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 142610944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142710944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 86843 # Table walker service (enqueue to completion) latency 142810944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -857364308 # Table walker pending requests distribution 142910944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean -0.833676 # Table walker pending requests distribution 143010944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1572128036 183.37% 183.37% # Table walker pending requests distribution 143110944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 714763728 -83.37% 100.00% # Table walker pending requests distribution 143210944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -857364308 # Table walker pending requests distribution 143310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 77968 89.78% 89.78% # Table walker page sizes translated 143410944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 8872 10.22% 100.00% # Table walker page sizes translated 143510944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 86840 # Table walker page sizes translated 143610944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101352 # Table walker requests started/completed, data/inst 143710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143810944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101352 # Table walker requests started/completed, data/inst 143910944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86840 # Table walker requests started/completed, data/inst 144010628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144110944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86840 # Table walker requests started/completed, data/inst 144210944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 188192 # Table walker requests started/completed, data/inst 144310535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 144410535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 144510944Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 82714274 # DTB read hits 144610944Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 74721 # DTB read misses 144710944Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 75460503 # DTB write hits 144810944Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 26631 # DTB write misses 144910535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 145010535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145110944Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 145210944Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 145310944Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 38549 # Number of entries that have been flushed from TLB 145410535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 145510944Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4418 # Number of TLB faults due to prefetch 145610535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145710944Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10567 # Number of TLB faults due to permissions restrictions 145810944Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 82788995 # DTB read accesses 145910944Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 75487134 # DTB write accesses 146010535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 146110944Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 158174777 # DTB hits 146210944Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 101352 # DTB misses 146310944Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 158276129 # DTB accesses 146410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 146610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 146810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 147110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 147210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 147310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 147410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 147510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 147610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 147710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 147810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 148210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 148310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 148410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 148510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 148610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 148710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 148810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 148910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 149010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 149110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 149210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 149310944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 60693 # Table walker walks requested 149410944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 60693 # Table walker walks initiated with long descriptors 149510944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 593 # Level at which table walker walks with long descriptors terminate 149610944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 54830 # Level at which table walker walks with long descriptors terminate 149710944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60693 # Table walker wait (enqueue to first request) latency 149810944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60693 100.00% 100.00% # Table walker wait (enqueue to first request) latency 149910944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60693 # Table walker wait (enqueue to first request) latency 150010944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 55423 # Table walker service (enqueue to completion) latency 150110944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 24648.566480 # Table walker service (enqueue to completion) latency 150210944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042 # Table walker service (enqueue to completion) latency 150310944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821 # Table walker service (enqueue to completion) latency 150410944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 49924 90.08% 90.08% # Table walker service (enqueue to completion) latency 150510944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 3716 6.70% 96.78% # Table walker service (enqueue to completion) latency 150610944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 553 1.00% 97.78% # Table walker service (enqueue to completion) latency 150710944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 965 1.74% 99.52% # Table walker service (enqueue to completion) latency 150810944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.06% 99.58% # Table walker service (enqueue to completion) latency 150910944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.63% # Table walker service (enqueue to completion) latency 151010944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 86 0.16% 99.78% # Table walker service (enqueue to completion) latency 151110944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 15 0.03% 99.81% # Table walker service (enqueue to completion) latency 151210944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 45 0.08% 99.89% # Table walker service (enqueue to completion) latency 151310944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 26 0.05% 99.94% # Table walker service (enqueue to completion) latency 151410944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.96% # Table walker service (enqueue to completion) latency 151510944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 12 0.02% 99.98% # Table walker service (enqueue to completion) latency 151610944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 151710944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 151810944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 151910944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 152010944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 55423 # Table walker service (enqueue to completion) latency 152110944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1656015036 # Table walker pending requests distribution 152210944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1656015036 100.00% 100.00% # Table walker pending requests distribution 152310944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1656015036 # Table walker pending requests distribution 152410944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54830 98.93% 98.93% # Table walker page sizes translated 152510944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 593 1.07% 100.00% # Table walker page sizes translated 152610944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55423 # Table walker page sizes translated 152710628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152810944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60693 # Table walker requests started/completed, data/inst 152910944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60693 # Table walker requests started/completed, data/inst 153010628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 153110944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55423 # Table walker requests started/completed, data/inst 153210944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55423 # Table walker requests started/completed, data/inst 153310944Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 116116 # Table walker requests started/completed, data/inst 153410944Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 437193188 # ITB inst hits 153510944Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 60693 # ITB inst misses 153610535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 153710535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 153810535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 153910535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 154010535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 154110535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 154210944Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID 154310944Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID 154410944Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 27130 # Number of entries that have been flushed from TLB 154510535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 154610535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154710535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154810535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154910535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 155010535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 155110944Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 437253881 # ITB inst accesses 155210944Sandreas.hansson@arm.comsystem.cpu1.itb.hits 437193188 # DTB hits 155310944Sandreas.hansson@arm.comsystem.cpu1.itb.misses 60693 # DTB misses 155410944Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 437253881 # DTB accesses 155510944Sandreas.hansson@arm.comsystem.cpu1.numCycles 94913359253 # number of cpu cycles simulated 155610535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 155710535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 155810944Sandreas.hansson@arm.comsystem.cpu1.committedInsts 436909780 # Number of instructions committed 155910944Sandreas.hansson@arm.comsystem.cpu1.committedOps 515262081 # Number of ops (including micro ops) committed 156010944Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 474007520 # Number of integer alu accesses 156110944Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 488695 # Number of float alu accesses 156210944Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 26553696 # number of times a function call or return occured 156310944Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 66234119 # number of instructions that are conditional controls 156410944Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 474007520 # number of integer instructions 156510944Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 488695 # number of float instructions 156610944Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 687449190 # number of times the integer registers were read 156710944Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 375811208 # number of times the integer registers were written 156810944Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 781283 # number of times the floating registers were read 156910944Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 430208 # number of times the floating registers were written 157010944Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 112572477 # number of times the CC registers were read 157110944Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 112287439 # number of times the CC registers were written 157210944Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 158166235 # number of memory refs 157310944Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 82712263 # Number of load instructions 157410944Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 75453972 # Number of store instructions 157510944Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93876093406.586029 # Number of idle cycles 157610944Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1037265846.413978 # Number of busy cycles 157710944Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.010929 # Percentage of non-idle cycles 157810944Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.989071 # Percentage of idle cycles 157910944Sandreas.hansson@arm.comsystem.cpu1.Branches 97493416 # Number of branches fetched 158010944Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 158110944Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 356171607 69.09% 69.09% # Class of executed instruction 158210944Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1079497 0.21% 69.30% # Class of executed instruction 158310944Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 59940 0.01% 69.31% # Class of executed instruction 158410944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.31% # Class of executed instruction 158510944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.31% # Class of executed instruction 158610944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.31% # Class of executed instruction 158710944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction 158810944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction 158910944Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.31% # Class of executed instruction 159010944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.31% # Class of executed instruction 159110944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.31% # Class of executed instruction 159210944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.31% # Class of executed instruction 159310944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.31% # Class of executed instruction 159410944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.31% # Class of executed instruction 159510944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.31% # Class of executed instruction 159610944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.31% # Class of executed instruction 159710944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.31% # Class of executed instruction 159810944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.31% # Class of executed instruction 159910944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.31% # Class of executed instruction 160010944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.31% # Class of executed instruction 160110944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.31% # Class of executed instruction 160210944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.31% # Class of executed instruction 160310944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.31% # Class of executed instruction 160410944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.31% # Class of executed instruction 160510944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.31% # Class of executed instruction 160610944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 68277 0.01% 69.32% # Class of executed instruction 160710944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.32% # Class of executed instruction 160810944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.32% # Class of executed instruction 160910944Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.32% # Class of executed instruction 161010944Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 82712263 16.04% 85.36% # Class of executed instruction 161110944Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 75453972 14.64% 100.00% # Class of executed instruction 161210535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 161310535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 161410944Sandreas.hansson@arm.comsystem.cpu1.op_class::total 515545598 # Class of executed instruction 161510535SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 161610944Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5256 # number of quiesce instructions executed 161710944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5176711 # number of replacements 161810944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use 161910944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks. 162010944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5177218 # Sample count of references to valid blocks. 162110944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.515202 # Average number of references to valid blocks. 162210944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8391490917000 # Cycle when the warmup percentage was hit. 162310944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 457.282743 # Average occupied blocks per requestor 162410944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.893130 # Average percentage of cache occupancy 162510944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.893130 # Average percentage of cache occupancy 162610944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id 162710944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 162810944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 162910944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id 163010944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id 163110944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 321544722 # Number of tag accesses 163210944Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 321544722 # Number of data accesses 163310944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 77092949 # number of ReadReq hits 163410944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 77092949 # number of ReadReq hits 163510944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 71608224 # number of WriteReq hits 163610944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 71608224 # number of WriteReq hits 163710944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 188155 # number of SoftPFReq hits 163810944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 188155 # number of SoftPFReq hits 163910944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 187532 # number of WriteLineReq hits 164010944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 187532 # number of WriteLineReq hits 164110944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684198 # number of LoadLockedReq hits 164210944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1684198 # number of LoadLockedReq hits 164310944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1657450 # number of StoreCondReq hits 164410944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1657450 # number of StoreCondReq hits 164510944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 148701173 # number of demand (read+write) hits 164610944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 148701173 # number of demand (read+write) hits 164710944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 148889328 # number of overall hits 164810944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 148889328 # number of overall hits 164910944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2950342 # number of ReadReq misses 165010944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2950342 # number of ReadReq misses 165110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1305907 # number of WriteReq misses 165210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1305907 # number of WriteReq misses 165310944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 613815 # number of SoftPFReq misses 165410944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 613815 # number of SoftPFReq misses 165510944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 479868 # number of WriteLineReq misses 165610944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 479868 # number of WriteLineReq misses 165710944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172330 # number of LoadLockedReq misses 165810944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 172330 # number of LoadLockedReq misses 165910944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 197330 # number of StoreCondReq misses 166010944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 197330 # number of StoreCondReq misses 166110944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4256249 # number of demand (read+write) misses 166210944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4256249 # number of demand (read+write) misses 166310944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 4870064 # number of overall misses 166410944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 4870064 # number of overall misses 166510944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42135771000 # number of ReadReq miss cycles 166610944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 42135771000 # number of ReadReq miss cycles 166710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22153910000 # number of WriteReq miss cycles 166810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 22153910000 # number of WriteReq miss cycles 166910944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 15218762000 # number of WriteLineReq miss cycles 167010944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 15218762000 # number of WriteLineReq miss cycles 167110944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2580362000 # number of LoadLockedReq miss cycles 167210944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2580362000 # number of LoadLockedReq miss cycles 167310944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4225919000 # number of StoreCondReq miss cycles 167410944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4225919000 # number of StoreCondReq miss cycles 167510944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2953000 # number of StoreCondFailReq miss cycles 167610944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2953000 # number of StoreCondFailReq miss cycles 167710944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 64289681000 # number of demand (read+write) miss cycles 167810944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 64289681000 # number of demand (read+write) miss cycles 167910944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 64289681000 # number of overall miss cycles 168010944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 64289681000 # number of overall miss cycles 168110944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 80043291 # number of ReadReq accesses(hits+misses) 168210944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 80043291 # number of ReadReq accesses(hits+misses) 168310944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 72914131 # number of WriteReq accesses(hits+misses) 168410944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 72914131 # number of WriteReq accesses(hits+misses) 168510944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 801970 # number of SoftPFReq accesses(hits+misses) 168610944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 801970 # number of SoftPFReq accesses(hits+misses) 168710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 667400 # number of WriteLineReq accesses(hits+misses) 168810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 667400 # number of WriteLineReq accesses(hits+misses) 168910944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1856528 # number of LoadLockedReq accesses(hits+misses) 169010944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1856528 # number of LoadLockedReq accesses(hits+misses) 169110944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1854780 # number of StoreCondReq accesses(hits+misses) 169210944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1854780 # number of StoreCondReq accesses(hits+misses) 169310944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 152957422 # number of demand (read+write) accesses 169410944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 152957422 # number of demand (read+write) accesses 169510944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 153759392 # number of overall (read+write) accesses 169610944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 153759392 # number of overall (read+write) accesses 169710944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036859 # miss rate for ReadReq accesses 169810944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036859 # miss rate for ReadReq accesses 169910944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017910 # miss rate for WriteReq accesses 170010944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses 170110944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765384 # miss rate for SoftPFReq accesses 170210944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.765384 # miss rate for SoftPFReq accesses 170310944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.719011 # miss rate for WriteLineReq accesses 170410944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.719011 # miss rate for WriteLineReq accesses 170510944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092824 # miss rate for LoadLockedReq accesses 170610944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092824 # miss rate for LoadLockedReq accesses 170710944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106390 # miss rate for StoreCondReq accesses 170810944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.106390 # miss rate for StoreCondReq accesses 170910944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027826 # miss rate for demand accesses 171010944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses 171110944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031673 # miss rate for overall accesses 171210944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031673 # miss rate for overall accesses 171310944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499 # average ReadReq miss latency 171410944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499 # average ReadReq miss latency 171510944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672 # average WriteReq miss latency 171610944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672 # average WriteReq miss latency 171710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647 # average WriteLineReq miss latency 171810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647 # average WriteLineReq miss latency 171910944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661 # average LoadLockedReq miss latency 172010944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661 # average LoadLockedReq miss latency 172110944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816 # average StoreCondReq miss latency 172210944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816 # average StoreCondReq miss latency 172310535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 172410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 172510944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415 # average overall miss latency 172610944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 15104.774415 # average overall miss latency 172710944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046 # average overall miss latency 172810944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 13200.993046 # average overall miss latency 172910535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173010535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173110535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173210535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 173310535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173410535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173510585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 173610535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 173710944Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3350646 # number of writebacks 173810944Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3350646 # number of writebacks 173910944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17552 # number of ReadReq MSHR hits 174010944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 17552 # number of ReadReq MSHR hits 174110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 421 # number of WriteReq MSHR hits 174210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 421 # number of WriteReq MSHR hits 174310944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45020 # number of LoadLockedReq MSHR hits 174410944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 45020 # number of LoadLockedReq MSHR hits 174510944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 17973 # number of demand (read+write) MSHR hits 174610944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 17973 # number of demand (read+write) MSHR hits 174710944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 17973 # number of overall MSHR hits 174810944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 17973 # number of overall MSHR hits 174910944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932790 # number of ReadReq MSHR misses 175010944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2932790 # number of ReadReq MSHR misses 175110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1305486 # number of WriteReq MSHR misses 175210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1305486 # number of WriteReq MSHR misses 175310944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 613815 # number of SoftPFReq MSHR misses 175410944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 613815 # number of SoftPFReq MSHR misses 175510944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 479868 # number of WriteLineReq MSHR misses 175610944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 479868 # number of WriteLineReq MSHR misses 175710944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127310 # number of LoadLockedReq MSHR misses 175810944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 127310 # number of LoadLockedReq MSHR misses 175910944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 197330 # number of StoreCondReq MSHR misses 176010944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 197330 # number of StoreCondReq MSHR misses 176110944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4238276 # number of demand (read+write) MSHR misses 176210944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4238276 # number of demand (read+write) MSHR misses 176310944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4852091 # number of overall MSHR misses 176410944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4852091 # number of overall MSHR misses 176510944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable 176610944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 12503 # number of ReadReq MSHR uncacheable 176710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable 176810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable 176910944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses 177010944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 25653 # number of overall MSHR uncacheable misses 177110944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38342874000 # number of ReadReq MSHR miss cycles 177210944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 38342874000 # number of ReadReq MSHR miss cycles 177310944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20834838000 # number of WriteReq MSHR miss cycles 177410944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 20834838000 # number of WriteReq MSHR miss cycles 177510944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12333914500 # number of SoftPFReq MSHR miss cycles 177610944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12333914500 # number of SoftPFReq MSHR miss cycles 177710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14738894000 # number of WriteLineReq MSHR miss cycles 177810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14738894000 # number of WriteLineReq MSHR miss cycles 177910944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690256500 # number of LoadLockedReq MSHR miss cycles 178010944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690256500 # number of LoadLockedReq MSHR miss cycles 178110944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4028650000 # number of StoreCondReq MSHR miss cycles 178210944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4028650000 # number of StoreCondReq MSHR miss cycles 178310944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2892000 # number of StoreCondFailReq MSHR miss cycles 178410944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2892000 # number of StoreCondFailReq MSHR miss cycles 178510944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59177712000 # number of demand (read+write) MSHR miss cycles 178610944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 59177712000 # number of demand (read+write) MSHR miss cycles 178710944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71511626500 # number of overall MSHR miss cycles 178810944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 71511626500 # number of overall MSHR miss cycles 178910944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2070021000 # number of ReadReq MSHR uncacheable cycles 179010944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2070021000 # number of ReadReq MSHR uncacheable cycles 179110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2282534000 # number of WriteReq MSHR uncacheable cycles 179210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2282534000 # number of WriteReq MSHR uncacheable cycles 179310944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4352555000 # number of overall MSHR uncacheable cycles 179410944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 4352555000 # number of overall MSHR uncacheable cycles 179510944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036640 # mshr miss rate for ReadReq accesses 179610944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036640 # mshr miss rate for ReadReq accesses 179710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017904 # mshr miss rate for WriteReq accesses 179810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017904 # mshr miss rate for WriteReq accesses 179910944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765384 # mshr miss rate for SoftPFReq accesses 180010944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765384 # mshr miss rate for SoftPFReq accesses 180110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.719011 # mshr miss rate for WriteLineReq accesses 180210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.719011 # mshr miss rate for WriteLineReq accesses 180310944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068574 # mshr miss rate for LoadLockedReq accesses 180410944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068574 # mshr miss rate for LoadLockedReq accesses 180510944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106390 # mshr miss rate for StoreCondReq accesses 180610944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106390 # mshr miss rate for StoreCondReq accesses 180710944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027709 # mshr miss rate for demand accesses 180810944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027709 # mshr miss rate for demand accesses 180910944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031556 # mshr miss rate for overall accesses 181010944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031556 # mshr miss rate for overall accesses 181110944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953 # average ReadReq mshr miss latency 181210944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953 # average ReadReq mshr miss latency 181310944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584 # average WriteReq mshr miss latency 181410944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584 # average WriteReq mshr miss latency 181510944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972 # average SoftPFReq mshr miss latency 181610944Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972 # average SoftPFReq mshr miss latency 181710944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647 # average WriteLineReq mshr miss latency 181810944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647 # average WriteLineReq mshr miss latency 181910944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610 # average LoadLockedReq mshr miss latency 182010944Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610 # average LoadLockedReq mshr miss latency 182110944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943 # average StoreCondReq mshr miss latency 182210944Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943 # average StoreCondReq mshr miss latency 182310535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 182410535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 182510944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828 # average overall mshr miss latency 182610944Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828 # average overall mshr miss latency 182710944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070 # average overall mshr miss latency 182810944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070 # average overall mshr miss latency 182910944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133 # average ReadReq mshr uncacheable latency 183010944Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133 # average ReadReq mshr uncacheable latency 183110944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038 # average WriteReq mshr uncacheable latency 183210944Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038 # average WriteReq mshr uncacheable latency 183310944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919 # average overall mshr uncacheable latency 183410944Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919 # average overall mshr uncacheable latency 183510535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 183610944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 5209177 # number of replacements 183710944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.272261 # Cycle average of tags in use 183810944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 431983494 # Total number of references to valid blocks. 183910944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 5209689 # Sample count of references to valid blocks. 184010944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 82.919248 # Average number of references to valid blocks. 184110944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8391463454000 # Cycle when the warmup percentage was hit. 184210944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.272261 # Average occupied blocks per requestor 184310944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969282 # Average percentage of cache occupancy 184410944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969282 # Average percentage of cache occupancy 184510535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 184610944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 184710944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 184810944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 440 # Occupied blocks per task id 184910944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 185010535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 185110944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 879596070 # Number of tag accesses 185210944Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 879596070 # Number of data accesses 185310944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 431983494 # number of ReadReq hits 185410944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 431983494 # number of ReadReq hits 185510944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 431983494 # number of demand (read+write) hits 185610944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 431983494 # number of demand (read+write) hits 185710944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 431983494 # number of overall hits 185810944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 431983494 # number of overall hits 185910944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5209694 # number of ReadReq misses 186010944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 5209694 # number of ReadReq misses 186110944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5209694 # number of demand (read+write) misses 186210944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 5209694 # number of demand (read+write) misses 186310944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5209694 # number of overall misses 186410944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 5209694 # number of overall misses 186510944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53989351000 # number of ReadReq miss cycles 186610944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 53989351000 # number of ReadReq miss cycles 186710944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 53989351000 # number of demand (read+write) miss cycles 186810944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 53989351000 # number of demand (read+write) miss cycles 186910944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 53989351000 # number of overall miss cycles 187010944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 53989351000 # number of overall miss cycles 187110944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 437193188 # number of ReadReq accesses(hits+misses) 187210944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 437193188 # number of ReadReq accesses(hits+misses) 187310944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 437193188 # number of demand (read+write) accesses 187410944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 437193188 # number of demand (read+write) accesses 187510944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 437193188 # number of overall (read+write) accesses 187610944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 437193188 # number of overall (read+write) accesses 187710944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011916 # miss rate for ReadReq accesses 187810944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011916 # miss rate for ReadReq accesses 187910944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011916 # miss rate for demand accesses 188010944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011916 # miss rate for demand accesses 188110944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011916 # miss rate for overall accesses 188210944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011916 # miss rate for overall accesses 188310944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014 # average ReadReq miss latency 188410944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014 # average ReadReq miss latency 188510944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency 188610944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10363.248014 # average overall miss latency 188710944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency 188810944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10363.248014 # average overall miss latency 188910535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 189010535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 189110535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 189210535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 189310535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189410535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 189510535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 189610535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 189710944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5209694 # number of ReadReq MSHR misses 189810944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5209694 # number of ReadReq MSHR misses 189910944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5209694 # number of demand (read+write) MSHR misses 190010944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5209694 # number of demand (read+write) MSHR misses 190110944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5209694 # number of overall MSHR misses 190210944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5209694 # number of overall MSHR misses 190310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 190410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 190510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 190610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 190710944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51384504000 # number of ReadReq MSHR miss cycles 190810944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 51384504000 # number of ReadReq MSHR miss cycles 190910944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51384504000 # number of demand (read+write) MSHR miss cycles 191010944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 51384504000 # number of demand (read+write) MSHR miss cycles 191110944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51384504000 # number of overall MSHR miss cycles 191210944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 51384504000 # number of overall MSHR miss cycles 191310944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9739500 # number of ReadReq MSHR uncacheable cycles 191410944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9739500 # number of ReadReq MSHR uncacheable cycles 191510944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9739500 # number of overall MSHR uncacheable cycles 191610944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 9739500 # number of overall MSHR uncacheable cycles 191710944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for ReadReq accesses 191810944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011916 # mshr miss rate for ReadReq accesses 191910944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for demand accesses 192010944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011916 # mshr miss rate for demand accesses 192110944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for overall accesses 192210944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011916 # mshr miss rate for overall accesses 192310944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average ReadReq mshr miss latency 192410944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9863.248014 # average ReadReq mshr miss latency 192510944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency 192610944Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency 192710944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency 192810944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency 192910944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average ReadReq mshr uncacheable latency 193010944Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091 # average ReadReq mshr uncacheable latency 193110944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average overall mshr uncacheable latency 193210944Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091 # average overall mshr uncacheable latency 193310535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 193410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7168932 # number of hwpf issued 193510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7168932 # number of prefetch candidates identified 193610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 193710628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 193810628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 193910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 888356 # number of prefetches not generated due to page crossing 194010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2018400 # number of replacements 194110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13471.145620 # Cycle average of tags in use 194210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 17736817 # Total number of references to valid blocks. 194310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2034046 # Sample count of references to valid blocks. 194410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 8.719968 # Average number of references to valid blocks. 194510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9876432033500 # Cycle when the warmup percentage was hit. 194610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5731.708202 # Average occupied blocks per requestor 194710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.533292 # Average occupied blocks per requestor 194810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 100.125774 # Average occupied blocks per requestor 194910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3516.826700 # Average occupied blocks per requestor 195010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3218.371115 # Average occupied blocks per requestor 195110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 832.580536 # Average occupied blocks per requestor 195210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.349836 # Average percentage of cache occupancy 195310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004366 # Average percentage of cache occupancy 195410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006111 # Average percentage of cache occupancy 195510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.214650 # Average percentage of cache occupancy 195610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196434 # Average percentage of cache occupancy 195710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050817 # Average percentage of cache occupancy 195810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.822213 # Average percentage of cache occupancy 195910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1631 # Occupied blocks per task id 196010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id 196110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id 196210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id 196310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id 196410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id 196510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 196610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 196710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 196810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 196910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id 197010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2682 # Occupied blocks per task id 197110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6101 # Occupied blocks per task id 197210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5119 # Occupied blocks per task id 197310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099548 # Percentage of cache occupancy per task id 197410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id 197510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id 197610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 350300692 # Number of tag accesses 197710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 350300692 # Number of data accesses 197810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 208719 # number of ReadReq hits 197910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141350 # number of ReadReq hits 198010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 350069 # number of ReadReq hits 198110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3350644 # number of Writeback hits 198210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3350644 # number of Writeback hits 198310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65287 # number of UpgradeReq hits 198410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 65287 # number of UpgradeReq hits 198510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34260 # number of SCUpgradeReq hits 198610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 34260 # number of SCUpgradeReq hits 198710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 879078 # number of ReadExReq hits 198810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 879078 # number of ReadExReq hits 198910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4680645 # number of ReadCleanReq hits 199010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4680645 # number of ReadCleanReq hits 199110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2771065 # number of ReadSharedReq hits 199210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2771065 # number of ReadSharedReq hits 199310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 220708 # number of InvalidateReq hits 199410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 220708 # number of InvalidateReq hits 199510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 208719 # number of demand (read+write) hits 199610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 141350 # number of demand (read+write) hits 199710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4680645 # number of demand (read+write) hits 199810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3650143 # number of demand (read+write) hits 199910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8680857 # number of demand (read+write) hits 200010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 208719 # number of overall hits 200110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 141350 # number of overall hits 200210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4680645 # number of overall hits 200310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3650143 # number of overall hits 200410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8680857 # number of overall hits 200510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10729 # number of ReadReq misses 200610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9390 # number of ReadReq misses 200710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 20119 # number of ReadReq misses 200810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 125786 # number of UpgradeReq misses 200910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 125786 # number of UpgradeReq misses 201010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 163059 # number of SCUpgradeReq misses 201110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 163059 # number of SCUpgradeReq misses 201210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses 201310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 201410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 237067 # number of ReadExReq misses 201510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 237067 # number of ReadExReq misses 201610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 529049 # number of ReadCleanReq misses 201710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 529049 # number of ReadCleanReq misses 201810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 902850 # number of ReadSharedReq misses 201910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 902850 # number of ReadSharedReq misses 202010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 257687 # number of InvalidateReq misses 202110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 257687 # number of InvalidateReq misses 202210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10729 # number of demand (read+write) misses 202310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9390 # number of demand (read+write) misses 202410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 529049 # number of demand (read+write) misses 202510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1139917 # number of demand (read+write) misses 202610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1689085 # number of demand (read+write) misses 202710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10729 # number of overall misses 202810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9390 # number of overall misses 202910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 529049 # number of overall misses 203010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1139917 # number of overall misses 203110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1689085 # number of overall misses 203210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 428489500 # number of ReadReq miss cycles 203310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 413569000 # number of ReadReq miss cycles 203410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 842058500 # number of ReadReq miss cycles 203510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2736210500 # number of UpgradeReq miss cycles 203610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2736210500 # number of UpgradeReq miss cycles 203710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3427875000 # number of SCUpgradeReq miss cycles 203810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3427875000 # number of SCUpgradeReq miss cycles 203910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2800500 # number of SCUpgradeFailReq miss cycles 204010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2800500 # number of SCUpgradeFailReq miss cycles 204110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9388085997 # number of ReadExReq miss cycles 204210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9388085997 # number of ReadExReq miss cycles 204310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15677246500 # number of ReadCleanReq miss cycles 204410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 15677246500 # number of ReadCleanReq miss cycles 204510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28842829500 # number of ReadSharedReq miss cycles 204610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 28842829500 # number of ReadSharedReq miss cycles 204710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 12565083500 # number of InvalidateReq miss cycles 204810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 12565083500 # number of InvalidateReq miss cycles 204910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 428489500 # number of demand (read+write) miss cycles 205010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 413569000 # number of demand (read+write) miss cycles 205110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 15677246500 # number of demand (read+write) miss cycles 205210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 38230915497 # number of demand (read+write) miss cycles 205310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 54750220497 # number of demand (read+write) miss cycles 205410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 428489500 # number of overall miss cycles 205510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 413569000 # number of overall miss cycles 205610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 15677246500 # number of overall miss cycles 205710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 38230915497 # number of overall miss cycles 205810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 54750220497 # number of overall miss cycles 205910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 219448 # number of ReadReq accesses(hits+misses) 206010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150740 # number of ReadReq accesses(hits+misses) 206110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 370188 # number of ReadReq accesses(hits+misses) 206210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3350644 # number of Writeback accesses(hits+misses) 206310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3350644 # number of Writeback accesses(hits+misses) 206410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 191073 # number of UpgradeReq accesses(hits+misses) 206510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 191073 # number of UpgradeReq accesses(hits+misses) 206610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 197319 # number of SCUpgradeReq accesses(hits+misses) 206710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 197319 # number of SCUpgradeReq accesses(hits+misses) 206810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 206910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 207010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116145 # number of ReadExReq accesses(hits+misses) 207110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1116145 # number of ReadExReq accesses(hits+misses) 207210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5209694 # number of ReadCleanReq accesses(hits+misses) 207310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5209694 # number of ReadCleanReq accesses(hits+misses) 207410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3673915 # number of ReadSharedReq accesses(hits+misses) 207510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3673915 # number of ReadSharedReq accesses(hits+misses) 207610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 478395 # number of InvalidateReq accesses(hits+misses) 207710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 478395 # number of InvalidateReq accesses(hits+misses) 207810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 219448 # number of demand (read+write) accesses 207910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150740 # number of demand (read+write) accesses 208010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5209694 # number of demand (read+write) accesses 208110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4790060 # number of demand (read+write) accesses 208210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10369942 # number of demand (read+write) accesses 208310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 219448 # number of overall (read+write) accesses 208410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150740 # number of overall (read+write) accesses 208510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5209694 # number of overall (read+write) accesses 208610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4790060 # number of overall (read+write) accesses 208710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10369942 # number of overall (read+write) accesses 208810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for ReadReq accesses 208910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.062293 # miss rate for ReadReq accesses 209010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.054348 # miss rate for ReadReq accesses 209110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.658314 # miss rate for UpgradeReq accesses 209210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.658314 # miss rate for UpgradeReq accesses 209310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826373 # miss rate for SCUpgradeReq accesses 209410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826373 # miss rate for SCUpgradeReq accesses 209510535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 209610535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 209710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.212398 # miss rate for ReadExReq accesses 209810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.212398 # miss rate for ReadExReq accesses 209910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.101551 # miss rate for ReadCleanReq accesses 210010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.101551 # miss rate for ReadCleanReq accesses 210110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245746 # miss rate for ReadSharedReq accesses 210210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245746 # miss rate for ReadSharedReq accesses 210310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.538649 # miss rate for InvalidateReq accesses 210410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.538649 # miss rate for InvalidateReq accesses 210510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for demand accesses 210610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.062293 # miss rate for demand accesses 210710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.101551 # miss rate for demand accesses 210810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.237976 # miss rate for demand accesses 210910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.162883 # miss rate for demand accesses 211010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for overall accesses 211110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.062293 # miss rate for overall accesses 211210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.101551 # miss rate for overall accesses 211310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.237976 # miss rate for overall accesses 211410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.162883 # miss rate for overall accesses 211510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average ReadReq miss latency 211610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44043.556976 # average ReadReq miss latency 211710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 41853.894329 # average ReadReq miss latency 211810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21752.901754 # average UpgradeReq miss latency 211910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21752.901754 # average UpgradeReq miss latency 212010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21022.298677 # average SCUpgradeReq miss latency 212110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21022.298677 # average SCUpgradeReq miss latency 212210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 254590.909091 # average SCUpgradeFailReq miss latency 212310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 254590.909091 # average SCUpgradeFailReq miss latency 212410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39600.981988 # average ReadExReq miss latency 212510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39600.981988 # average ReadExReq miss latency 212610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 29632.881831 # average ReadCleanReq miss latency 212710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 29632.881831 # average ReadCleanReq miss latency 212810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31946.424655 # average ReadSharedReq miss latency 212910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31946.424655 # average ReadSharedReq miss latency 213010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 48761.029854 # average InvalidateReq miss latency 213110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 48761.029854 # average InvalidateReq miss latency 213210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency 213310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency 213410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency 213510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency 213610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 32414.129838 # average overall miss latency 213710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency 213810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency 213910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency 214010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency 214110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 32414.129838 # average overall miss latency 214210628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 214310535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214410628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 214510535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 214610628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 214710535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 214810535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 214910535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 215010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 952252 # number of writebacks 215110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 952252 # number of writebacks 215210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3771 # number of ReadExReq MSHR hits 215310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 3771 # number of ReadExReq MSHR hits 215410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 320 # number of ReadSharedReq MSHR hits 215510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 320 # number of ReadSharedReq MSHR hits 215610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4091 # number of demand (read+write) MSHR hits 215710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4091 # number of demand (read+write) MSHR hits 215810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4091 # number of overall MSHR hits 215910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4091 # number of overall MSHR hits 216010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10729 # number of ReadReq MSHR misses 216110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9390 # number of ReadReq MSHR misses 216210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 20119 # number of ReadReq MSHR misses 216310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 95458 # number of CleanEvict MSHR misses 216410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::total 95458 # number of CleanEvict MSHR misses 216510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 646749 # number of HardPFReq MSHR misses 216610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 646749 # number of HardPFReq MSHR misses 216710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 125786 # number of UpgradeReq MSHR misses 216810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 125786 # number of UpgradeReq MSHR misses 216910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 163059 # number of SCUpgradeReq MSHR misses 217010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 163059 # number of SCUpgradeReq MSHR misses 217110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses 217210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 217310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 233296 # number of ReadExReq MSHR misses 217410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 233296 # number of ReadExReq MSHR misses 217510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 529049 # number of ReadCleanReq MSHR misses 217610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 529049 # number of ReadCleanReq MSHR misses 217710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 902530 # number of ReadSharedReq MSHR misses 217810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 902530 # number of ReadSharedReq MSHR misses 217910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 257687 # number of InvalidateReq MSHR misses 218010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 257687 # number of InvalidateReq MSHR misses 218110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10729 # number of demand (read+write) MSHR misses 218210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9390 # number of demand (read+write) MSHR misses 218310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 529049 # number of demand (read+write) MSHR misses 218410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135826 # number of demand (read+write) MSHR misses 218510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1684994 # number of demand (read+write) MSHR misses 218610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10729 # number of overall MSHR misses 218710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9390 # number of overall MSHR misses 218810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 529049 # number of overall MSHR misses 218910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135826 # number of overall MSHR misses 219010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 646749 # number of overall MSHR misses 219110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2331743 # number of overall MSHR misses 219210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 219310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable 219410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 12613 # number of ReadReq MSHR uncacheable 219510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable 219610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable 219710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 219810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses 219910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25763 # number of overall MSHR uncacheable misses 220010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of ReadReq MSHR miss cycles 220110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 357229000 # number of ReadReq MSHR miss cycles 220210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 721344500 # number of ReadReq MSHR miss cycles 220310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 24507257017 # number of HardPFReq MSHR miss cycles 220410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 24507257017 # number of HardPFReq MSHR miss cycles 220510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2611582999 # number of UpgradeReq MSHR miss cycles 220610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2611582999 # number of UpgradeReq MSHR miss cycles 220710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2531997500 # number of SCUpgradeReq MSHR miss cycles 220810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2531997500 # number of SCUpgradeReq MSHR miss cycles 220910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2434500 # number of SCUpgradeFailReq MSHR miss cycles 221010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2434500 # number of SCUpgradeFailReq MSHR miss cycles 221110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7622486997 # number of ReadExReq MSHR miss cycles 221210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7622486997 # number of ReadExReq MSHR miss cycles 221310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12502952500 # number of ReadCleanReq MSHR miss cycles 221410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12502952500 # number of ReadCleanReq MSHR miss cycles 221510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23395380000 # number of ReadSharedReq MSHR miss cycles 221610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23395380000 # number of ReadSharedReq MSHR miss cycles 221710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11018961500 # number of InvalidateReq MSHR miss cycles 221810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11018961500 # number of InvalidateReq MSHR miss cycles 221910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of demand (read+write) MSHR miss cycles 222010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 357229000 # number of demand (read+write) MSHR miss cycles 222110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12502952500 # number of demand (read+write) MSHR miss cycles 222210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31017866997 # number of demand (read+write) MSHR miss cycles 222310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 44242163997 # number of demand (read+write) MSHR miss cycles 222410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of overall MSHR miss cycles 222510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 357229000 # number of overall MSHR miss cycles 222610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12502952500 # number of overall MSHR miss cycles 222710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31017866997 # number of overall MSHR miss cycles 222810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24507257017 # number of overall MSHR miss cycles 222910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 68749421014 # number of overall MSHR miss cycles 223010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8914500 # number of ReadReq MSHR uncacheable cycles 223110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1969997000 # number of ReadReq MSHR uncacheable cycles 223210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1978911500 # number of ReadReq MSHR uncacheable cycles 223310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2183909000 # number of WriteReq MSHR uncacheable cycles 223410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2183909000 # number of WriteReq MSHR uncacheable cycles 223510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8914500 # number of overall MSHR uncacheable cycles 223610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4153906000 # number of overall MSHR uncacheable cycles 223710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4162820500 # number of overall MSHR uncacheable cycles 223810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for ReadReq accesses 223910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for ReadReq accesses 224010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.054348 # mshr miss rate for ReadReq accesses 224110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 224210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 224310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 224410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 224510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.658314 # mshr miss rate for UpgradeReq accesses 224610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.658314 # mshr miss rate for UpgradeReq accesses 224710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826373 # mshr miss rate for SCUpgradeReq accesses 224810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826373 # mshr miss rate for SCUpgradeReq accesses 224910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 225010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 225110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.209019 # mshr miss rate for ReadExReq accesses 225210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.209019 # mshr miss rate for ReadExReq accesses 225310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for ReadCleanReq accesses 225410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101551 # mshr miss rate for ReadCleanReq accesses 225510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245659 # mshr miss rate for ReadSharedReq accesses 225610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245659 # mshr miss rate for ReadSharedReq accesses 225710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.538649 # mshr miss rate for InvalidateReq accesses 225810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.538649 # mshr miss rate for InvalidateReq accesses 225910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for demand accesses 226010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for demand accesses 226110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for demand accesses 226210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for demand accesses 226310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.162488 # mshr miss rate for demand accesses 226410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for overall accesses 226510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for overall accesses 226610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for overall accesses 226710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for overall accesses 226810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 226910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.224856 # mshr miss rate for overall accesses 227010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average ReadReq mshr miss latency 227110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average ReadReq mshr miss latency 227210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329 # average ReadReq mshr miss latency 227310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average HardPFReq mshr miss latency 227410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609 # average HardPFReq mshr miss latency 227510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833 # average UpgradeReq mshr miss latency 227610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833 # average UpgradeReq mshr miss latency 227710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391 # average SCUpgradeReq mshr miss latency 227810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391 # average SCUpgradeReq mshr miss latency 227910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818 # average SCUpgradeFailReq mshr miss latency 228010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818 # average SCUpgradeFailReq mshr miss latency 228110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100 # average ReadExReq mshr miss latency 228210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100 # average ReadExReq mshr miss latency 228310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average ReadCleanReq mshr miss latency 228410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831 # average ReadCleanReq mshr miss latency 228510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053 # average ReadSharedReq mshr miss latency 228610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053 # average ReadSharedReq mshr miss latency 228710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854 # average InvalidateReq mshr miss latency 228810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854 # average InvalidateReq mshr miss latency 228910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency 229010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency 229110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency 229210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency 229310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645 # average overall mshr miss latency 229410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency 229510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency 229610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency 229710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency 229810944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average overall mshr miss latency 229910944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120 # average overall mshr miss latency 230010944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average ReadReq mshr uncacheable latency 230110944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133 # average ReadReq mshr uncacheable latency 230210944Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880 # average ReadReq mshr uncacheable latency 230310944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038 # average WriteReq mshr uncacheable latency 230410944Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038 # average WriteReq mshr uncacheable latency 230510944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average overall mshr uncacheable latency 230610944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224 # average overall mshr uncacheable latency 230710944Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985 # average overall mshr uncacheable latency 230810535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 230910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 557907 # Transaction distribution 231010944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9467454 # Transaction distribution 231110944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 231210944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 13150 # Transaction distribution 231310944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 6658964 # Transaction distribution 231410944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 9333240 # Transaction distribution 231510944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 797552 # Transaction distribution 231610944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 400874 # Transaction distribution 231710944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 357340 # Transaction distribution 231810944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 454404 # Transaction distribution 231910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution 232010944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 232110944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1816504 # Transaction distribution 232210944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1125838 # Transaction distribution 232310944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5209694 # Transaction distribution 232410944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 5632852 # Transaction distribution 232510944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 585123 # Transaction distribution 232610944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 478395 # Transaction distribution 232710944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15628224 # Packet count per connected master and slave (bytes) 232810944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16712375 # Packet count per connected master and slave (bytes) 232910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332083 # Packet count per connected master and slave (bytes) 233010944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 514043 # Packet count per connected master and slave (bytes) 233110944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 33186725 # Packet count per connected master and slave (bytes) 233210944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333420856 # Cumulative packet size per connected master and slave (bytes) 233310944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 527793939 # Cumulative packet size per connected master and slave (bytes) 233410944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205920 # Cumulative packet size per connected master and slave (bytes) 233510944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1755584 # Cumulative packet size per connected master and slave (bytes) 233610944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 864176299 # Cumulative packet size per connected master and slave (bytes) 233710944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 9912470 # Total snoops (count) 233810944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 31389750 # Request fanout histogram 233910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.322129 # Request fanout histogram 234010944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.467292 # Request fanout histogram 234110535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 234210535SN/Asystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 234310944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 21278201 67.79% 67.79% # Request fanout histogram 234410944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 10111549 32.21% 100.00% # Request fanout histogram 234510535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 234610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 234710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 234810944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 31389750 # Request fanout histogram 234910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 14234291993 # Layer occupancy (ticks) 235010535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 235110944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 190598993 # Layer occupancy (ticks) 235210535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 235310944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7814651000 # Layer occupancy (ticks) 235410535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 235510944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7637949368 # Layer occupancy (ticks) 235610535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 235710944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 181343000 # Layer occupancy (ticks) 235810535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 235910944Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 294595499 # Layer occupancy (ticks) 236010535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 236110944Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40360 # Transaction distribution 236210944Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40360 # Transaction distribution 236310892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136623 # Transaction distribution 236410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136623 # Transaction distribution 236510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes) 236610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 236710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 236810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 236910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 237010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 237110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 237210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 237310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 237410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 237510726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 237710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 237810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 237910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 238010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes) 238110944Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) 238210944Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) 238310535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 238410535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 238510944Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) 238610892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes) 238710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 238810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 238910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 239010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 239110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 239510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239610726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 239710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 239810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 239910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 240010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 240110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes) 240210944Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) 240310944Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) 240410535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 240510535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 240610944Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496887 # Cumulative packet size per connected master and slave (bytes) 240710892Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks) 240810535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 240910535SN/Asystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 241010535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 241110535SN/Asystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 241210535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 241310535SN/Asystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 241410535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 241510535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 241610535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 241710535SN/Asystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 241810535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 241910535SN/Asystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 242010535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 242110535SN/Asystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 242210535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 242310535SN/Asystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 242410535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 242510535SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 242610535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 242710726SN/Asystem.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 242810535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 242910535SN/Asystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 243010535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 243110535SN/Asystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 243210535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 243310535SN/Asystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 243410535SN/Asystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 243510944Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 569839842 # Layer occupancy (ticks) 243610535SN/Asystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 243710535SN/Asystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 243810535SN/Asystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 243910892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks) 244010535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 244110944Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) 244210535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 244310892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 244410535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 244510944Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115629 # number of replacements 244610944Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.301329 # Cycle average of tags in use 244710535SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 244810944Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115645 # Sample count of references to valid blocks. 244910535SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 245010944Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9148621285000 # Cycle when the warmup percentage was hit. 245110944Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.403816 # Average occupied blocks per requestor 245210944Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.897512 # Average occupied blocks per requestor 245310944Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.462739 # Average percentage of cache occupancy 245410944Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.243595 # Average percentage of cache occupancy 245510944Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706333 # Average percentage of cache occupancy 245610535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 245710535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 245810535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 245910944Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1041045 # Number of tag accesses 246010944Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1041045 # Number of data accesses 246110535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 246210944Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses 246310944Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8941 # number of ReadReq misses 246410535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 246510535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 246610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 246710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 246810535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 246910944Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses 247010944Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8944 # number of demand (read+write) misses 247110535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 247210944Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8904 # number of overall misses 247310944Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8944 # number of overall misses 247410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 247510944Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1656855076 # number of ReadReq miss cycles 247610944Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1662050076 # number of ReadReq miss cycles 247710726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 247810726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 247910944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12632251766 # number of WriteLineReq miss cycles 248010944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12632251766 # number of WriteLineReq miss cycles 248110892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 248210944Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1656855076 # number of demand (read+write) miss cycles 248310944Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1662419076 # number of demand (read+write) miss cycles 248410892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 248510944Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1656855076 # number of overall miss cycles 248610944Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1662419076 # number of overall miss cycles 248710535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 248810944Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) 248910944Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) 249010535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 249110535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 249210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 249310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 249410535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 249510944Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses 249610944Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses 249710535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 249810944Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses 249910944Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses 250010535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 250110535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 250210535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 250310535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 250410535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 250510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 250610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 250710535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 250810535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 250910535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 251010535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 251110535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 251210535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 251310892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 251410944Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288 # average ReadReq miss latency 251510944Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 185890.848451 # average ReadReq miss latency 251610726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 251710726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 251810944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707 # average WriteLineReq miss latency 251910944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118359.303707 # average WriteLineReq miss latency 252010892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 252110944Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency 252210944Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 185869.753578 # average overall miss latency 252310892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 252410944Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency 252510944Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 185869.753578 # average overall miss latency 252610944Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 32671 # number of cycles access was blocked 252710535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252810944Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked 252910535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 253010944Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.525073 # average number of cycles each access was blocked 253110535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253210585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 253310535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 253410944Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106695 # number of writebacks 253510944Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106695 # number of writebacks 253610535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 253710944Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses 253810944Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses 253910535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 254010535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 254110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 254210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 254310535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 254410944Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses 254510944Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses 254610535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 254710944Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses 254810944Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses 254910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 255010944Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1211655076 # number of ReadReq MSHR miss cycles 255110944Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1215000076 # number of ReadReq MSHR miss cycles 255210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 255310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 255410944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7295851766 # number of WriteLineReq MSHR miss cycles 255510944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7295851766 # number of WriteLineReq MSHR miss cycles 255610892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 255710944Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1211655076 # number of demand (read+write) MSHR miss cycles 255810944Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1215219076 # number of demand (read+write) MSHR miss cycles 255910892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 256010944Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1211655076 # number of overall MSHR miss cycles 256110944Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1215219076 # number of overall MSHR miss cycles 256210535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 256310535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 256410535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 256510535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 256610535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 256710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 256810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 256910535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 257010535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 257110535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 257210535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 257310535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 257410535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 257510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 257610944Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288 # average ReadReq mshr miss latency 257710944Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451 # average ReadReq mshr miss latency 257810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 257910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 258010944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707 # average WriteLineReq mshr miss latency 258110944Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707 # average WriteLineReq mshr miss latency 258210892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 258310944Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency 258410944Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency 258510892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 258610944Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency 258710944Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency 258810535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 258910944Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1275038 # number of replacements 259010944Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63572.316878 # Cycle average of tags in use 259110944Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4892898 # Total number of references to valid blocks. 259210944Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1334308 # Sample count of references to valid blocks. 259310944Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.666993 # Average number of references to valid blocks. 259410892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 259510944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 18943.726739 # Average occupied blocks per requestor 259610944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 66.506889 # Average occupied blocks per requestor 259710944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 88.082899 # Average occupied blocks per requestor 259810944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3576.388780 # Average occupied blocks per requestor 259910944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 7769.332592 # Average occupied blocks per requestor 260010944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6333.160086 # Average occupied blocks per requestor 260110944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 237.192415 # Average occupied blocks per requestor 260210944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 333.040502 # Average occupied blocks per requestor 260310944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3918.032205 # Average occupied blocks per requestor 260410944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 9111.997525 # Average occupied blocks per requestor 260510944Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246 # Average occupied blocks per requestor 260610944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.289058 # Average percentage of cache occupancy 260710944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001015 # Average percentage of cache occupancy 260810944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.001344 # Average percentage of cache occupancy 260910944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.054571 # Average percentage of cache occupancy 261010944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.118551 # Average percentage of cache occupancy 261110944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.096636 # Average percentage of cache occupancy 261210944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.003619 # Average percentage of cache occupancy 261310944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.005082 # Average percentage of cache occupancy 261410944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.059784 # Average percentage of cache occupancy 261510944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.139038 # Average percentage of cache occupancy 261610944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.201338 # Average percentage of cache occupancy 261710944Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.970037 # Average percentage of cache occupancy 261810944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10413 # Occupied blocks per task id 261910944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 223 # Occupied blocks per task id 262010944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48634 # Occupied blocks per task id 262110944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 260 # Occupied blocks per task id 262210944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 499 # Occupied blocks per task id 262310944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9654 # Occupied blocks per task id 262410892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 262510944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id 262610944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 262710944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 262810944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1442 # Occupied blocks per task id 262910944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id 263010944Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 42029 # Occupied blocks per task id 263110944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.158890 # Percentage of cache occupancy per task id 263210944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003403 # Percentage of cache occupancy per task id 263310944Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.742096 # Percentage of cache occupancy per task id 263410944Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 61952788 # Number of tag accesses 263510944Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 61952788 # Number of data accesses 263610944Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2200570 # number of Writeback hits 263710944Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2200570 # number of Writeback hits 263810944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 25702 # number of UpgradeReq hits 263910944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 29550 # number of UpgradeReq hits 264010944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 55252 # number of UpgradeReq hits 264110944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 5421 # number of SCUpgradeReq hits 264210944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 6216 # number of SCUpgradeReq hits 264310944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 11637 # number of SCUpgradeReq hits 264410944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 145994 # number of ReadExReq hits 264510944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 170556 # number of ReadExReq hits 264610944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 316550 # number of ReadExReq hits 264710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4694 # number of ReadSharedReq hits 264810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3455 # number of ReadSharedReq hits 264910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 439478 # number of ReadSharedReq hits 265010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 496055 # number of ReadSharedReq hits 265110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 255928 # number of ReadSharedReq hits 265210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5679 # number of ReadSharedReq hits 265310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4922 # number of ReadSharedReq hits 265410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 484783 # number of ReadSharedReq hits 265510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 520043 # number of ReadSharedReq hits 265610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283587 # number of ReadSharedReq hits 265710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2498624 # number of ReadSharedReq hits 265810944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 4694 # number of demand (read+write) hits 265910944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits 266010944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 439478 # number of demand (read+write) hits 266110944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 642049 # number of demand (read+write) hits 266210944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 255928 # number of demand (read+write) hits 266310944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5679 # number of demand (read+write) hits 266410944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4922 # number of demand (read+write) hits 266510944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 484783 # number of demand (read+write) hits 266610944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 690599 # number of demand (read+write) hits 266710944Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 283587 # number of demand (read+write) hits 266810944Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2815174 # number of demand (read+write) hits 266910944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 4694 # number of overall hits 267010944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits 267110944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 439478 # number of overall hits 267210944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 642049 # number of overall hits 267310944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 255928 # number of overall hits 267410944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5679 # number of overall hits 267510944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4922 # number of overall hits 267610944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 484783 # number of overall hits 267710944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 690599 # number of overall hits 267810944Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 283587 # number of overall hits 267910944Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2815174 # number of overall hits 268010944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 41366 # number of UpgradeReq misses 268110944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 45574 # number of UpgradeReq misses 268210944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 86940 # number of UpgradeReq misses 268310944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 9742 # number of SCUpgradeReq misses 268410944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11031 # number of SCUpgradeReq misses 268510944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 20773 # number of SCUpgradeReq misses 268610944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 487808 # number of ReadExReq misses 268710944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 146598 # number of ReadExReq misses 268810944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 634406 # number of ReadExReq misses 268910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 811 # number of ReadSharedReq misses 269010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 757 # number of ReadSharedReq misses 269110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 42366 # number of ReadSharedReq misses 269210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 114531 # number of ReadSharedReq misses 269310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq misses 269410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq misses 269510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2560 # number of ReadSharedReq misses 269610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 44266 # number of ReadSharedReq misses 269710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 108963 # number of ReadSharedReq misses 269810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq misses 269910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 676832 # number of ReadSharedReq misses 270010944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 811 # number of demand (read+write) misses 270110944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 757 # number of demand (read+write) misses 270210944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 42366 # number of demand (read+write) misses 270310944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 602339 # number of demand (read+write) misses 270410944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) misses 270510944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2399 # number of demand (read+write) misses 270610944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2560 # number of demand (read+write) misses 270710944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 44266 # number of demand (read+write) misses 270810944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 255561 # number of demand (read+write) misses 270910944Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) misses 271010944Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1311238 # number of demand (read+write) misses 271110944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 811 # number of overall misses 271210944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 757 # number of overall misses 271310944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 42366 # number of overall misses 271410944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 602339 # number of overall misses 271510944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 184040 # number of overall misses 271610944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2399 # number of overall misses 271710944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2560 # number of overall misses 271810944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 44266 # number of overall misses 271910944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 255561 # number of overall misses 272010944Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 176139 # number of overall misses 272110944Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1311238 # number of overall misses 272210944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 225555000 # number of UpgradeReq miss cycles 272310944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 234735000 # number of UpgradeReq miss cycles 272410944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 460290000 # number of UpgradeReq miss cycles 272510944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 48941500 # number of SCUpgradeReq miss cycles 272610944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 54202000 # number of SCUpgradeReq miss cycles 272710944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 103143500 # number of SCUpgradeReq miss cycles 272810944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 40891325500 # number of ReadExReq miss cycles 272910944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 11909713000 # number of ReadExReq miss cycles 273010944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 52801038500 # number of ReadExReq miss cycles 273110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 72944500 # number of ReadSharedReq miss cycles 273210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 67955000 # number of ReadSharedReq miss cycles 273310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 3540995500 # number of ReadSharedReq miss cycles 273410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 10155548500 # number of ReadSharedReq miss cycles 273510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of ReadSharedReq miss cycles 273610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 211977500 # number of ReadSharedReq miss cycles 273710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 227366000 # number of ReadSharedReq miss cycles 273810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 3707983000 # number of ReadSharedReq miss cycles 273910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 9711131500 # number of ReadSharedReq miss cycles 274010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of ReadSharedReq miss cycles 274110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 68879114830 # number of ReadSharedReq miss cycles 274210944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 72944500 # number of demand (read+write) miss cycles 274310944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 67955000 # number of demand (read+write) miss cycles 274410944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 3540995500 # number of demand (read+write) miss cycles 274510944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 51046874000 # number of demand (read+write) miss cycles 274610944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of demand (read+write) miss cycles 274710944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 211977500 # number of demand (read+write) miss cycles 274810944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 227366000 # number of demand (read+write) miss cycles 274910944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 3707983000 # number of demand (read+write) miss cycles 275010944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 21620844500 # number of demand (read+write) miss cycles 275110944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of demand (read+write) miss cycles 275210944Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 121680153330 # number of demand (read+write) miss cycles 275310944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 72944500 # number of overall miss cycles 275410944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 67955000 # number of overall miss cycles 275510944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 3540995500 # number of overall miss cycles 275610944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 51046874000 # number of overall miss cycles 275710944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of overall miss cycles 275810944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 211977500 # number of overall miss cycles 275910944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 227366000 # number of overall miss cycles 276010944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 3707983000 # number of overall miss cycles 276110944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 21620844500 # number of overall miss cycles 276210944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of overall miss cycles 276310944Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 121680153330 # number of overall miss cycles 276410944Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2200570 # number of Writeback accesses(hits+misses) 276510944Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2200570 # number of Writeback accesses(hits+misses) 276610944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 67068 # number of UpgradeReq accesses(hits+misses) 276710944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 75124 # number of UpgradeReq accesses(hits+misses) 276810944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 142192 # number of UpgradeReq accesses(hits+misses) 276910944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 15163 # number of SCUpgradeReq accesses(hits+misses) 277010944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 17247 # number of SCUpgradeReq accesses(hits+misses) 277110944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 32410 # number of SCUpgradeReq accesses(hits+misses) 277210944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 633802 # number of ReadExReq accesses(hits+misses) 277310944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 317154 # number of ReadExReq accesses(hits+misses) 277410944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 950956 # number of ReadExReq accesses(hits+misses) 277510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5505 # number of ReadSharedReq accesses(hits+misses) 277610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4212 # number of ReadSharedReq accesses(hits+misses) 277710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 481844 # number of ReadSharedReq accesses(hits+misses) 277810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 610586 # number of ReadSharedReq accesses(hits+misses) 277910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 439968 # number of ReadSharedReq accesses(hits+misses) 278010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8078 # number of ReadSharedReq accesses(hits+misses) 278110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7482 # number of ReadSharedReq accesses(hits+misses) 278210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 529049 # number of ReadSharedReq accesses(hits+misses) 278310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 629006 # number of ReadSharedReq accesses(hits+misses) 278410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 459726 # number of ReadSharedReq accesses(hits+misses) 278510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3175456 # number of ReadSharedReq accesses(hits+misses) 278610944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 5505 # number of demand (read+write) accesses 278710944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 4212 # number of demand (read+write) accesses 278810944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 481844 # number of demand (read+write) accesses 278910944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1244388 # number of demand (read+write) accesses 279010944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 439968 # number of demand (read+write) accesses 279110944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8078 # number of demand (read+write) accesses 279210944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7482 # number of demand (read+write) accesses 279310944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 529049 # number of demand (read+write) accesses 279410944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 946160 # number of demand (read+write) accesses 279510944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 459726 # number of demand (read+write) accesses 279610944Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4126412 # number of demand (read+write) accesses 279710944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 5505 # number of overall (read+write) accesses 279810944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 4212 # number of overall (read+write) accesses 279910944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 481844 # number of overall (read+write) accesses 280010944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1244388 # number of overall (read+write) accesses 280110944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 439968 # number of overall (read+write) accesses 280210944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8078 # number of overall (read+write) accesses 280310944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7482 # number of overall (read+write) accesses 280410944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 529049 # number of overall (read+write) accesses 280510944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 946160 # number of overall (read+write) accesses 280610944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 459726 # number of overall (read+write) accesses 280710944Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4126412 # number of overall (read+write) accesses 280810944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.616777 # miss rate for UpgradeReq accesses 280910944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.606650 # miss rate for UpgradeReq accesses 281010944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.611427 # miss rate for UpgradeReq accesses 281110944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.642485 # miss rate for SCUpgradeReq accesses 281210944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639589 # miss rate for SCUpgradeReq accesses 281310944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.640944 # miss rate for SCUpgradeReq accesses 281410944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.769654 # miss rate for ReadExReq accesses 281510944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.462230 # miss rate for ReadExReq accesses 281610944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.667124 # miss rate for ReadExReq accesses 281710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for ReadSharedReq accesses 281810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.179725 # miss rate for ReadSharedReq accesses 281910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.087925 # miss rate for ReadSharedReq accesses 282010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187576 # miss rate for ReadSharedReq accesses 282110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for ReadSharedReq accesses 282210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for ReadSharedReq accesses 282310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.342155 # miss rate for ReadSharedReq accesses 282410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.083671 # miss rate for ReadSharedReq accesses 282510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173230 # miss rate for ReadSharedReq accesses 282610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for ReadSharedReq accesses 282710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.213145 # miss rate for ReadSharedReq accesses 282810944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for demand accesses 282910944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.179725 # miss rate for demand accesses 283010944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.087925 # miss rate for demand accesses 283110944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.484044 # miss rate for demand accesses 283210944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for demand accesses 283310944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for demand accesses 283410944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.342155 # miss rate for demand accesses 283510944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.083671 # miss rate for demand accesses 283610944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.270103 # miss rate for demand accesses 283710944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for demand accesses 283810944Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.317767 # miss rate for demand accesses 283910944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for overall accesses 284010944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.179725 # miss rate for overall accesses 284110944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.087925 # miss rate for overall accesses 284210944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.484044 # miss rate for overall accesses 284310944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for overall accesses 284410944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for overall accesses 284510944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.342155 # miss rate for overall accesses 284610944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.083671 # miss rate for overall accesses 284710944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.270103 # miss rate for overall accesses 284810944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for overall accesses 284910944Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.317767 # miss rate for overall accesses 285010944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5452.666441 # average UpgradeReq miss latency 285110944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5150.634133 # average UpgradeReq miss latency 285210944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 5294.340925 # average UpgradeReq miss latency 285310944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5023.763088 # average SCUpgradeReq miss latency 285410944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4913.607107 # average SCUpgradeReq miss latency 285510944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 4965.267414 # average SCUpgradeReq miss latency 285610944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 83826.680784 # average ReadExReq miss latency 285710944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 81240.624019 # average ReadExReq miss latency 285810944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 83229.096982 # average ReadExReq miss latency 285910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average ReadSharedReq miss latency 286010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89768.824306 # average ReadSharedReq miss latency 286110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83581.067365 # average ReadSharedReq miss latency 286210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88670.739800 # average ReadSharedReq miss latency 286310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average ReadSharedReq miss latency 286410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average ReadSharedReq miss latency 286510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88814.843750 # average ReadSharedReq miss latency 286610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83765.937740 # average ReadSharedReq miss latency 286710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89123.202371 # average ReadSharedReq miss latency 286810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average ReadSharedReq miss latency 286910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 101766.930095 # average ReadSharedReq miss latency 287010944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average overall miss latency 287110944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 89768.824306 # average overall miss latency 287210944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 83581.067365 # average overall miss latency 287310944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 84747.748361 # average overall miss latency 287410944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average overall miss latency 287510944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average overall miss latency 287610944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 88814.843750 # average overall miss latency 287710944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 83765.937740 # average overall miss latency 287810944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 84601.502185 # average overall miss latency 287910944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average overall miss latency 288010944Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 92797.915657 # average overall miss latency 288110944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average overall miss latency 288210944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 89768.824306 # average overall miss latency 288310944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 83581.067365 # average overall miss latency 288410944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 84747.748361 # average overall miss latency 288510944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average overall miss latency 288610944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average overall miss latency 288710944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 88814.843750 # average overall miss latency 288810944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 83765.937740 # average overall miss latency 288910944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 84601.502185 # average overall miss latency 289010944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average overall miss latency 289110944Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 92797.915657 # average overall miss latency 289210944Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 289310515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 289410944Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 289510515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 289610944Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 289710515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 289810515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 289910515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 290010944Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1000989 # number of writebacks 290110944Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1000989 # number of writebacks 290210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 84 # number of ReadSharedReq MSHR hits 290310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 16 # number of ReadSharedReq MSHR hits 290410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 106 # number of ReadSharedReq MSHR hits 290510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 84 # number of ReadSharedReq MSHR hits 290610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 290 # number of ReadSharedReq MSHR hits 290710944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 84 # number of demand (read+write) MSHR hits 290810944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 16 # number of demand (read+write) MSHR hits 290910944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 106 # number of demand (read+write) MSHR hits 291010944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits 291110944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits 291210944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 84 # number of overall MSHR hits 291310944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 16 # number of overall MSHR hits 291410944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 106 # number of overall MSHR hits 291510944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits 291610944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 290 # number of overall MSHR hits 291710944Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 40865 # number of CleanEvict MSHR misses 291810944Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 40865 # number of CleanEvict MSHR misses 291910944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 41366 # number of UpgradeReq MSHR misses 292010944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 45574 # number of UpgradeReq MSHR misses 292110944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 86940 # number of UpgradeReq MSHR misses 292210944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9742 # number of SCUpgradeReq MSHR misses 292310944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11031 # number of SCUpgradeReq MSHR misses 292410944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 20773 # number of SCUpgradeReq MSHR misses 292510944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 487808 # number of ReadExReq MSHR misses 292610944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 146598 # number of ReadExReq MSHR misses 292710944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 634406 # number of ReadExReq MSHR misses 292810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 811 # number of ReadSharedReq MSHR misses 292910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 757 # number of ReadSharedReq MSHR misses 293010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 42282 # number of ReadSharedReq MSHR misses 293110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 114515 # number of ReadSharedReq MSHR misses 293210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq MSHR misses 293310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq MSHR misses 293410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2560 # number of ReadSharedReq MSHR misses 293510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44160 # number of ReadSharedReq MSHR misses 293610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 108879 # number of ReadSharedReq MSHR misses 293710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq MSHR misses 293810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 676542 # number of ReadSharedReq MSHR misses 293910944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 811 # number of demand (read+write) MSHR misses 294010944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 757 # number of demand (read+write) MSHR misses 294110944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 42282 # number of demand (read+write) MSHR misses 294210944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 602323 # number of demand (read+write) MSHR misses 294310944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) MSHR misses 294410944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2399 # number of demand (read+write) MSHR misses 294510944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2560 # number of demand (read+write) MSHR misses 294610944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 44160 # number of demand (read+write) MSHR misses 294710944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 255477 # number of demand (read+write) MSHR misses 294810944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) MSHR misses 294910944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1310948 # number of demand (read+write) MSHR misses 295010944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 811 # number of overall MSHR misses 295110944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 757 # number of overall MSHR misses 295210944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 42282 # number of overall MSHR misses 295310944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 602323 # number of overall MSHR misses 295410944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of overall MSHR misses 295510944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2399 # number of overall MSHR misses 295610944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2560 # number of overall MSHR misses 295710944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 44160 # number of overall MSHR misses 295810944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 255477 # 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mshr miss rate for CleanEvict accesses 303010892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 303110944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.616777 # mshr miss rate for UpgradeReq accesses 303210944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.606650 # mshr miss rate for UpgradeReq accesses 303310944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.611427 # mshr miss rate for UpgradeReq accesses 303410944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.642485 # mshr miss rate for SCUpgradeReq accesses 303510944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639589 # mshr miss rate for SCUpgradeReq accesses 303610944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.640944 # mshr miss rate for SCUpgradeReq accesses 303710944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.769654 # mshr miss rate for ReadExReq accesses 303810944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462230 # mshr miss rate for ReadExReq accesses 303910944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.667124 # mshr miss rate for ReadExReq accesses 304010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for ReadSharedReq accesses 304110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for ReadSharedReq accesses 304210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for ReadSharedReq accesses 304310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187549 # mshr miss rate for ReadSharedReq accesses 304410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for ReadSharedReq accesses 304510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for ReadSharedReq accesses 304610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for ReadSharedReq accesses 304710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for ReadSharedReq accesses 304810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173097 # mshr miss rate for ReadSharedReq accesses 304910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for ReadSharedReq accesses 305010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.213053 # mshr miss rate for ReadSharedReq accesses 305110944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for demand accesses 305210944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for demand accesses 305310944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for demand accesses 305410944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for demand accesses 305510944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for demand accesses 305610944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for demand accesses 305710944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for demand accesses 305810944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for demand accesses 305910944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for demand accesses 306010944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for demand accesses 306110944Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.317697 # mshr miss rate for demand accesses 306210944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for overall accesses 306310944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for overall accesses 306410944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for overall accesses 306510944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for overall accesses 306610944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for overall accesses 306710944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for overall accesses 306810944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for overall accesses 306910944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for overall accesses 307010944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for overall accesses 307110944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for overall accesses 307210944Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.317697 # mshr miss rate for overall accesses 307310944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168 # average UpgradeReq mshr miss latency 307410944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918 # average UpgradeReq mshr miss latency 307510944Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411 # average UpgradeReq mshr miss latency 307610944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782 # average SCUpgradeReq mshr miss latency 307710944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300 # average SCUpgradeReq mshr miss latency 307810944Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566 # average SCUpgradeReq mshr miss latency 307910944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784 # average ReadExReq mshr miss latency 308010944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019 # average ReadExReq mshr miss latency 308110944Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982 # average ReadExReq mshr miss latency 308210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average ReadSharedReq mshr miss latency 308310944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average ReadSharedReq mshr miss latency 308410944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average ReadSharedReq mshr miss latency 308510944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155 # average ReadSharedReq mshr miss latency 308610944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average ReadSharedReq mshr miss latency 308710944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average ReadSharedReq mshr miss latency 308810944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average ReadSharedReq mshr miss latency 308910944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average ReadSharedReq mshr miss latency 309010944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868 # average ReadSharedReq mshr miss latency 309110944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average ReadSharedReq mshr miss latency 309210944Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343 # average ReadSharedReq mshr miss latency 309310944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency 309410944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency 309510944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency 309610944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency 309710944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency 309810944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency 309910944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency 310010944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency 310110944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency 310210944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency 310310944Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency 310410944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency 310510944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency 310610944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency 310710944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency 310810944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency 310910944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency 311010944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency 311110944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency 311210944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency 311310944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency 311410944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency 311510892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency 311610944Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081 # average ReadReq mshr uncacheable latency 311710944Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average ReadReq mshr uncacheable latency 311810944Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258 # average ReadReq mshr uncacheable latency 311910944Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322 # average ReadReq mshr uncacheable latency 312010944Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766 # average WriteReq mshr uncacheable latency 312110944Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650 # average WriteReq mshr uncacheable latency 312210944Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586 # average WriteReq mshr uncacheable latency 312310892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency 312410944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495 # average overall mshr uncacheable latency 312510944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average overall mshr uncacheable latency 312610944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351 # average overall mshr uncacheable latency 312710944Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123 # average overall mshr uncacheable latency 312810515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 312910944Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 81967 # Transaction distribution 313010944Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 767450 # Transaction distribution 313110944Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38603 # Transaction distribution 313210944Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38603 # Transaction distribution 313310944Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1107684 # Transaction distribution 313410944Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 202348 # Transaction distribution 313510944Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 391044 # Transaction distribution 313610944Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 311393 # Transaction distribution 313710944Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 114065 # Transaction distribution 313810944Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 650749 # Transaction distribution 313910944Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 628057 # Transaction distribution 314010944Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 685483 # Transaction distribution 314110892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 314210892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 314310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes) 314410535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 314510944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26828 # Packet count per connected master and slave (bytes) 314610944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4735959 # Packet count per connected master and slave (bytes) 314710944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4885501 # Packet count per connected master and slave (bytes) 314810944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342529 # Packet count per connected master and slave (bytes) 314910944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 342529 # Packet count per connected master and slave (bytes) 315010944Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5228030 # Packet count per connected master and slave (bytes) 315110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes) 315210535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 315310944Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53656 # Cumulative packet size per connected master and slave (bytes) 315410944Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147705452 # Cumulative packet size per connected master and slave (bytes) 315510944Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 147915041 # Cumulative packet size per connected master and slave (bytes) 315610944Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264128 # Cumulative packet size per connected master and slave (bytes) 315710944Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7264128 # Cumulative packet size per connected master and slave (bytes) 315810944Sandreas.hansson@arm.comsystem.membus.pkt_size::total 155179169 # Cumulative packet size per connected master and slave (bytes) 315910944Sandreas.hansson@arm.comsystem.membus.snoops 613936 # Total snoops (count) 316010944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3578377 # Request fanout histogram 316110535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 316210535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 316310535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 316410535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 316510944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3578377 100.00% 100.00% # Request fanout histogram 316610535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 316710535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 316810535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 316910535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 317010944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3578377 # Request fanout histogram 317110944Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 101272500 # Layer occupancy (ticks) 317210535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 317310944Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 317410535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 317510944Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 23177500 # Layer occupancy (ticks) 317610535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 317710944Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7575699049 # Layer occupancy (ticks) 317810535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 317910944Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 7326536131 # Layer occupancy (ticks) 318010535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 318110944Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 229377455 # Layer occupancy (ticks) 318210535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 318310515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 318410515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 318510515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 318610515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 318710515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 318810515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 318910515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 319010515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 319110515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 319210585SN/Asystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 319310515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 319410515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 319510515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 319610585SN/Asystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 319710515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 319810515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 319910515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 320010515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 320110515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 320210515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 320310515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 320410515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 320510515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 320610515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 320710515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 320810515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 320910515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 321010515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 321110515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 321210515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 321310515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 321410515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 321510515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 321610515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 321710515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 321810515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 321910515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 322010515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 322110515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 322210515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 322310515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 322410515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 322510944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 81969 # Transaction distribution 322610944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4074898 # Transaction distribution 322710944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution 322810944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38603 # Transaction distribution 322910944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 3308322 # Transaction distribution 323010944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1226405 # Transaction distribution 323110944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 439947 # Transaction distribution 323210944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 323030 # Transaction distribution 323310944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 762977 # Transaction distribution 323410944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution 323510944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution 323610944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1086983 # Transaction distribution 323710944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1086983 # Transaction distribution 323810944Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4000171 # Transaction distribution 323910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 324010944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7169000 # Packet count per connected master and slave (bytes) 324110944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6360157 # Packet count per connected master and slave (bytes) 324210944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 13529157 # Packet count per connected master and slave (bytes) 324310944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 219530790 # Cumulative packet size per connected master and slave (bytes) 324410944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185908027 # Cumulative packet size per connected master and slave (bytes) 324510944Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 405438817 # Cumulative packet size per connected master and slave (bytes) 324610944Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3048406 # Total snoops (count) 324710944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 11669556 # Request fanout histogram 324810944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.129089 # Request fanout histogram 324910944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.335298 # Request fanout histogram 325010515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 325110515SN/Asystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 325210944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 10163148 87.09% 87.09% # Request fanout histogram 325310944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 1506408 12.91% 100.00% # Request fanout histogram 325410515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 325510515SN/Asystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 325610515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 325710944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 11669556 # Request fanout histogram 325810944Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 7690985653 # Layer occupancy (ticks) 325910515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 326010944Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2550000 # Layer occupancy (ticks) 326110515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 326210944Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4244781764 # Layer occupancy (ticks) 326310515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 326410944Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3859650249 # Layer occupancy (ticks) 326510515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 326610515SN/A 326710515SN/A---------- End Simulation Statistics ---------- 3268